Page 1
!DmD~lI
RX02
Page 2
EK-ORX02-TM-001
RX02 Floppy Disk System
Technical
Manual
digital equipment
corporation.
maynard, massachusetts
Page 3
Copyright
@
1978
by Digital Equipment Corporation
1st
Edition, October 1978
The material in this manual
is
for informational purposes
and
is
subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any
errors which may appear in this manual.
Printed
in
U.S.A.
This document was set on DIGITAL's DECset-8000 computerized
typesetting system.
The following are trademarks
Maynard, Massachusetts:
DIGITAL
DEC
PDP
DECUS
UNIBUS
D ECsystem-l 0
DECSYSTEM-20
DIBOL
EDUSYSTEM
VAX
VMS
of
Digital Equipment Corporation,
MASSBUS
OMNIBUS
OS/8
RSTS
RSX
lAS
Page 4
PREFACE
CONTENTS
Page
CHAPTER
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.3
1.3.1
1.3.1.1
I ~ 1 2
1.3.1.3
1.3.2
1.3.2.1
1.3.2.2
1.3.2.3
1.4
1.5
1.5.1
1.5.2
1.5.2.1
1.5.2.2
1.5.3
1.5.3.1
1.5.3.2
1.5.3.3
1.5.3.4
GENERAL
1
INTRODUCTION
GENERAL
Interface Modules ........................................................................................ 1-2
Microprogrammed Controller ..................................................................... .1-2
Read/Write
Electromechani cal Dri
Power Su pply ...............................................................................................
OPTION
Operation
Operation
R XV211 ) ...................................................................................................... 1 -7
SPECIFI
SYSTEMS
Media
Recording Scheme ...................................................................................... 1-10
Logical
INFORMATION
..............................................................................................
DES<::
DESCRIPTION
PDP-8
PDP-!!
LSI-II
PDP-8
PDP-II
LSI-II
CATIONS
CO
...........................................................................................................
Double
Miller
Header Field Description ....................................................................
Data
Track
CRC
RI
PTION
Electronics ................................................................................ 1-2
For
Single Density Recording Only (RX8E,
Operation
Operation ................................................................................
Operation ................................................................................. 1-7
For
Single
Operation
Operation
Operation
............................................................................................. 1-8
MPATIBILITY
Frequency
Code
(MFM)
Format
...........................................................................................
Field Description .......................................................................
Usage ....................................................................................... 1-14
Capability .................................................................................. 1-14
............................................................................... 1-2
ve
.............................................................................. 1-2
...................................................................................
RXII,
.................................................................................. 1-6
or
Double Density Recording RX28,
.................................................................................. 1-7
................................................................................ 1-7
.................................................................................
........................................................................... .1-9
(FM)
..................................................................... I-IO
...........................................................................
RXVll)
RX2II,
........
1-1
1-4
1-4
1-6
1··6
1-7
1-9
1-10
1-12
1-1
1-13
3
CHAPTER
2.1
2.1. ]
2.1.2
2.1.3
2.1.3.1
2.1.3.2
2
INSTALLATION
SITE
PREPARATION
Space ............................................................................................................
Cabling ........................................................................................................ 2-2
AC
........................................................................................
Power ..................................................................................................... 2-3
Power Requirements ............................................................................ 2-3
Input Power Modification Requirements ............................................. .2-3
2-1
2-1
iii
Page 5
2.1.4
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.5
2.6
CONTENTS (Cont)
Fire
and
Safety Precautions .......................................................................... 2-4
CONFIGURATION
ENVIRONMENTAL
General ....................................................................................................... .2-4
Temperature,
Heat
Dissipation .......................................................................................... 2-4
Radiated
Cleanliness .................................................................................................. .2-6
UNPACKING
General
Tools ............................................................................................................ 2-6
Unpacking ................................................................................................... 2-6
INSTALLATION
TESTING
&nissions ..................................................................................... .2-4
........................................................................................................ 2-6
Cabinet-Mounted
Separate Container ............................................................................... 2-7
Inspection ............................................................................................ 2-7
..........................................................................................................
GUIDELINES
CONSIDERA
Relative
AND
................................................................................................ 2-7
Humidity
INSPECTION
................................................................................. 2-6
.................................................................. 2-4
TIONS
................................................................. .2-4
................................................................... 2-6
....................................................... 2-4
Page
2-11
CHAPTER
3.1
3.2
3.2. i
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.3
3.4
CHAPTER
4.1
4.1.1
4.1.2
4.1.2
.1
4.1.2.2
4.1.2.3
4.1.2.4
4.1.2.5
4.1.2.6
4.1.2.7
4.1.2.8
4.1.3
3
USER
CUSTOMER
CARE
Handling Practices
Diskette Storage ........................................................................................... 3-2
Shipping Diskettes ........................................................................................ 3-2
OPERATING
OPERATOR
PROGRAMMING
4
RX8E
Device Codes ................................................................................................ 4-1
Instruction
Register Description ..................................................................................... 4-4
INFORMATION
RESPONSIBILITY
OF
Short
Long
and
RX8E
RX28
Transfer
STR
SER
SDN
INTR
INIT
MEDIA
RX28
.............................................................................................. 3-1
Term
(Available for Immediate Use) ........................................... 3-2
Term
........................................................................................... 3-2
INSTRUCTIONS
TROUBLESHOOTIN G __
PROGRAMMING
Set .............................................................................................. 4-2
Load
Command
Load
Command -(First
Data
- 67x3 ........................................................................................... 4-4
- 67x4 ........................................................................................... 4-4
- 67x5 .......................................................................................... 4-4
- 67x6 ........................................................................................ 4-4
- 67x7 .......................................................................................... 4-4
....................................................................... 3-1
and
Precautions .............................................................. 3-1
....................................................................... .3-3
Register
.. _ """"""''''''''''
INFORMATION
(LCD) - 67xl ................................................... 4-2
byte
67xl,
(XDR)
- 67x2 ................................................... 4-3
''''''''''".,
....................................
Second byte 67x2) ................ 4-3
....................... 3-3
.4-1
iv
Page 6
CONTENTS (Coot)
Page
4.1.3.1
4.1.3.2
4.1.3.3
4.1.3.4
4.1.3.5
.6
4.1.3
4.1.3.7
4.1.4
4.1.4.1
4.1.4.2
.3
4.1.4
4.1.4.4
4.1.4.5
4.1.4.6
4.1.4.7
4.1.4.8
4.1.4.9
4.1.4.10
4.1.5
4.1.5.1
4.1.5.2
4.1.6
4.1.6.1
4.1.6.2
4.1.6.3
4.1.7
4.1.8
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.3.4
4.2.3.5
4.2.3.6
4.2.3.7
Command
Error
RX2TA RX2SA RX2DB - RX
RX8E -
RX28 -
Register ............................................................................... 4-4
Code Register ............................................................................. 4-5
RX
Track
RX
Sector Address ............................................................... 4-6
RX
Error
RX
Error
Address ................................................................ 4-6
Data
Buffer .................................................................... 4-7
and Status ............................................................... 4-7
and Status ................................................................ 4-8
Function Code Description .......................................................................... 4-9
Fill Buffer
(000) .................................................................................. 4-10
Empty Buffer (001) ............................................................................. 4-10
Write Sector (010) ...............................................................................
Read Sector (011) ...............................................................................
Set Media Density
Maintenance
Status (101) for
Read
Write Deleted
Read
Error
Code Function (111) ......................................................... 4-12
(l00)
for RX28 Only ..............................................
Read
Status (101) for RX28 Only ................................... 4-12
Da
RX8EOnly
ta
Sector (
...................................................... .4-12
11
0) ......................................................... 4-12
Power Fail .......................................................................................... 4-12
Ericr
Recovery ........................................................................................... 4-13
RX8E ................................................................................................. 4-13
RX28 .................................................................................................. 4-13
RX8E
Programming Examples ................................................................... 4-14
Write/Write
Deleted
Data/Read
Functions ....................................... .4-14
Empty Buffer Function ....................................................................... 4-16
Fill Buffer Function ............................................................................ 4-17
RX28
Programming Examples ................................................................... .4-17
Restrictions and Programming Pitfalls ........................................................ 4-23
RXII
and RXVl1
PROGRAMMING
INFORMATION
................................. 4-24
Register and Vector Addresses ............................................. ,' ..................... 4-24
Register Description ................................................................................... 4-24
RXCS RXDB RXTA RXSA RXDB RXES - RX
Command
Data
RX
Track
RX
Sector Address ............................................................... 4-26
RX
Data
Error
and
Status (177170) .............................................. 4-24
Buffer Register (177172) .............................................. 4-26
Address ............................................................... 4-26
Buffer .................................................................... 4-27
and
Status ............................................................. 4-27
Function Codes .......................................................................................... 4-28
Fill Buffer
Empty Buffer
Write
Read
(000) .................................................................................. 4-29
(001) ............................................................................. 4-29
Sector (010) ............................................................................... 4-29
Sector (011) ............................................................................... 4-30
Read Status (101) ................................................................................ 4-30
Write Sector with Deleted
Code
Read Error
Function
Data
(110) ................................................. .4-31
(111
) ......................................................... 4-31
4-11
4-11
4-11
v
Page 7
CONTENTS (Cont)
Page
4.2.3.8
4.2.4
4.2.4.1
4.2.42
4.2.4.3
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.2.5
4.3.2.6
4.3.2.7
4.3.2.8
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.3.3.5
4.3.3.6
4.3.3.7
4.3.3.8
4.3.3.9
4.3.4
4.3.5
4.3.5.1
4.3.5.2
Power Fail ..........................................................................................
Programming Examples .............................................................................. 4-31
Read
Data/Write
Data
.......................................................................
Empty Buffer Function ....................................................................... 4-33
Fill Buffer Function ............................................................................
and
Restrictions
Error
RX211
Register
Recovery ........................................................................................... 4-35
and
RXV21
and
Programming Pitfalls ........................................................ 4-33
PROGRAMMING
INFORMATION
.............................. .4-36
Vector Addresses ................................................................... .4-37
Register Description ................................................................................... 4-37
RX2CS RX2DB RX2TA -
RX2SA RX2W C RX2BA RX2DB -RX
RX2ES
Command
Data
RX
Track
RX
Sector Address .............................................................. 4-39
RX
RX
Bus Address Register ................................................... .4-39
Data
-
RX
Error
and
Status (177170) ........................................... .4-37
Buffer Register (177172) ............................................. 4-38
Address ................................................................ 4-38
Word
Count
Register .................................................. 4-39
Buffer .................................................................. 4-40
and Status ............................................................ 4-40
Function Codes .......................................................................................... 4-41
Fill Buffer
Empty
Write
Read Sector
Set
Media
Maintenance
Write Sector with Deleted
Read
(000) .................................................................................. 4-41
Buffer (001) ............................................................................. 4-42
Sector (010) ............................................................................... 4-42
(011) ............................................................................... 4-43
Density (100) ..................................................................... .4-43
Read
Status (101) .......................................................... .4-44
Data
(110) .................................................. 4-44
Error
Code
(111) ........................................................................ 4-44
RX02 Power Fail ................................................................................ 4-44
Error
Recovery ........................................................................................... 4-45
R)f~
11
/RXV2I
Write/Fill
Read/Empty
Programming
Examples
..
.,
... " ........................................... 4-45
Buffer ................................................................................ 4-45
Buffer ............................................................................ 4-46
4-31
4-31
4-3
3
CHAPTER 5
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
THEORY OF OPERATION
OVERALL
Omnibus
Unibus
LSI-II
Interface
~CPU
Read/Write
INTERFACE
RX8E/RX28
SYSTEM
to
RX8E/RX28
to
RXll/RX211
Bus
to
RXV11/RXV21 Interface Signals ........................................... 5-4
Module
Controller
Electronics to
MODULES
Interface (M8357) Block
BLOCK
to
~CPU
to
Read/Write
BLOCK
DIAGRAM
Interface Signals ..................................................
.......................................................
.5-1
5-1
Interface Signals .................................................... 5-3
Controller
Signals .............................................. 5-6
Electronics Signals .................................... 5-8
Drive
Signals ..................................................... .5-9
DIAGRAM
DESCRIPTION
Diagram
................... 5-10
Description ...................... 5-10
vi
Page 8
CONTENTS (Coot)
Page
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.1.5
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.2.6
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.3.7
5.2.4
.1
5.2.4
5.2.4.2
5.2.4.3
5.2.4.4
5.2.4.5
5.2.4.6
5.2.4.7
5.2.4.8
5.2.5
5.2.5.1
5.2.5.2
5.2.5.3
5.2.5.4
5.2.5.5
5.2.5.6
5.2.5.7
5.2.5.8
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
Device
Select and
Interrupt
Control
lOT
Decoder .......................................................... 5-10
and Skip Logic ........................................................ 5-12
C Line Select Logic ............................................................................. 5-12
Interface Register ............................................................................... 5-12
Sequence and Function Control Logic ................................................ 5-13
RXll
Interface (M7846) Block Diagram Description .................................. 5-14
Address Decoder ................................................................................ 5-14
Data
Path Selection ............................................................................ 5-14
Interface Data Buffer Register ............................................................ 5-16
and
Sequence
Function Control Logic ................................................ 5-16
Interrupt Control Logic ...................................................................... 5-17
Vector Address Generator .................................................................. 5-17
11
RXV
Interface (M7946) Block Diagram Description ............................... 5-17
Address Decoding Logic ..................................................................... 5-17
I/0
Control Logic ..............................................................................
RX
Data
Buffer (RXDB) Register ...................................................... 5-17
Command/Status
RX
(RXCS) Register ..............................................
Status and Control Signal Interface Logic ........................................... 5-19
Interrupt
Contro
1 Logic ......................................................................
Initialize Logic .................................................................................... 5-19
RX211 Interface (M8256) Block Diagram Description ................................ 5-19
Address Decoder, Buffer Selector,
Command
and
Status Buffer ............................................................... 5-20
SSYN Register .............................. 5-19
Data Buffer ........................................................................................ 5-20
Data
Input/Output
and
TRANSMIT
DA
TA
CIRCUIT
.................... 5-20
Address Circuits ................................................................................. 5-20
Interface Control Circuits ................................................................... 5-20
Bus Control Circuits ............................................................................ 5-22
Interrupt Circuits ................................................................................ 5-22
RXV21 Interface
Input/Output
Command
Data
Buffer ........................................................................................ 5-24
Input/Output
(M8029) Block Diagram Description ............................... 5-22
Transceiver, Buffer Selector .......................................... 5-22
and
Status Buffer ............................................................... 5-22
Transceiver and Transmit/Receive
Data
Circuit ........... 5-24
Address Circuits ................................................................................. 5-24
Interface Control Circuits ................................................................... 5-24
Bus Control Circuits ........................................................................... 5-25
In terrupt Circuits ................................................................................
UNIT
LEVEL
DESCRIPTION
.........................................................................
Microprogrammed Controller (M7744) Hardware Description ...................
PROM,
Branch
I/O
Sector
ROM
Control
Register, Processor and Sequencer Circuits ..................
Circuits ...................................................................... 5-30
Control Circuits ........................................................................... 5-30
Buffer
and
Control Circuits ......................................................
5-17
5-17
5-1
5-2
5-25
5-25
5-25
5-31
9
5
vii
Page 9
CONTENTS (Coot)
Page
5.3.1.5
5.3.1.6
5.3.1.7
5.3.2
5.3.2.1
5.3.2.2
5.3.2.3
5.3.2.4
5.3.2.5
5.3.2.6
5.3.2.7
5.3.2.8
5.3.2.9
5.3.2.10
5.3.2.11
5.3.2.12
5.3.2.13
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.4
5.3.4.1
5.3.4.2
~
-. A -.
~."'.'+.'"
5.3.4.4
Data
Selection
and
CRC
Circuits ........................................................
5-31
Timing and Synchronizing Circuits ..................................................... 5-32
Power Fail Circuit .............................................................................. 5-32
Microprogrammed Controller Software Description ................................... 5-32
Initialize Routine ................................................................................ 5-32
Find Header
Read Address
Read
(RD)
Write/Write
Read Error Register
(FIND
Mark
HD)
Subroutine ................................................. 5-32
(RDAM)
Subroutine .......................................... 5-35
Sector Subroutine ............................................................. 5-35
Sector Subroutine ........................................................... 5-35
(RDERRG)
and Set Density (SET
DEN)
Subroutines ........................................................................................ 5-35
Fill/Empty
Buffer Routine ................................................................. 5-35
Find Track Subroutine ....................................................................... 5-35
Decode
Command
(DECCMD)
Routine ............................................ 5-45
Maintenance Read Status (MRDST) and Check Ready
(CHKRDY)
Get
Parameter
Subroutines .................................................................... 5-45
(GET
PAR), Step
Head
(STEPHD), Wait,
Wait Run, and Write Zeros (WRTS) Subroutines ............................... 5-45
Find Sector (FINDSE),
Send Word 8 (SNDW8),
Get
Word
(GET
WRD)
Maintenance Check Ready
Read/Write
Drive
Position
Read/Write
Block Diagram Description ..................................................... 5-52
and
Head Control ..................................................................... 5-52
Data
Selection ....................................................................... 5-52
Circuit ............................................................................ 5-52
Mechanial Drive Description ......................................................................
Drive Mechanism ...............................................................................
Send Word
Get
Command
12
(SNDWI2),
(GET
CMD),
and
Subroutines ................................................... 5-45
(MAINT
CHK)
Subroutine .....................
5-45
5-55
5-55
Spin die Mechanism ............................................................................ 5-55
Positioning Mechanism .................................. ,,,.,, .............................. 5-55
Head Load Mechanism ....................................................................... 5-58
CHAPTER
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.4.1
6.4.2
6.5
6.5.1
MAINTENANCE
6
EQUIPMENT
TROUBLESHOOTING
M7744, M7745 Failures ................................................................................
Drive Failures ..............................................................................................
TROUBLESHOOTING
TROUBLESHOOTING
RX211
PDP-8
and
and
REMOVAL
Module Replacement Procedures .................................................................
CARE
..........................................................................................
THE
RX02 ...................................................................
WITH
WITHOUT A DIAGNOSTIC
DIAGNOSTICS
...............................................
...................................... 6-2
RXV21 Systems .........................................................................
CM05-8 Based Systems ...............................................................
AND
REPLACEMENT
..................................................................
viii
6-1
6-1
6-1
6-1
6-1
6-2
6-5
6-5
6-5
Page 10
CONTENTS (Cont)
Page
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
APPENDIX
Figure No.
1-1
1-2
1
'1
1.
'.-'
1-4
1-5
1-6
1-7
1-8
1-9
1-10
2-1
2-2
2-3
2-4
2-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
Drive
A RX02
Replacement
Front
Drive
Drive Belt
Handle
Motor
Replacement
Quick Check
SUMMARY
Replacement
Procedure
Replacement
Procedures ............................................................ 6-10
For
Belt
on
...................................................................... 6-8
Procedure
Procedures
.......................................................... 6-8
.......................................................... 6-9
Pulleys ................................................................. 6-10
FIGURES
Title
Floppy
Front
Interface
Top
Underside View
Diskette
Flux
FM
Track
Sector
RX02 Outline
Cabinet
RX02
RX02 Unpacking ................................................................................................. 2-8
RX02
LCD
Command
Command
Command
Error
RX2TA
RX2SA
RX2DB
RXES
RX2ES
RX8E
RX8E
RX8E
Disk
Configuration
View
of
the
Floppy
~,,1odules
View
of
Media
................................................................................................
RX02
................................................................................ , .............. 1-6
of
Drive ...................................................................................... 1-7
..................................................................................... " ............ 1-10
Reversal Pattern s for
Versus
MFM
Format
Format
Encoding
(Each
Track)
(Each Sector) ...............................................................................
Dimensions
Layout
Rear
Cabinet
Word
Code
Format
Format
Format
Format
Format
Write/Write
Empty
Fill Buffer
Dimensions
View ............................................................................. " ................... 2-3
Mounting
Format
Word
Register
Register
Register
(RX8E)
Format
Format
Format
Format
(RX8E/RX28)
(RX8E/RX28)
(RX8E/RX28)
(RX8E)
(RX28) ................................................................ , ....................... 4-8
Deleted
Buffer Example ............................................................................. 4-17
Example
................................................................................. .1-3
Disk System .................................................................
FM
...........................................................................
............................................................................... 1-12
................................................................................ 1-12
...................................................................................
................................................................................. 2-2
Information
.................................................................
................................................................................. 4-2
(RX28)
......................................................................... 4-3
(RX8E)
(RX28F)
(RX8E/RX28A)
..................................................................... 4-4
................................................................... 4-5
......................... , ........................... .4-6
........................................................................... 4-7
............................................................................ 4-7
........................................................................... 4-7
.................................................................. , ...................... 4-7
Data/Read
Example ............................................... 4-15
................................................................................. .4-18
Page
1-4
i-5
1-11
1-13
1-1
1-9
ix
Page 11
FIGURES (Coot)
Figure No.
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
~
1 1
J-ll
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
RX28
Write/Write
Deleted
Title
Data/Read
Example ............................................... 4-19
Page
RX28 Fill Buffer Example .................................................................................. 4-21
RX28 Empty Buffer Example ............................................................................ .4-22
RXCS
RXTA
RXSA
RXDB
RXES
RXII
RXII
RXII
RX2CS
RX2TA
RX2SA
RX2WC
RX2BA
RX2 ES
RX211/RXV21
RX211/RXV21
RX02 System Block
Omnibus
Unibus
LSI-II
Interface
ILCPU
Read/Write
RX8E/RX28
RXII
RXV
RX211 Interface l\1odule Block
RXV21 Interface
ILCPU
Arithmetic and Logical Instruction
Branch Instruction
I/O
JMP / JSR
Initialize
Find
Read Address Mask
Read
Format
Format
Format
Format
Format
/RXVII
/RXVII
/RXVII
(RXll/RXVll)
(RXl1/RXVll)
(RXl1/RXVll)
(RXll/RXVll)
(RXl1/RXV
Write/Write
Empty Buffer Example ................................................................ 4-34
Fill Buffer Example ...................................................................... 4-35
Format
Format
Format
Format
and
RX2DB
Format
to
to
Bus
to
(RX211 / RXV21 ) ..................................................................... .4-40
RX8E/RX28
RXll/RX211
to
RXVll/RXV21
ILCPU
Controller
Electronics to Drive Signals ............................................................ 5-10
Interface Block
Interface Block
11
Interface Biock
Controller
Instruction
Instruction
Routine
Header
Sector
Subroutine
Subroutine
.......................................................................... 4-25
......................................................................... 4-26
.......................................................................... 4-26
........................................................................ .4-27
11
) ......................................................................... .4-27
Deleted
(RX211/RXV21)
(RX211/RXV21)
(RX211/RXV21)
(RX211/RXV21)
Format(RX211/RXV21)
Write/Fill
Read/Empty
Diagram
Buffer
Example
Buffer Example .................................................... 4-47
............................................................................... 5-2
Interface Signals .......................................................... 5-2
Interface Signals ............................................................ 5-4
Interface Signals ................................................... 5-5
Controller
to
Read/Write
Signals ................................................................... 5-6
Electronics Signals ............................................ 5-8
Diagram
Diagram
Diagram
.......................................................................... 5-15
........................................................................
Diagram
Module
Block
Format
Format
Flowchart
Block
Diagram
Diagram
....................................................................... 5-26
................................................................................. 5-28
...................................................................................... 5-28
Format
............................................................................ 5-28
............................................................................... 5-33
Flowchart
Subroutine
Flowchart ......................................................... 5-36
Flowchart.
Data/Read
Example .................................. 4-32
...................................................................... 4-37
...................................................................... 4-39
..................................................................... .4-39
..................................................................... 4-39
................................................. 4-40
....................................................... .4-46
...............................................................
.................
""
" .....................................
5-11
5=
18
5-21
........................................................... 5-23
Format
........................................................ 5-28
.................................................................... 5-34
.................................................................... 5-39
x
Page 12
FIGURES (Coot)
Figure No.
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
6-1
h_'"
A-I
Title
Write/Write
Read
Error
Fill/Empty
Select Drive and Find
Decode
Maintenance Read
Get
Parameter, Step
Subroutines Flowchart ....................................................................................... 5-49
Find Sector, Send
Flowchart Subroutines ....................................................................................... 5-50
Maintenance Check Ready Subroutine Flowchart ..............................................
Read/Write
Data
SYNC
Disk Drive Mechanical System ........................................................................... 5-56
Drive Mechanism ................................................................................................ 5-56
Centering
Positioning Mechanism ...................................................................................... 5-58
RX02
Component
Drive
~~1otor
RX02
System Interconnection Diagram .............................................................. A-4
Sector Subroutine Flowchart. ......................................................... 5-40
Register
Buffer Routine Flowchart ................................................................ 5-43
Command
Electronics Block Diagram ............................................................. 5-53
Timing
Cone
Positioning
and
Set Density Subroutines
Track
Routine
Status
Head,
Word
Diagram
and Drive
Location Diagram ................................................................... 6-6
Subroutines
Flowchart ............................................................... 5-46
and
Check Ready Subroutines Flowchart. .................. 5-48
Wait,
12,
Hub
Diagram
Wait
Send
............................................................................. 5-54
.......................................................................... 5-57
........................................................................ 6-9
Word
Flowchart.
Run,
8,
and
Get
Command
Flowchart.
.......................................... 5-44
Write Zeros
............................. 5-42
and
Get
Word
Page
5-51
Table No.
1-1
2-1
2-2
2-3
3-1
4-1
5-1
6-1
6-2
6-3
TABLES
'"
....... .3-3
Page
Title
Data
Address
RX02 Configurations ........................................................................................... 2-5
Controller Configuration Switch Positions .......................................................... .2-6
Interface
Operator
Device Code Switch Selection ............................................................................... 4-2
C Line Transfer
Troubleshooting
Error
Code
M7745 Connectors
Mark
Code
................................................................................... 1-14
Code/Jumper
Troubleshooting
Control
Chart
Probable Causes ................................................................................ 6-4
Configuration ................................................................ 2-10
Guide
Signals ......................................................................... 5-13
......................................................................................... 6-2
..
, ............................................................................................ 6-7
..............................................................
xi
Page 13
The
manual
RX02 Floppy Disk System in any
the
PDP-8,
and maintenance information for the
with the
is
intended to provide the user with sufficient information to correctly set up and operate
PDP-II,
PDP-8,
or LSI-II computers. The manual presents general, installation, user, programming
PDP-II,
and LSI-II computer systems.
PREFACE
of
the various configurations that are available for use with the
RX02 Floppy Disk System and the interface options associated
Page 14
GENERAL INFORMATION
1.1
INTRODUCTION
The RX02
flexible diskettes with preformatted industry standard headers.
PDP-8, a
puter being used
is
a low cost, random access mass memory device
PDP-II,
or
an
and
either single
LSI-II system. Various interface modules are selected according to the com-
or
double density recording.
that
CHAPTER
stores
The
data
in fixed length blocks on
The
RX02 interfaces with either a
various configurations are:
1
Designation
RX8E
RX28
RXII
RX211
RXVII
RXV21
The
RX02 consists
programmed controller module, and a power supply, enclosed in a rack-mountable,
cooled chassis. A cable
interface module,
varies according
512K 8-bit bytes
retrieved.
12-bit words (PDP-8) can be stored and retrieved.
when single density data recording
for each drive.
For
of
one
or
an
LSI-It
to
the configuration.
of
data (PDP-8,
each drive system using single density recording, up to 256K 8-bit bytes
Computer
PDP-8
PDP-8
PDP-II
PDP-II
LSI-II
LSI-ll
The single density recording configurations RX8E,
RXII,
Floppy Disk System
module has been switched to be compatible with
these configurations. (See
is
and
RXVII
or
two flexible disk drives, a single
included for connection to either a PDP-8 interface module, a
interface module. The amount
For
PDP-It,
is
used.
Interface
Module
M8357
M8357
M7846
M8256
M7946
M8029 Single
NOTE
are compatible with the RXOI
when
each drive system using double density recording, up to
LSI-ll)
If
two drives are used, the recording density can be different
the M7744 controller
Table 2-2.)
or
256K 12-bit words (PDP-8) can be stored and
The
RX02 interfaces with IBM-compatible devices
Recording
Density
Single
Single
Single
Single
Single
read/write
of
data
that
or
Double
or
Double
or
Double
electronics module, a micro-
can be stored on the RX02
10-1/2 inch, self-
PDP-II
of
data
or
128
For
single
or
double density recording, the RX02
8),
an M8256 interface module
ules convert the
the interrupts to the
and the host computer. Each interface module
RX02
I/O
CPU initiated by the RX02 and handles the data interchange between the RX02
(PDP-Il),
bus to the bus structure
or
an M8029 interface module (LSI-II). The interface mod-
is
used with either an M8357 interface module (PDPof
the computer being used. Each module controls
is
powered by the host processor.
1-1
Page 15
In addition, the RX02
the
RXOI. The interface module used
is
used for single density recording when it
is
either an M8357 (PDP-8), an M7846 (PDP-II), or an M7946
is
configured to be compatible with
(LSI-II).
To
record
or
retrieve data the RX02 performs implied seeks. Given an absolute sector address, the
RX02 locates the desired sector and performs the indicated function, including automatic head position verification and hardware calculation and verification
character. The
CRC
character that
is
read
and
generated
of
the cyclic redundancy check (CRC)
is
compatible with IBM 3740 equipment.
1.2 GENERAL DESCRIPTION
An RX02 Floppy Disk System consists
of
the following components:
M7744 Controller Module
M7745 Read/Write Electronics Module
H771-A, -C,
RX02-CA Floppy Disk Drive (60 Hz max
RX02-CC Floppy Disk Drive (50
or
-D Power Supply
Hz
max
of
of
2)
2)
One interface module
M8357
M7846
(PDP-8, Programmed
(PDP-II,
M7946 (LSI-II, Programmed
All components except the interface modules are housed in a 10-1/2 inch rack-mountable box.
is
used:
Programmed
I/O)
I/O)
I/O)
M8256
(PDP-II
with DMA)
M8029 (LSI-II with DMA)
The
power supply, M7744 module, and M7745 module are mounted above the drives. Interconnection
from the
Figure I-I is a configuration drawing
with DMA; part B shows the configuration for all
shows the configuration for a bus interface (programmed
front
RX02 to the interface is with a 40-conductor BC05L-15 cable
of
the system:
part
A shows the configuration for a bus interface
Omnibus interfaces (programmed I/O);
I/O)
that
view
of
a dual drive system.
is
RXOI
of
standard length
compatible. Figure
(15
part
1-2
ft).
C
is
1.2.1 Interrace Modules
The interface modules plug into a slot on the bus for
1-3
shows the outline
1.2.2 Microprogrammed
of
the various modules
Controiier
and
The M7744 microprogrammed controller module
1-4.
The
M7744
is
hinged on the left side and lifts up for access to the M7745 read/write electronics
module.
PDP-8,
areas
is
located in the RX02 cabinet as shown in Figure
of
interest
PDP-II,
on
and LSI-II computers. Figure
each module.
.
a
1.2.3 Read/Write Electronics
is
The M7745 read/write electronics module
located in the RX02 cabinet as shown in Figure
1.2.4 Electromechanical Drive
A maximum
of
two drives can be attached to the read/write electronics. The electromechanical drives
are mounted side by side under the read/write electronics board (M7745). Figure
view
of
the drive showing the drive motor connected to the spindle by a belt. (This belt and the drive
on
the
50
Hz
and
60
Hz
pulley are different
units; see Paragraph 2.1.3.2 for complete input power
modification requirements.)
1-2
1-5
is
1-4.
an underside
Page 16
POWER
SUPPLY H771
DISKETTE
DISKETTE
JlCPU
CONTROLLER
M7744 *
M8029
BUS
INTERFACE
M8256
UNIBUS
INTERFACE
L
I S I
I
I B I
I U I
I S I
UI
NI
I .
I B I
lui
S
LSI-l1
PDP-11
POWER
SUPPLY H771
DRIVE
DRIVE
# 0
# 1
DISKETTE
IA
7015-580
B.
Omnibus Interface, Programmed
DISKETTE
A. Bus Interface with
BC05L-15
JlCPU
CONTROLLER
M7744 *
JlCPU
CONTROLLER
M7744 *
DMA
OR
--
I/O
M8357
OMNIBUS
INTERFACE
____
M8357
OMNIBUS
INTERFACE
M7846
UNIBUS
INTERFACE
....-1
o
MI
~
B I
I U I
S
0
M
I N I
I I I
I
~
I S I
U
N I
I
I I
I B I
U
I S I
I
PDP-8
PDP-8
I
I
PDP-11
POWER
SUPPLY H771
C. Bus Interface, Programmed
Figure
I/O
(RXOI
Compatible)
I-I Floppy Disk Configuration
1-3
M7946
BUS
INTERFACE
L I
I
I s I
I I I
B .
I U I
s
LSI-11
Page 17
_ama
RX02
~
•
II
l[
l
I
I
/
Figure
1.2.5 Power Supply
The H771 power supply is mounted
H771-A
at
is
rated
50
Hz
+ 1/2
90-120 Vac
100-128 Vac
at
60
Hz
Hz
over four voltage ranges:
}
1-2
±1/2
Hz
over a voltage range
3.5 A circuit breaker; H771-C
Front
at
the rear
View
]
I[
l
of
the Floppy Disk System
of
the
RX02 cabinet as shown in Figure
of
90-128 Vac. The H771-C and
,
,
J
I
J
\
MA-1824
-D
1-4.
The
are rated
184-240 Vac
200-256 Vac
Two configuration plugs are provided
applicable
1.3
The optional interface modules
are listed in Paragraphs
selected
IBM system
M7744 controller module's configuration switch
RXO
The
module configuration switch is positioned
figurations.
to
the H771-A.
OPTION DESCRIPTION
is
determined by the computer being used and whether the data interchange
3740 compatible devices
l.
The RX02 interfaces with IBM compatible devices when single density
RX02 interfaces with
}
1.75 A circuit breaker; H771-D
to
adapt
that
are used to interface the RX02 with a PDP-8,
1.1
and
1.2. (Each module
or
DIGITAL
DIGITAL
system double density recording devices when the controller
to
be
the H771-C
is
system double density devices. Also, when an
is
set
compatible with RX28, RX211, and RXV21 con-
1-4
or
-D
to each voltage range. This
PDP-II,
powered by the
to
be compatible, the RX02 can operate as an
host
processor.) The module
data
recording
and
LSI-II
is
between either
is
is
not
used.
Page 18
BC05L-15
CABLE
W7
.....
W8
.....
W16 ....
W1D
....
Wll
....
W12
REV B
CONNECTION
W13
W14
W9
W17
W15
..
W1.
W2
W4
....
....
BC05L - 15
CABLE
}~
CONNECTION
DEVICE CODE SWITCH
PRIORITY
PLUG
BC05L - 15
CABLE
CONNECTION
r7~
...
W3
W5
W6
---,
I
I
M8357
E33
MODULE (RX8E
OR
RX28)
M7846
MODULE
(RXll)
~
ElCOoL-l b
CABLE CONNECTION
.......
.......
·······W3
.......
·······W5
BC10L-15
CABLE CONNECTION
W7
W8
W9
....
.
Wl0
....
.
Wll _ ...
.
W12
....
.
M7946 MODULE
Wl
W2
W4
Wl
W2
W3
W4
W5.
W6
....
....
....
....
...
.
.
.
.
{RXVlll---'
---1
ADDRESS
SWITCH
OFF
= 1
BC05L -
15
CABLE CONNECTION
I
M8256 MODULE {RX2111
BC05L-
15
CABLE
CONNECTlO",!
V2
~r(A3
l~
~!
ADDRESS.......-I
JUMPERS
M8029 MODULE (RXV21)
L:;t
V8
~
·All
0
00/
00
__
_
MA-2496
Figure
1-3
Interface Modules
1-5
Page 19
M7745
~
REAO/'NRITE
ELECTRONICS
MODULE
MA-1751
For
1.3.1 Operation
1.3.1.1
ule converts the RX02
initiated by the RX02, controls
I/O,
1.3.1.2
converts the RX02
the
RX02
PDP-8
and
handles
PDP-II
RX02, decodes
and
the
host
Single Density Recording Only (RX8E,
Operation -
input/output
Operation -
I/O
Unibus
CPU
The
I/O
bus
The
bus to
addresses for register selection,
main memory
Figure 1-4
RX02 connects
to
PDP-8 family
data
interchange between the RX02
transfers used for maintenance status conditions.
RX02 connects
PDP-II
Unibus structure. It controls interrupts
by
Top
View
to
the M8357 Omnibus interface module. This mod-
Omnibus
to
the M7846 Unibus interface module. This module
programmed
1-6
of
RX02
RXll,
structure. It controls interrupts
and
I/O.
RXVll)
and
handles
the host
data
to
the
CPU
CPU
by programmed
to
the
CPU
initiated by
interchange between the
Page 20
DRIVE
BELT PULLEY
AC
DRIVE
MOTOR~ITIrGtJ1rtrr-4--
AC
POWER
CONNECTOR"
DC
STEPPER
MOTOR
MOTOR
______
DRIVE SPINDLE
l
Figure
1.3.1.3
module converts the
initiated
the
LSI-II
by
Operation - The RX02 connects to the M7946
RX02
I/O
the RX02, decodes LSI-II bus addresses for register selection,
RX02 and the host CPU main memory by programmed
1-5
Underside View
of
Drive
bus to the LSI-II bus structure.
I/O.
1.3.2 Operation For Single or Double Density Recording (RXl8,
1.3.2.1 PDP-8 Operation - The
ule converts the RX02
initiated
and handles
1.3.2.2
converts the
the
between the
1.3.2.3
by
the RX02, controls transfer
input/output
PDP-II
RX02
RX02, decodes Unibus addresses for register selection, and initiates
RX02 and the host CPU main memory.
LSI-II
module converts the
initiated
by
the RX02, decodes LSI-II bus addresses for register selection, and initiates
I/O
transfer used to test status conditions.
Operation - The RX02 connects to the M8256 Unibus interface module. This module
I/O
bus to
Operation - The RX02 connects to the M8029 LSI-II bus interface module. This
RX02
to transfer data between the
RX02 connects to the M8357 Omnibus interface module. This mod-
bus to PDP-8 family Omnibus structure.
of
data between the RX02 and host
PDP-II
I/O
RX02 and the host
Unibus structure.
It
controls interrupts to the
bus to the LSI-II bus structure. It controls interrupts to the
CPU
main memory.
MA-1850
LSI-ll
It
RXlII,
bus interface module. This
controls interrupts to the CPU
and
transfers data between
RXV21)
It
controls interrupts to the
CPU
by programmed
CPU
initiated by
NPR
requests to transfer data
NPR
requests
CPU
I/O,
CPU
1-7
Page 21
1.4 SPECIFICATIONS
System Reliability
Minimum number
lutions per track
Seek error rate
Soft data error rate
Hard
data error rate
Drive Performance
of
revo-
The above error rates only apply to
media that is properly cared for. Seek error and soft
data errors are usually attributable to random effects
in the head/media interface, such as electrical noise,
dirt, or dust. Both are called
ror is recoverable in
"Hard"
ries should be preceded
3 million/media (head loaded)
1()6
1 in
1 in
1 in
errors cannot be recovered. Seek error ret-
seeks
1()9
bits read
12
10
bits read
NOTE
10 additional tries or less.
by
or
written
or
written
DEC
"soft"
a recalibrate.
errors if the er-
approved
Capacity
Per diskette
Per track
Per sector
Data
transfer rate
Diskette to controller buffer
Buffer to
Track-to-track move
Head settle time
Rotational speed
Recording surfaces per disk
Tracks per disk
Sectors per track
Recording technique
Bit density maximum on
inner track
Track density
A verage access
CPU interface
Recording
FM
MFM
FM
MFM
FM
MFM
4
~s/data
2
~s/data
1.2
~s/bit
PDP-8 interface can operate in 8- or 12-bit modes
under software control.
6 msitrack maximum
25
ms maximum
360 rpm
1
77
(0-76)
26 (1-26)
Double frequency (FM)
3200 bpi
48
tracks/inch
262
ms, computed as follows:
r
77
_ 6,656
bit (FM)
bit
NOTE
±
2.5%;
or
or
(FM)
Seek
tks/3
8-bit bytes
256,256
512,512
3,328
128
256
(MFM)
166
(0-1148)
(0-328)
or
modified
A
X
,
6ms
12-bit words
128,128
256,256
1,664
3,328
64
128
ms/rev nominal
or
modified M
(MFM)
Settle
~
+
25ms
FM
+
Rotate
~
166
ms/2 =
262
ms
1-8
Page 22
Environmental Characteristics
Temperature
RX02, operating
RX02, nonoperating
Media, nonoperating
Media temperature must be within operating temperature range before use.
Heat
Dissipation (RX02 System)
150 to
320 C (590 to
maximum
-350 to
-350 to
Less
+600 C
+520 C
than
temperature
(-300 to
(-300 to + 125
NOTE
225
Btu/hr
900 F)
ambient;
gradient =
+ 140
0
0
F)
F)
110 C/hr
(20
0
F
/hr)
Relative humidity
RX02, operating
RX02, nonoperating
Media, nonoperating
Magnetic field
Interface modules
Operating temperature
Reiative humidity
Maximum
wet
Minimum dew
F1ectrical
Power consumption
RX02
PDP-II
interface (M7846,
M8256)
PD
P-8 interface (M 8357)
LSI-II
interface (M7946,
M8029)
AC
power
bulb
point
250 C (77
20 C (36
20%
5%
10%
Media
greater
50
to
10%
0
32
0
F)
0
F)
to
80% relative humidity
to
98% relative humidity
to
80% relative humidity
exposed
may
500 C
to
~O%
C (900 F)
20 C (360 F)
5 A
at
+5
Vdc,
31
W
1.8 A at
1.5 A at
1.8 A
4 A
2 A
at
at
115
at
230 Vac
5 Vdc
5 Vdc
5 Vdc
Vac
maximum wet bulb
minimum dew
to
a magnetic field strength
lose
data.
(410 to
122
25
W; 0.14 A
0
point
F)
at
(no
condensation)
-5
Vdc, 0.7 W;
of
50 oersteds
1.3
A t
+24
or
Vdc,
1.5
SYSTEMS COMPATIBILITY
This section describes the physical, electrical,
with IBM system
3740 devices
and
for
and
logical aspects
data
interchange with
of
compatibility for
double
1.5.1 Media
The media used on the RX02 Floppy Disk system is compatible with
and
is
ment
shown in Figure 1-6.
disk architecture, resulting in a flexible oxide-on-mylar surface.
envelope with a hole for the
index mark. The envelope
to
the
supplied
customer preformatted
is
The
read/write
"diskette"
head, a hole for
media was designed by applying
lined with a fiber material
and
pretested.
1-9
The
the
drive spindle hub,
that
cleans
the
density devices.
the
IBM
3740 family
tape
diskette
is
encased in a plastic
and
a hole for
diskette surface.
data
interchange
technology
The
of
equip-
the
hard
media is
to
Page 23
INDEX
....
HOLE
______
__+_
REGISTRATION
HOLE
....
-------+-HEAD
Figure
1-6
Diskette Media
1.5.2 Recording Scheme
There are two recording schemes used in the
(MFM). The
system
Figure
3740 devices. (When this recording scheme
t -t
density data recording which
FM
part
C, the RX02
scheme is used for single density data recording which is compatible with IBM
is
compatible with the RXOl.) The
is
compatible with
RX02: double frequency (FM) and modified Miller code
is
used and the RX02
DIGITAL
double density devices but
patible with other manufacturers.
1.5.2.1 Double Frequency (FM) tween bits
reversal every four
of
a constant clock stream. The clock stream consists
J.l.S
(Figure i-7). A data Hone" is indicated by an additional reversal between docks
For
the double frequency recording scheme data
(Le., doubling the bit stream frequency; hence the name). A data
between clocks.
READ/WRITE
APERTURE
MA-1750
is
configured as shown in
MFM
of
"zero"
scheme
a continuous pattern
is
indicated by no flux reversal
is
used for double
is
not
is
recorded be-
of
one flux
com-
A continuous stream
bit stream, and a continuous stream
"IF"
or
as a
fundamental frequency bit stream.
1.5.2.2 Miller Code
data stream. The data stream consists
"zero."
A clock is recorded only between
data fields map into a preamble
of
ones, shown in the bottom waveform in Figure
of
zeros, shown in the top waveform in Figure
(MFM) -MFM
and
or
Miller code encodes clocks between data bits
of
flux reversals for a data
data
"zeros." Because it
ID
mark, the
MFM
encoding is modified slightly to prevent a
"one"
false header from being detected within a double density data field.
NOTE
De
modified
other manufacturers.
MFM
encoding is not compatible with
•
1-10
1-7,
would appear as a
1-7,
would appear
of
a continuous
and no flux reversal for a data
is
possible to have double density
"2F"
Page 24
--1
0'
,
0
0
I
I
I
--+l4~sec
I
I+-
0
0
0 0
ALL
ZEROS
PATTERN
0
0
0
0
0
0
0
0 0
I
I
I
0
CHANGING
PATTERN
0
1
0
ALL
ONES
PATTERN
CP-1506
Figure
The encoding algorithms for implementing modified
Encoding Algorithm
On
0
1
#1
(MFM
Data
Dn+
0
0 1
or
1
1-7
Flux Reversal Patterns for
Miller
Code
Algorithm)
0 1
I
Encoding Algorithm
On
#2
I
(MFM
Dn+
Modified Algorithm)
Data
1·
Dn+2 Dn+3
o
FM
MFM
are:
Encoded
On
0
Data
I
Cn
0
0 0 I
1 0 1
Dn+4
Cn+3
Dn+4
On + 1
0
0
Dn+5
o
Cn+4
Dn+5
o
The decoding algorithm used in
o
On
o
0 0 0
0 1
1
0
1 0
o
data
separation is:
Encoded
Cn
0
0
o o
On + 1
o o
Decoded
On On + 1
1
0 0
0
1 0 1
1
1-11
1
1 1
I
0
0
Page 25
Figure
MFM code, and modified
1-8
shows the waveforms that are generated for a data stream
MFM
code are used.
of
zeros and ones when FM code,
1.5.3 Logical Format
Data
is
recorded on only one side
"tracks" numbered 0-76. Each track
sector contains two major fields: the header field and the data field (Figure
of
the diskette. This surface
is
divided into
26
is
divided into
sectors numbered 1-26 (Figure
77
concentric circles or
1-9).
1-10).
Each
DATA
F M
MFM
MODIFIED
MFM
DATA
MODIFIED n n
MFM
0
,
I
I
I
I
~
I
I
I
--.J
*
001 1 101
I I I I I I I I I I I I I
I I I I I I I I I I I I I
I I I I I I I I I I I I I
..J
U
WHERE/DATA
0
I
I
I
L..J
1 1
r1
* =
Figure
1000
n r
W U
2/DATA
1-8
FM
1111114~--MODIFYING
ALGORITHM
Versus
MFM
Encoding
---4
..... 1
'""--
.....
MA·1856
L
I
I
I
r
SECTOR PRE-IN
#
26
1
----'----'
.r
,
HARD
INDEX
MARK
l
J
DEX
GAP
~320
B
YTES
I
)
SOFT
INDEX
4 ROTATION
Figure
L.E.D. TRANSDUCER OUTPUT
SECTOR
#1
SECTOR
#2
t
MARK
1 BYTE
1-9
Track Format (Each Track)
1-12
SECTOR
#3
SECTOR
#4
\\
1
"
CP·1507
Page 26
W
....J
II>
alO
2w
«I-
1->-
~al
a..~
II
II
INTERSECTOR GAP
BYTES
26
1'5 OR 0'5
o
Lti
-en
u.w
(.)1z>-
>-al
en
en
0 2
to
~
a:
«
en
en
w
a:
Ow
01«>-
e~
al
en
en
w
a:
o
o
«
G~
«>-
a:al
I-~
HEADER
FIELD
en
en
w
a:
o
o
«
a:
w
01-
1->-
~al
en~
_ w
'(nl-
->-
;'al
-
-----'"")
HEADER
CRC
2
BYTES
DATA
II
"
r-----------II-~~----------~
o
«
....J
I-
W
«
128
U.
o
10
DATA
OR
256
10
(MODIFIED)
DATA
I.
BYTES
BYTES
FIELD
OF
OF
FM
MFM
DATA
CRC
2
BYTES
I"
WRITE
FOR
DATA
"
GATE
WRITE
OF PRECEEDING
FIELD
TURN
L
PREAMBLE
OFF
I
~
t
Figure
1.5.3.1 Header Field Description -
information
its preamble
1
~
.
2.
3.
and
is preceded by a field
are
always recorded in
Byte
~~
o.
bits)
that
FE
hex, clock =
Byte
No.2:
contains
Byte
No.3: -Zeros
1:
ID
Address r"lark -
is decoded by the
C7
hex.)
Track
track
Address - This is
address
information
+-
ROTATION
1-10 Sector
The
header
of
at least six bytes
FM.
Thi~
i~
controller
the
to
"
11
BYTES
--1.J
IDGAP
"5
OR 0'5
Format
field is
a uni4 ue stream
to
identify
L
(Each
broken
of
Sector)
into
zeros for synchronization.
of
the
beginning
absolute (0-1148)
identify its location
II
L--
6
BYTES
WRITE
GATE
FIELD
TURN
OF
NEXT
FOR
DATA
WRITE
seven bytes (eight
flux reversais
of
the
header
binary
track
on 1 of
the
ON
bits/byte)
The
header
(not
a string
field.
(Data
address. Each
77 tracks.
MA-1827
and
of
data
sector
of
=
4.
Byte
No.4:
Sector Address - This
contains sector address
is
no
5.
6,7.
sector
Byte
No.5: -Zeros
Bytes
No.6
O.
and
7:
CRC
each sector from the first five
1.5.3.2 Data Field Description -
depending
the
header
on
the recording scheme.
field (Figure 1-10).
1.
Byte
No.1:
unique because
beginning
RX02 can identify
a unique address
is
the first byte
Data
or
it
of a data
mark
of
Deleted
contains missing clocks. It
field.
and
each
is
information
- This is
the
header
The
data
field contains either
This
field is preceded by a field
Data
Address
The
deleted
write deleted
the absolute
to
identify its circumferential position
cyclic
redundancy
bytes using the
mark
data
mark
data
marks
binary
sector address (1-328). Each sector
check
IBM
character
3740 polynomial.
13110
or
25910
of
zeros for synchronization
- This byte is always recorded in
is
decoded by the controller
is
not
under
used during
program
normal
control
for each density as shown in the following table.
data
field.
1-13
on
a track.
that
is calculated for
bytes
of
information
to
identify the
operation
as required.
One
of
these
FM
There
There
and
and
but
the
marks
is
is
Page 27
Table
1-1
Data Address
Mark
Code
Hex Byte
Mark
Density
FM
Data
FB C7
Clock
Data
C7
C7
C7
the data field and it can be
128
or
25610
10
DELETED
DATA
2.
Bytes
No.2:
-129 (FM) or -257
recorded in either FM
upon encoding) 8-bit bytes
MFMmod.
FM
MFMmod.
or
MFM
of
(MFM
(modified).
information.
FD
F8
F9
modified) - This
It
is
used to store
is
NOTE
Partial data fields are not recorded.
3. Bytes No.
calculated for each sector from the first
ard polynomial division algorithm designed to detect the types
130
and
131
or
258
and
259
- These bytes comprise the CRC character that
129
or
257
data field bytes using the industry stand-
of
failures most likely to
occur in recording on the floppy media. These bytes will be recorded with the same encoding
scheme as the data field.
(depending
is
1.5.3.3 Track Usage - In the IBM 3740 system, some tracks are commonly designated for special
purposes such as error information, directories, spares, or unused tracks. The
recreating any system structure through the use
of
make use
all the available tracks as data tracks. Any special
of
special systems programs, but normal operation will
file
structures must be accomplished
RX02
is
capable
of
through user software.
1.5.3.4
CRC
write operation and checked to ensure all bits were read correctly during a read operation. The
character
eRC
Capability
~
Each sector has a two-byte header
character to ensure data integrity. The
is
the same as that used in IBM 3740 series equipment.
CRC
characters are generated
eRe
character and a two-byte data
by
the hardware during a
eRe
1-14
Page 28
2.1
SITE PREPARATION
This chapter contains information
testing
configurations that are available.
of
the RX02 Floppy Disk System. Information
CHAPTER 2
INSTALLATION
that
is required for site preparation, unpacking, installation, and
is
also provided
to
identify the various system
2.1.1
The RX02
ration cabinet. This rack-mountable version is approximately
(19
Space
is
a cabinet-mountable unit that may be installed in a standard Digital Equipment Corpo-
inches) and
42
cm deep (16-1/2 inches) as shown in Figure 2-1.
Iluimll~mm~~lmllllllllglllllll~~1
19"
(FRONT VIEW)
17.0"
(4302Cmll
0
0
--
--
--
--
--
--
--
--
(FRONT)
.. (48.3cm) •
I
I~
-
0
28
cm high, (10-1/2 inches),
Ii
I
10.5"
~l
I
SEE
NOTE
TR
ACK
I
0
,INSIDE
CIl :J
48
cm wide,
26.5"
I:
NOTE: DUST COVER ATTACHED TO CABINET NOT RX02
Figure
2-1
RX02 Outline Dimensions
(66.3cm)
(SIDE VIEW)
2-1
..
MA-1825
Page 29
When the RX02
of
approximately
is
mounted in a cabinet (Figure 2-2), provision should be made for service clearances
56
cm (22 inches)
at
the front
extended or the cabinet rear door opened.
and
rear
of
the cabinet so that the RX02 can be
REMOVABLE_
END
PANEL
CABLE
CASTER
RADIUS
(6.12 em)
(4) CASTERS
ACCESS-~I+--i"
S~IVEL
2\
132
WINGING
\
-=:::::....... -::--=- -
q "
1/
~
~
I \
DOOR
R.H. OR L.H.
......
//
\
:::::;~-::;...-
~"
/.
:;;"
..........
:;..-
"
"
I
rt'~'
~~~~~~~~f-
....
,
r-
I
I
I
I
+
21
11/16
(54.87em)
RX02
EXTENDED
FROM
i I
L-
______
CABiNET
SWINGING
FRAME
'\
DOOR R.H. OR
~\
'\
\
--------+-
t'
I
I
I
J
____
MOUNTING
REMOVABLE
END
PANEL
-'--_
L.
H.
187132"
(46.35em)
48
( 122.47em)
3.0"
(76.2em)
7
132"
CABINET
(FLOOR
71
LINE
7/16"
(182.28 em) HIGH
TO
CABINET
TOP)
Figure 2-2 Cabinet Layout Dimensions
2.1.2 Cabling
The standard interface cable provided with an RX02 (BC05L-15)
ing
of
the RX02 in relation to the central processor should
RX02 should be placed near the control console
The
access to load
cord
is
about 2.7 m (9 ft) long.
or
unload disks. The position immediately above the
be
planned to take this into consideration.
or
keyboard so that the operator
2-2
is
4.6 m
(15
CPU
ft)
in
length; the position-
will
have easy
is
preferred. The ac power
Page 30
2.1.3 AC Power
2.1.3.1 Power Requirements - The
The
60
Hz version
operating. The
will
50
Hz version
operate from 90-128 Vac, without modifications, and
fication/modification to ensure that the correct voltage option
90-120 Vac and 184-240 Vac
200-256 Vac
will
use
less than 2
will
power from an ac source (e.g.,
2.1.3.2 Input Power Modification Requirements - The
power supply and
power source
will
operate on 90-128 Vac, without modification. To convert to operate on a
in
the field, the H771-A supply must be replaced with an H771-C
RX02
will
operate within four voltage ratings and
is
designed to use either a 60 Hz
is
use less than 4 A operating. The voltage ranges
A.
Both versions
861
power control) that
of
the RX02
is
60
will
controlled by the system's power switch.
Hz version
the drive motor belt and drive motor pulley must be replaced (Figure
90-120
power source.
ranges, the power harness and circuit breaker must be changed.
Vac
or 100-128 Vac power source. The H771-0 operates on a 184-240 Vac
To
convert the H771-C to the higher voltage ranges
or
See
jumper and circuit breaker.
~~~~_
.... _ ...
~
__
... _ ...
JUMPER
_.~._
.... _ ...
~
__
..
_._L_
.....
__ .........
__
P1
.. _ ..... _ ..
or
a 50 Hz power source.
will
use less than 4 A
will
require field veri-
selected. The voltage ranges
of
100-128 Vac and
of
be required to receive the input
of
the RX02 uses the H771-A
50
Hz
or
-0
(Figure
1-5).
The H771-C operates on a
or
1-4)
and
200-256 Vac
the H771-0 to the lower voltage
Figure
.
2-3
for the appropriate
SHIPPING
RESTRAINT
VOLTAGE
90-120
100-128
184-240
200-256
(RED)
(VAC)
JUMPER
70-10696-02
70-10696-01
70-10696-04
1 0696-03
70-
Figure
2-3
POWER
CIRCUIT
3.5 A, 12-12301-01
3.5 A, 12-12301-01
1.75
1.
RX02 Rear
2-3
PLUGS
BREAKER
A,
12-12301-00
75 A, 12-12301-00
View
MA·1866
Page 31
2.1.4 Fire and Safety Precautions
The
RX02 Floppy Disk System presents no additional fire
system. Wiring should be carefully checked, however, to ensure
and
added load
2.2
CONFIGURATION GUIDELINES
The
most common RX02 Floppy Disk System configurations available are listed in Table 2-1. Each
for any contemplated expansion.
interface module listed in the table plugs into a computer bus; it
that
there
is
computer so
interface module and the
cable which
is
4.6 m (15 ft) maximum. (See Table 2-2 for the controller module configuration switch
adequate power
RX02 controller for each
to
operate each module. The interconnections between each
of
or
safety hazards to an existing computer
that
the capacity
is
compatible with the applicable
the configurations in Table
is
adequate for the
2-1
is
by a BC05L-15
positions. )
NOTE
For single drive configurations, the drive will be identified as drive
0 and will be mounted as the left drive.
For dual drive configurations, the left drive will be
identified as drive
fied as drive
0 and the right drive will be identi-
1.
2.3 ENVIRONMENTAL CONSIDERATIONS
2.3.1 General
The
RX02
operating environment must be determined by the most restrictive facets
is
capable
of
efficient operation in computer environments; however, the parameters
of
the system, which in this
case are the diskettes.
of
the
2.3.2 Temperature, Relative Humidity
The
operating ambient temperature range
of
imum temperature gradient
is
age)
increased
to
-34.40 to
110 C/hr
51.60 C (-300 to
has stabilized within the operating temperature range before use. This range will ensure
will not be operated above its absolute temperature limit
Humidity control is
with memory. The RX02
percent, with a maximum wet bulb temperature
0
(36
F).
2.3.3
The
Heat
Dissipation
heat dissipation factor for the RX02 Floppy Disk System
important
is
designed
in any system because static electricity can cause errors in any
figure to the total heat dissipation for
compensate for such factors as the number
of
the diskette is
(200 F
/hr).
The
1250 F),
to
operate efficiently within a relative humidity range
of
250 C (770 F) and a minimum dew point
the
other
system components
of
personnel, the heat radiation from adjoining areas,
150 to
320 C (590 to
900 F) with a max-
media nonoperating temperature range (stor-
but
care must be taken
of
51.60 C (1250 F).
is
less
than
and
to
ensure
225
Btu/hr.
then adjusting the result
that
the media
that
the media
of
20 to
By
adding this
of
CPU
80
20 C
and
sun exposure through windows, the approximate cooling requirements for the system can be deter-
mined.
advisable
to
allow a safety margin
of
at
least
25
percent above the maximum estimated
It
is
requirements.
2.3.4 Radiated Emissions
Sources
close to the computer system, may affect
the
50 oersteds or greater might destroy all or some
of
radiation, such as
FM
radio broadcasts, vehicle ignitions, and radar transmitters located
the
performance
of
the RX02 Floppy Disk System because
possible adverse effects magnetic fields· can have on diskettes. A magnetic field with
of
the information recorded
on
the diskette.
an
intensity
of
of
to
2-4
Page 32
Table 2-1 RX02 Configurations
Computer System
Designation
RX8E
PDP-8
RX28E
RXII
~CPU
Controller
M7744
M7744
M7744
Interface RX02 Drive
Module Model No.
M8357
RX02-AA Single/I
RX02-AC Single/I
RX02-AD Single/230
M8357
M7846
RX02-BA
RX02-BC
RX02-BD
RX02-AA
RX02-AC
RX02-AD
RX02-BA
RX02-BC
RX02-BD
RX02-AA
Dual/I
Dual/II5
Dual/230
Single/I
Single/I
Single/230
Dual/
Dual/Il5
Dual/230
Single/l
RX02-AC Single/I
RX02-AD Single/230
RX02-BA
RX02-BD
n,,~l
_100+
....... , .............
Dual/230
115
/11
15
15
15
15
15
15
15
'i
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V I"..()
-
~,v
V,
60
Hz
50
Hz
50
Hz
60
Hz
50
Hz
50 Hz
60
Hz
50
Hz
50
Hz
60
Hz
50
Hz
50
Hz
60
Hz
50
Hz
50 Hz
U7
.....
'
.J.&~
50 Hz
PDP-II
LSJ-ll
RX211 M7744 M8256
RXVII
RXV21 M7744
M7744 M7946 RX02-AA Single/
M8029
RX02-AA Single/I
RX02-AC
Single/I
15
15
RX02-AD Single/230
RX02-BA
RX02-BC
RX02-BD
Dual/I
15
Dual/II5
Dual/230
115
RX02-AC Single/I
RX02-AD Single
RX02-BA
Dual/I
15
/230
15
RX02-BC Dual/115
RX02-BD
RX02-AA
RX02-AC Single/I
RX02-AD
RX02-BA
RX02-BC
RX02-BD
Dual/230
Single/I
15
15
Single/230
Dual/115
Dual/I
15
Dual/230
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
V,
60
Hz
50
Hz
50 Hz
60
Hz
50
Hz
50 Hz
60
Hz
50
Hz
50 Hz
60
Hz
50
Hz
50 Hz
60
Hz
50
Hz
50
Hz
60
Hz
50
Hz
50
Hz
2-5
Page 33
Table 2-2 Controller Configuration Switch Positions
Interface
RX211, RXV21,
RX8E,
RX28
2.3.5 Cleanliness
Although cleanliness
case
of
moving magnetic media, such as the RX02. Diskettes are not sealed units and are vulnerable to
dirt. Such minute obstructions as dust specks or fingerprint smudges may cause data errors. Therefore,
the
RX02 should
sive airborne particles.
RXII,
is
important in all facets
not
be sUbjected
RXVII,
Removable media
nance which are beyond DIGITAL's direct control.
DIGITAL disclaims responsibility for performance
of the equipment
meeting DIGITAL specifications
maintained in accordance with procedures approved
by
DIGITAL. DIGITAL shall not be liable for damages to the equipment or to media resulting from
such operation.
SI-1
OFF
ON
OFF
to
unusually contaminated atmospheres, especially one with abra-
involve
SI-2
ON
OFF
OFF
of
a computer system, it
NOTE
use, handling, and mainte-
when
operated with media not
or
with media not
2
1
ON
is
SI
Top
View
particularly important in the
2.4 UNPACKING AND INSPECTION
2.4.1 General
The
RX02 Floppy Disk System can be shipped in a cabinet as an integral part
separate container.
installation location before proceeding with the installation.
2.4.2 Tools
Installation
tools are all
for receiving and installing a cabinet-mounted system.
2.4.3 Unpacking
2.4.3.1 Cabinet-Mounted
I.
2.
3.
4. Remove the shipping restraint from the
of
that
Remove the protective covering over the cabinet.
Remove the restraint
Carefully roll the cabinet off the pallet; if a forklift
move the cabinet.
If
the RX02
an RX02 Floppy Disk System requires no special tools
are necessary. However, a forklift truck
is
shipped in a cabinet, the cabinet should be positioned in the final
or
pallet handling equipment may be needed
on
the rear
door
latch
and
open the door.
is
available, it should be used to lift and
RX02 and save it for possible reuse.
of
a system or in a
or
equipment. Normal hand
5.
Slide the RX02
Paragraph 2.4.3.3.
out
on
the chassis slides and visually inspect for any damage as indicated in
2-6
Page 34
2.4.3.2 Separate Container
1.
Open the
2.
Lift the RX02
3.
Remove the shipping fixtures from
as indicated in
4.
Attach
5.
Locate the proper holes in
cabinet.
6.
Place the tracks attached to the RX02 inside the extended cabinet tracks
until the tracks lock in the extended position.
7.
Attach the front bezel with
8.
Locate the RX02 cover in the cabinet above the unit
2-5).
2.4.3.3 Inspection
1.
Inspect the front cover(s)
allows the spring-loaded front cover
carton
out
Paragraph
the inside tracks
(Figure 2-4)
of
the carton.
2.4.3.3.
of
the chassis slides provided in the
the
of
the RX02 to be sure it operates freely. Compress the latch which
and
remove the packing pieces.
both
sides
of
the RX02
cabinet rails (Figure 2-5)
the
screws supplied.
to
open.
and
and
inspect for shipping damage
carton
and
secure it
to
the
RX02 (Figure 2-1).
attach the outside tracks
and
to
the
cabinet rails (Figure
to
the
slide the unit in
2.
Inspect the
sure the fuse
3.
Visually inspect
4. Loosen the screws securing the hinged
modules M7744 and M7745
5.
Verify
interface cable (BC05L-15)
2.5
INST
ALLA
1.
Ensure
2.
Loosen the screws securing the upper module (M7744)
3.
Inspect the wiring and connectors for
rectly.
rear
of
the RX02 chassis
is
not
damaged.
the
interior
that
the items listed
If
any shipping damage is found, the customer should
be notified
and record the information on the acceptance form.
TION
that
power for the system is off.
on
at
to
be sure there are
of
the unit for damaged wires
upper
can
be inspected for damaged components
the shipping
and
the
appropriate
NOTE
this time so he can contact the carrier
proper
module (M7744)
order
are
interface module are included.
routing
no
broken
or
included in
and
swing it up
and
ensure
or
bent
plugs. Also, be
loose hardware.
and
raise the module so
or
wires.
the
shipment. Be sure the
on
the hinge.
that
they
are
that
seated cor-
4. This step
jumpers
is
for 50
and
Hz
versions only. Check the power configuration to ensure
the correct circuit breaker
are
installed (Figure 2-3).
2-7
that
the
proper
Page 35
---SLIDES
DUST
COVER
ONE
PIECE
FOLDER
\
BRACE
WOOD
---JI"..--
/
___
-:..---
SCOR
ED
SHEET
REGULAR
SLOTTED
CARTON
Figure 2-4 RX02 Unpacking
2-8
SHiPPiNG
CARTON
MA-1854
Page 36
....;.-....--
COVE
R
CP-1594
Figure
5.
Connect the BC05L-15 cable
chassis through the back of the RX02
for the
PDP-S,
The cable
PDP-II,
is
connected to the M7744 module with the red stripe on the left, looking from the
component side
toward the center
6.
Refer to Table
7.
Refer to Table
S.
Insert the interface module into the Omnibus (PDP-S), available SPC slot (PDP-II), or LSI
2-2
2-3
bus (LSI-II). The
numbered available option location. Modules that use
higher priority than programmed
PDP-II
SPC slot, ensure that the
2-5
RX02 Cabinet Mounting Information
to
the M7744 module and route it along the near side
to
the CPU; then connect it to the interface module
or LSI-II.
of
board; the cable
of
the module.
is
connected to the interface module with the red stripe
for the correct controller configuration switch positions.
for correct device code or addressing jumpers on the interface module.
PDP-II
and
LSI-II interface modules must be inserted
I/O
NPG
devices.
(NPG
For
modules using
IN,
NPG
DMA
OUT) line
processing should have a
DMA
processing in the
(CAI-CBI)
in
is
backplane.
9.
Connect the RX02
ac
power cord into a switched power source.
of
the
the lowest
cut on the
10.
Turn the power on, watching for head movement on the drive(s) during the power up,
initialize phase. The head(s) should move one track toward the center and back to track
zero.
2-9
Page 37
Table 2-3 Interface Code /
Jumper
Configuradon
61QX*
61lX
672X
61JX
6~X
6~X
676X
677X
DR Priority
BR7 -54-08782
BR6 -54-08780
BR5 -54-08778
BR4 -57-08776
SWI
ON
ON
ON
ON
OFF
OFF
OFF
OFF
Unibus Address 17717X*
A
12
- Removed
All
- Removed
*
A I 0 - Removed
A9 - Removed
A8 - Installed
A7
-Installed
A6
-Removed
A5 - Removed
AA43"
- Removed
_ - Removed
I
PDP-8
SW2
ON
ON
OFF
(M8357)
Device Codes
SW3
ON
OFF
ON
OFF OFF
ON ON
ON OFF
OFF
ON
OFF OFF
PDP-II
(M7846) (M8256)
SWIOOFF
SW9
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SWI
LSI-II
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
(M8029)
SW4
OFF
OFF
OFF
OFF
ON
ON
ON
ON
Vector Address (264,)*
V2
- Installed
V3-
Removed
V4 - Installed
V5
- Installed
V6 - Removed
V7
- Installed
V8
-Removed
SW5
OFF
OFF
ON
ON
OFF
OFF
ON
ON
SWION
SW20FF
SW30N
SW40N
SW50FF
SW60N
SW70FF
SW6
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Register Address*
(17717X)
A
12
= Installed
II
- Installed
A
A
10
- Installed
A9 - Installed
A8 - Removed
A7 - Removed
A6 - Installed
A5 - Installed
A4 - Installed
A3
- Installed
* Standard
Vector Address (264g)
V2
- Installed
V3
- Removed
V 4 - Installed
V5
- Installed
V6-
Removed
V7
- Installed
V8
- Removed
2-10
Page 38
Table
2-3
Interface Code/Jumper Configuration (Cont)
264s
W6-Removed
W5 - Installed
W4-Removed
W3
-Removed
W2 - Installed
WI-Removed
.., I:.
Tl:;"C"Tl",rr"
....
v .I.
L~
.1
.l.l
~
\J
To
test the operation
sequence listed for
RX8
or
RX
11
Data
Reliability/Exerciser - 3 passes
DECX-8
or
Vector Address
270s
W6-
Removed
W5 - Installed
W4-Removed
W3 - Removed
W2-
Removed
WI
- Installed
of
RX02,
the
number
Diagnostic - 2 passes
DECX-ll -10
run
of
passes (time) indicated.
minutes
the
LSI-II
(M7946)
Register Address
177170
W
17
- Removed
W16 - Removed
W14 - Removed
W
13
- Installed
11
- Removed
W
WI0
- Removed
W9 - Removed
W8 - Removed
W7 - Installed
DEC
diagnostics supplied. Perform the diagnostics in
177150
W17 - Removed
W16 - Removed
W14 - Removed
W
13
- Installed
Wll
- Removed
WI0
- Removed
W9 - Installed
W8
- Removed
W7 - Installed
the
If
any
errors
occur
contact
Field Service.
2-11
Page 39
USER INFORMATION
3.1
CUSTOMER RESPONSIBIUlY
It
is the user's responsibility to ensure
from excessive dust and dirt, and meets
1.4.
The exterior
the diskettes are handled and stored properly in order to prevent errors
when recording
of
the RX02 should be kept clean. Also, it
or
reading data; diskette handling procedures are described in Paragraph 3.2.
3.2 CARE OF MEDIA
that
the RX02 is located and operated in an area that
or
exceeds the environmental conditions listed in Paragraph
is
the user's responsibility to ensure that
CHAPTER 3
or
data loss which might occur
is
free
3.2.1
To prolong the diskette life and prevent errors when recording
taken when handling the media. The following handling recommendations should
prevent unnecessary loss
Handling Practices
1.
Do
not write on the envelope containing the diskette. Write any information on a label prior
to affixing it to the diskette.
2.
Paper clips should not be used on the diskette.
3.
Do not use writing instruments that leave flakes (such as lead
of
the media.
4.
Do not touch the disk surface exposed
5.
Do not clean the disk
6. Keep the diskette away from magnets
exposed to a magnetic
7.
Do not expose the diskette to a heat source or sunlight.
8.
Always return the diskette to the envelope supplied with it to protect the disk from dust and
dirt. Diskettes not being used should be stored in a
and
of
data
Precautions
or
interruptions
in
any manner.
field
may lose information.
or
reading, reasonable care should be
of
system operation.
or
grease pencils) on thejacket
in
the diskette slot or index hole.
or
tools that may have become magnetized. Any disk
file
box
if
possible.
be
followed to
9.
When the diskette
materials.
10.
Do not place heavy items on the diskette.
11.
Do not store diskettes on top
fans into the diskette interior.
is
in use, protect the empty en velope from liquids, dust, and metallic
of
computer cabinets or
3-1
in
places where dirt can be blown
by
Page 40
12.
If
a diskette has been exposed to temperatures outside the operating range, allow five minutes for thermal stabilization before use. The diskette should
during this time.
Do not use paper
•
dips
• Do not expose the diskette to a heat source
light.
• Keep the diskettes from magnetic fields.
•
Do
not write on the diskette with an instrument
that leaves an impression
3.2.2 Diskette Storage
3.2.2.1 Short Term (Available for Immediate Use)
1.
Store diskettes in their envelopes.
2.
Store horizontally, in piles
be supported so
forces.
3.
Store in an environment similar
Permanent deformation
that
of
they do
ten
not
may
or
less.
lean
or
result from improper storage.
to
that
of
the operating environment range.
be removed from its packaging
CAUTION
on diskettes.
or
sun-
or
Oakes.
If
vertical storage is necessary, the diskettes should
sag,
but
should
the operating system;
not
be subjected
at
to
compressive
a minimum, store within
3.2.2.2 Long
stored in their original shipping containers within
Term
- When diskettes
do
not
need to be available for immediate use, they should be
the
nonoperating range
3.2.3 Shipping Diskettes
Data
recorded
contact with the disk surface.
precautions against possible exposure
netic source
least 3 inches within the
sources likely
on
disks may
is
the best protection against accidental erasure
to
be encountered during transportation, making it generally unnecessary
be
degraded by exposure
If
diskettes are
to
magnetic sources. Because physical separation from the mag-
outer
box. This separation should be adequate
to
to
be shipped in the cargo hold
any sort
of
of
small magnet
a diskette, diskettes should be packed at
to
ettes in specially shielded boxes.
to
When shipping, be sure
DO
NOT
EXPOSE
label the package:
TO
PROLONGED
HEA T OR
SUNLIGHT.
When received, the carton should be examined for damage. Deformation
receiver
the diskette
to
possible damage
or
for future shipping.
of
the diskette.
The
carton
should be retained, if it is intact, for storage
of
the media.
brought
of
an aircraft, take
into close
protect against any magnetic
to
ship disk-
of
the carton should alert the
of
3-2
Page 41
3.3 OPERATING INSTRUCTIONS
NOTE
The left drive is always identified as drive
The
RX02 has no operator controls
pressing the latch to allow the spring-loaded front cover to open. Place the diskette with the label
top
up (the jacket seams are on the
is
automatically lock when it
audible clicking sounds which indicate the head
Data
storage
and
retrieval is controlled by the user's program.
pushed down. Initialize the system (from the computer) and listen for
Do not open the drive door while the diskette is
use; this results in errors.
and
indicators. The diskette is inserted on a drive after com-
bottom)
on the drive spindle. Close the front cover which will
is
moving over the diskette; the RX02
CAUTION
O.
in
is
ready for use.
or
3.4 OPERATOR
Table
problem cannot
No
3-1
is
a list
be
Problem
power
(drive inoperative)
Drive not ready
Error in recording
TROUBLESHOOTING
of
possible problems and some probable causes the operator may encounter.
corrected, refer the problem to
Table
3-1
Operator Troubleshooting Guide
Probable Cause
a. Power cord disconnected
b. Blown fuse
c.
Circuit breaker open
a. Drive
b. Diskette improperly in-
stalled
a. Diskette wear
b. Diskette mounting hole
c. Mismatch in recording
density on a diskette
door
open
DIGITAL
Field Service.
I Correction
a. Connect power cord
b. Replace fuse
c.
Close circuit breaker
a. Close
b. Properly seat diskette
If
a.
If
b.
centric, replace diskette
c.
If
not compatible with
to be recorded, replace
diskette with a new preformatted diskette.
door
worn, replace
the hole is not con-
diskette data density
If
the
is
data
3-3
Page 42
CHAPTER 4
PROGRAMMING
This chapter contains programming information for the following interface options: RX8E, RX28,
RXll,
first, followed by the
presented. The RX8E,
patible with the
single or double density recording.
4.1
The RX8E interface allows two modes
the 12-bit mode,
information. The diskette capacity
transfer mode,
a
IBM-compatible diskettes, since 12-bit mode does
puts
bit mode
RX02 and servicing
RX02 to be interrupted without loss
RXVll,
RX8E and RX28 PROGRAMMING INFORMATION
33
percent increase
in
the extra
(18
RX211, and RXV21. The RX8E and RX28 programming information
RXll
RXOI
64
words are written in a diskette sector, thus requiring 2 sectors
128
8-bit words are written in each sector. Disk capacity
in
Os.
Data
ms for 8-bit mode). There
of
and
RXVll
RXll,
Floppy Disk System. The RX28E, RX211, and RXV21 can be used for either
disk capacity over the 12-bit mode. The 8-bit mode must be used for generating
that
and
transier requests occur
request by the host processor. This allows the data transfer to and from the
information, and then the RX211 and RXV21 information
RXVll
in
options are used for single density recording and are com-
of
data transfer: 8-bit word length
this mode is 128,128 12-bit words
not
23
ms aiter the previous request was serviced ior
is
no maximum time between the transfer request from the
of
data.
is
presented
is
and
12-bit word length. In
to
store 1 page
(1001
is
256,256 8-bit words, which
fully pack the sectors with data. The hardware
pages). In the 8-bit
of
12-
is
The
RX28 interface allows two modes
each mode
12-bit mode single density recording,
ity
is
capacity
written
8-bit bytes written in a sector with a diskette capacity
12-bit data words are loaded into the buffer and then the hardware forces zeros to
of
end
4.1.1 Device Codes
The eight possible device codes that can be assigned to the interface are
define address locations
a single PDP-8. These multiple device codes are also shared with
other devices are on the system, the
to the
The
device codes are selected by switches according to Table 4-1. These switches control ac bits 6-8,
while ac bits 3-5 are fixed at
connected and will not affect the device selection code.
switch package
of
data transfer there can be either single density
128,128 12-bit words; for double density, there are
of
256,256 12-bit words. In the 8-bit word mode single density recording,
in
each sector and the diskette capacity is 256,256 8-bit bytes; for double density, there are 256
the buffer so
P D P-8 Small Computer Handbook for specific device codes.)
that
that
the buffer
of
a specific device and allow up to eight
Is. The device code
is
located on the M8357
of
data
transfer: 8-bit word length and 12-bit word length.
or
double density storage
64
words are written in a diskette sector,
128
words written in a sector with a diskette
of
512,512 8-bit bytes.
is
filled.)
RX8E/RX28
other
RX8E/RX28
device code can be selected to avoid conflicts. (Refer
is
initially selected to be
The
switches are all located on a single
RX8E/RX28
interface board.
of
data. In the
and
the diskette capac-
128
8-bit bytes are
(For
the 12-bit mode, all
add
extra bits to the
70-77. These device codes
interfaces to be used on
devices. Depending on what
70.
Switches 7 and 8 are not
For
DIP
4-1
Page 43
Table 4-1 Device Code Switch Selection
Device
SI
S2
Code
77
76 0 0
75
74
73
72
71
70 1
4.1.2 Instruction Set
The
RX8E/RX28
operating as an RX28, for the 8-bit mode, all instruction set commands are transferred in two 8-bit
bytes.
lOT
67xO
67xl LCD Load Command, Clear
67x2
67x3
67x4
67x5
67x6
67x7
0
0
0
1 0
1
1 1
instruction set is listed below
Mnemonic Description
XDR
STR
SER
SDN
Ir--lTR Enable
INIT
S3 S4
0 0
1
1
0
1 1 1
0
0
1 0 1
0 0 0
1 1
No
Transfer
Skip on Transfer Request Flag, Clear Flag
Skip on
Skip
Initialize Controller
S5
S6 S7
1 I
1 1
1
0
0
0 1 1 X
0 0
Operation
Data
Error
on
Done
or
Disable Disk Interrupts
X
1
0 X
X
1
X
0
X
0
X
1
X
0
and
Register
Flag, Clear Flag
Flag, Clear Flag
S8
X
X
X
X
X
X
X
X
described in the following paragraphs. When
AC
and
Interface
o (OFF) 1
(ON)
SI
S2
S3
S4
S5
S6
S7
S8
4.1.2.1 RX8E
interface register and clears the AC.
10
on the drive specified by AC
the previous function.
described in greater detail in Paragraph 4.1.3.1.
Load Command (LCD) -
The
7.
A new function
The
command word
00
01
02
03
T
NOT
USED
Figure
4-1
67xlRX02 begins
is
defined as shown in Figure 4-1.
05
04
18/121
I
,
1 I I
MAINT
LCD
This command transfers the contents
to
execute the function specified in AC
cannot
06
NOT
USED
Word
4-2
be initiated unless the RX02 has completed
The
command word is
08
07
I~:~I
FUNCTION
Format
(RX8E)
09
10
11
I
NOT
USED
MA·1853
I
of
the AC to the
8,
9,
and
Page 44
4.1.2.2 RX28 Load Command - (First byte
contents
specified in AC
the
and
of
the
AC
to the interface register and clears the AC. The RX02 begins to execute the function
8,9,
and
10
on the drive specified by AC
RX02 has completed the previous function. The command word
is
described in greater detail in Paragraph 4.1.3.1.
02
IDENI
I
(XDR)
03
12
BIT
MODE
8
BIT
MODE
00
NOT RESERVED
USED
TRANSFER
BYTE 1
TRANSFER
BYTE 2
01
!
6701
6702
67xl,
04
Is
I
MAINT
0
0
Second byte 67x2) - This command transfers the
7.
07 08 09
06
05
1121
I
i
UNIT
SEL
2
2 3
3
A new function cannot be initiated unless
is
defined as shown in Figure 4-2
11
10
FUNCTION
I
7
4
4
6
5
04:
11
7
6
5
00:03
MA·1792
Figure 4-2 Command Word
When operating in the 8-bit mode, the Load command
of
the command word (shown as bits 4-11 in Figure 4-2) are stored; then
performed
justified.
of
the second 8-bit byte, Done
to
transfer the remaining bits
The
extra bits in the second 8-bit transfer are filled with zeros.
is
asserted to end the function.
of
data
(bit 3,
Format
is
stored in two 8-bit transfers.
DEN,
(RX28)
and bit
TR
is
asserted and an
2,
as shown in Figure 4-2) right-
Upon
completing the transfer
The
first 8 bits
XDR
4.1.2.3 Transfer Data Register (XDR) - 67x2 - With the maintenance flip-flop cleared, this instruction operates as follows. A word
of
transfer
is
governed by the RX02 and the length
selected (8-bit or 12-bit). When
I.
The last
can proceed,
2.
The data
data
word supplied by the RX02 has been accepted by the
or
or
address word requested by the RX02 has been provided by the PDP-8,
transferred between the
Done
is
negated, executing this instruction indicates to the RX02 that:
AC
and the interface register. The direction
of
the word transferred
is
governed by the mode
PD
P-8, and the RX02
and
the
is
RX02 can proceed.
AC
A data transfer (XDR) from the
AC
0-3 are transferred to the interface register but are ignored by the RX02. Transfers into the AC are
12-bit
jam
and AC
transfers when
0-3 remain unchanged. When the RX02
in
12-bit mode. When in 8-bit mode, the 8-bit word
RXES status word from the interface register
always leaves the AC unchanged.
is
done, this instruction can be used to transfer the
to
the AC. The selected mode controls this transfer as
If
operation
is
in 8-bit mode,
is
ORed into AC 4-11
indicated above.
is
4-3
Page 45
4.1.2.4
(TR) flag has been set by
data
transferred,
where an
4.1.2.5
been set by an error condition in the
set
STR -67xl
or
address words with the
or
XD
R follows an
SER
- 67x4 - This instruction causes the next instruction to be skipped
(Paragraph 4.1.3.6).
- This instruction causes the next instruction
after
an
RX02
LCD
LCD,
and
XD
instruction
the
clears the flag.
R instruction
to
ensure the command is in the interface register. In cases
TR
flag needs
RX02
and
clears the flag.
to
be skipped
The
TR
flag should be tested prior
to
ensure the
to
be tested only once between the two instructions.
data
or
address has been received
An
error also causes the done flag to be
if
the transfer request
to
transferring
if
the error flag has
or
4.1.2.6
been set by the
done flag is set, it
4.1.2.7 INTR - 67x6 - This instruction enables interrupts by the done flag if AC
interrupts
4.1.2.8 INIT - 67x7 - The instruction initializes the RX02 by moving the head position mechanism
drive I (if drive 1
status register
before the
Omnibus Initialize.
4.1.3 Register Description
Oniy one physicai register (the interface register) exists in the RX8E/RX28,
the six RX02 registers described in the following paragraphs, according to the protocol
in progress.
4.1.3.1 Command Register (Figures 4-3 and
by the
graphs 4. i .2. i and
SDN - 67x5 - This instruction causes the next instruction
RX02, indicating
is
cleared by the
if
AC
11
=0.
is
available)
and
sets Done upon successful completion
RX02 returns to the
LCD
instruction for RXSE and by a load command
4.
i .2.2).
the
to
SON
track
Done
completion
instruction. This flag will interrupt
O.
It
state. Initialize can
of
a function
reads track
4-4) - The command is loaded into the interface register
1,
sector I
of
Initialize.
be
or
(LCD
to
be skipped if the done flag has
detection
generated by the program
of
and
of
an error condition.
if
interrupts are enabled.
II
=
l.
drive
O.
It
zeros the error
Up
to 1.8 seconds may elapse
but
it may represent one
of
the function
XDR)
for the RX28 (Para-
It
disables
or
by the
If
and
the
of
of
00
01
02
03
04
05
ISI12I
J
I
NOT
USED
Figure 4-3 Command Register
MAINT
07
06
I~:~I
09
08
FUNCTION
10
I
NOT
USED
Format
4-4
(RXSE)
11
I
I
NOT
USED
MA·1793
Page 46
00
01
02 03 04 05 06 07 08 09 10
11
12-BIT
The function codes (bits
Code
000
001
010
011
100
101
110
111
MODE
8-BIT MODE
I !
,----;
NOT RESERVED
USED
{
Figure 4-4 Command Register Format (RX2SF)
8,
9,
10)
Function
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not
Read Status
Write Deleted
Read Errror Register
IDENI
I I I
1ST
BYTE
181121
MAINT
o
I!
NOT
USED
2 3 4 5 6
FUNCTION
C::
UNIT
SEL NOT
o
2ND BYTE
T
NOT
USED
are suummarized below and described in Paragraph 4.1.4.
used (RXSE) - Set Density (RX2S)
Data
Sector
I
I
7
USED
04:
00:03
MA-1794
11
The
DR V (UNIT)
performed:
AC7
AC7
The
8/12
bit (bit
AC5
AC5=1
The
DEN
bit (bit
double). The RX8E/RX28
4.1.3.2 Error Code Register (Figure 4-5) - Specific error codes can be accessed
code function (111) (Paragraph 4.1.4.9). The specific octal error codes are given in Paragraph 4.1.5.
The maintenance bit (M bit) can be used to diagnose the
conditions. The off-line condition exists when the BC05L-15 cable
on-line condition exists when the cable
SEL bit (bit
=0
= 1
5)
selects the length
=0
3)
for RX2S indicates the density for the function to be performed
7)
selects one
Select drive
Select drive 1
12-bit mode selected
8-bit mode selected
will
initialize into 12-bit mode.
0
of
the
is
connected to the RX02.
of
data
4-5
the two drives upon which the function will be
word.
RXSE interface under off-line and on-line
is
disconnected from the RX02; the
by
(0
use
of
the read error
= single, 1 =
Page 47
00
01
02 03 04 05 06 07 08 09 10
11
Figure 4-5
If
an
LCD
lOT
(I/O
maintenance flip-flop
data
register transfers
to
be written
a
Load
and
Command
read for maintenance checks.
lOT
the maintenance bit in
The
contents
mand
lOT,
antee the contents
using the
of
the
which sets
XDR
lOT
interface buffer
of
the interface register.
to transfer those contents into
------------~,~---------------T------------~
NOT
USED
Error
Code
Register
transfer) is issued with
is
set,
the
assertion
(XDR)
are forced
into
of
AC
RUN
the
The
with
AC
4 =
O.
The
following
an
off-line mode.
cannot
the
maintenance flip-flop. However, successive
be guaranteed immediately following the first
The
contents
ERROR CODE
CP-1515
4 =
following
AC.
Format
1,
The
(RX8E/RX28A)
the
maintenance flip-flop is set. When the
XDR
maintenance
instructions is inhibited,
bit
allows the interface register
maintenance flip-flop is cleared by Initialize
paragraphs
of
the interface register can then
the
AC.
describe more explicitly how
Load
Command
lOTs
and
Load
will guar-
be
verified by
all
or
by
to
use
Com-
In addition, the maintenance flip-flop directly sets the skip flags, which will remain set as long as the
maintenance flip-flop is set. Skipping
clear the flags. Setting
condition.
The
skip
and
lOTs
then clearing the maintenance flip-flop will leave the skip flags in a set
can
on
these flags as long as the maintenance flip-flop is set will
then be issued
to
determine whether
or
not
a large
portion
of
not
the
interface skip logic is working correctly.
With the maintenance flip-flop set, it can be deiermined if the interface is capable
interrupt
enable flip-flop can be set by issuing
interrupt
The
cleared
successful, all
Set.
In
the
face register.
should be implemented in the on-line mode. Exiting from
finalized by an initialize
4.1.3.3
77 (0-76) tracks a given function is to operate.
function in progress
4.1.3.4
26 (1-26) sectors a given function is
function in progress
on
the Omnibus. When
the
maintenance flip-flop is set,
an
INTR
enable should generate an interrupt.
maintenance flip-flop can also be used
to
generate
on-line mode, use
The
RXlT
RXlSA
the
flags,
and
INIT
lOT
of
the
flags
and
the
interrupt
of
the maintenance bit should be restricted
same procedure described
to
the
RX02.
A - RX
Track
Address (Figure 4-6) - This register is loaded to indicate
(Paragraph
4.1.4). Bits
- RX Sector Address (Figure 4-7) - This register is loaded to indicate
to
operate.
(Paragraph
4.1.4). Bits
the
done
flag is set,
lOT
with
AC
bit
to
test
the
IN
is then executed.
IT
11 = 1.
lOT.
If
The
The
maintenance flip-flop is set
execution
enable flip-flop shouid be cieared
to
writing
to
write
and
read
the
interface register in the off-line mode
the
on-line maintenance bit mode should be
It
can
be
addressed only under the protocol
0-3
are
It
0-3
are unused
unused
can
and
are
ignored
be
addressed only under the protocol
and
are
ignored by the control.
combination
of
INIT
if
they were previously
and
by
the control.
of
generating
and
the interrupt
of
done
an
and
and
lOT
is internally
reading the inter-
on
on
which
which
of
of
of
of
the
the
the
the
4-6
Page 48
00
01
02 03
04
05
06
08 09 10
07
11
I
•
NOT
USED
Figure 4-6 RX2T A Format (RX8E/RX28)
02
01
00
• •
NOT USED
Figure
RX
4.1.3.5 RX2DB -
Data Buffer (Figure 4-8) - All information transferred to and from the floppy
media passes through this register and
ress. The length
of
data transfer
register when the Load Command lOT
03
4-7
is
either 8 or i 2 bits, depending on the state
0
•
114
0-
8
10
09
I
32
1-
8
I
04
0
I 0 I
05
06
0
07
08
RX2SA Format (RX8E/RX28)
is
addressable only under the protocol
is
issued (Paragraph 4.1.3.1).
MA·181S8
11
I
MA·181S9
of
oi
the function
bit 5
oi
the command
in
prog-
RX
4.1.3.6 RX8E conditions
(
101).
is
accessed by the XD R instruction. The meaning
The
of
the selected drive. This read-only register can be accessed by the read status function
RX
ES
Error and Status (Figure 4-9) - The RXES contains the current error and status
is
also available in the interface register upon completion
00
01
02 03 04 05 06
12
BIT
MODE
00
ONLY
Figure
01
02 03 04
4-8
RX2DB Format (RX8E/RX28)
I~~~I
NOT USED
Figure 4-9 RXES Format (RX8E)
of
05 06
DO I
the error bits
07
08 09 10
•
8
OR
12
BIT
MODE
07
08 09 10
lID
NOT USED
of
any function. The RX
is
given below.
11
MA·18&O
11
I
ICRcl
MA·1861
ES
4-7
Page 49
Bit No.
Description
11
9
5
4
CRC
Error -The
error.
up
The
to
10
Initialize
due
to
RX02 power failure, system power failure,
bit is
not
Deleted
data
times, as
Done
available within
Data
the identification field. The
the
deleted
or
actual deletion
bit will
be
data
set
Drive Ready - This
cyclic redundancy check
must
be considered invalid;
most
data
errors
are
recoverable (soft).
- This bit indicates completion
the
(DO)
- In
mark
of
data
if
a successful
bit
the
course
data
has
no
further significance within
due
or
is asserted
RXES
to
from a read status function.
of
reading data, a deleted
following will be collected
this
mark
unsuccesful Write Deleted
if
the
unit currently selected exists, is properly supplied
at
the
it
is suggested
of
the
or
must
be accomplished by user software. This
with power, has a diskette installed properly, has its
speed.
NOTE
1
This bit is only valid for either drive when retrieved
via a Read
pletion
If
the error bit was set in the
are
not set in the RXES, specific error conditions can
Status
of
an Initialize.
function
NOTE
or
for drive 0 upon com-
2
RX2eS
be accessed via a read error register function.
end
of
the
data
that
the
Initialize routine.
programmable
data
and
the
RX02.
Data
door
closed,
but error bits
field has indicated
data
transfer be retried
It
can be asserted
or
bus Initialize. This
mark
was detected in
an
transferred normally as
Any
alteration
of
files
function is performed.
and
has a diskette up
to
4.1.3.7 RX28 - RX
conditions
(101).
The
of
the selected drive. This read-only register can
RX2ES
RX2ES is accessed
Error
and
Status
is
also available in the interface register
by
the
XDR
01
00
"-
____
y-----J
NOT USED
(Figure 4-10) -
instruction.
03 04 05
02
1
The
The
meaning
06 07
Figure 4-10 RX2ES
RX2ES contains the
be
accessed by the read status function
upon
completion
of
the
error
08 09 10
I RESE'RVED
RX02
Format
(RX28)
bits
11
MA-1862
current
of
any function. The
is
given below.
error
and
status
4-8
Page 50
Bit No.
Description
11
10
9
8
7
6
5
CRC
Error
- The cyclic redundancy check
error.
The
data
must be considered invalid; it is suggested
up
to
10
times; as most
Reserved.
Done
Initialize
due
to
RX02 power failure, system power failure,
bit is
not
RX02 - This bit is asserted
DEN
ERR
drive density.
serts
error
DR V DEN
1 = double).
Deleted
the identification field. The
the deleted
or
bit will be set
Data
actual deletion
- This bit indicates completion
available within
- This
Upon
and
done.
- This bit indicates the density
(DD)
data
mark
if
a successful
data
bit
indicates
detection
- In the course
has
of
data
at
the end
errors
the
if
data
no
further significance within the RX02.
due
or
are
recoverable (soft).
of
RX2ES from a read status function.
an
RX02 system is being used.
that
the
density
of
this
error
the control terminates the operation
of
the diskette in the drive selected (0 = single,
of
reading data, a deleted
following will be collected
to this
mark
must be accomplished by user software. This
unsuccessful write deleted
of
the
that
the
Initialize routine.
or
programmable
of
the function does not agree with the
data
field has indicated an
the
data
transfer be retried
It
can be asserted
or
bus Initialize. This
data
mark
was detected in
and
transferred normally, as
Any
alteration
data
function
is
performed.
and
of
as-
files
4
4.1.4 Function Code Description
The
RX8E/RX28
4.1.2.1 and 4.1.2.2. The
verify
receiving a
while
the
protocol be followed for the successful transfer
for each function
Drive Ready - This bit
with power, has a diskette installed properly, has its
speed.
This bit is only valid for either drive when retrieved
via a read status function
pletion
If
the error bit was set in thee RX2CS but error bits
are not set
can be accessed via a read error code function.
functions are initiated by means
done
that
the
RX8E/RX28
command
command
instruction while in the
is
decoded. Each
is
described in the following sections. A summary table
is
asserted
of
an Initialize.
in
the RX2ES, specific error conditions
flag should be tested
is
in the
Done
of
the eight functions summarized below requires
if
the unit currently selected exists, is properly supplied
door
NOTE
or
NOTE
and
state
prior
Done
state, the
of
data, status,
closed,
1
for drive 0 upon com-
2
of
the Load
cleared with the
to issuing the
command
RX8E/RX28
and
address information. The protocol
and
has a diskette up to
described in Paragraphs
SDN
instruction in
command
enters the
is
instruction.
Not
Done
that
presented below.
order
to
Upon
state
a strict
4-9
Page 51
Octal 8 9
AC
10
Function
0
2
4
6
10
12
14
16
0
0 0
0 0 1
0 1 0 Write Sector
0
1
1
1
1 Read
0
1
0
1
0
1
1 0
1
1
Fill Buffer
Empty Buffer
Sector
Not
Used (RX8E), Set Density (RX28)
Read
Status
Write Deleted
Data
Sector
Read Error Register
NOTE
AC bit
since AC bit
4.1.4.1 Fill Buffer (000) host processor with
64
12-bit words
function loads the sector buffer in 12-bit mode with
words for double density; in the 8-bit mode, the buffer
or
256 8-bit bytes for double density. This instruction only loads the sector buffer. In order to complete
the transfer
read back by means
Upon
to
the diskette, another function, write sector, must be performed. The buffer may also be
of
the empty buffer function in order
decoding the fill buffer function, the RX02 will set the transfer request (TR) flag, signaling a
request for the first data word.
STR instructions prior
transferred
to
the interface register by means
from the interface register
The
sequence above
mode
or
128
data transfers for 8-bit mode). After the 64th (or 128th) word has been loaded into the
sector buffer, the
the completion
the
data
transfers. Any
of
loaded in the AC.
to
each successive
to
is
repeated, until the sector buffer has been loaded (64 data transfers for 12-bit
RX2ES
is
the function. Therefore, it
XDR
The
sector buffer must be completely loaded before the
and recognize a new command. An interrupt would now occur
11
is assumed to be 0 in the above octal codes
11
can be 0 or
For
RX8E this function
ifin
12-bit mode or
1.
is
64
The
TR
flag must be tested and cleared by the host processor with the
XDR
of
lOT
(Paragraph 4.1.2.4).
the
XD
the sector buffer and sets the
moved
to
the interface register, and the RX02 sets the done flag to indicate
is
unnecessary for the host processor to keep a count
commands after Done
is
used
to
load the RX02 sector buffer from the
128
8-bit words
12-bit words for single density or
is
loaded with
to
verify the data.
RIOT.
The
TR
flag as a request for the next data word.
ifin
8-bit mode.
For
RX28 this
128
128
8-bit bytes for single density
The
data word can then be
RX02 next moves the data word
set will result in the RX2ES status word being
RX8E/RX28
will set Done
if Interrupt Enable were set.
12-bit
of
4.1.4.2 Empty Buffer
sor.
Upon
decoding this function RX2ES bits are cleared and the
in the interface register. This
the host processor.
XDR
command.
(001) - This function moves the contents
TR
flag signifies the request for a data transfer from the RX8E/RX28 to
The
flag must be tested and cleared; then the word can be moved to the AC by an
The
direction
of
transfer for an
XDR
command
flag is set again with the next word in the interface register.
words
the
now occur
or
bytes have been transferred, thus emptying the sector buffer. The done flag is then set after
RX2ES is moved in the interface register to indicate the end
if
Interrupt Enable were set.
NOTE
The empty buffer function does not destroy the contents of the sector buffer.
4-10
of
the sector buffer to the host proces-
TR
flag
is
set with the first data word
is
controlled by the RX02. The
The
above sequence
of
the function. An interrupt would
is
repeated until all
TR
Page 52
4.1.4.3 Write Sector (010) - This function transfers the contents
and
the
sector
TR
on
the diskette.
Upon
decoding this function, the
flag, signifying a request for the sector address.
The
the binary sector address can be loaded into the interface register by means
of
the sector buffer
RX8E/RX28
TR
flag must be tested
clears the RX2ES
of
the
sector address must be within the limits 1-328.
The
TR
flag is set, signifying a request for the track address.
then the binary track address may
mand.
The
the
The
track address must be within the limits 0-1148.
RX02 tests the supplied track address
RX2ES
is
moved to the interface register,
be
loaded into the interface register by means
to
determine
the
error
The
TR
flag must be tested
if
it is within the allowable limits.
and
done flags are set,
terminated.
If
the track address is legal,
the requested sector, transfers the contents
the
RX02 moves the head
of
of
the selected drive
the sector buffer
and a CRC
to
the selected track, locates
character to
sets Done. Any errors encountered in the seek operation will cause the function
be loaded into the interface register,
tered, the
RX2ES is loaded into the interface register
and
the
error
NOTE
and
and
done flags
to
be set.
only the done flag is set.
The write sector function does not destroy the con-
tents
of
the sector buffer.
to
a specific track
and
cleared before
XDR
command.
and
of
the
XD
If
and
the function
that
sector,
to
cease, the RX2ES to
If
no
errors are encoun-
and
sets
The
cleared;
R com-
it is not,
is
and
4.1
~4.4
Rf'ftd
Seo<.-tor
the sector buffer.
signifying the request for the sector address.
(011) - This function moves a sector
Upon
decoding this function, the
The
then loaded into the interface register by means
request for the track address.
is
then loaded into the interface register by
checked by the RX02.
register
and
the function is terminated. Otherwise, the RX02 moves
If
locates the specified sector, transfers the
data.
If
no errors occur, the done flag is set with the RX2ES in the interface register.
anytime during the execution
flags with
If
a deleted
4.1.4.5
assigned
RX2ES in the interface register. A detection
data
mark was encountered
Set Media Density (100) for RX28 Only - This function causes the entire diskette
to
a new density.
control reformats the diskette by writing new
ing
out
all
data
fields on the diskette. Before executing the
protective key word
of
The control starts at sector
writing the new
is
damaged, the control will
data
address mark
The
flag is tested
illegal,
the
error
and done flags are set with the RX2ES moved
data
of
the function, the function
at
the beginning
The
density bit (bit 3 RX2CS) indicates the new density
01001001 (ASCII'I').
1,
track 0 and reads the header information, then starts a write operation,
and
data
abort
the operation
an
data
field as well as
of
data from a specified track and sector to
RX8E/RX28
clears RX2ES
flag must be tested and cleared.
of
the
XDR
and
cleared by
XD
R command.
command.
the
The
host processor
The
legality
the
to
the sector buffer, computes
is
terminated by setting the
of
CRC
error
results in RX2ES bit
of
the desired
data
address marks (double
command
CRC
characters.
and
assert
DONE
and
ERROR.
and
sets the
The
sector address
TR
flag is set, signifying a
and
the track address
of
the track address
to
head
to
the specified track,
and
checks
If
an
error
TR
flag,
the interface
CRC
for the
error
occurs
and
done
11
being set.
field, RX2ES bit 5 is set.
to
be
rt>-
of
the diskette. The
or
single density) and zero-
the control will look for a
If
the header information
is
is
This operation takes
about
15
seconds
and
should
not
be interrupted.
interrupted, an illegal diskette has been generated which may have
diskette should again be completely reformatted.
4-11
If
for any reason the operation
data
marks
of
both
densities. This
is
Page 53
4.1.4.6 Maintenance Read Status (101) for RX28 Only - This function updates the drive ready and
of
drive density status
the density error bit and leaves the remainder
by loading the head on the selected drive (without changing head and reading position) with the first
header and data mark that randomly appears under the head. The control will then generate the
appropriate number
interface.
ation.
Upon completion
the selected drive, clears the
of
shift pulses which will transfer the RX2ES (error and status) register over the
of
the RX2ES transfer, the control asserts Done to complete the oper-
INIT
DONE
of
the RX2ES unchanged. The drive density
bit, updates the Unit Sel, possibly sets
is
updated
4.1.4.7 Read
to the RX8E interface register and sets the done flag. The RXES can then be read
register (XDR) command. The bits are defined
4.1.4.8 Write Deleted
that a deleted data mark
1.5.3.2).
function.
4.1.4.9 Read Error Code Function (111) - The read error code function can be used to retrieve explicit
error information upon detection
error code to the interface register and sets Done. The interface register can then be read via an XD R
command and the code interrogated to determine which type
Status (101) for RX8E Only - Upon decoding this function, the RX02 moves the RXES
by
the transfer data
in
Paragraph 4.1.3.6.
NOTE
The average time for this function is 250
sive
use of this function
reduced throughput.
Data
Sector (110) - This function
is
written prior
RX2ES bit 5 (Deleted Data) will be set in the interface register upon completion
Care should
The program must perform tbis function before a
read status because tbe error register is always modi-
by
fied
a read status function.
to
the data field rather than the normal data mark (Paragraph
of
the error flag. Upon receiving this function, the RX02 moves an
be
exercised in the use of this function.
will
NOTE
result
is
ms.
Exces-
in
substantially
identical to the write data function except
of
failure occurred (Paragraph 4.1.5).
of
the
4.1.4.10 Power Fail - There
senses a loss
invalid while power
When the RX02 senses the return
1.
2.
3.
4.
There
However, all other information
INIT
is
lOT
of
power, it will unload the head
is
low.
Move drive 1 head position mechanism to track
Clear any active error bits.
Read sector 1
Set Initialize Done bit
no guarantee that information being written at the time
is
a method
of
is
no actual function code associated with power fail. When the RX02
of
track 1
on
aborting an incomplete function (Paragraph 4.1.2.7).
and
abort all controller action. All status signals are
of
power, it will remove Done and begin a sequence to:
o.
of
drive 0 into the buffer.
of
the RX2ES, after which Done
the diskette will remain unaltered.
4-12
is
again asserted.
of
a power failure
will
be retrievable.
Page 54
4.1.S Error Recovery
4.1.S.1 RX8E - There are two error indications given by the RX8E system. The read status function
(Paragraph 4.1.4.7) will assemble the current contents
sampled to determine errors. The read error register function
of
the RXES (Paragraph 4.1.3.6), which can be
(Paragraph 4.1.4.9) can also be used to
retrieve explicit error information.
The results
when Done sets, indicating the completion
the contents
of
the read status function
of
the interface register to the PDP-8's AC.
or
the read error register function are in the interface register
of
the function. The
XDR
lOT
NOTE
A read status function is not necessary
if
the 0 RV
READY bit is not going to be interrogated because
the RXES is
the interface register
at
the com-
in
pletion of every function.
The error codes for the read error register function are presented below.
Octal
Code Error Code Meaning
0010 Drive 0 failed to see home
0020 Drive 1 failed to see home
0030 Found home when stepping
0040 Tried to access a track greater than
0050 Home was found before desired track was reached
0070 Desired sector could not be found after looking at
0110 More than 40
/-£s
and no SEP clock seen
on
Initialize.
on
Initialize.
out
10
tracks for
77
IN
IT
52
headers
0120 A preamble could not be found.
0130 Preamble found
0150 The header track address
0160
0170
0200
Too
many tries for an
Data
AM
CRC
error on reading the sector from the disk.
but
no
I/O
mark found within allowable time span
of
a good header does not compare with the desired track.
lOAM
(identifies header)
not found in allotted time
No
code appears in the ERREG.
0210 All parity errors
0220 Self diagnostic error on Initialize
0240 Density Error
must be issued to transfer
(2
revolutions)
4.1.S.2 RX28 - There are two error indications given by the RX28 system.
will
assemble the current contents
of
the RX2ES which can be sampled to determine errors. The read
error register function can also be used to retrieve explicit error information.
The results
when Done sets, indicating the completion
the contents
of
the read status function
of
the interface register to the PDP-8's AC.
or
the read error register function are in the interface register
of
the function. The
XDR
lOT
must be issued to transfer
NOTE
A read status function is not necessary
if
the DRV
ROY bit is not going to be interrogated because the
RX2ES is
of
every function.
in
the interface register
at
the completion
The error codes for the read error register function are presented below.
4-13
The
read status function
Page 55
Octal
Code Error Code Meaning
00
1 0 Drive 0 failed to see home on Initialize.
0020 Drive 1 failed to see home on Initialize.
0040 Tried to access a track greater than
76
0050 Home was found before desired track was reached.
0070 Desired sector could not be found after looking at
0110 More than
40
J.lS
and no SEP clock seen
52
headers
0120 A preamble could not be found.
0130 Preamble found
0150
0160
The header track address
Too many tries for an IDAM (identifies header)
but
no
ID
mark found within allowable time span
of
a good header does not compare with the desired track.
0170 Data AM not found in allotted time
0200 CRC error on reading the sector from the disk
0220
R/W
electronics failed maintenance mode test.
0240 Density error
0250 Wrong key word for Set Media Density command
4.1.6 RX8E Programming Examples
4-11
4.1.6.1 Write/Write Deleted Data/Read Functions - Figure
presents a program for implementing a write, write deleted data, or a read function with interrupts turned off
preset the PTR
any number. Starting
Once the command
request (TR). When TR
while waiting for the controller to respond with another TR. When
ioaded and the AC
Y,
CTR
Y, and STR Y retry counters, which are set at
at
RETRY, the program tests for 8-or 12-bit mode, type of function, and drive.
is
loaded, the program waits in a loop for the controller to respond with transfer
is
set, the sector address
is
cieared again. The program loops to wait for the Done condition.
is
loaded and the AC
10
retries but can be changed to
is
cleared. The program loops
TR
is reset, the track address
(2
revolutions).
(IOF). The first 3 steps
is
flag
is
When the done
set.
If
the AC =0000, the error
status from the
RXES is saved and tested to determine the error (Paragraph 4.1.3.6). The RXES
not include the select drive ready bit.
PTRY retry counter.
have not occurred, a branch
set, the program checks for an error condition, indicated
is
a seek error; if bit
If
a parity error
If
a parity error persists after
is
made to RETRY and the sequence
11
of
the AC
is
detected, the program increments and tests the
10
tries, it
is
After a parity test, the program tests to see if the CRC error bit
program increments and tests the CTRY retry counter.
considered a hard error.
If
10
retries have not occurred, a branch
If
a CRC error persists after
is
set, the error
considered a hard error.
is
repeated.
is
set.
If
is
made to RETRY and the sequence
by
the error
is
a CRC error. Error
a CRC error
flag
If
10
retries
is
detected, the
10
retries, it
repeated.
A seek error
is
performed (Paragraph 4.1.2.8). During a write or write deleted data function, the sector buffer must
be refilled because INIT
previous contents of the sector buffer. The instruction sequence for a
in
Figure 4-11, but
increments and tests the
hard error.
is
assumed if neither a CRC nor a parity error
will
cause sector 1
is
presented in Figure 4-13. After the system has been initialized, the program
STR Y retry counter.
If
10
retries have not occurred, a branch
of
track 1
If
a seek error persists after
is
detected. An Initialize (INIT) instruction
of
drive 0 to be read, which
fill
buffer function
10
tries, it
is
made to RETRY and the sequence repeated.
will
destroy the
is
not included
is
considered a
4-14
being
will
is
Page 56
1
2
3
4
5
6
7
8
9
UI
11
:.2
13
14
15
:6
17
18
:iY
2'"
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
5;2
53
54
55
56
57
58
59
61!1
61
62
63
64
65
66
67
68
69
71
71
72
73
74
75
76
77
78
79
8'"
61
a2
83
84
85
86
87
88
89
91!1
91
92
93
94
95
96
97
98
6711
671U
6713
6714
67115
.716
6717
1231 1254
1231 3255
1212
1254
1213
325.
1204
12,4
120'
3257
.20.
1261
12~7
1261
1112:;'
1262
fIIZ11 6701
"212 6703
U13
5212
1214 1263
111215
6702
1216 7211
1217 6713
11122111
5217
1221 1264
.222
6712
ii2:3
naiO
1224
,7"5
1225 5224
122.
67"4
1227 74"2
11231
6702
11231
3265
.232
7315
11233
0265
1234
"'I
123'
5241
'236
2255
'237
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12411
7412
1241
7Jel
1242
~265
1243 7651
1244 5251
IPROGRAMM I NG
I
ITHE
rOl.1.0WING
I
ITHE
STANDARO
I
LCO-6'"l
XDR-6712
STR.67a;J
SER-6714
SON-671115
HITRa.716
I~IT·6717
I
ITHE
rOl.1.0WING
I
ITO
WRITE.
I
iLOCATION
I
lIN 8
I
START.
I
IwRITE.
I
RC;TRY.
I
IwAIT
I
I
I~A[T
I
ITH~
I
IWAIT
I
Ilr
I
I
ITHE
I
ITHE
I
Ilr
Ilr
IIF'
I
I
IA
I
IINCREMENT
I
lAND
I
lOR
I
I
/THE
I
/TEST
I
TeRC.
OR
12
TAO
DCA
TAO
DCA
TAO
DCA
WRITE
TAO
TAO
TAO
L.CO
rOR
STA
JH"
TAO
XOII
CI.A
rOR
nA
JMP
TAD
XOR
Ci,.A
SECTOR
rOR
THE
rUNCTION
ERROR
CONTENTS
TRANsrER
TRANsrER
TRANsrER
XOR
DCA
CL.I.
AND
SNA
JM"
PARITV
RETRY
UNTIL.
IS!
JI1P
MI.T
ERROR
rOA A CRC
CLI.
AND
SNA
JH'
SECTORi
THE
THE
THE
ERROR
THE
EItAHPLES
ARE
RXll
lOT
DEVICE
IS A
WRITE
DELETED
or
BIT
HODE
KHlI
PTRy
ICH1I
CTRy
KI111
STRy
DELETED
MODE
COMMAND
UNIT
TRANsrER
,-1
SECTOA
TRANsrER
,-1
TRACK
AND
TRACK
DONE
rLAC
HAS
fLAG
[S
SET
or
THE
REGISTER
REGISTEA
REGISTER
ASTATUS
CLA
lAC
ASTATUS
Cl'
TCRC
HAS
AND
TEST
THE"
COHMAND " UNTIL.
PTRY
COUNTER
PTRY
RETRY
fL.AG
[S
SET
ERROR
CLA
lAC
'STATUS
CLA
SEEK
rOR
THE
RU/RXIll
lOT
COOE
CODE
15
IIOT
TO
LOAU
IIOT
TO
LOAD
IIOT
TO
SKIP
IIOT
TO
SKIP
IIOT
TO
SKIP
I
CAC)
• I
IIOT
TO
INITIII.IAE
PROGRAMMING
TRACK
DATA.
REQUEST
REQUEST
ADDRESSES
COHPI.ETEO
TRA~S'ER
BITS
BIT
BIT
DATA.
AND
11
1.
"T"
CHECK
18.
EXAMPI.!
OR
ITHE
OR
READ
F'LAC
F'LAC
HAVE
5UCCEssrULLY
RECISTER
AND
• 1
a 1
RAL
OCCURED
THE
'ARITY
ERROR
OVERF'LOWS
BUT
THE
ERMOR
F'LEX
ISLE 0 ISKETTE
DEF'I~lTIO~S
67'-
THE
COMMAND.
OR
READ
THE
ON
A
TRA~SF'ER
ON
AN
ERRnR
ON
THE
THE
or
THE
AT
SECTOR
CONTENTS
DONE
ENABLE
RxI/RX.l
P~OTOCOL
or
PROC;~A"
I
IPARITY
INTERRUPT
REAU
ICRC
ISEEIC
I'
I 4
IDATA,
I
IIOT
THEN
TAANsrEA
1101
IWAIT
I 1
IIOT
leLA
THEN
T~A~S'ER
110T
IWAIT
I •
IIOT
11;;
YEEN
TRANS'ERR~D
'OR
ANY
ERRORI
C"O
ERROR
IIOT
IWAIT
IIOT
I
IS
THE
ERROR
11
- I
THEN
THEN A CRC
THEN A PARITY
METRY
THE
PANITY
TO
IS
10HE
ERROR
ERROR
IGET
lAND
I I
ITEIT
ISICI'
I"OT A PARITY
COUNTER
ERAOR
III
IRETAY
IHARD
NOT A PARITY
I 1
ITEST
ISKIP
INDT A CRC -HUST
CAC)
IS
REQUEST
0"1
CAC)
SUBSYSTEH
THE
REGISTER
F'LAG
TRAHSF'ER
F'LAG
rLAG
REQUIRED
"5"
(THE
CONTENTS
1.0CATIO~
-121
RETRy
RETRY
COUNTER
RETRY
COUNTER
"
la-SIT.
I'
WRITE.
OR 6 Ir
21
I'
UNIT
21.
67Xl
TO
THE
SECTOR
67'X3
TO
rOR
TRANsrEA
TO
3110CULl
TO
~OAO
IECAUSE
THE
TRACK
ADDAESS
"XI
TO
rD.
TRANSfER
TO
11.COCTA~)
TO
~O'O
....
i[C;AVSl
TO
THE
RXll
'LAC)
THEN
67X1
TO
'0.
DO~E
67X4
IA~PLES
OK -COHPLtTEO
STATUS
TY,E
0'
HAS
PRoGRAH
IEEIC
oceURED.
MAS
OCCUREO
CO"TENTS
SAVE
'OR
PARITY
IF'
PARITY
I.OCATION • PTRY
AECOvERS
THE
COMMAND
'ARITY
ERROR
'OR A CRC
Ir A CRe
COMMAND
• 1
MEANS
or
TRACKI
COUNTER
111
I'
14
I'
WRITE
REAO
21
I'
LOAD
THE
ADDAESS
REQUEST
SECTOR
lOT
XOA
REQUEST
TRACK
1
10
Aoil 1)0,,5"" I
VIA
HALT
rLAG
CRROR
ERROR
Or
TA
CERROR
,RROR
ERROR
ERROR
-
ERROR
ERROR
ERROR
IE A
ON
PROGRAM
I-SIT
DELETED
UNIT
1
CO~HAND
rL.AC
DOESN'T
THE
XOR
'I.AG
HAS
OCCURED.
STATUS)
~AY8E
"
SEEK
lOT
CRC
Figure
4-11
RX8E Write/Write Deleted
4-15
Data/Read
Example (Sheet 1
of
2)
Page 57
99
1011J
101
102
103
104
105
106
107
124'
138
1246
139
1247
118
111
112
113
114
115
1H>
117
118
119
12511J
121
121
l22
123
l24
125
126
11251
127
11252
128
11253
129
l311l
131
1254
132
133
134
135
136
125'
137
1IJ256
8257
138
139
Hill
141
142
143
8261
1.44
145
146
147
148
149 0261
151
151
152
153
154
l55
.262
156
157
.:.58
159
1IJ263
...
6'"
161
162
163
1264
164
165
166
167
168
.169
17'"
.i.
71
172
173
22'6
'2.6
74.2
6717
22'7
'2"6
7482
7771
..,311JI
~0.11J
iUII
01'1'
~011l1
0311
02'11
~0111J
IA
CRC
ERROR
I
IINCREMENT
I
lAND
I
lOR
UNTI~
I
I
ITHE
I
ITHE
I
'THERErDRE
I
(CONTENTS
I
I
SEEK.
I
IINCREMENT
I
lAND
I
lOR
UNTIL
I
ITHE
I
KI1U.
I
ITHE
I
PTRY.
CTRy.
STRY.
I
IPROGRAM
'CO~TAINS A 11~
,
~100E.
I
IPROGRAM
I
IWRITE
,
COMI14'lO,
,
IPROGRAI1
I
IUNIT
I
T
•
u:u
I
!pROCRAM
I
SECTOR.
I
IPROGRAM
I
TRACI(.
I
IPROGRAM
1
IAT
THE
I
ItRROR
I
I
"STATUS,
HAS
AND
RETRY
THE
THE
CTRY
lSI
CTRY
.1M'
RETRY
H~T
ERROR
rLAG
ERROR
IS
CNOT] A 'ARITY
IS
MUST
or
INIT
AND
RETRY
THE
THE
CTRY
lSi
STRY
.111'
RETRY
H~T
rOLLowING
-u
rOLLOWING 3 PROGRAM
e
II
III
LOCATION"
LOCATION"
(4),
WRITE
I
~OCATION
IIJ
CI).
OR
I.OCAT
I
II
LOCATION"
I!
~OC'TION
DETECTION
STATUS
1
OCCURED
TEST
THE
CRC
COMMAND
UNTI~
COUNTER
OVERr~OWS
IS
SET
BE A SEEK
THE
TRANsrER
TEST
THE
SEEK
COMMAND
UNTI~
COUNTER
OVERr~ows
PROGRAI1
~OCATIONS
~OCATIONS
MODE"
Ir
DE~ETED
" UNIT"
UNIT
ON
"
"
or
CONTAINS
e-BIT
110DE
COMMAND"
DATA
CONTAINS
1
(21)
SECTOR " CONTA
TRACK"
.STATUS " CONTAINS
AN
ERROR
ERROR
RETMY
THE
CRC
ERROR
ERROR
REGISTER
ERROR
THE
SEEK
ARE
CONTAINS
(14).
I HI
CONTAINS
(ERROR
COUNTER
ERROR
RECOYERS
TO
I
AND
IS
CNOT] A CRC
MITS
11.
RETRY
COUNTER
ERROR
TO
I
REFERENCED
ARE
THE
ERROR
A •
Ir
12-11'
THE
COI1MA~D
oR
READ
THE
UNIT
THE
SECTOR
THE
TRACK
THE
CONTE~TS
r~AG
•
'ROGRAM
IRETRY
IHARO
AND
11 •
IIOT 67X7
PROGRAM
RECOVERS
IRETRY
IHARD
WITHIN
RETRY
IPARITY
ICAC
ERROR
ISEEI(
MODE.
I •
OR
TO
(6).
OR
E~'TY
I
4.
14.
DESIGNATION
1
III,
OR
AOOIlESS
1
TO
I
ADDRLSS
I I
TO
0'
1)
WHICH
CORRESPONDS
ISTATUS
~OCATION
TWE
CRC
ERROR
I)
TilE
SEEK
TWIS
COUNTERS
ERROR
ERROR
OR
111
BE
2111
32
,.
114
TWE
AT
•
COMMAND
ERROR
TO
INITIILIAr
LOCATION • STRY
COMMAND
ERROR
EXAMPLE
RETRY
RrTRY
COUNTER
RETRY
ISSUEO
VIA
BUrrER
OR
••
OR
(1
TO
32
OCTAL
TO
114
OCTA~)
OCTA~
T_ANsrER
TO
ERROR
CTRY
"
"
COUNTER
COUNTER
THE
~CO
(2)
2
OCTA~)
REGISTER
THE
lOT
Figure
4-11
RX8E
Write/Write
4.1.6.2 Empty Buffer Function - Figure
function with interrupts
set in
the
AC
to
indicate
program
to
wait for another
jumps
to
from the sector buffer. When
set, the
program
retries 10 times.
problem in the interface
turned
an
EMPTY
TR.
This process continues until either
off (lOF). The first instruction sets the number
Empty Buffer command and the
to
transfer a word to the
Done
is set, the program tests
If
the
cable.
Deleted
4-12
shows a program for implementing
Data/Read
Example (Sheet 2
command
BUFFER
error persists, a
location. A
64
words or
to
see
hard
if
the error bit
parity
4-16
of
is
loaded. When
jump
is
128
bytes have been
is
error
is
assumed, indicating a
of
2)
an
empty buffer
retries
at
10. A 2
TR
is set. the
is
made back to loop
em
ptied
set. If the error bit is
Page 58
228
229
230
231
232
233
234
235
236
237
238
239
24e
241
242
243
244
245
246
247
248
249
2"
2'1
252
253
254
2"
256
257
258
259
2U
261
262
263
264
26'
266
267
261
269
27111
211
272
273
214
276
277
278
219
2U
281
282
283
284
285
1312
12'4
1313 3255
11314
1377
131'
3011
1316
12611
.:517
1261
IUZI
67n
1321 6113
1U22 7418
'323
un
1324
61.,
'n' 5274
67'4
1326
1327 7412
1:53.
22"
13:51
'314
1332
7482
UJ3
6712
1:5J4 3418
UJ'
'321
13317
1311
a
40111
1iJ41111
Utili
run
ITHt
rO~~OWING
I
IEMPTY
T~t
I
IEMPTY
I
EtNTRY,
e::stTuP,
I
IWAIT
I
10ATA
I
IWAIT
I
ITESTING
I
ELOOP,
I
ITHE
I
ITEIT
I
I
IINCREMENT
I
lAND
I
lOR
I
I
ITHE
I
11~~N~f~~
I
EMPTY,
SECTOR
THE
SECTOR
TAD
DCA
TAD
OCA
TAD
TAD
~CD
rOR A TR'NsrER
BurrER
rOR A DONE
THE
STR
SJ(P
.,11'11'
SON
JI~'"
DONE
'LAG
ro.
ANV
AND
RETRV
THE
U~TIL
THE
III
",I'll'
HI.
T
TRANS'ER
~.TA
XgR
DCA
JHI'
!tACt
ITHE
rOLLOWING
I
BurrtR, I
e8u,rER+2U
s
IS A PROGRAMMING
BurrER
or
BurrER
or
KMU
PTRy
(BUrrtR-l)
Al.
HOOt
CO"HAND
REQUEST
rROM
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RX8E
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4.1.6.3 Fill Buffer Function - Figure 4-13 presents a
very similar
to
the empty buffer example.
4.1.7 RX28 Programming Examples
and
Figures 4-14, 4-15,
for fill buffer functions,
to the
RX8E
programming examples described in Paragraph 4.1.6. Basically, there are two differences
between the RX8E
bit mode
command
as
there
of
operation, it
word (see location 0225 in Figure 4-14); second, for the RX28, there
is
in the RX8E; instead there
4-16 are programming examples for write, write deleted
and
for empty buffer functions, respectively. These examples are very similar
and
RX28 examples. First, for
is
transferred in two 8-bit words using an
is
a density
the
error
4-17
Buffer Example
program
to implement a fill buffer function. It
RX28 when a
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or
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is
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to
transfer the second
is
no parity
error
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8-
check
Page 59
174
175
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4-18
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Figure 4-15
RX28 Fill Buffer Example
4-21
Page 63
un
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Figure 4-16
RX28 Empty Buffer Example
4-22
Page 64
4.1.8 Restrictiom and Programming Pitfalls
of
11
A set
1.
restrictions and programming pitfalls for the
When performing the following sequence
STR
SKP
JMP
SON
JMP
(done)
(fill or empty buffer)
If
interrupts are
not
off, the following sequence
enabled and the RX8E issues an interrupt request just before the
instruction will be executed as the last legal instruction before the processor takes over.
is
However, since the done flag
cleared
the device that issued the interrupt.
2.
The program must issue an SER instruction to test for errors following an
3:
For maximum data throughput for consecutive writes or reads
in
every three sectors;
12-bit mode, interleave every two sectors. (This
program overhead.)
RX8E
of
instructions, interrupts
of
by
the
SON
is
events will occur. Assume interrupts are
instruction, the processor will not find
presented below.
must
SON
instruction; the
SON
in
8-bit mode, interleave
of
course depends on
be off.
SON
instruction.
4.
When issuing the JOT
377
must be given because the most significant bits (0-3) contain
XOR
at the end
of a function
to
test
the
~tatu5>
part
the instruction
of
the previous com-
mand word.
5.
If
an error occurs and the program executes a read error register function (111) (Paragraph
4.1.4.9), a parity error may occur for that command. The error code coming back would
be for the original error in which the read error register function was issued, but for the
parity error resulting from the read error register function. Therefore, check for parity error
with the read status function (101) before checking for errors with the read error register
function (111).
SEL
6. The
either drive,
7.
It
is
Fill Buffer
8.
Sector Addressing: 1-26 or 1-328
OR V ROY
or
at
not necessary to load the drive select bit into the command word when
(000)
Track Addressing: 0-76
9.
If
a read error register function (111)
before a read status function (101), because the content
bit
is
present only
completion
or
Empty Buffer (001).
or
of
1-1148
at
the time
an Initialize for drive
(No
sector 0)
is
desired, the program must perform this function
of
the read status function (101) for
O.
the
of
the
error register
is
always modi-
fied by a read status function.
10.
The instructions STR, SON, SER also clear the respective flags after testing
is
software must store these flags if future reference to them
needed after performing one
these instructions.
AND
not
command is
so
that the
of
4-23
Page 65
11.
Excessive use of the read status function (101) will result in drastically decreased throughput
because a read status function requires between one and two diskette revolutions
250
ms
to complete.
or
about
4.2
RXll
and
RXVll
PROGRAMMING INFORMATION
This section describes device registers, register and vector address assignments, programming specifi-
cations, and programming examples for the
All software control
and status
(RXCS) register
of
the
RX11
/RXV11
and
a multipurpose data buffer (RXDB) register. These registers have been
is
RXll
performed
and RXV11 interfaces.
by
means
of
two device registers: the command
assigned bus addresses (Paragraph 4.2.1) and can be read or loaded, with certain exceptions, using any
instruction referring to their addresses.
RX02, which includes the mechanical drive(s), read/write electronics, and
The
J.LCPU
controller, con-
tains all the control circuitry required for implied seeks, automatic head position verification, and
of
calculation and verification
the CRC; it has a buffer large enough to hold one full sector
data (128 8-bit bytes). Information is serially passed between the interface and the
A typical diskette write sequence, which
1.
Fill Buffer - A command to
is
initiated by a user program, would occur in two steps:
fill
the buffer is moved into the RXCS. The Go bit (Paragraph
4.2.2.1) must be set. The program tests for transfer request (TR). When
of
128
bytes
of
data
to
program moves the first
moved into the RX02. The program retests
true. When the RX02 sector buffer
is
full, the Done bit will set, and an interrupt will occur if
the RXDB.
TR
and moves another byte of data when
TR
goes false while the byte
RX02.
TR
of
diskette
is
detected, the
TR
is
is
the program has enabled interrupts.
2.
Write Sector - A command to write the contents
RXCS. Again the
Go
bit must be set. The program tests
program moves the desired sector address
handles the sector address. The program again waits for
TR
is
address to the RXDB, and again
negated. The RX02 locates the desired track and
sector, verifies its location, and writes the contents
When this
is
done, an interrupt
will
occur if the program has enabled interrupts.
of
to
the RXDB.
the buffer onto the disk
TR,
and when
TR
goes false while the RX02
TR
and moves the desired track
of
the sector buffer onto the diskette.
is
issued to the
TR
is
true, the
A typical diskette read occurs
(iead sector) and then unloading the buffer into core (empty buffer). In either case. the content
buffer is not valid if Power Fail or Initialize follows a
injust
the reverse way: first locating and reading a sector into the buffer
fill
buffer or read sector function.
4.2.1 Register and Vector Addresses
RXCS register is normally assigned Unibus address 177170 and the RXDB register
The
is
Unibus address 177172. The normal BR priority level
different priority plug located on the interface module. The vector address
5, but it can be changed
is
264.
by
insertion
is
assigned
4.2.2 Register Description
4.2.2.1
with bit
RXCS - Command and Status (177170) - Loading this register while the RX02
0 = 1 will initiate a function
as
described below and indicated in Figure 4-17. Bits 0-4 are write-
is
not busy and
only bits.
4-24
of
the
of
a
Page 66
15
14
13 12
11
10
09
08
07
06
05
04
03
02
01
00
Bit No.
o
1-3
I I
ERJOR I
RX
INIT
Description
Go
- Initiates a
Function
described in
Code
000
001
010
011
100
101
110
III
I
[
v
NOT USED
Figure 4-17
command
Select - These bits code
Paragraph
RXCS
to RX02. This
4.2.3. These are write-only bits.
Function
Fill Buffer
Empty
Write Sector
Read
Sector
Not
used
Read
Status
Write Deleted
Read
Error
Format
one
Buffer
RegIster
J
TR
of
Data
I
I I
FUNCTION
I
I
D~NE
INT
ENS
(RXll,
is
a write-only bit.
the
eight possible functions listed below
Sector
I
UNIT
SEL
RXVll)
I
GO
MA-1864
and
4 Unit select - This bit selects one
is
function. This
5
6
7 Transfer Request - This bit signifies
8-13
14
Done
- This
when asserted
Interrupt
has completed
the
available. This
Unused
RX
initializing all devices
Upon
head position mechanism
successful Initialize, the
and
drive
Enable - This bit is set by the
time a function
Initialize - This bit
setting this bit in the RXCS, the RX
set
RXES
O.
a write-only bit.
bit
indicates the completion
if
Interrupt
an
operation (Done).
is
is
a read-only bit.
Loading the lower byte
the upper byte
bit 7
(DRV
Enable (RX2CS bit 6) is set. This
initiated. This bit is cleared by Initialize
is
set by the
on
the Unibus. This
of
of
RX02 will zero the
RDY)
of
CAUTION
the
RXCS.
drive I (if
if unit 0
the two possible disks for execution
of
program
The
condition
that
program
of
the RX
two
are available)
is
a function.
to enable an
the
RXII
to initialize the
is
a write-only bit.
CS
will also load
II
or
RXVII
error
and
ready. It will also read sector 1
Done
will generate an
is
a read-only bit.
interrupt
of
this bit is normally determined
and
is a read/write
or
RXVII
will negate
to
track
status register, set Initialize
needs
RXII
O.
Upon
or
Done
of
the
desired
interrupt
when the RX02
bit.
data
or
has
data
RXVII
completion
and
of
without
move
Done,
track
of
1 on
at
the
a
4-25
Page 67
Bit No.
Description
15
4.2.2.2 RXDB between
protocol
This register
manipulated without affecting
register
TR
is set.
4.2.2.3 RXTA - RX
77
(114g) tracks a given function
function in progress (Paragraph 4.2.3). Bits 8-15 are unused
Error
attempt
command
the
of
the function in progress (Paragraph 4.2.3).
will only accept
..
- This bit
Data
RX02
is
and
read/write
14
15
is
set by the RX02 to indicate
to
execute a command. This read-only bit
or
an
Initialize (Paragraph 4.2.6).
Buffer Register (177172) - This register serves as a general purpose
the interface. It may represent
if
the RX02 is
the
RX02 subsystem.
data
if
RXCS
Violation
may cause permanent
Track
Address (Figure 4-18) - This register is loaded to indicate on which
13
11
12
NOT USED
not
bit
7 (TR)
of
protocol
is
to operate.
10
in
the
CAUTION
in
manipulation
data
It
08
09
is
one
process
If
set. In addition, valid
loss.
can be addressed only under the protocol
07
0
~
of
the RX02 is actively executing a command, this
06 05
that
an
error
has occurred during an
is
cleared by
of
four RX02 registers according to the
executing a command;
of
this register
and
are ignored by the control.
03
04
I
I I I
114
0-
data
T
the
initiation
data
that
is, it may be
can only be read when
01
CP
00
~
1510
02
8
of
a new
path
of
the
of
the
Figure 4-18
4.2.2.4 RXSA - RX Sector Address (Figure 4-19) - This register is loaded to indicate
26 (328) sectors a given function is to operate.
function
in
progress (Paragraph 4.2.3). Bits 8-15 are unused
14
15
I
\
13
I
NOT USED
Figure 4-19 RXSA
12
11
Y
10
RXTA
09
Format
It
can
07
08
0
Format
4-26
(RXll/RXVll)
be addressed oniy under
and
are ignored by the control.
04
03
06
05
0
0
l
(RXll/RXVll)
02
V""
1-32
8
the
01
I I I
on
which
protocol
00
CP-1511
of
of
the
the
Page 68
4.2.2.5 RXDB - RX
media passes through this register and
ress (Paragraph 4.2.3).
Data
Buffer (Figure 4-20) - All information transferred
is
addressable only under
the
protocol
to
of
and
from the floppy
the
function in prog-
15 14
I I
4.2.2.6 RXES - RX Error and Status (Figure 4-21) - This register contains the
status conditions
addressed only under the protocol of the function
located in the
RXDB
15
13 12
I I I I
of
the drive selected by bit 4
upon
14 13
NOT
11
Figure 4-20
completion
11
12
'Y
USED
10 09 08
I I
RXDB
(Unit
of
a function.
10
09 08
I
~
UNiT
SEL
07 06 05 04
I I I I
Format
in
I
(RXI1/RXVll)
Select)
07
DRV
RDY
of
the RXCS. This read-only register can be
progress (Paragraph 4.2.3).
05
06
I
DD
I
DRV
DEN
I I I I
04 03
I~~~I
03
02
02
iD
01
The
01
00
I
MA·1866
current
RXES
00
CRC
MA·1867
error
and
content
is
RXES bit assignments are:
Bit No.
o
2
3
Description
CRC
Error
- A cyclic redundancy check
from a
are asserted.
Initialize
routine which can be caused by
mable
data
field
Done
or
Unibus Initialize.
Figure
4-21
of
the diskette. The RXES
- This bit
RXES
is
asserted in the
Format
RX02 power failure, system
4-27
(RXll,
error
is
RXES
RXVll)
was detected as information was retrieved
moved
to
the RXDB, and Error and
to
indicate completion
power
of
failure,
Done
the Initialize
or
program-
Page 69
Bit
No.
Description
6
4
5
7
Density Error - This bit
not
match the drive density. Upon detection
ation
and
Error and Done are asserted.
Bits 4
density when the
Drive Density - This
asserted, double density
Data
Deleted
Detected - During data recovery, the identification mark preceding the data
is
asserted to indicate the density
and S are
bit
indicates the density
is
NOTE
asserted
system
indicated.
of
this error the control terminates the oper-
for the occurrence
is RXOl-compatible.
of
of
the diskette in the drive selected. When
of
the function
double
in
progress does
field was decoded as a deleted data mark (Paragraph 1.5.3.2).
is
Drive Ready - This bit
asserted if the unit currently selected exists, is properly supplied
with power, has a diskette installed correctly, has its door closed, and has a diskette up
speed.
The
drive ready
read
status
when
it
If
the
error
not
set
in
accessed
graph
4.2.3.7).
function
indicates
bit
was
the
RXES,
via a
NOTE
bit
is only valid when retrieved via a
or
status
NOTE
set
in the
specific
read
error
1
at
completion
of
drive
O.
2
RXCS
register function
error
but
conditions
of
error
Initialize
bits
are
can
be
(Para-
to
8
4.2.3 Function Codes
Following the strict protocol
RXVII
of
protocoi can be permanent
A summary
Unit Select - Drive 0 is selected if this bit is
of
the individual function, data storage and recovery
occur with careful manipulation
data
of
the function codes
000
001
010
011
100
101
110
111
Fill Buffer
Empty ButTer
Write Sector
Read
Sector
Not
used
Read
Status
W rite Deleted
Read Error Register
of
the RXCS and RXDB registers. The penalty for violation
loss.
is
presented below:
Data
Sector
"0";
drive I
is
selected if this bit
on
the
is
a
RXll
"1."
and
The following paragraphs describe in detail the programming protocol associated with each function
encoded and written into
RXCS bits 1-3 if
Done
is
set.
4-28
Page 70
4.2.3.1 Fill Buffer (000) - This function
the
from
has been filled. The contents
host processor. Fill buffer
of
the buffer can be written onto the diskette by means
is
used to fill the RX02 buffer with
is
a complete function in itself; the function ends when the buffer
128
8-bit bytes
of
of
a subsequent
data
write sector function, or the contents can be returned to the host processor by an empty buffer func-
tion.
RXCS bit 4
command has been loaded, RXES,
of
byte
appropriate number
each byte
bytes
and
ignored by the RX
4.2.3.2 Empty Buffer
data
bytes loaded from a previous Read Sector
RXCS bit 4
same manner as for the fill buffer
When
RXI1/RXVII
RXDB~
until
128
(Unit Select) does not affect this ftinction since no diskette drive
OUT,
the data may be loaded into the data buffer. The control then clears
of
shift pulses to store the data, again asserts
of
data is loaded. The RX02 counts the bytes transferred; it will
will ignore those in excess. Any read
II
/RXVII.
When the complete buffer has been filled, the control asserts Done.
(001) - This function is used to empty into the interface the buffer
(Unit Select) and negate Done.
but
TR
sets, the program may unload the first
again negates
TR.
When
which again negates TR. Alternate checks on
bytes
of
data have been moved from the RXDB. Done sets, ending the operation.
The empty buffer function does not destroy the con-
of
tents
the sector buffer.
and Done are cleared. When the
TR.
of
the
or
Fill Buffer command. This function will ignore
For
this function,
the buffer
is
emptied.
of
TR
resets, the second byte
TR
NOTE
RXDB
128
and
during
TR
and shift pulses are generated
data bytes from the RXDB. Then the
data transfers from the RXDB
is
involved. When the
TR
bit
is
asserted, the first
TR
and after supplying the
The same
the
of
data may be unloaded from the
TR
cycle
not
accept less than
cycle
of
128
will
occur as
transfers
of
the
~unlinue
in
128
is
128
the
4.2.3.3 Write Sector
(010) - This function
sector with the contents
of
the internal sector buffer. The initiation
is
used
to
locate a desired track and sector and write the
Done.
When
negate TR. When
RXDB, which will negate TR.
operation, move the contents
initiate an interrupt if RXCS bit 6 (Interrupt Enable)
TR
locate the desired sector within two diskette revolutions, the
move the contents
interrupt if RXCS bit 6 (Interrupt Enable)
TR
is
asserted, the program must move
TR
is
again asserted, the program must load the desired track address into the
If
the desired track
of
the RXES to the RXDB, set RXCS bit
the
desired sector address into the RXDB, which will
is
not found, the
is
set.
will remain negated while the RX02 attempts to locate the desired sector.
RXll/RXV11
of
the RXES to the RXDB, set RXCS bit
is
set.
15
(Error), assert Done, and initiate an
4-29
of
this function clears
RXII/RXVII
15
(Error), assert Done, and
If
the RX02
will
will abort the operation,
TR
abort
is
unable to
and
the
Page 71
If
the desired sector
internal
RXll/RXVl1
Enable) is set.
buffer followed by a 16-bit
is
successfully located,
ends the function
CRC
by
asserting
the
RXll/RXVll
character
Done
will write
that
is automatically calculated by the RX02.
and
initiating
an
interrupt
the
128
bytes stored
if
RXCS
in
the
The
bit 6 (Interrupt
The contents
after a power loss has been detected by the RX02.
The
write sector function, however, will
as a valid function, and the random contents
buffer will be written, followed by a valid
The
write sector function does not destroy the con-
tents
of
Read
4.2.3.4
contents
RXES,
When
negate
RXDB,
If
RXES
(Interrupt
TR
the
presumably correct track, the RX
to
Enable)
Done,
TR
TR.
the desired
to
and
RX02
the
RXDB,
Sector (011) - This function is used
of
the
data
field to
and
OUT.
is asserted, the
When
which will negate
the
Enable) is set.
Done
is
is
set.
TR
track
is
not
RXDB,
will remain negated while the RX02 attempts
unable
set
set
to
RXCS
the
program
is
again asserted, the
TR.
found,
RXCS
locate the desired sector within
bit
15
(Error), assert
NOTE
of
the sector buffer
NOTE
the sector buffer.
J,LCPU
the
bit
controller
must
load
RXll
15
(Error),
11/RXVll
the desired sector address into the
program
/RXVl1
\vill
Done,
1
are
not valid
be
2
to
locate
sector buffer. The initiation
will
assert
abort
and
a desired
must load the desired
abort
the
Done,
the
and
to
locate the desired track
two
diskette revolutions after locating the
operation,
initiate
an
data
accepted
of
the
CRC.
track
operation,
initiate
move the contents
interrupt
and
sector
track
move the contents
an
interrupt
if
and
of
this function clears
RXDB,
address into
if
and
RXCS
bit 6
transfer
which will
RXCS
sector.
of
the
RXES
(Interrupt
the
the
of
bit 6
the
If
If
the desired sector is successfully located, the
mark
or
a deleted
the
sector
If
the
the
sector buffer, a
non-zero residue indicates
and
to
the
4.2.3.5 Read
the
current
the
drive selected
RXES
RXCS
RXES
into
deleted
RXCS
RXDB,
bits will reflect
bit 5 (Done)
bits
data
address mark.
the sector buffer.
data
address
CRC
bit
15
(Error).
sets
Done,
Status
contents
are
(101) -
of
the
by
RXCS
the
is again asserted.
defined
in
If
either
mark
was detected,
is computed,
that a read
The
RXl1/RXVl1
and
initiates
The
RXES
bit 4 (Unit
conditions created by
Paragraph
The
average time for this function is 250 ms. Excessive use
reduced throughput.
based
error
an
RXll/RXVl1
into
the
Select) at the time
An
4.2.2.6.
of
this function will result in substantially
control
mark
the
on
the
has
occurred.
ends
interrupt
will negate
RXDB.
interrupt
NOTE
4-30
will
attempt
is
properly located,
control
the
RXES
the
will
will assert
data
field
The
operation
if
RXCS
RXCS
bit 7 (Drive Ready) will reflect the status
the
read
last
command.
occur
to
locate a
the
RXES
and
CRC
bytes previously recorded. A
control
by moving
bit 6 (Interrupt
if
RXCS
sets
bit
5 (Done)
status function was given. All
RXES
bit 6
standard
control will read
bit 6
(DD).
RXES
the
(Interrupt
bit 0 (CRC
contents
Enable) is set.
and
begin
may be sampled when
data
address
data
from
As
data
enters
Error)
of
the
RXES
to
assemble
of
other
Enable) is set.
Page 72
4.2.3.6 Write Sector with Deleted
sector) with the exception
ard
data address mark (Paragraph 1.5.3.2).
that
a deleted data address mark precedes the
Data
(110) - This operation is identical to function 010 (write
data
field instead
of
a stand-
4.2.3.7 Read Error Code Function
error information provided by the
tion
is
initiated, and bits
0-6
controller then generates the appropriate number
the interface register
and
completes the function by asserting Done.
(Ill)
#LCPU
of
the RXES
- The read error code function can be used
controller upon detection
are
cleared. Out
of
shift pulses
read and the error code interrogated to determine the type
NOTE
Care should be exercised
in
the use
since under certain conditions, erroneous error infor-
mation may result (Paragraph 4.2.5).
4.2.3.8 Power Fail - There
senses a loss
of
power, it
is
no actual function code associated with Power Fail. When the RX02
will
unload the head
and
abort all controller action.
invalid while power is low.
When the RX02 senses the return
1.
Move drive I head position mechanism to track
2.
Clear any active error bits.
3. Read sector 1
of
track.l
4. Set RXES bit 2 (Initialize Done)
5.
There
Set Drive Ready
is
no guarantee
of
that
information being written
However, all other information
of
power, it will remove
of
drive 0 into the sector buffer.
(Para~raph
the RXES according to the status
at
on
the diskette will remain unaltered.
to
retrieve explicit
of
the general error bit.
is
asserted
to
transfer the specific error code to
The
of
failure that occurred (Paragraph 4.2.6).
of
this function,
Done
and begin a sequence to:
and
Done
is
negated.
interface register can now be
All
status signals are
O.
4.2.2.6) after which
of
drive
the time
of
a power failure will be retrievable.
Done
O.
is
again asserted_
The
func-
The
of
A method
aborting a function
through the use
console
START
of
the system Initialize signal
key,
or
system power failure.
is
through the use
that
of
RXCS
is
generated by the
bit
4.2.4 Programming Examples
4.2.4.1 Read
Data/Write
Data
- Figure 4-22 presents a program for implementing a write, write
deleted data, or a read function, depending on the function code
up
the error retry counters,
word for a write, write deleted data,
of
The set
three instructions beginning at the label
after transfer request (TR), which
move the track address to the
ning at the label
3$
looks for the done flag to set
An error condition, indicated by bit
error has occurred, and a branch
to
PARER.
made to
refilled by a
If
neither
SEEKER,
JMP
where the system is initialized. In the case
to
FILLBUF.
PTRY,
CTRY,
or
is
bit
read into the RXCS.
7,
has been set. The three instructions beginning
RXll/RXVII
15
setting, is checked beginning at
is
made
to
of
the above occurs, a seek
In the case
and
STRY. The instruction
1$
moves the sector address
after
TR
has been set.
and
checks for errors.
CRCER.
of
a read function, a
If
a parity error has occurred, a branch is
error
is
assumed to have occurred and a branch
of
14
(RX Initialize). Another method is
that
The
PDP-II
is
used. The first instructions set
ERFLAG.
RESET instruction,
RETRY
moves the
to
the
RXll/RXVII
at
command
the label
group of instructions begin-
If
bit 0
is
set, a
CRC
made
a write function, the sector buffer is
JMP
is
made to
EMPBUFF.
the
2$
is
4-31
Page 73
1
2
3
4
,
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I
9
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12
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14
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16
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2.
21
22
23
24
2'
26
27
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29
3.
31
32
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33
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34
1il
3'
36
37
......
31
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42
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Figure
4-22
RXll/RXVll
Write/Write Deleted
4-32
Data/Read
Example
Page 74
In
each
of
the
menting
counters can
the
PAR,
respective retry counter.
be
set
CRC,
up
and
SEEK
to
retry as many times as desired.
A
fiU
buffer function is performed before a write
function, and an empty buffer function is performed
after
a read function.
routines,
If
an
error
the
command
persists
NOTE
after
sequence
10
tries, it is a
is
retried
10
hard
times by decre-
error.
The
retry
4.2.4.2 Empty Buffer Function - Figure 4-23 shows a
function.
is placed in register
error
loaded
If
no
retested if
core
set.
4.2.4.3 Fill Buffer Function - Figure 4-24 presents a
very similar
4.2.5 Restrictions and Piogramming Pitfalls
A set
The
first instruction sets the
is
checked
again.
error
locations
of
restrictions
I. Depending
imum
mended.
2.
If
may
error
If
is
indicated,
TR
is
of
to
the
an
error
occur for
code
starting
an
not
BUFFER.
interleave
number
RO,
and
the
Empty
at
instruction 3$.
error
persists for 10 retries,
the
program
set. Once
empty
and
programm
on
how
occurs
that
function was originally required.
TR
The
process continues until
buffer example.
much
of
two
sectors
and
the
command.
Buffer
looks
sets, a byte is
ing pitfalls
data
program
of
error
command
If
a
parity
the
for the transfer request
moved
for
handling
may
be used,
executes a read
The
error
error
error
program
the
is
done
but
status
program
retries
is placed in
is detected,
is
from the
the
sector
RX
11
by
to
would
for implementing
to
10.
The
address
the
RXCS.
the
Empty
considered
to
implement
/RXV
the
be safe a three-sector interleave
error
not
hard.
(TR)
flag
to
RX
11
/RXV
buffer
II
program
code
is
empty
a fill buffer function. It
is presented below.
between sectors, the min-
function (111), a pari ty
be for
the
error
an
of
the
memory
Existence
Buffer
set.
The
11
sector buffer
and
the
in which
empty
buffer
buffer
of a parity
command
error
flag is
to
Done
is
recom-
error
the
is
the
bit is
is
read
3.
The
DRV
SEL
ROY
bit
is
only
updated
drives,
other
4. It is
Buffer
5.
Sector Addressing: 1-26
Track
6. A power failure causing the recalibration
same as finishing reading a sector. However,
Done)
7.
Excessive use
put,
about
and
after
an
Initialize,
functions
not
required
(000)
Addressing: 0-76
will set. Checking this bit will indicate a
because a read
250 ms to complete.
it
reflects the drive status
to
load
or
Empty
of
Buffer (010).
the
read status function
status
depending
the
Drive Select bit into the
(No
sector 0)
function requires between
4-33
at
the time
on
the
of
the last
of
the drives will result in a
during a power
(l
01) will result in drastically decreased
of
status
power
a read
of
drive
Read
RXCS
fail
one
status
O.
At
Status
condition.
and
or
when the
failure,
two
function (101) for
the
termination
Initialize
command
Done
RXES
diskette revolutions
of
command.
condition,
bit
2 (Initialize
through-
both
is
any
Fill
the
or
Page 75
1611
161
162
163
164
01111242
165
nI2',
166
nl254
167
168
169
171
171
172
173
174
175
176
""'262
177
111266
178
01.2711 332767
179
01111276
181
181
182
183
184
185
nUf/JfI
186
018304
187
nUB6
188
189
1911
191
192
193
194
195
iilU311
196
~BU14
197
;.lU3l6
198
199
2011
201
202
203
""1321
204
BU324
206
207
11Je!!!326
20!
U133,
209
~IIIU32
21111
211
2:.2
213
214
215
0Ull4
216
217
218
219
2211
01U36
221
222
223
224
"'134,
225
226
227
228
229
231
231
232
a12767
312711111
"16767
ln767
811114
001771
"'0,767
11101101
001'01
"U267
2111113"
00U00
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idUI0.
:J"I!IIi!J"1II
"11111111'
001'011
on,40
214'100
31111342
30111'42
IIIU'01
177770
O~"'342
kHllllll54
1767212
176664
:'J01U2
176646
l1li11156
176716
,
,EHpTY
TWE
J
EEt4TRYI
ESETUP,
,
,WAIT
IDATA
,WAIT
I
"RIOR
I
ELOOPI
I
,THE
,
iTEST
,
IINcrEHE~T
,
IANO
I
lOR
UNTIL
,
15:
I
iTHE
,
JTRANS'ER
,
EMPTYI
ITHE
,
PTRY:
CTRY:
STRY:
,
IPRO~RAH
,
IWRITE
J
COI1~A~OI"
J
,PROCRAM
,
SECTOR:
I
IPRO~RAM
,
TRACK
,
iPROCRAM
,
DONUlTa4,
INI1-411
BurrER-,
SECTOR
HOV
'-11,
HOV
'lurrER,
HOV
COHHA~D,
'OR A TRANSrER
Bur'ER
rOR A DONE
TO
TESTIN G THE
TSTI
tiMI
t;"4PTY
lIT
'OON£IIT,
IEQ
ELOOP
DONE
rLAG
'OR
ANY
TST
RXCS
IN£
11
HALT
ANO
RETRY
THE
THE
INC
PTRY
aNE
ESETUP
HALT
TRANSrER
DATA
HOVI
1Ft
ELOOP
rOLLOWING
LOCATION"
(4),
WRITE
LOCATION
III
LOCATION • TMACK " CONTAINS
I "
EQUIVALE~TS
..
,.aun"ER·ZIIII
.END
pTRY
rRON
THE
rLAC
RXCS
15
SET
ERRORS
TEST
COHMANQ
pTRY
REQUEST
TO
THE
Rxoa,
3
PROGNA~
DELETED
"
BurrER or 121
M'
RXCS
REQUEST
rLAC
RX'l
lECTOR
TO
I~DICATE
ERROR
rLAC
RXCS
(ONLY
ERROR
THE
PARITY
UNTIL
THE
CUNTER
OVER'LOWS
'LA~
Is
SET
P~O~RA"
'(M').
LOCATIO~S
CO""AND
•
CONTAI~S
DATA
S~CTOR
•
CONTAINS
a.IIT
•
TRYS
PROHCR'MI
ISSUE
IE'ORE
IU"ER
THt
COHpLETIo~
TEST
INt
lr
TEIT
I[Q
UNTIL
poSSIILE
ERROR
RETRY
ERRoR
TO
RtTRY
~AAD
DATA
su,rER
ARt
i
PARITY
;
CRC
ER~O~
i
SEEK
(14),
OR
; 4, 14, 6,
THE
; 1
TO
TH[
i I
TO
IYTES
TO
EHPTY
OAT
A Burr'R
THE
COHMANO
TRANS'ERRING
rOR
TRANsrER
TRA~S'ER
'OR
DONE
'LAG
THE
DONt
IS A PARITY
P.OGRAM
RECOVERS
I
TO
EMPTY
PARITY
ERROR
rRO"
THE
T~[
[.ROR
[RROR
RETRY
_tfRy
ERROR
RETRY
T~E
COMMAND
READ
(6),
eR
2 •
SECTOR
31
OCUL
TRACK
AOORESS
114
OCTAl.
THE
lECTOR
DATA
TO
0'
THE
EMpTY
REoutlT
REQUEST
rLAC
'LAG
'LA'
IETI
rRROR)
LOCATioN • pTRY
THE
SrCTOR
BurrER
RX'l
SECTOR
RtTRY
COUNTERS
COUNTER
COUHlt-
COUNTER
TO
IE
IISUED
OR
E"PTY
Bur'ER C2)
(GO
lIT
1 • 1)
AODRtlS
(1
TO
II
TO
114
8urrER
THt
IUrrER
II
BurrER
VIA
32
OCTAL)
PROGRAM,
CO""AND
SET
•
THE
~CO
OCT'~)
lOT
Figure 4-23
RXII/RXVll
4-34
Empty Buffer Example
Page 76
111
112
113
114
115
116
117
118
1"156
119
111164
121
11'17,
121
122
123
124
125
126
127
128
129
131
11'176
131
1,.202
132
11.214
133 0S1212 011771
134
135
136
137
138
139 011214
141
111221
141
SI1222
142
143
144
145
146
147
148
149
111224
151
181231
151 011232
152
153
154
155
156
111234 113167
157
158
11'24'
~12767
012701
016767
11'767
SI1414
032767
al,767
SI11S1
alllSI
10'267
SI13"
IIIISS
11175.
177773
001342
"31141
176766
01i!1S41
176750
176732
1.1142
176772
176756
ITHE
rO~~OWING
I
Irl~L
THE
I
I
NOTE;
I
I
rENTRY;
SETUPI
I
;WAIT
I
IDATA
1
IWAIT
I
IPRIOR
,
LOOP'
,
ITHE
I
ITEST
I
I
ilNCREMENT
I
lAND
,
lOR
I
11:
I
ITHr
I
ITRANsrER
I
riLL:
THE
EVEN
MOV
MOV
MOV
rOR A TRANsrER
BurrER
rOR A DONE
TO
TST8
.,1'1
lIT
IEQ
DoNE
rOR
TST
INE
HALT
RETRY
UNTIL
INC
aNE
HALT
TR'N~rrR
MOva
IA
IS A PROGRAMMING
lECTOR
BurrER
DATA
To
rlL~
ADORESSEI
'-1'.
PTRY
'8urfER,
COMMAND,
R.
Nxes
REQUEIT
TO
THE
RX'l
rLAT
TO
TESTING
r~AG
ANY
THE
DATA
RXCS
fILL
'DONEIIT,
LOOP
IS
ERRORS
RXCS
11
AND
TEST
THE
COMMANO
PTRY
PTRY
SETUP
Rr~ur~T
rROM
'(RI).,
LOOP
THE
ERROR
RXCS
SET
(oNLY
THE
COUNTER
rl'G
THE
RXOB
WITH
121
THE
SECTOR
IYTES
0'
r~AC
SECTOR
INDICATE
r~AG
ERROR
PARITY
UNTIL
THE
OVER'LOWS
!~
!t.
PROGRAMS
EXAM'~E
a·IIT
IU,rER
121
WORDS
I •
TRYI
;
'ROGRA~S
;
ISSUE
'E'ORE
aU,rER
THE
CO~PLETION
TtST
'EO
l'
TEST
.to
UNTI~
PoSSI.~E
tRROR
RETRY
ERROR
To
~ETRY
WA~O
OAT
A au,rER
;
'ROGRA~S
or
TWE
PROTOCO~
IYTES
CAN
BE
OR
TO
THE
TRA~srERRING
rOR
TRANsrER
'OR
ASIEMI~EO
IH
80TM
'ILL
TME
DATA
IU"ER
COMMAHD
0'
T'AHS'ER
REQUelT
TWE
DONE
'HE
DONE
THE
REDUEST
'~AG
IS A PARITY
PROGRAM
LDCATION • ,TRY
RECoVERS
•
TO
riLL
THE
[RROR
TO
THC
IU"ER
lECTOR
RX'l
'ARITY
DATA
REOUIRED
,YTrl
lECTOR
DATA
riLL
r~AG
ERROR)
SECTOR
IS
IN
CORE
0'
6.
.u,rER
rROM
,ur'ER
'~AG
r~AG
SET
SET'
.ur'E~
64
WOROI
TO
IN
WORDI
TME
'ROGRA"'
COMMAND
•
BurrER
IN
TNE
LENGTH
Figure 4-24
RXll/RXVll
4.2.6 Error Recovery
There are two error indications given by the
RXll
graph 4.2.3.5) will assemble the current contents
sampled
retrieve explicit error information. The
mine the type
to
determine errors. The read
of
failure that occurred. A list
error
RXll
code function (Paragraph 4.2.3.7) can also be used
/RXVl1
of
error codes follows.
NOTE
A read status function is not necessary if the DRV
RDY bit is not going to
RX2ES is
of
every function.
in
the interface register
be
Fill Buffer Example
/RXVll
of
the RXES
system. The read status function (Para-
(Paragraph
4.2.2.6), which can be
interface register can be interrogated
interrogated because the
at
the completion
to
to
deter-
4-35
Page 77
Octal
Code
Error Code Meaning
0010
0020
0040
0050
0070
0110
0120
0130
0140
0150
0160
0200
0220
0240
4.3 RX211 and RXV21
Drive 0 failed
Drive 1 failed to see home on Initialize
Tried
to
Home was found before desired track was reached
Desired sector could
More than
A pream ble could
Preamble found
CRC
error on what appeared to be a header. Error
The header track address
Too many tries for an
CRC
error on reading the sector from the disk
R/W
electronics failed maintenance mode test
Density Error
to
see home on Initialize
access a track greater than
not
be
found after looking
40
#-,s
and no SEP clock seen
not
be found
but
no
ID
mark found within allowable time span
of
a good header does not compare with the desired track
IDAM
PROGRAMMING
(identifies header)
INFORMATION
77
at
52
is
headers
(2
not asserted
revolutions)
This section describes device registers, register and vector address assignments, programming specifications, and programming examples for the RX211 and RXV21 interfaces.
of
All software control
mand and status register
assigned bus addresses
The
RX02 contains all the control circuitry required to read from and write on the disk and to calcu-
the RX211/RXV21
(RX2CS) and a multipurpose data buffer register (RX2DB) which have been
and
can be read or loaded.
late and verify the CRC. It has a buffer large enough to hold one full sector
is
performed by means
of
two device registers: the com-
of
diskette data
(128
or
256
8-bit bytes). Information is serially passed between the interface and the RX02.
A typical diskette write sequence, which
Fill Buffer - A command to
program tests for TR. When
RX2DB.
moves
word
into
fills the remainder
TR
goes false while the word count
the bus address into the RX2DB. The device now requests bus mastership and
at
a time into the RX2DB and shifts it across the RX02 data bus serially one 8-bit byte at a time
the
sector buffer. When the word count register overflows
of
the sector buffer) the Done bit
fill
the buffer
TR
is
initiated by a user program, would occur
is
moved into the RX2CS. The
is
detected, the program moves the desired word count into the
is
moved to the RX02. The program retests
(if
neCeSsaiY,
is
set, and an interrupt will occur if the program
Go
the RX02 control zero-
in
two steps:
bit must be set. The
TR
DMA's
one data
and
has enabled interrupts.
Write Sector - A command
RX2CS. The program tests
TR
remains false while the sector address
when
it
is again set, moves
to
write the contents of the sector buffer onto the disk
TR
and when
the
desired track address register to the RX2DB. Again
TR
is set, moves the desired sector address to the RX2DB.
is
shifted to the RX02 control. The control retests
is
moved into the
TR
is
negated. The
TR
and
RX02 locates the desired track and sector and compares the diskette density against the assigned
function density
the write operation
and
writes the contents
is
completed, the Done bit is set and an interrupt will occur if the program has
of
the sector buffer onto the disk if the densities agree. When
enabled interrupts.
4-36
Page 78
A typical disk read operation occurs in the reverse order. First, the desired track and sector are located
and the contents
sector buffer
are not valid if either a Power Fail or Initialize follows a fill buffer
of
the sector are read into the sector buffer (read sector). Then the contents
is
unloaded into memory (empty buffer). In either case, the contents
or
read sector function.
of
the sector buffer
of
the
4.3.1
The RX211/RXV21 use two registers for
status register (RX2CS) normally assigned bus address
Register and Vector Addresses
comm~nicating
177170
normally assigned bus address 177172. The vector address
4.3.2 Register Description
4.3.2.1
and
Bit No.
RX2CS - Command and Status (177170) - Loading this register while the RX02
with bit
0=
1 will initiate a function as described below and indicated in Figure 4-25.
15 13 12
ERROR
11
10 09 08 07 06 05 04 03 02
RX02
Figure 4-25 RX2CS
INTR
ENB SEL
Format
Description
with the host computer: the command and
and
the data buffer register (RX2DB)
is
264.
is
not busy
01
00
FUNCTION
UNIT
DONE
MA-1906
(RX211/RXV2l)
o
1-3 Function Select - These bits code one
Go
- Initiates a command to RX02. This
is
a write-only bit.
of
the
eight possible functions described in Paragraph
4.3.3 and listed below. These are write-only bits.
Code Function
000 Fill Buffer
00
1
Em
pty Buffer
010 Write Sector
4
011
100
101
110
III
Unit select - This bit selects one
function. This bit
Read Sector
Set Media Density
Read Status
Write Deleted
Data
Sector
Read Error Code
of
the two possible disks for execution
is
readable only when Done is set, at which time it indicates the unit
previously selected. This is a read/write bit.
5 Done - This bit indicates the completion of a function. Done will generate
asserted if Interrupt Enable (RX2CS bit
6)
is
set. This is a read-only bit.
of
the desired
an
interrupt when
4-37
Page 79
Bit No. Description
6 Interrupt Enable - This bit is set by the
completed an operation (Done). The condition
is
a function
7 Transfer Request - This bit signifies
able. This is a read-only bit.
8 Density - This bit determines the density
only when
executed. This is a
9-10
II
12-13 Extended address - These bits are used
14
Reserved for future use. Must be written as zero.
RX02 - This bit is set by the interface to inform the programmer
system. This
only bits.
RX211 /RXV21 Initialize - This bit
without initializing all devices on the Unibus. This
initiated. This
Done
is
set,
read/write
is
a read-only bit.
Loading the lower byte of the
the upper byte
bit
is
cleared by Initialize
that
at
which time it indicates the density
bit.
is
CAUTION
of
the RX1CS.
program
the RX211/RXV21 needs
of
to
declare an extended bus address. These are write-
set by the program to initialize the RX211 /RXV21
to
enable
of
this bit is normally determined at the time
the function to be executed. This
is
RXlCS
an
interrupt when the RX02 has
and
is a read/write
of
a write-only bit.
will
also load
bit.
data
or has
bit
the
function previously
that
this
is
data
avail-
is readable
an RX02
Upon
head position mechanism
of
Done.
IS Error - This bit
to execute a command. This read-only bit
an Initialize.
4.3.2.2 RX2DB between the RX02
protocol
This register is
manipulated without affecting
register
TR
4.3.2.3
4
11
function in progress
of
will
is
set.
RX1T A - RX
8 (0-7610) tracks a given function is
setting this bit in the RX2CS, the RX211/RXV21 will negate Done
a successful Initialize, the RX02 will zero the error
It
will also read sector I
is
set by
Data
Buffer Register (177172) - This register serves as a general purpose data path
and
the interface.
the function in progress (Paragraph 4.3.3).
read/write
only accept
if the RX02 is not in the process of executing a command; that is, it may be
the
data
if RX2CS bit 7 (TR)
Violation
may cause permanent data loss.
Track
(Paragraph 4.3.3). Bits 8-15 are unused and are ignored by the control.
Address (Figure 4-26) - This register is loaded
of
both
drives (if two are avaiiable) to track
and
of
track 1
the
RX02
It
RX02 subsystem.
of
protocol in manipulation of this register
to
may represent one
CAUTION
to
operate.
on
drive 0 into the buffer.
indicate
that
an error has occurred during an attempt
is
cleared
If
the RX02
is
set. In addition, valid data can only be read when
It
can
by
the initiation
of
six
RX02 registers according to the
is
actively executing a command, this
be
addressed only
and
move the
o.
Upon
status register, and set Initialize
of
a new command
to
indicate on which
under
the protocol
completion
or
of
the
of
the
4-38
Page 80
15
14 13
12
11
10
09
08
07
06
05
04
03
02
01
00
I I
0
J
NOT USED
Figure 4-26
4.3.2.4 RX2SA - RX Sector Address (Figure 4-27) - This register
328
(1-2610)
function in progress (Paragraph 4.3.3).
sectors a given function
14
I
\
15
I
13
I
I
NOT USED
Figure 4-27 RX2SA
12
11
Y
RX2TA
is
to
operate. It can be addressed only under the protocol
10
09
Format
08
)
Format
(RX211/RXV2l)
07
06 05
0
0
0
(RX211/RXV21)
't
114
0-
8
is
loaded to indicate on which
04
03 02
l.
V'
1-32
CP
1510
01
00
8
CP-1 51 1
.,
)
of
of
the
the
For
4.3.2.5 RX2WC - RX Word Count Register (Figure 4-28) -
is
word count
beyond the limit for the density indicated, the control asserts Word
RX2ES). This
count
4.3.2.6 RX2BA data transferred during fill buffer, empty buffer,
takes place after a memory transaction has occurred. The RX2BA, therefore,
dress
is
of
the first
12810.
is
loaded into the register.
15
For
a single density sector the maximum word count is
a write-only register. The actual word count and not the 2's complement
14 13
RX
data
12
11
10
09
08 07
] 0
Figure 4-28
Bus Address Register (Figure 4-29) - This register specifies the bus address
word to be transferred. This
RX2WC
Format
and
06
I
..
(RX211/RXV2l)
read definitive error operations. Incrementation
is
a 16-bit, write-only register (Paragraph 4.3.3).
a double density sector the maximum
Count
04
03
02
05
I
T
0-128\ 0
6410.
If
a word count is
Overflow (bit
of
01
00
I
I
MA-1868
is
loaded with the ad
10
of
the word
of
4-39
Page 81
15 14 13
12
11
10 09 08 07 06 05 04 03 02
I I
01
00
MA-1869
Figure 4-29 RX2BA and RX2DB
Data
4.3.2.7 RX2DB - RX
media passes through this register and
Buffer (Figure 4-29) - All information transferred to and from the floppy
is
addressable only under the protocol
ress (Paragraph 4.3.3).
4.3.2.8 RX2ES - RX Error and Status (Figure
status conditions of the drive selected by bit 4
be
addressed only under the protocol
of
located in the RX2DB upon completion
1 5 14 13 12
NOT
USED
11
10 09 08 07 06 05 04 03 02
NXM
WC
OVFL
RESERVED
(Unit Select) of the RX2CS. This read-only register can
the function
of
a function.
UNIT
SEL
Format
(RX211/RXV21)
of
the function
in
prog-
4-30) - This register contains the current error and
in
DRV
ROY
progress (Paragraph 4.3.3). The RX2ES
01
00
DRV
DEN
DO
RX
AC
LO
DEN 10
ERR
CRC
RESERVED
MA-1870
is
Figure 4-30 RX2ES
Format
(RX211 /RXV21)
RXES bit assignments are:
Bit No. Description
o
2 Initialize Done - This bit
CRC
Error - A cyclic redundancy check error was detected as information was retrieved
from a data field
is
moved to the RX2DB, and Error and Done are asserted. It
transfer be retried up to
routine which can be caused by
of
the diskette. The data collected must be considered invalid. The RX2ES
10
times,
is
asserted in the RX2ES
as
most errors are recoverable (soft).
RX02 power failure, system power failure,
or bus Initialize.
3 RX AC LO - This bit is set by the interface
to
system.
4 Density Error - This bit indicates that the density
the drive density.
Upon detection
of
this error the control terminates the operation and
asserts Error and Done.
is
suggested that the data
to
indicate completion
of
the Initialize
or
programmable
indicate a power failure in the RX02 sub-
of
the function in progress does not match
4-40
Page 82
Bit No. Description
5 Drive Density - This bit indicates the density
8).
The
by bit
6 Deleted
address
whether
ing the
further significance
deletion
mark
mark
density
Data
- This bit indicates
was detected
the
mark
will be collected
of
data
7 Drive Ready - This bit indicates
operation
RX02
is currently selected.
empty buffer
may
Select - This bit indicates
Count
Overflow - This bit indicates
Memory
and
the memory address specified in RX2BA
8
10
11
for disk
The
when retrieved via a read status function
Unit
that
Word
or
Nonexistent
performed
of
the drive is determined
at
the beginning
was a single
other
due
to
are satisfied, such as
be
presumed
operation
Error
or
double density deleted
and
than
to
this
mark
that
to
be ready
that
is terminated
- This bit
that
in
the
transferred normally, as
establish drive density. Any alteration
must
be accomplished by user software.
the
selected drive
door
to
or
drive 0 is selected
that
and
is
set by
of
the
diskette in
during
course
of
the
closed, power okay, diskette up
perform any
initialize.
the
Error
the
read
of
recovering
data
data
is
ready if bit 7 = I and all conditions
if
bit 8
word
count
and Done are set.
interface when a
the
drive selected (indicated
and
write sector operations.
data,
the
field.
The
Drv
address mark. The
the
deleted
operation.
=0.
is
is
nonexistent.
This bit is only valid
This bit indicates
beyond sector size. The fill
DMA
Den bit indicates
data
of
transfer
"deleted
data
mark
files
or
to
speed, etc.
the
is
data"
follow-
has no
actual
drive
being
4.3.3 Function Codes
Following the strict
RX211/RXV21 occur with careful manipulation
violation
A
summary
of
protocol can be
of
the
000
001
010
011
100
101
110
III
The
following
encoded
paragraphs
and
written into
4.3.3.1 Fill Buffer (000) - This function
of
data
specified by the
when RX2WC overflows,
of
contents
returned
function
RX2ES.
the buffer may be written on the disk by means
to
the host processor by
is
terminated,
protocol
function codes is presented below:
Fill Buffer
Empty
Write
Read
Set
Read
Write Deleted
Read
describe in detail
RX2CS
RX2WC
and
Error
of
the individual function,
permanent
Buffer
Sector
Sector
Media
Status
Error
register. Fill buffer is a complete function in itself:
if
necessary,
and
data
Density
Data
Code
bits 1-3
is
an
Empty
Done
Sector
the
if
used
the
are
loss.
Done
asserted,
of
the
RX2CS
programming
is set.
to
fill
the
control
Buffer
has zero-filled
command.
and
data
storage
and
RX2DB
protocol
RX02
data
buffer with the
the
of
a subsequent Write Sector
If
the
the
Word
registers.
associated with each function
remainder
word
count
Count
and
recovery
The
number
the
function ends
of
the
is
too
overflow bit is set in
on
penalty for
of
word~
buffer. The
command
large,
the
or
the
4-41
Page 83
To initiate this function the RX2CS
not affect this function since
no
since this determines theword count limit. When the command has been loaded, the Done bit
bit 5) goes false. When the
When
TR
is
again asserted, the RX2BA may be loaded into the RX2DB. The data words are trans-
TR
is
loaded with the function. Bit 4
disk operation
is
involved. Bit 8 (Density) must be properly selected
of
the RX2CS (Unit Select) does
(RX2CS
bit is asserted the RX2WC may be loaded into the data buffer register.
ferred directly from memory and when RX2WC overflows and the control has zero-filled the remainder
of
the sector buffer,
is
Enable)
set, an interrupt
the interface. After Done is true the
if
necessary, Done
is
initiated. Any read
is
asserted ending the operation.
of
the RX2DB during the data transfer
If
bit 6 RX2CS (Interrupt
RX2ES is located in the RX2DB register.
is
ignored by
4.3.3.2 Empty Buffer
through the RX211/RXV21 for use
previous Fill Buffer or Read
The programming protocol for this function is identical to
(001) - This function
by
the host processor. This data
Sector command.
is
used to empty the contents
is
in the buffer as the result
that
for the Fill Buffer command. The
of
the internal buffer
of
RX2CS is loaded with the command to initiate the function. (This function will ignore bit 4 RX2CS,
Unit Select). RX2CS bit 8 (Density) must be selected to allow the proper word count limit. When the
command has been loaded, the
Done
RX2WC may be loaded into the RX2DB. When
the RX2DB. The RX211/RXV21 assembles one word
memory. Transfers occur until word count overflow,
Done goes true.
the RX2
ES
4.3.3.3 Write Sector
with the contents
When
TR.
TR
When
which will drop TR.
The diskette density
do not agree, the operation
(bit
15
RX2CS)
is
set.
If
bit 6 RX2CS (Interrupt Enable) is set, an interrupt
is located in the data buffer register.
(010) - This function
of
the internal buffer. The initiation
is
asserted, the program must load the desired sector address into RX2DB, which will drop
TR
is again asserted, the program must load the desired track address into the RX2DB,
TR
will remain unasserted while the RX02 attempts to locate the desired sector.
is
determined at this time and
is
terminated; bit 4 RX2ES
is
set, Done
is
asserted, and an interrupt is initiated, if bit 6 RX2CS (Interrupt Enable)
bit (RX2CS bit
TR
is
used to locate a desired sector on the diskette and
is
compared to the function density.
5)
goes false. When the
is
again asserted the RX2BA may be loaded into
of
data at a time and transfers it directly to
at
which time the operation
is
of
the function clears RX2ES,
is
set, RX2ES
is
moved to the RX2DB, Error
TR
bit is asserted, the
is
complete and
initiated. After Done
TR,
and Done.
If
the densities
is
true,
fill
a
it
If
the densities agree but the RX02
tions, the interface will abort the operation, move the contents
15
RX2CS), assert Done, and initiate an interrupt if bit 6 RX2CS (interrupt Enabie)
If
the desired sector has been reached and the densities agree, the RX211/RXV21 will write the
or
6410
words stored in the internal buffer followed by a
lated by the
(Interrupt Enable)
RX02. The RX211/RXV21 ends the function by asserting Done and if bit 6 RX2CS
is
set, initiating an interrupt.
is
unable to locate the desired sector within two diskette revolu-
of
RX2ES to the RX2DB, set Error (bit
is
set.
CRC
character which
is
automatically calcu-
CAUTION
The contents
after a power loss has been detected
However,
struction and the (random) contents
be written, followed
of
the sector buffer are not valid data
by
write sector
wHI
be accepted as a valid in-
by
a valid CR C.
of
the buffer
the RX02.
will
NOTE
The contents
of
the sector buffer are not destroyed
during a write sector operation.
4-42
12810
Page 84
4.3.3.4 Read Sector (011) - This function is used to locate the desired sector
of
the data field
(5
ms) the current status
to
the internal buffer in the control. This function may also be used
of
the drive selected.
The
initiation
of
this function clears RX2ES,
Done.
TR
When
drop
RX2DB, which will drop
TR
and
unable
will
abort
RX2DB,
If
the desired sector is successfully located, the control reads the
density
operation
Error) and the
is
initiated.
If
a legal data mark
data from the sector into the internal buffer.
will
set bit 6 RX2ES (DD). As
field and the
curred
ends the operation by asserting
RX2eS is set, an interrupt
is asserted the program must load the desired sector address into the
TR.
When
TR
is
again asserted, the
program
must load the desired track address into the
TR.
Done
to
of
and
will remain negated while the RX02 attempts
to
locate the desired sector.
locate the desired sector within two diskette revolutions for any reason, the RXV21 /RX211
the operation, set
and
if
bit 6 RX2CS (Interrupt Enable) is set, initiate
the diskette.
is
terminated
RX2ES
is
CRC
bytes previously recorded. A non-zero residue indicates
the control sets bit 0 RX2ES
Done
If
the diskette (drive) density does
and
Done
is
moved
and
Error
and
Error
to
the RX2DB.
(bit
15
RX2CS), move the contents
(bit
15
RX2CS) are asserted. Bit 4 RX2ES is set (Density
If
bit 6 RX2CS (Interrupt Enable) is set, an interrupt
successfully located, and the control
If
data
Done
is
initiated.
a deleted
enters the internal buffer, a
(CRC
and
error) and bit
moving the contents
data
an
interrupt.
data
address mark
not
agree with the function density the
and
densities agree, the control will read
address mark was detected, the control
CRC
is computed based on the
15
RX2CS (Error). The RX211 /RXV21
of
the RX2ES into the
and
transfer the contents
to
retrieve rapidly
RX2DB,
of
the RX2ES
and
that
a read error has oc-
which will
If
the RX02
determines the
RX2DB.lfbit
TR,
to
and
is
the
data
6
If
the desired sector
error,
Done
will be set and
is
successfully located, the densities agree,
if
bit 6 RX2CS (Interrupt Enable)
and
is
interrupt.
4.3.3.5
density. Bit 8
ing new
The function
RX2ES and Done. When
the protocol. This extra character is a safeguard against an
Set
Media Density (100) - This function causes the entire diskette
RX2CS (Density) indicates the new density.
data
address marks (double or single density) and zeroing all
is
initiated by loading the RX2CS with the command. Initiation
TR
is
set, an ASCII
"I"
(111) must be loaded into the RX2DB to complete
The
control reformats the diskette by writ-
error
in loading the command. When the
control recognizes this character it begins executing the command.
The control starts at sector
the header information
If
the operation
interrupt
is
is
initiated.
is
successfully completed,
track 0
damaged, the control will
and
reads the header information, then starts a write operation.
abort
the operation.
Done
is set and
if
bit 6 RX2CS (Interrupt Enable)
1,
CAUTION
This operation takes about
be
interrupted.
If
for any reason the operation is in-
15
seconds and should not
terrupted, an illegal diskette has been generated
which may have
diskette
should again be completely reformatted.
data
marks
of
both densities. This
the
data
is transferred with no
CRC
set the RX211 /RXV21 initiates an
to
of
the
be reassigned
data
fields on the diskette.
of
the function clears
to
a new
If
is
set,
an
4-43
Page 85
4.3.3.6 Maintenance Read Status (101) - This function is initiated by loading
command.
the control.
data
RX2CS) is again asserted
operation requires approximately 250 ms
mark.
Done
is cleared.
The
Drive Density is
The
RX2ES is moved
The
Drive Ready
updated
and
if
into
the RX2DB.
bit
RX2CS
bit
(bit 7 RX2ES) is
by loading
(Interrupt
to
complete.
updated
the
head
of
the selected drive
The
RX2CS may be sampled when
by counting index pulses in
Enable) is set, an interrupt will occur. This
the
RX2CS with
and
reading the first
Done
the
(bit 5
4.3.3.7 Write Sector with Deleted Data (110) - This operation
sector) with
the
standard
single
4.3.3.8 Read Error Code (111) -
addition
This is the only way
the
exception
data
address mark.
or
double density deleted
to
the specific
error
that
that
the
a deleted
The
data
The
code a
word
data
Density
address
read
dump
count
address
mark
error
of
the
bit
mark
is written preceding
associated with the function indicates whether a
will
be
written.
code function implies a read extended status. In
control's
internal scratch
register can be retrieved. This function is used
specific information as well as drive status information depending
bit.
The
transfer
the
command
and
TR
of
the registers is a
and
goes false.
DMA
then
Done
goes false. When
The
registers are assembled
transfer.
TR
one
The
function
is
true, the RX2BA may be loaded into the RX2DB
word
at
a time
is
initiated by loading the RX2CS with
Register Protocol
Word I <7:0>
Word
I < 15:8>
Word 2 <7:0>
Word
2 < 15:8>
Word 3 <7:0>
Word
3 < 15:8>
Word 4 <7>
Word 4 <5>
Word 4 <6><4>
Word 4 <0>
Word
4 < 15:8>
Definitive
Word
Current
Current
Target
Target
U nnit Seiect Bit
Head
Drive Density Bit
Density
Track
Error
Count
Track
Track
Track
Sector
Load
Bit
of
Read
Address
Codes
Register
Address
Address
of
Current
of
Current
of
Both Drives
Error
of
Selected Drive
of
Drive 0
of
Drive I
Disk
Access
Disk
Register
Access
Command
is
identical to function 010 (write
the
data
rather
pad
registers also occurs.
to
upon
detection
and
transferred directly
of
the
general
to
memory.
*
*
*
t
than
retrieve
Error
4.3.3.9
unload
RX211/RXV21
the
When
•
t The Track Address
RX02
the
RXAC
the
1.
2.
3.
4. Assert Initialize
For
DMA interfaces the controller status soft register
bits are included
bit 4, Density
of
the cylinder that the head reacheed on a seek error.
Power Fail -
head
and
that
subsystem
L bit in
the
RX02 senses the return
abort
RX2ES.
When
the
all controller action.
power
of
Move each drive head position mechanism
Clear any active
Read sector I
in
an 8-bit word. Unit Select = bit
of
Read Error Register Command = bit
of
error
bits
of
track I,
Done
the Selected Drive - Error is only meaningful on a code
in the RXES.
RX02
control
senses a loss
The
is gone.
The
RX211
power, it will remove
to
on
drive 0
is
sent to the interface at the end
7,
Density
of
O.
4-44
RXAC
L line is asserted to indicate
/RXV21
Done
track 0
Drive I = bit
of
power within
asserts
and
6,
Head Load = bit
150
Done
begin a sequence to:
of
the command. The four status
error. The register contains the address
the
and
5,
Density
RX02,
Error
of
it
win
to
the
and
sets
Drive 0 =
Page 86
Upon completion
mation being written
of
the power up sequence,
at
the time
of
a power failure will be retrievable; however, all other information
Done
is
again asserted. There
is
no guarantee
that
infor-
on the diskette will remain unaltered.
4.3.4 Error Recovery
There are two error indications given by the RX211/RXV21 system. The maintenance read status
function (Paragraph 4.3.3.6) will assemble the current contents
determine errors.
error information.
failure
that
occurred. The error codes
The
read
error
code function (Paragraph 4.3.3.8) can also be retrieved for explicit
The
RX211 /RXV21 interface register can be interrogated to determine the type
and
their meaning are listed below.
of
the RX2ES which can be sampled to
of
Octal
Code Error Code Meaning
0010 Drive 0 failed
0020 Drive 1 failed to see home
to
see home
on
Initialize.
on
Initialize.
0040 Tried to access a track greater than 76
0050 Home was found before desired track was reached.
0070 Desired sector could not be found after looking at
0110 M ore than 40
J.LS
and no SEP clock seen
52
headers
(2
revolutions).
0120 A preamble could not be found.
0130 Preamble found
0150 The header track address
0160 Too many tries for an
0170
0200
0220
Data
AM
not found in allotted tIme
CRC
error on reading the sector from the disk.
R/W
electronics failed maintenance mode test.
but
no
ID
IDAM
mark found within allowable time span
of
a good header does not compare with the desired track.
(identifies header)
No
code appears in the
ERREG.
0230 Word count overflow
0240 Density Error
0250 Wrong key word for set media density command
4.3.5 RX211/RXV21 Programming Examples
4.3.5.1 Write/Fill Buffer
Figure
routines. Initially, the write subroutine tests to see
an error, a branch
fill
Buffer command
RX02/RXCS. After a
the RX02/RXDB. After another
memory
bytes indicated then the RX02 controller sets the
in
the write command and interrupt enable are set, the density
RX02/RXCS. There
another wait for
buffer
4-31
illustrates a program to write data on a disk by performing write and
if
there
is
an error from the last operation.
is
made and the write subroutine
is
not
performed; otherwise a
jump
fill
buffer sub-
If
is
made to the
there
buffer subroutine. (Before data can be written the RX02 sector buffer must be filled.) The Fill
is
set, the density (single
TR
is
received, the word count (for either
TR
is
is
loaded in the RX02/RXDB. The RX02 controller fills the sector buffer with the number
the RXCS and the program halts.) The program returns
is
a wait for TR, then the sector address
TR
and the track address
is
written by the RX02 controller on the selected drive (disk)
or
double)
-is
set, and the command
128
or
256 bytes
received, the starting address where
Done
bit.
(If
is
loaded in the
an Error
to
the write subroutine, the drive
is
set, and the command
is
loaded in the RX02/RXDB; there
RX02/RXDB.
is
The data loaded in the sector
at
the selected track
is
loaded in the
of
data)
is
loaded in
data
will be retrieved from
detected, the Error bit
is
selected,
is
loaded in the
and
sector.
is
of
set
While the controller writes the data, the program waits for an interrupt (which signifies the completion
of
write data) to occur in order to return
to
the main program.
is
is
4-45
Page 87
IllIllU
,e1113
•
11174
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5761
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tMAlilfiM
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OtJ8U.21
UiDOC21
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RX211 jRXV21 Write/Fill Buffer Example
•...
MOiJULf
4.1
• fILL
------
...................•......•.....•••••...•..•. -.....
MOY
IIU
,.ov
J5M
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MOV
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tit
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TIT
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,AXDB
4.3.5.2 Read/Empty Buffer
Figure 4-32 illustrates a program to read
subroutines. The drive to be read
density is set, and the command
sector address
is
loaded in the
is
is
loaded in the
RX02/RXDB;
data
from the disk by performing read and empty buffer
selected, the read command and interrupt enable are set, the
RX02/RXCS.
there
is
another wait for
loaded in the RX02/RXDB. While the RX02 controller reads
selected disk into the
a
jump
to the empty buffer subroutine. The empty buffer command is set, the density
command is loaded into the
RX02/RXDB;
loaded into the
when the buffer
RX02 sector buffer, the program waits for an interrupt to occur and then there
RX02/RXCS. After a
there is another wait for
RX02/RXDB.
is
emptied, there
The
data
is
a return
TR
and the address in memory where the data
is
emptied from the sector buffer by the RX02 controller, and
to
TR
is
received, the word count is loaded into the
the main program.
BUfrEIl
,SET
rILL
~urr~~
,ILt
ot;"'UlY
,
LOAD
COMIoIUD
,!loUT
rOR
,If'
fIlII
,EQUALS
,L(lAD
,WAIt
J
If
,EQUALI
,LOAO
,!loAn fOil
,EQUALI
.Ir
,IS
,ERIIOR
,
RUURIiI
There
data
rLAG
IEIIO
"OttO
t'OR
UU
fLAG
IERO
tlAIE
fUll
rLAG
IIttO
D~VIeE
an
THiN
HALt
is
from the selected location on the
COMM)IIID
-Til-
tKEN
CUUJIIT
-Tit-
T"E~
AUR
rOA
OUTPUt
-00"'tKEIil
'MROR
81T
a wait for
TR,
and the track address
BurrLR
TR
is
is
to
"",·18111
and then the
set, and the
--.
is
is
be stored is
4-46
Page 88
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Figure 4-32
RX211/RXV21
Read/Empty
447
Buffer Example
MA·,
••
2
Page 89
THEORY
CHAPTER 5
OF OPERATION
This chapter describes the functional operation
of
the hardware and
~CPU
software
of
the RX02
Floppy Disk System. This information combined with the programming information and descriptions
of
contained in the other chapters should give the reader an understanding
of
System theory
The first section
operation.
of
this chapter describes the overall system block diagram and the interconnection
the RX02 Floppy Disk
between system assemblies; the second section describes the interface modules; and the third section
the
describes the assemblies housed within
Peripherals Handbook, the Microcomputer Handbook
input/output
5.1
OVERALL SYSTEM BLOCK DIAGRAM
The floppy disk system consists
1.
transfer information for each computer.)
of
four elements (Figure 5-1):
Drive mechanics, which includes actuators and transducers (up to two per controller) to
RX02 cabinet. (Reference should be made to the
and
the PDP-8 Small Computer Handbook for
PDP-II
read/write data.
2.
Read/write electronics, which transfers control
and
control logic.
3.
Microprogrammed controller, which includes all control logic.
4.
Bus interface module, which transfers control and data signals between the host processor
bus and the
RX02 microprogrammed controller.
and
data
signals between drive mechanics
Operation
the RX02 Floppy Disk System
is
governed by the host processor. General functions
of
(such as write data, read data) to be performed are initiated by the processor and coupled through the
interface module to the
~CPU
microprogram, initiates specific functions to accomplish the general function. The
erns the read/write electronics which
in
heads
elements
ics,
5.1.1
The
the desired location in order to read
is
bidirectional so that for reading,
to
the
~CPU,
to the interface, and then to the host processor; for writing, the data flow
Omnibus to RX8E/RX28 Interface Signals
RX8E/RX28
interface communicates with the PDP-8 Omnibus via the signals shown
controller. The
in
turn develop the necessary signals to position the read/write
the
~CPU
decodes the general function,
~CPU
or
write data. The data paths between each
data
flow
is
from the disk
to
the read/write electron-
and
using its own
output
is
in
gov-
of
the
reversed.
Figure
5-
2 and described below.
DA
TA
BUS
- Twelve parallel bits
output data between the AC register
of
data
are transferred along a bidirectional bus for both input and
in
the processor
and
the interface register
in
the interface module.
5-1
Page 90
DISK
DRIVE
INTERFACE
RX02
DATA
BUS
RX8/RX28
INTERFACE
DRIVE
I~_"""I
1~-
READ/WRITE
...
.IlI
ELECTRONICS
Figure
I~~""'-I
l"-r-"'"
5-1
RX02 System Block Diagram
ILCPU
CONTROLLER
ADDRESS
SIGNAL
~
(18)
OR
OR
RX11/RX211
INTERFACE
RXV 1 1
INTERFACE
4.
)
v
/RXV2
~
.,.._
1
1."--
MA-2005
RX11
OR
RX211
INTERFACE
/
"
DATA
SIGNAL
MSYN
-
SSYN L
-
-
NPR L m
L
(16).)
-
Cl
L
INIT
-
INTR L
SACK
L
BBSY L
-
BR
(7:4)
BG
(7:4)
-
)
v
-
-
-
-
--
~
MA-2006
(J)
::l
z
::l
Figure 5-2 Omnibus to RX8E/RX28 Interface Signals
7
5-2
Page 91
MEMORY
DATA
BUS
- This signal provides
interface.
TP3
H,
TP4 H - These signals are used to clear the flag and clock the interface register
in
transferring data along the data bus.
I/O
transfer (lOT) instructions from memory
of
the interface
to
the
INTERNAL
internal
I/O
Omnibus
- This signal
I/O
transfer (lOT) instructions. Failure
is
grounded by the interface selector decoder to inhibit decoding any
to
ground this line will result in long
lOT
timing.
SKIP
L - An
of
the program counter (PC) plus one
register
INT
RQST
interface signals the processor
CO,
Cl
These signals control the
lOT
checks the flag for a
to
implement a skip.
L - This signal
- Signals
CO
and CI determine the type
ONE
state.
If
the flag
is
loaded into the central processor memory address (CPMA)
is
part
of
the Omnibus interrupt structure.
that
it has
data
path within the processor and determine if data
data
to
be serviced.
of
transfer between the interface and the processor.
is
set,
SKIP L is
asserted
It
is
the method by which the
and
the address
is
to be placed on the
data bus or received from the data bus. They are also used to develop the necessary load control signals
required
INIT
H -
I/O
PA
interface
load either the accumulator (AC)
INIT H is
USE
L - This signal
of
the PDP-8 decoders.
a signal used to clear all flags
is
used to gate the select and operation codes into the programmed
or
the program counter (PC)
in
the interface and initialize the RX02.
in
the processor.
I/O
to
5.1.2 Unibus to RXII/RX211 Interface Signals
RXll/RX2Il
The
interface communicates with the
PDP-II
Unibus via the signals shown in Figure
5-
3 and described below.
ADDRESS
of
the
DA
TA
(A Lines) - The
RXll/RX211
(D Lines) - The
18
address lines are used by the
CPU
to select the device register addresses
which are 177170 (RXCS) and 177172 (RXDB).
16
parallel data lines are used
to
transfer information in and
face.
M
SY
N L - This signal
has control
SSY
N L - This signal
of
the Unibus for data transmission.
MSYN L signal from the processor
is
the master synchronization control signal
is
the slave synchronization control signal
or
another device that has control
that
that
is
initiated by the device
is
initiated in response
of
the Unibus and
send data.
NPR
L - This signal from the processor will inhibit the interface from issuing a bus grant.
NOTE
The
RX
II
is
C 1 L - This bus signal
to the Unibus) if it
is
not an N PR device. The RX211
NPR
device.
is
coded by the master device to control the slave in
negated, and
Data
Out
mode (passing
data
is
an
Data
from the Unibus) if it
out
of
the inter-
is
about
In mode (passing
is
asserted.
that
to
data
an
to
5-3
Page 92
i.
:.
RX8E
OR
RX28
INTERFACE
/
/
"
-
"
--
-
-
-
Figure 5-3
Unibus
DATA
BUS (12)
MEMORY DATA BUS (9)
TP3 H
TP4 H
to
INT
RXII
INTERNAL
SKIP L
RQST
CO.C1
INIT H
I/O PAUSE
I/O
L
/RX211
L
Interface Signals
:>
en
::>
co
z
~
0
-
-
-
MA-2007
INIT
L - This is
when a
itialize
INTR
It directs the processor
SA
being transferred
BBSY
signal follows the
BR
Each device
requested bus control; in this case, the requesting device blocks the signal from
and
BG
sor
5.1.3
The
4
RESET
the
L - This signal
CK
L - This signal
L - This
(7:4) - These four priority bus request lines are used by the interface to request bus mastership.
assumes bus control.
(7:4) - These are four priority bus
uses them
LSI-II
RXVII
and
described below.
the
signal asserted by
instruction
system.
is
to
it. This signal inhibits further bus grants by the processor.
is
the
SACK
of
the same priority level passes a
to
respond
Bus
to
RXVII/RXV21
or
RXV21 interface module communicates with the
is
executed,
asserted by the interface when it has bus control during an interrupt sequence.
to
go
to
interrupt
is
sent by the interface
signal sent
L signal.
to
a specific bus request.
the
processor when
or
when
the
power fail sequence occurs. This signal will in-
service routine.
to
the
processor in acknowledgment
by
the interface when asserting master control
grant
signal
grant
lines corresponding
Interface Signals
the
START
to
the next device
to
the four request lines. The proces-
LSI-II
key
on
the console
of
of
the Unibus. This
on
the line, unless it has
the
following devices
via signals shown in Figure
is
Unibus control
pressed,
5-
BDALO:15L
and
address information in
(Datal
Address) - The
and
out
16
data/address
of
the
interface module.
lines are used by
5-4
the
CPU
to
communicate
data
Page 93
RXV11
OR
RXV21
INTERFACE
~
BOAl
_ BDIN L
BDOUT L
BRPLY L
BSYNC L
BIRQ L
BIAK I L
-
BIAK 0 L
BBS7 L
BINIT L
BDMGI L
BDMGO L
BWTBT L
BAD
BAD 17 L
BDMR L
BPOK H
BSACK L
00
16
L
TO
15:)
..
-
LSI-11 BUS
..
MA·2008
Figure 5-4 LSI-II Bus to
BDIN
L - This signal is used with BSYNCL to indicate that the
used without BYSNCL, it
BDOUT
BRPLY
L - This signal
L - This signal
is
is
used to indicate
is
used by the
asserted
by
CPU
the interface module to indicate
RXVII/RXV21
that
the CPU has an interrupt in progress.
to
indicate
accepted data from the bus or placed data on the bus.
BSYNC
when it has control
BIRQ
BIAK
BIRQL.
BBS7
L - This signal
L - The interface asserts this signal to indicate to the
IL,
BIAK
If
the interface IS not asserting BIRQL, it will pass the signal via BIAK OL to the next device.
L - The master device asserts this signal when an address in the 28K-38K range is placed on the
OL
is
the master synchronization control signal asserted
of
the bus for transmitting an address.
- BIAK IL, interrupt acknowledge in, is asserted by the
bus.
BINIT
devices connected to the
L - This signal
is
asserted by the
I/O
bus.
CPU
to initialize
Interface Signals
CPU
is
ready to accept data. When
that
valid data
CPU
or
clear the interface module
is
available on BDAL 0-15.
to
the
that it has data to be processed.
CPU
that it has either
by
the master device
CPU
in response to a
as
well as all
BDMGI
L,
BDMGO
device on the bus.
BDMGO
L.
L - BDMGI L,
If
the device
DMA
is
not requesting the bus, the signal
grant-input,
is
asserted by the
5-5
CPU
and routed to the first
is
routed to the next device via
Page 94
B
WTBT
is
to follow; it
L - This signal, write/byte,
is
also asserted during
is
asserted during BSYNC L to indicate that an output sequence
BDOUT
L for byte addressing.
BAD16
BDMRL
L,
BAD17
- This signal, direct memory access request,
L - Extended address bits.
ship.
BPOK
BSA
H - This signal indicates the processor power supply operation
CK
L - This signal
is
5.1.4 Interface Module to
The
#LCPU
controller and interface modules communicate via the signals shown
described below.
JLCPU
CONTROLLER
--------~~------------------~.~--------~
asserted by the interface
#LCPU
Controller Signals
__
RX
DATA
L
RX
DONE L
RX
TRANSFER REQUEST L
SHIFT L
RX
RX OUT L
RX
ERROR L
_ RX RUN L
_
RX
INIT
L
..
RX
12
BIT L
.,.
RX
DMA
MODE
RX AC L
is
asserted by the interface to request bus master-
is
normal.
to
indicate it
is
bus master.
in
Figure
-
..
INTERFACE
-
-
ONLY)
I
H
(PDP-8
,.
I
MA·2009
5-5
and
Figure
RX
INIT
L - The RX02 will negate
to
track
O.
exists)
The RX02 will also read sector 1
without error upon successful completion
RX
DONE
L - This signal, asserted low, indicates that there
itiating any function will cause
initiate any function other than Initialize while
RX
RUN
L - This signal initiates communication between interface and controller.
while
DONE
L is true, passes a command from interface to controller serially.
5-5
DONE
DONE
Interface to
#LCPU
Controller Signals
L and move the head position mechanism
of
track 1
of
the function.
L to be negated for the duration
DONE L is
negated
negated until the command has been executed (or until Initialize
DONE L is
must be stable
false, signals transfer
75
ns before
RUN L is
of
data to or from the controller. All control lines
asserted.
5-6
of
drive 1 (if it
of
drive 0 and then assert
is
no RX02 function in progress. In-
of
that function. Attempting to
is
illegal and may result in an error.
RUN
DONE
is
asserted).
RUN
L, asserted while
to
DONE
L,
asserted
L will be
the controller
L
Page 95
RX
OUT
L - This signal indicates the direction in which the RX02
OUT L is
the direction
L
is
RX
handshake set.
that
data
asserted, the direction
is
from interface
of
to
controller.
negated by Initialize.
TRANSFER
REQUEST L (TRL)
On transfers from controller to interface
the next
data
element has been transferred
element will be initiated by asserting
has been assembled in the interface.
transfer
is
from controller
OUT
L is never asserted while
- This signal with
to
RUN
L. This will negate
is
prepared to transfer data. When
to
interface. When
OUT L is
DONE L is
RUN L and
(OUT
L asserted),
OUT
L forms a bidirectional
TR
L going true indicates
the interface register. The transfer
TR
L until the new
negated,
true,
and
of
the following
data
element
OUT
On transfers from interface to controller
prepared
assertion
RX
appended to the serial
DA
to
accept the next element
of
RUN
TAL
- This
L.
Assertion
is
a bidirectional line for transfer
data
of
stream by the interface when the direction
(OUT
of
data. The arrival
RUN
L while
L negated),
TR L is
of
data to
TR
asserted indicates
of
the new
negated
and
controller. The controller will interrogate the parity bit for validity.
RX
SHIFT
DATA
1.
2. Controller
L - The
SHIFT
L pulse strobes information
line.
Interface
data
Lor
on the length
The first bit
pulse width
Subsequent bits
TR
to
Controller Transfer words begins with the assertion
TR
L will be negated and a number
of
the data element
of
data
(or command) must be stable when
is
200 ns nominal.
of
data may be brought up on the trailing edge
OUT
of
to
SHIFT
is
RUN
of
be passed.
L pulses will not occur more often than every 400 ns.
L will be reasserted following the last
to
Interface Transfer -
OUT
is
SHIFT
asserted and the assertion
controller's readiness to transfer data. Assertion
of
train
SHIFT
valid only while
data.
DONE
L pulses. The
SHIFT L is
data
is
asserted.
to
be sampled on the leading edge
TR
L will be reasserted
L will be asserted following transfer
to
or
from the controller bit-by-bit via the
negated
SHIFT
and
the transfer
L.
Following the assertion
L pulses will occur. The number depends
RUN L is
L pulse.
of
RUN
of
the last element
that
the controller is
data
element will be signaled by
is
an error.
from the controller. A parity bit
of
the data transfer
of
asserted. The
of
SHIFT
of
L will negate
at
the end
either commands
of
TR
TR
of
of
of
data in a block.
is
into the
RUN
L,
DONE
SHIFT
L.
DONE L or
L indicates the
L and initiate a
SHIFT L and
each element
is
or
L
is
of
RX
12
Bit L - This signal
is
asserted
by
the interface to controller
pulses generated by the controller for each byte transferred.
12
Signal
Bit L asserted
controller upon the assertion
for
data
transfer between the interface
remain asserted throughout the entire
is
transferred first.
will
produce
of
RUN
12
SHIFT
L. Signal
and
data
L pulses for data transfer between the interface and
12
Bit L negated will produce eight
controller upon the assertion
transfer. When
data
NOTE
Signal
for I2-bit words.
LSI-II
12
Bit L is only asserted by a
It
is
never asserted
interface.
5-7
and
is
transferred, the most significant bit
PDP-8
interface
by a PDP-II
determines the number
SHIFT
of
RUN
L.
This line must
or
of
shift
L pulses
Page 96
RX
ERROR
detected.
flag. This line
RX
DMA
RX
A C L - This line is asserted when the RX02 has lost power.
L - This
The
detection
MODE
is
is
cleared by
H - This line
an
error
of
ERROR
INIT L or
summary bit generated by the controller
L stops all controller action
is
asserted
the initiation
to
of
indicate direct memory access mode
and
asserts
a new function.
that
sets when any
DONE
L and the
of
operation.
error
Error
is
5.1.5
The
~CPU
~CPU
controller
Controller to Read/Write Electronics Signals
described below.
and
read/write electronics communicate via the signals shown in Figure 5-6 and
RIW
ELECTRONICS
DRV READ STROBE H
DRV
SEL HDO H
DRV SEP CLK H
DRV
WRT
-
DRV ERASE H
..
..
DRV
DRV
-
DRV WRITE
DRV STEP L
DRV
DRV
DRV SEP
DRV SEL DK1 H
AC
-
DRV READ 2F L
-
DRV LOCK CLK H
MAINT
..
GATE H
OUT/ABOVE
LOAD
HEAD H
DATA
SEL TRKO H
SEL INDEX H
DATA
LO
L
MODE
TRK
H
H
-
43
J,LCPU
CONTROLLER
MA-2010
DRV
OUT/ABOVE
lower
of
center
Figure 5-6
TRK
two write current levels when operating
of
the disk, the bit density increases as linear velocity decreases, necessitating a reduction in
~CPU
43-
When writing data, this signal
Controller
to
on
Read/\Vrite Electronics Signals
is
asserted by the controller to select the
a track above 43. As the head moves closer to the
write current. When reading data, this signal determines the direction in which the head will move
response to a
outer edge
DRV
WRITE
TTL
logic levels. Each transition
DR V SEP
asserted with
STEP
of
L signal; when
the disk.
DATA
OUT
/ ABOVE
- This signal conveys
on
this line results in a flux reversal on the disk.
the
complete
TRK
DA T A H - This signal conveys the complete
READ
STROBE H and remains valid for 4
43
is
asserted, the heads will travel toward the
data
stream
data
stream recovered from the diskette.
J,LS
for single density data
to
the
read/write
and
electronics
2
~s
It
for double
density data.
5-8
in
at
is
Page 97
DR V SEL
DKI H -
This
signal uniquely selects
this line will select logical drive 1 for use.
one
Unit
0 is physically
of
the
two
possible disk drives.
the
left-hand
unit
in
The
the
assertion
rack.
of
DR V WRITE
This level
last
bit
of
DRV
ERASE
erase drivers.
determined
DR V LOA
GA
TE
must
be asserted
the
data
H -
This
It
is asserted
by
the
microprogrammed
D HEA D H -
head.
DR V STEP
L - This signal is asserted twice
direction determined
(6 ms step time
DR V SEL
over
track
DRV
SEL
has been detected.
detect
A C
afl~f
"up
La
L - This signal is asserted by
a iuss
per
TRK
0 H -
O.
INDEX
This
to speed."
of
power
H-
This
prior
field.
This
signal is used in
and
This
signal
by
signal
track).
This
signal is asserted by
H -
This
signal is asserted by
occurs
(an
initialize is
signal is asserted by
to
the
beginning
of
timing is completely
conjunction
negated
after
the
controller.
is
asserted by
by
the
OUT
H.
There
are
two
the
the
once
per revolution
an
Initialize signal from
provided
over this Hne).
the
controller
the
data
field
under
with
assertion
the
controller
microprogram
DRY
of
controller
to
step pulses
selected drive
selected drive
and
is used by
to
to
be
WRITE
DRY
to
hold
change
per
track
to
indicate
to
the
the
controller
enable
the
written
control.
GATE H to
WRITE
the
media
head
position
for each
that
indicate
control
selected write drivers.
and
GATE
that
to
to
the
is negated
enable
H,
against
by
track
its
head
the
head
time
operations
drives,
after
the
with timing
the
selected
one
track
to
be
stepped
is
positioned
index hole
during
the
tunnel
in a
and
and
DR V
REA D STROBE
and
SEP
CLK H are
for single density
DR V
SEL H DOH
DR V SEP
CLOCK
J,LSS
for
DR V
and/or
DR V LOCK
the
PLL
address marks.
DRV
trieving
preamble
5.1.6
The
read/write
Figure 5-7
CLK
H is asserted with
double
READ
density.
2 F L -
maintain
eLK
will
acquire
The
MAINT
data
MODE
from the media.
recognition circuitry,
Read/Write
electronics
and
described below.
H -
This
signal is asserted
valid
and
may
be stored.
and
every 2
- This line
H -
This
This
phase
lock.
H - This signal
phase lock
PLL
H -
J,LS
for
double
(for future
line indicates
READ
signal
STROBE H and
controls
controls
during
does
not
function when
When
asserted,
This
the
PLL,
mode
that a separated
Electronics to Drive Signals
and
drive(s)
The
communicate
plug designations for
density.
use) selects
the
density
the
the
six bytes
the
tests
and
the
by
the
This
signal is asserted
one
clock
remains
at
which
phase
lock
of
zeros preceding
LOCK
R/W
electronics
the
digitized
data
separator.
through
selected drive
for
of
two possible
has
been detected in a
valid for 4
the
phase
loop
(PLL)
CLK
H is negated.
are
portion
five sets
the
cabling
are
to
indicate
approximately
heads
J,LS
for single density
lock
loop
and
preamble
the
ID,
Data,
exercised
of
of
signals
also
without
R/W
electronics including
per
shown
that
SEP
DATA
1
J,LS
every 4
on
a disk drive.
data
stream.
and
for 2
(PLL)
will
acquire
detection so
or
deleted
storing
or
drive as shown in
in
Figure
5-7.
H
J,LS
SEP
that
data
re-
H EA D - This
is
an
analog
signal
that
conveys
data
5-9
to
and
from
the
drive head.
Page 98
DRIVE
0
-
HEAD
INDEX
TRACK
HEAD STEPPER
HEAD LOAD
00
SOLENOID
P3
P6
P7
P4
P5
-
_
_
READIWRITE
ELECTRONICS
HEAD
INDEX
DRIVE
1
-
TRACK
HEAD STEPPER
HEAD LOAD SOLENOID
-
Figure
INDEX
for determination
TRA
tioning at track
H EA D
- This
CK
()()
STEPPER
is
a set
- This
O.
of
signals connected
of
diskette rotational position and speed.
is
a set
- This signal
track to track.
HEAD
LOAD
SOLE/VOID
during a read/write operation. The head
not performing a read/write operation.
5-7
Read/Write
of
signals connected
is
output
- These signals activate a solenoid to hold the head against the diskette
P3
-
P6
00
P7
P4
P5
..
MA-2011
Electronics to Drive Signals
to
a LED-phototransistor pair which locates the index hole
to
a LED-phototransistor pair, which indicates posi-
from the read/write electronics, which moves the head from
is
unloaded from the diskette to reduce diskette wear when
S.2
INTERFACE
MODULES
BLOCK DIAGRAM
DESCRIPTION
The following paragraphs contain functional block diagram descriptions
ules used with the
RX02.
5.2.1 RX8E/RX28 Interface (M8357) Block Diagram Description
Figure
IC chip designations
5.2.1.1
from the memory data
control logic, and the sequence
5-8
presents a block diagram
on
the
Device Select and
lOT
bus
of
the
RX8E/RX28
RX8/RX28
print set, which
Decoder - The device select
and
generates signals to
and
function control logic.
interface. The E references on the diagram are
is
a separate document.
and
lOT
decoder logic decodes instructions
the
interrupt control and skip logic, the
5-10
of
each
of
the interface mod-
Cline
Page 99
"
~
INT
RQST
L
SKIP L
SKP
STR
DEVICE
MD03-MDll
1/0
PULSE L
INT
1/0
L
RX
CO
Cl
en
::l
III
z
:i:
0
v-
I
DATA
00
11
DATA
TP3 H
TP4 H
INIT H
8 SEL L
L
L
SELECT
AND lOT
DECODER
E32.35.40.41
J
INTERFACE
E3.921
I
f
XFER
I
INIT lOT L
MSB
MSB 8 (1) H
DATA
INIT
B DATA 5
B DATA 4 (1) H
B DATA
ClK
ENB
lOT H
lOC
lOT l
12
(1) H
L
(1)
11
(1) H
BUFF L
BUFF LOAD L
lOT L
SKP
ERR
lOT L
SKP DONE lOT L
INTERRUPT lOT L
H
"I
"-
-
CLINE
SELECT
LOGIC
El0.12.14
I
I
...J
...J
::I:
-
!::
w
§
N
Go
1
SEQUENCE
AND
FUNCTION MAINT (1) L
CONTROL
LOGIC
E3.4.7.14.15
16.18.24.27
28
~
Z
«
:i:
::I:
Z
0
~
a:
a
~
III
BTP
3 L
BTP
4 H
INIT H
XFER
B
DONE H
B
ERROR
RX
DATA L
RX
SHIFT L
RX
TRANSFER
RX
OUT L
RX
DONE L
RX
ERROR
REQ
INTERRUPT CONTROL
H
H
REQUEST
L
J
AND
SKIP LOGIC
15, 18,22,26,
E
E30
L
r---
TO
#,CPU
CONTROLLER
""
>'
Figure
5-8
RX8E/RX28 Interface Block Diagram
RX
12
RX
RX
BIT L
INIT L
RUN
L
"---
MA·2012
l
Page 100
Device selection codes are determined by the switch configuration with relation to the state
and
MD7,
MD03
and signal
is
being executed by the program.
(lOTs) while this instruction
fers
MD8. When the correct code for the
L-MD08
INT
L and
I/O
I/O
is
asserted on the Omnibus.
PAUSE L is asserted, MD09
INT
I/O
is
being executed.
RX8E/RX28
L-MDll
I/O
PAUSE L is
is
input
to
the device select logic on
L are decoded by the decoder
present anytime an
L prevents the processor from executing
lOT
other
instruction
of
I/O
MD6,
E41
trans-
Decoder
1,
which
input
input on
E41
is
a BCD
is
unused, to be asserted low.
of
010 (decimal
MD09
L-MDII
to
decimal decoder. All
2)
will cause
L, only one
An
input
XFER
of
the decoder
Os
applied
of
001 will cause signal
lOT L to
to
inputs DO-D3 (D3
LCD
lOT
be asserted. Therefore, for each function code
output
lines will be asserted. The function codes
are further explained in Paragraph 4.1.2.
5.2.1.2 Interrupt Control and
signal on the
Omnibus. Bit
Skip Logic - The interrupt control logic asserts the BUS
11
of
the
data
bus must be set
and
an
INTERRUPT
decoded by the interface to set the interrupt enable flip-flop. The combination
and
buffered done flip-flops will assert BUS
that
no RX02 function
is
currently in progress.
The skip logic implements the three
Error
Flag (SER), and Skip on
Done
lOT
INT
RQST L. Setting the buffered done flip-flop indicates
commands Skip on Transfer Request Flag (STR), Skip on
Flag (SDN) as described in Paragraph 4.1.2.
NOTE
When using these instructions, the respective flags
are cleared after they are tested.
Signal
respective flag has been asserted by the
The
XFER
skip
SKIP
L will be asserted
RX8E/RX28
REQ,
lOTs
ERR,
to assert the BUS
if
any
of
the above instructions are decoded by the
RX02.
asserts the flags by causing a positive transition on the clock inputs
and
DONE.
The
SKIP
signal
M1A1INT
(1) L will directly set the skip flags
L signal when decoded by the
lOT
decoder.
is
MSB) will cause pin
L to be asserted.
INT
RQST L
lOT
L must be
of
the interrupt enable
lOT
decoder and the
of
flip-flops
to
allow the
An
5.2.1.3 C Line
flow between the processor
completion
signal
rvfAlt~T
control
LCD
(1) L
of
Select Logic - The C line select logic (EI0, E12, E14) controls
AC
and
the
data
bus and determines whether
of
the transfer.
lOT L is
or
B
DOt~E
CO
L will be asserted during a load command (LCD) instruction when
asserted. Assertion
L
to
be asserted
of
C 1 L requires
or
WRT H to
XFER
be negated.
the C bits according to Table 5-1.
5.2.1.4 Interface Register - The interface register (E9, E21, E3)
data
registers. This register temporarily stores
controller
During a
or
during transfers from the
data
transfer from the Omnibus (Fill Buffer), the
JLCPU
enabled by signal RX8 SEL L from the device select logic.
when signals ENB
BUFF
serially for transmission to
BUFF
L from the sequence and function control logic clocks
LOAD
the
Land
CLK
#,CPU controller, ENB
during transfers from the Omnibus to the RX02
controller to the Omnibus.
12
Data
BUFF
L are asserted. In shifting data out
BUFF
LOAD
5.2.1.5).
data
During
into the buffer. ENB
transfer to the Omnibus (Empty Buffer), serial data from the #,CPU controller
BUFF
LOAD
L must be negated while
CLK
5-12
the
or
lOT H to
Data
is
made up
direction
not the AC
is
be asserted
transfers occur under the
of
three
8271
of
data
cleared upon
and
either
4-bit shift
JLCPU
parallel data lines to the register are
is
parallel-loaded into the register
of
the register
L must be negated. Signal
data
out
of
the buffer (Paragraph
BUFF
L supplies the clock
is
shifted
pUlses.
eLK
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