Digital Equipment DMO9AL, PDP-9 Instruction Manual

INSTRUCTION

DMOSA

MANUAL

ADAPTER/MUL

TIPLEXER

DIGITAL

EQUIPMENT

CORPORATION.

MAYNARD,

MASSACHUSETTS

DMDSA

DEC-09-19AA-D

ADAPTER/MUL

INSTRUCTION

TIPLEXER

MANUAL

DIGITAL

EQUIPMENT

CORPORATION.

MAYNARD.

MASSACHUSETTS

October 1968

Copyright © 1968 by Digital Equipment Corporation

The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:

DEC
FLIP

CHIP

DIGITAL

ii

PDP
FOCAL
COMPUTER

LAB

CONTENTS

Page

1 •
1 . 1
1

.2

2.

2.1

2.2

Introducti

Specifications

on
Related
Engineering Drawing References

Environmental
Power Requirements 2

Documentation

2.3 Physical

2.4

Controls

and

2.5 Performance

3.

4.

4.1

4.2

4.2.1

4.2.2

4.2.3

Installation
Principles

Basic
Detailed

Power
Internal
Single-Fast-Input

of

Operation

Indi

cators

Turn-On

Control Pulse Train 4

Cycle

1

1
2
2
2

2
2
2
3
3
3

4
4

5

4.2.4

4.2.5

5.

6.

6.1

6.2

6.3

7.

1-1
3-1
4-1

4-2

Single-Slow-Output

Double (Back
Acceptance
Maintenance

General
Delay
Module

Engineering Drawings

Basic DM09A System Block Diagram
Installation
Control Pulse Train
Control Pulse Train Time Relationship

Test

Adjustments

Complement

Diagram

to

Procedure

Circuitry

Cycle

Back) -

ILLUSTRATIONS

Fast-Output

Cycles

6

7

11
11
11

11
11

12

3
5
5

iii

CONTENTS

TABLES

(Cant)

1-1

4-1

4-2

4-3

6-1
7-1

Reference
Single-Fast-Input

Single-Slow-Output

Double
Module
Engineering

Documents

{Back

to

Back)-Fast-Output

Complement

Drawings

Cycle

Cycle

Signal Flow

Signal

Flow

Cycles

Signal Flow

1

8

9

10

12
12

iv

1 • INTRODUCTION

The DM09A

Corporation

(DEC), provides

PDP-9 memory

This document
installation,
is

fami

liar

with

via

the

operation

the

basic

Adapter/Multiplexer

an

interface

DMA

channel. A basic

an

option

to

through which

system

block

the

PDP-9 manufactured by Digital Equipment

three

I/O

diagram

Figure 1-1 Basic DM09A System Block Diagram

and

the

and

maintenance

documents

referenced

of

the

option.

herein

provide

The level

PDP-9.

devices

of

may'gain

is

given

in Figure

the

information necessary for

discussion assumes

access

1-1.

that

to

the

the

user

1 • 1 Related Documentation

DEC

documents listed in

this

document.

The

Title

P DP-9 User Handbook

PDP-9

Maintenance

Volumes I

and

Manual
II

DIGITAL Logic Handbook

Table

1-1

contain

Table 1-1

Reference Documents

Document Number

F-95

F-97

C-105

material

Operation
for

Operation
for
engineering
theory

Specifications
FLIP

which

supplements information in

Description

and

programming information

the

PDP-9.

and

maintenance

the

PDP-9

including

drawings.

of

operation.

and

descriptions

CHIP moduies used in

information

basic

PDP-9

Basic DM09A

of

most

the

DM09A.

1

.2

Engineering Drawing References

II

be

Engineering drawings wi

referenced

using

an

abbreviated

code.

As

an

example,

drawing

D-BS-DM09-A-2,

[DM-2(2)] •

2.

2.1

Therefore,

2.2

No

additional

2.3

DMA

Adapter

Multiplexer

SPECIFICATIONS

Environmental

DM09A consists

The

entire

Iy

of

modu les

PDP-9 environmenta I spec ifications

Power Requirements

The option obtains a

power

supplies,

II

necessary

operating

power control

Physica I

The DM09A consists

entirely

of

modules which

Control,

of

the

apply

to

power from

or

fan assemblies

sheet 1 of

type used in

the

DM09A.

the

are

are

housed by two

2,

wi

II

be

referenced

the

PDP-9

centra

I processor.

PDP-9 power supply system.

necessary.

DEC

standard 1943 mount-

as

panels,

ing

tion

3,

2.4

control

2.5

thus requiring

INSTALLATION.

Controls

No

of

the

and

controls

PDP-9

or

and

PeITormance

The multiplexer

high

speed

and

thus

achieve
low speed of 3 iJS/transfer
the

speed range

applies

1 iJS/transfer.

10-1/2

Indicators

indicators

the

I/O

operates

a 1 iJS/transfer

to

permit

only

to

the

in.

of

mounting

are

associated

space.

with

devices.

at

two

speeds.

rate;

I/O

sufficient

data-line

DM09A. The PDP-9

the

I/O

devices

devices

settling

Placement of these panels

DM09A. The option

with 10

mHz

logic may request

is

is

entirely

with low speed logic should request

DMA

time.

channel

It should

and

the

be

remembered

memory require

given

in

Sec-

under

the

that

only

the

the

2

3.

INSTALLATION

prewired
Figure

3-1

Implementation

locations in

the

•

of

the

option

basic PDP-9

Figure

involves insta

cabinet.

3-1

The

PAPER

READER AND

OPERATOR'S CONSOLE

TABLE

Insta

II

location

RESERVED

FOR

DM09A

RESERVED

FOR

ME09B

TAPE

PUNCH

Ilation

ing

the

option

in

which

Diagram

modules

the

option

into

their

preassigned,

mounts is shown in

The following

Drawing

Number

D-CD-DM09-A-9

CD-D-DM09-A-10

CD-D-DM09-A-11

4.

4.

1 Basic

Channel

is

also

PRINCIPLES

A

basic

Transfers, of

contain

in

engineering

(Rev. A)

OF

description

the

PDP-9

that

section.

drawings

Title

Memory

Interface
DM09 Memory

Cabling

Inter-Memory

OPERATION

of

DM09A logic

Maintenance

provide

Interface

Cabling

DMA

Manual,

all

Interface
PDP-9 memory.

Interface
extension
bank.

Interface

and

operation

Volume

necessary

between

between

control

between

MM09A,

can

be

1. A detailed

interface

information.

Description

the

DM09A

the

DM09A, ME09A memory

and

MM09A

the

MC70B

Band C extended

obtained

from

and

extended

basic

memory

Section

DM09A

the

basic

memory

PDP-9 memory

banks.

3.8.3,
block

DMA

diagram

This

document

describes in

detail

the

operation

3

of

the

DM09A

DMA

Adapter/Multiplexer.

4.2

Detai led

A

variety

of

transfer

type

combinations

are

possible with

the

DM09A.

To

avoid

excessive
repetition,
cyc

Ie

and

only

Doub

three

Ie

Certain

initialization

via
descriptions assume
Simi lar

operations

All transfer types

cing

with

a PDP-9
made
With

ready,

multiple

in which a

transfers,

When reading

referenced

DM-8(2) should

4.2.1

on

the

Power

When

be

Turn-On

the

types will

(Back

to

Back)-Fast-Output

DM09A

power

I/O

wi

ClK

operations
turn-on
device 0 is

II

result

pulse.
device
synchronization

the

signal flow

referenced

system

be

described

are

executed

and

when

can

be thought

interna

being

any

I DM09A control pulse

acted

other

of

Single transfers consist

is

synchronized

is

established

logic

descriptions,

tables.

for

is

first turned

In

specific

addition,

timing

on,

herein;

cyc

Single-Fast-Input

les.

regardless

upon.

device

is

acted

as consisting

to

the

PDP-9,

during

the

user should

DM09A timing

information.

PK

ClR

(power

All

of

time

of

transfer

train

reference

upon.

of

a number

states

or in which a

the

previous

refer

diagrams,

and

key

cycle,

type;

generation.

wi

II

be

of

"time

in

which

data

to

the

clear)

Single-Slow-Output

namely,

control

Transfer

made

to

I/O

device

either

data

states"

transfer

an

each

I/O

takes

transfer.

engineering

drawings

drawings DM-8(1)

pulses

arrive

at

circuitry

type

O.

commen-

device

place.

and

the

DM09A

is

control
The

operations

4.2.2

generate

system

logic

and

produce

performed

Clear

SYNC

Clear

SET

Clear

SET

Clear

DEV 0 CaNT

Clear

SLOW CYCLE A

Interna I Contro I

Following

an

internal

Ti

me

re lationships

is

operat i ng

AO

DO

PK

DM09A

•

PWR

are

0

Pu

ClR,

ClR

POS (power

as follows:

Ise T ra i n

ClK

(clock) pulses

control

are

pulse

illustrated

train

via

in Figure

clear

arrive

the

positive)

at

circuitry

4-2.

pulses

to

the DM09A control logic

of

Figure

The pulse

train

condition

4-1.

is

generated

the

and

control

are

used

whenever

logic.

to

the

4

ClK

---+---JII

150fl

WI)05

A23

W005

W005

A23

A23

u

A D

PHASE PHASE

W005

A23

D

H

o

'VA

RIll

A21

F
U

4.2.3

ClK

A PHASE

lOAD

AMEMA

D PHASE

Sing

le-Fast-Input

Figure

-----.U

I

~oons-n~------'n'---------

I

----:-1-----------'

__

!-14-------650ns----n

--'-

________

..

~----7oons----n

I

I

I

I

Figure

4-2

Cycle

4-1

Control Pulse Train

Circuitry

U

.....

----------'

----=.J

Control Pulse Train Time Relationship

L..

________

n

--I

n

~---

L..

__

_

this time
Referring
to

generate

The DM09A

the

I/O

to

Table 4-1

an

AM

adapter/multiplexer

device

RQ

break

and

level.

the

drawing D-BS-MC70-B-1 (sheet

is

then

produced.

100

ns,

generates

During

SYNC

SYNCIN

ClK

request
referenced
This level

2). A ClK
G,

to

set

the

is

flag

is

set

engineering

is

applied

pulse marking

the

centra

AM

SYNC

uti

lized

during

providing

drawings,

to

the

I processor has

flip-flop

5

the

memory

the

DM09A

internal

PDP-9 memory

the

beginning

access

to

in memory

read/write

with

a CH 0
control
control

of

the

core

control

cycle.

BK

RQ

level.

logic

operations

circuitry

SYNCING

shown on

time

memory. C LK,

via

AM

RQ{l).

During

serve

state

delayed

AM

SYNC(l)

produces AM

SYNC(l)B

and

AM

SYNC

BUS(l).

AM

SYNC(l)B

is

utilized

by

CM

(control
memory) timing
ning

of

the

DATA

The

is

POST

ClK
access
memory
lOT
AM

to

memory whi Ie MODE (1) signifi es CP

cycle

instruction

SYNC(l)B

During
circuitry
memory
inverter
bits

are

modules

access

of

the

designated

to

An AMI
AMI is
AMEMA

the

04

result

are

to

prevent

XFER

DATA

XFER

and

resets

(SYNCING)

immediately

is

delayed

the

current

AM

REGISTER

CH 0

shown.

the

jam input

(adapter

of

AM GRANT*

used

with

SM(l)

from

time

state.

time

state

the

MODE

sets

the

precedes

to

generate

time

state,

(refer

ADDR

ADDR

gates

0,

the

of

multiplexer

or

PDP-9 systems

restarting

is

entered

flip-flop

MEM

DONE

the

DM09A

the

CM

via

another

conditioned

access

to memory.

flip-flop

request,

AM GRANT SMlTD

I/O

to

drawing

BIT

05 through

result

the

AM

device

of

REGISTER

0 address bits

DM-3(2».

CH 0 ADDR

DEY

0 CONT(O)

input) pulse jam transfers

AM GRAND

containing

SMlTD.

extended

on

the

PDP-9

by AM

and

produces AM

AM GRANT

(simulated).

Address bits uti

BIT

as

lAM

05 through

The

memory

next

ClK

ClK

SYNC(l).

PRE-WRITE

are

present

17.

and

SET

the

13-bit

flip-flops

banks.

pulse

pulse.

MODE(O)

OFF

GRANT.

is

not

produced.

at

lized

The bits

DO(1),

lAM

address

designated

Inverter

which

ClK,

of

the

by a

are

applied

allows

17.

marks

the

delayed

signifies

the

previous

If

an

EAE

In

this

input

gating

PDP-9

with

to

the

address

into

the

register.

AMEMA 03

inputs

are

begin-

50
AM

or

case

basic

the

and

CH 0

ns,

core

an

ADDR

pulse

also

BIT

lOAD

AMEMA jam transfers

is

I/O

device 0 data
applied

produced

transferred

4.2.4

I/O

device

be

transferred

type

of

data
requests
AM

multiplexer

RQ

NEG.

03

and

SET

AO(l) for AMEMA 03

650

ns

after

Following memory

word consists

to

a network

into

the

AM

of

REGISTER

Single-Slow-Output

Table

4-2

illustrates

is

programmed
and

the

transfer

address

are

basically

to

service

SYNC

0(1)

and

the

extended

ClK

by

addressing,

of

CH 0

inverter

modules.

by a

Cycle

the

signal

indicate

of

the

first

simi lar

via

CH 0

CH 0

FAST

and

CH 0

ADDR

memory addressing bits

the

control
an
DATA

second

flow

that

word,

to

BK

RQ.

an

RQ

pulse

18-bit

BIT

data
00

The

AMI pulse

associated

output

DM09A

those

of

The control

condition

through

enabling

transfer

the

BIT

04

and

SET

AO(l) for AMEMA

into

their

respective

train

word

which

circuitry

is

CH 0 DATA

signal

described

jam transferred

BIT

is

DEY

O.

is

produced

by AM STROBE.

with a Single-Slow-Output

is

to

take

place,

control

Single-Fast-Input

the

logic

set

logic

operations

proceeds

DCD

gate

cycle.

to

generate

of

the

flip-flops.

in S.ection

into

the

17.

The

The

data

4.2.2.
AM REGISTER.
data
word

cycle.

the

number of words

which

result from this

The

I/O

AM

RQ

SLOW CYCLE A

04.

'word

is

jam

The

device

and

This

is

to

be

*Both may

present

but

the

circuit

is a logical

OR.

6

flip-flop
the
this

which

multiplexer

pulse jam transfers

is
and

set

in

by

the

the

the

positive

PDP-9,

device

going

transition

an

AM GRANT pulse

supplied

address

of

into

AM RQ

is

issued

the

AM

NEG.

to

produce

register.

Following

AMI.

This

is

logic

With

not

operations

input

necessary

in

transfers,

with

the

current

cycle,
to

produce
access
transfer

to

4.2.5

DM09A
DM09A
condition
time

state

DCD

gate

sired;

the

type

of

transfer.

Following

PDP-9

AM

SAl (sense

the

jam

these

bits

Doub Ie (Back

Signal
control
that

service

the

set

sets

SYNC 0 to

to

produce

computer

The A

STROBE

input

into

flow for

logic

is

DCD

responds

PHASE

further

amplifier

are

AM

DM09A

arrives

gates

of

the

AM

register.

to

Back)-Fast-Output

the

current

CH 0

requested.

gate

of

the

establish

RQ

and

with

pulse

of

control

at

the

DM09A. This

input) thus

the

AM

BK

RQ,

This

SYNC 0 flip-flop.

device
AM
AM

SYNCING

allowing

register. A second

transfer

CH 0

signal

priority.

RQ

NEG.

SYNC(l)

logic

Cyc

type

FAST

and

B.

1 sets

operations,

pulse

PDP-9

les

is

given

RQ

and

internal

The D

This

conditions

AM RQ

SET

signals

AO

similar

is

sense

AMI pulse

in

Table

CH 0

SLOW CYCLE

PHASE

and

generates

to

gated

with

amplifier

4-3.

RQ

IN.

pulse

the

the

PDP-9

those

CH 0

bits

is

produced

Initial
CH 0

A(O)

preceding

CH 0

that

CLR

of

Single-Fast-Input
RQ

IN

and

SA

00

through

at

this

time

signals

BK

produce

FAST

a DMA

SYNC.

sent

RQsignals

SYNC

the

SYNCING

CLR

and
cycle

This

SET

SA

to

to

the

0 EN

sets

is

clears

DO(l)

17

jam

the

to

1

the

de-

SYNC
SET

EN
set
another

CLK,

XFER 1 and

the

operations,

amplifier

AM reg ister •

place

O.

SET

AO(l)

DO

fl

ip-flop.

The following D

which

again

AM REGISTER. During

with

A PHASE,

because

AM RQ

the

to

jam

signa

flip-flop

The

PDP-9

SYNCING 2 time

and

syncing

AM

STROBE

bits,

SA

DATA

transfer

XFER

and

AM

SYNC(l)B

PHASE

maintains

SLOW CYCLE

I.

Because

remains

00

set.

produced

these

operations

arrives

through SA '17,

2 is

entered.

the

data

bits

generate

pulse sets

SLOW CYCLE A(O), a

A(O)

and

this

signal

AM GRANT

states

are

time

for

from

the

access

SET

of

the

CH 0

entered.
states
the

next

PDP-9

AO

second

SET

is

arrives

the

through

is

SET

DO.

BK

RQ

applied

at

The pulse

data

data

and

generates

cleared

word

DO

EN

SET

AO(l)

are

to

the

the

multiplexer

transfer

transfer

the

AM

and

into

the

which

characteristic

sti

PDP-9

jam-transfers

take

SAl

register

operations

conditions

and

SET

II

present.

AM

control

associated

pla.ce.

and

AMI,

gating

AM

register.

the

DO(l)

of

fast

Setting

SYNC

circuitry

address

with

the

thus a Ilowi ng
circuitry

simi lar to

The D

set

DCD

gate

produce

transfers.

fl

ip-flop

DATA

CLR

SLW

SYNC 0 is

SYNC 0 generates

prior

as

the

information

preceding

and

PHASE

syncing

the

sense

into

XFER 1 take

pulse

of

CYC

to

SYNC

DATA

into

the

at

the

the

end

of

the

current

ti me

state

c I

ears

SET

DO.

7

Time

Control

State

Pulse

D

PHASE

SYNCING A

PHASE

D

PHASE

DATA

XFER

A

PHASE

D

PHASE

Table 4-1

Single-Fast-Input Cycle Signal

Flow

Signal Conditions

SYNC 0

EN

CH 0 BK

RQ * SLOW

CYCLE

A(O)

SYNC 0(1)

D

PHASE

* SYNC 0

EN

AM

RQ

SYNC 0(1)

AM

SYNC(l)B

From

PDP-9

SET

AO(l)

A

PHASE

* SYNC 0(1)

CLR

SYNC A

PHASE * AM

SYNC(l

)B(B)

SET

DO

EN

AM

SYNC(l)B *

SET

AO

(1)

CH 0 FAST

CLR

CLR

SYNC * SYNC 0

(1)

SYNC 0(0)

SYNC

0(1) *

CLR

SYNC

SET

DO(l)

D

PHASE * SET

DO

EN

CLR

SLW

CYC

EN

SET

AO(O) * SET

DO(l)

AM

GRANT

From

PDP-9

CH 0 ADDR

ACC

A

PHASE * SET

AO(l) *

SET

DO(l)
IN
DEV

0 CONT(l)

CH 0 ADDR

ACC

IN * SET

DO(l)

DEVICE

0

DEV

0 CONT(l) *

SET

DO(l) * CH 0 RQ

IN

SET

AO

(0)

A

PHASE

* SYNC 0(0) *

SET

DO(l)

CH 0 ADDR

ACC

CH 0 AD

DR

ACC

IN

SLOW

CYCLE

A(O)

A

PHASE * CLR

SLW

CYC

EN

AM

STROBE

From

PDP-9

CH 0 DATA

RDY

D

PHASE * SET

DO(l) * SLOW

CYCLE

D(O)
IN
INH 0

DAP(O)

CH 0 DATA

RDY

IN

CH 0 DATA

RDY

CH 0 DATA

RDY

IN

CH 0 DATA

ACC

DPHASE

*CH

ORQIN * INHODAP(O)*SETDO(l)

SET

DO(O)

D

PHASE * SET

AO(O) * SLOW

CYCLE

D(O)

Drawing

Number

DM-2(2)
DM-2(1)
DM-2(2)
MC-1

(2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
DM-2(1)
MC-1

(2)
DM-2(1)

DM-2(1)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)
MC-2
DM-2(2)

DM-2(2)
DM-2(2)
DM-2(l)
DM-2(1)

Time

Control

State

Pulse

SYNC
D

PHASE

SYNCING

A

PHASE

D

PHASE

DATA

XFER

A

PHASE

D

PHASE

Table

4-2

Single-Slow-Output Cycle Signal Flow

Signal

Conditions

SYNC 0

EN

CH 0 BK

RQ * SLOW

CYCLE

A(O)

SYNC 0(1)

D

PHASE

* SYNC 0

EN

AM

RQ

SYNC 0(1)

i

SLOW

CYCLE

A(l)

SYNC 0(1) *

CH 0 FAST

RQ * AM

RQ

NEG

-+

0

AM

SYNC(l)B

From

PDP-9

SET

AO(l)

A

PHASE

* SYNC 0(1)

CLR

SYNC

A

PHASE * AM

SYNC(l)B(B)

SET

DO

EN

AM

SYNC(l)B *

SET

AO(l)

CH 0 FAST

CLR

CLR

SYNC * SYNC 0

(1)

SYNC 0(0)

CLR

SYNC * SYNC 0(1)

SET

00

(1)

D

PHASE * SET

DO

EN

AM

GRANT

From

PDP-9

CH 0 ADDR

ACC

A

PHASE * SET

AO(l) *

SET

00(1)
IN
DEV 0 CONT(l)

CH 0 ADDR

ACC

IN *

SET

DO(1)

SET

AO(O)

A

PHASE

* SYNC 0(0) *

SET

00(1)

CH 0 AD

DR

ACC

CH 0 ADDR

ACC

IN

CLR

SLW

CYC

EN

SET

AO(O) * SET

D(l)

SLOW

CYCLE

A(O)

A

PHASE * CLR

SLW

CYC

EN

AM

STROBE

From

PDP-9

AMI

AM

STROBE + AM

GRANT

SAl

AM

STROBE * CH 0 RQ

IN * SET

DO(l)

SET

DO(O)

D

PHASE * SET

AO(O) * SLOW

CYCLE

D(O)

Drawing

Number

DM-2(2)
DM-2(1)
DM-2(2)
DM-2(1)
MC-1(2)
DM-2(1)
DM-2(2)
DM-2(2)
DM-2(1)
DM-2(1)
DM-2(1)

MC-1

(2)

DM-2(1)
DM-2(1)
DM-2(l)
DM-2(1)

DM-2(1)
DM-2(l)
MC-2
DM-2(2)
DM-2(2)

DM-2(1)

Table

4-3

Double (Back to

Back)-Fast-Output

Cycles Signal Flow

Time

Control

Signal

Conditions

Drawing

State

Pulse

Number

SYNC 0

EN

CH 0 BK

RQ * SLOW

CYCLE

A(O)

DM-2(2)

D

PHASE

SYNC 0(1)

D

PHASE

* SYNC 0

EN

DM-2(1)

AM

RQ

SYNC 0(1)

DM-2(2)

AM

SYNC(l)B

From

PDP-9 MC-1

(2)

SYNCING 1

A

PHASE

CLR

SYNC A

PHASE * AM

SYNC(l)B(B) DM-2(2)

CH 0 FAST

CLR

CLR

SYNC * SYNC 0(1) DM-2(1)

SET

AO(l)

A

PHASE

* SYNC 0(1)

DM-2(1)

SET

DO

EN

SET

AO(1) * AM

SYNC(l)B

DM-2(2)

SYNC 0(0)

CLR

SYNC * SYNC 0(1)

DM-2(1)

D

PHASE

SET

DO(l)

D

PHASE * SET

DO

EN

DM-2(1)

SYNC

0(1) D

PHASE * SYNC 0 EN

DM-2(1)

-

a

AM

RQ

SYNC

0(1)

DM-2(2)

AM

GRANT

From

PDP-9

MC-2(1)

DATA

XFER

1

A

PHASE

CH 0 ADDR

ACC

A

PHASE * SET

AO(l) *

SET

00(1)

SYNCING

2

IN

DM-2(1

)

CH 0 ADDR

ACC

CH 0 ADDR

ACC

IN

DM02(l)

DEV

0 CONT

(l)

SET

DO(1) * CH 0 ADDR

ACC

IN

DM-2(1)

AM

STROBE

From

PDP-9

MC-2

SAl

CH 0 RQ

IN *

SET

DO(l) * AM

STROBE

DM-2(2)

SYNC 0(0)

CLR

SYNC

* SYNC 0(1)

DM-2(l)

CH 0 FAST

CLR

CLR

SYNC

* SYNC 0(1)

DM02(1)

D

PHASE

CH 0 DATA

RDY

D

PHASE * SET

DO(1) * SLOW

CYCLE

D(O)

DM-2(2)
IN
CH 0 DATA

RDY

CH 0 DATA

RDY

IN

DM-2(2)
AM

GRANT

From

PDP-9

MC-2(l)

CLR

SLW

CYC

EN

SET

AO(O) * SET

DO(1)

DM-2(l)

DATA

XFER

2

A

PHASE

SLOW

CYCLE

A(O)

A

PHASE * CLR

SLW

CYC

EN

MC-2(1)

CH 0 ADDR

ACC

A

PHASE * SET

AO(l) *

SET

DO(l)

DM-2(1 )

IN

DM-2(1

)

CH 0 ADDR

ACC

CH 0 ADDR

ACC

IN

AM

STROBE

From

PDP-9

MC-2

SAl

CH 0 RQ

IN * SET

DO(l) * AM

STROBE

DM-2(2)

D

PHASE

SET

DO(O)

D

PHASE * SET

AO(O) * SLOW

CYCLE

D(O)

DM-2(1)

5.

ACCEPTANCE

TEST

PROCEDURE

with

6.

Acceptance

the

DM09A Tester

Minimum margin

MAINTENANCE

testing

at

of

both

specifications

the

normal

Trial

1
2

3

DM09A

operating

DM09A-O
DM09A-O
DM09A-O

for

+10V

+6V I

option

conditions

Test

rack A and

Margin

-6V

consists

Aggravation

Condition

None
Margin
Margin

rack B are

-15V

+4V ,

of

executing

and

the

rack
rack

-4V

Test

voltage

A
B

listed

Procedure

margins

below.

DM09A-O

specified

below.

6.1

apply

6.2

6.3

to

General

The

the

DM09A

Delay

Adjust

Module

Table

general

option.

Adjustments

the

R302

Complement

6-1

lists

maintenance

Delay

the

at

module

procedures

A27

according

complement

described

to

the

of

the

in

the

data

DM09A

PDP-9

given

option.

maintenance

on

engineering

manual

drawing

also

DM-2(2).

11

Table

6-1

Module Complement

7.

DEC

Type

B169
B213 Jam
R002 Diode
R111
S107
S202

S203

Module

Inverter

Diode
Inverter
Dual

Triple

Type

Flip-Flop

Cluster
Gate

Flip-Flop

Flip-Flop
S603 Pulse Amplifier 5
W005
W300

Clamped

Delay

Line

Loads 3

W612 Pulse Amplifier

R302

*Contained

in

ENGINEERING

One-Shot

the

basic

DRAWINGS

De

lay

processor

spare

Quantity

Recommended

17 2*
14

2 1*

12

2 1*
7 1*

1

1 1

S

1 1*

parts

kit.

Spare

1*

1*

1*

1*

Quantity

Drawing

DM-2(1)
DM-2(2)
DM-3(1 )
DM-3(2)
DM-4(1)
DM-4(2)
DM-5
DM-S(l
DM-S(2)

Table

Number

)

7-1

lists

the

DEC

engineering

Engineering Drawings

DMA

Adapter

DMA

Adapter
AM Register
AM Register
Cab

Ie

Diagram BS-

Cable

Diagram

Module Uti

Multiplexer

Multiplexer
BS-DM09-A-3
BS-DM09-A-3

BS-DM09-A-4

Iization
DM09A Timing Diagram
DM09A Timing Diagram

drawings

Table

associated

7-1

Title

Control
Control

Sheet 1 of
Sheet 2 of

DM09-A-4

Sheet 1 of
Sheet 2 of

MU-DM09-A-5

TD-DM09-A-S

TD-DM09-A-S

with

the

BS-DM09-A-2
BS-DM09-A-2

2
2

2
2

Sheet 1 of
Sheet 2 of

D"A09A

option.

Sheet 1 of
Sheet 2 of

2
2

Revision

2
2

J
J
B
B

0

A

H

0
0

12

D

c

B

A

8 7

CH ¢

ADDR

~ee

LN

H..J

ST

CH ¢

ADOI'<

ACC

5T

SET

AI(I)

K

S=:T 0 1(1)

L

HJ

6

PWR

C L R

POS----'---t:I--r==-:----=.-f--L--------O'-i'=-.!-='-i-...l-------C>J--i==-'--'::.....;:...l

D

PHASE.

S=:T

A ¢

(rf;)

SLOW

c.YCl:E:Otf),

=:

A

PHAS.E

'.3ET D ¢(I)

PWR

CLR

D

PHASE

CLR

SYNC

.=:..(:{;?3:}---+------'.N,,-o!8j--+--------'D~C8:I

:E.N

'SYNC

I

(I)

'SYNC

2..(I~

8

7

\...

6

5

4

3

2

CH I ADDR

Ace

IN

CH 2 ADDR

Ace

IN

1'\

D

CH I ADDR

Ace

CH

2.

ADDR

Ace

CH ¢ DATA

Ace

CH I

Rq

IN

wl1Jr/is

CI9

58"

A2

(I)

SET

D2(1)

Ace

eN

2

RQIN_~~~

SLOW

CYCLE 0

(I)

eLR

W~rj5

C.19

CH

'2. F

.....

ST

C.LR

CH ¢ OAT A RDY

HJ

CH I DATA

RD'I

IN

CH 2

D"TA

RDY

IN

SHA¢(;)

SET

D <)(1)

CH

if;

ADDR. ACe.

~N

CH I

"'-DDR

ACC

IN

CH e

ADOR

Ace

IN

5

DPHASE:

.s

T

;:,

T

SLOW·

CYCLE

0(1)

K

A PIfAS£'

---1>Ei;;;:"\--;;>f)<:]

CH

2.

DATA

Ace

c

PWR

CLR

POS

--;;:O-=;=-''-=--=T-'

/I

PHitS~

fl

M.

RQJi

EG.

CH i

CH

2

B

t----------...-------+-----<O

CLR

SLW

eye

EN

3

A

2

BS-DM09-A-2

Sheet

1 of 2 DMA Adapter

Multiplexer Control

13

D

c

B

A

',7?5

r 2.(.'

8

CH

CH ¢ DATA RDY

IN

H F

C H 0 RQTN

--q~("V

IS/()7

824

8

7

6

•

EN

~5ET D ~SET

D Z

EN

I--

__

--'-K~

..

I---~~N

AM

SYNC(i)e.CB')

L

SYNC.

2.

EN

ROY

K

L

SYNC

2.

(¢)

A.

PHASE

SnlC.

2.

(91)

7 6

SYNC

¢

(I)

SYNC

1(1)

5

p

5

M

F

K

F

H

A

PHASE

(B)

4

I\M

RQ

AM

RQ

NE~.

AMI

-=

SAL

A

D

4

3

CHQRQIN

DEV ¢ CONTROL(I)

DEV

SET

0 i/'J(I)

CH 1 RQ

IN

\

CONTROL(I)

SE.T

D 1

(I)

A2d

LOflD

/lMEMA

CH Z RQ

IN

DEV 2 CONTROL(I)

SET

D2.(I) U

PK

CLR

I!>¢A

3

2

W¢¢5

A2?

I

D

1M

-=

DEVICE

Q

U

/\

V

DEVIC.£ \

C

K

/\

L

/1

M

GRIiNT

SNiLTD

1M

/1

M S Y N

C.

(I) B

--_£PI.2;sJ

v

PWR

ClR

pas

2

liDJUS

r

/t/J/I

GR/jf'{T

SMLTD.

TO

occuR

AT

AM

GRliNT

TIME.

B

A

BS-DM09-A-2 Sheet 2 of 2

DMA

Adapter

Multiplexer

Control

15

D

C

8

A

8

7

SA0£!

SA I

CH 0 DATA-BITll0

DEV

~

CH

I DATA-BIT.0'.0'

DEVI

CH

2 DATA-BIT¢¢

DEV2

M

C

::-

NOTE:

loon,

tw,

lOt,

TERM I NATORS

TO

GROUND

MUST

BE

PUT

ON

SA00

THRU SA

17.

8

SA

12

SAl

CH

0 DATA-BIT

12

DEV 0

CH

I DATA-BIT

12

DEV

I

CH 2 DATA-

BIT

12

7

6 5

3

2

D

c

M

loon

B

M

c

c c

A

6

5

4

3

2

BS-DM09-A-3 Sheet 1 of 2

AM

Register

17

o

C

B

A

8

CH

\)

ADDP.

BIT03-

SET

A(11)

CH I

ADDR

BIT 03

SET

AI (I)

CH

2

ADOP.

BIHl3

CHiZlAOOR

BIT

ADD!?

JIJ

C"

IAOORBITI4

ADDIl

I

CH

2 ADOP

BIT

14

AODR

2

8

7

E 0 E D P,.,.....,..------,...-,

M

LAM

14

M

CH

I

ADD!?

BIT

0'4

CH

2AooR

BIT

04

CH0AODR

B!T

15

C,.,I"'OOR

BiT

15

CH2ADOR

V

BIT

15

C

-=-

LAM

15

7

':'

BIT

16

CH2AOOR

BIT

lEi

CH

iZlAooR

BIT

05

CH,AoOR
BIT

05

CH2ADDR

V

BIT

05

M

-=-

LAM

16

BIT

17

CWI

AOO~

BIT

17

CH 2 ADDP

BI

T 17

6

6

LAM.0'5

LAM

06

CH

0ADoR

BIT

1216

CH

IAOoR

BIT

06

CH 2 AOoP

BIT

1216

C

M

-=-

-=

LAMI7

c

5

4

LAM

(67

LAM

I2IB

CH 0 AODP

CH

0AoOR

CHrllAODR

BIT07

BIT

08

BIT

0'9

CHIAoORS

CH

I AOOR

CHIAOoR

BIT

07

BIT

(lj8

BIT

09

CH 2 AoOR V

CH2

AODP

CH2ADDRV

BIT

07

81T

£18

BIT

1'19

C M

-=

-=-

W005

A23

H

DEV

CONTROL

(0)

U

1\

v

5

..

3

LAM

09

LAM

10

C

DEV

2CONTROL(0)K

3

CH 0 AODP

BIT

II

CH

IADDP

BiT

II

CH 2 AOOR V
BIT

II

LAM

II

c

LAM

12

M

ADDR

2

2

2

BIT

13

CH2ADDRV

BiT

13

D

LAM

13

C

c

B

A

BS-DM09-A-3 Sheet 2 of 2

AM

Register

19

8

7

o

c

8

A

8

7

CH

0 BK RQ

RQ

IN

FAST

CH 0 FAST

CH

I BK

RQ

RQ

IN

DATA

FAST

RQ

CH I FAST

CH

2 BK

RQ

RQ

IN

ADOR ACC

DATA ACC

FAST

RQ

CH 2 FAST

CLR

6

WC/J31

DC/J4

W031

012

6

CLK

AM

SYNC(I)B

AM

RQ

AM

STROBE

AMEMA

134

(0)

CH

0

6K

RQ

CH

I/J

RQ

IN

CH 0 FAST

RQ

CH

I BK

RQ

CH

I RQ IN

CH I

FAST

RQ

CH

2 BK RQ

CH 2

RQ

IN

CH 2 FAST

RQ

AM

(/)9 (il

l\il

II
12
13

14

15

16

AM

17

(Il

5

W¢33

G795

AI/J5

AI5

"*

•

E

·

H

I(

M

•

p

•

S

T

•

V

SA

¢i/J

QlI

02
03
¢4

(/15

06

0

7

SA

(/18

4

SA

09

1(/1

II

12

13

14

15

16

SA

17

"*

USED

FOR

TERMINATION

ONLY

NOT A

CABLE.IOPTIONAL)

W031

013

*

Wy)33

A04

5

AM

i/JC/>

(I)

I/JI

1/J2

03

04

05

1/J6

07

AM

08 (I)

AM

C/J9

(I)

llil

11

12
13
14
15
16

AM

17

0)

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-

H

~K

-4M

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S

~T

-4

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W031 W031

D¢2

0¢6

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W031

010

(IT'

AM

00

(I)

01

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E

-4H

(t5'

E E

02
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04

05

06

07

-41(

-4""

-4p

-4S

.-

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H

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P P

S S

T T

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(1)8

(I)

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~

(CH

I)

W¢31

0¢7

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E

H

K

M

P

S

T
V

(CH

2)

W031

011

(15'

E

H

K

M
P

S

T
V

4

"-"

'--'

(CH~)

(CH

Il

(CH 2)

NOTE:

PINS

C,F,

J, L,N,R,U

ARE GND

FOR

ALL

WQl31'S

AND

Wr/J33'S

3 2

D

c

B

A

3

2

BS-DM09-A-4 Sheet 1

of 2 Cable

Diagram

21

D

c

B

A

8

7

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\1'1031

,ClIO

: C(;llI

I I

C~(,i'DP.-f'.b-;-

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M

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----;-------=-~.

P

CP5

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I T

(j)'7

----;-----ec...:.~.

t v

Crl

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FI

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B-CS-R302-0-1

One-Shot

36

Delay

DIGITAL

EQUIPMENT

CORPORATION.

MAYNARD.

MASSACHUSETTS

Printed

in U.S.A.