Digital Equipment GT44 User Manual
~TAA
U
.........
user's
guide
IIIIIII
~TAA
U
.........
user's guide
DEC-II-HGT44-A-D
digital equipment corporation · maynard. massachusetts
Copyright © 1973 by Digital Equipment Corporation
1st Edition, December 1973
. The material in this manual
purposes and
Digital Equipment Corporation assumes no responsibility
manual.
is
subject to change without notice.
tOI
any errors which may appear in this
Printed
The foHowing are trademarks
in
is
U.S.A.
of
for informational
Digita1
Corporation, Maynard, Massachusetts:
Equipment
DEC
FLIP
CHIP
DIGITAL
UNIBUS
PDP
FOCAL
COMPUTER
LAB
CONTENTS
Page
1.1
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.302
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.5.1
2.1.5.2
3.1
3.1.1
3.1.1.1
3.1.2
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.6.3
PURPOSE
GENERAL
SYSTEM DESCRIPTION
EQUIPMENT
OPERATING CONTROLS
GT44
GT44 PROGRAMMING CONCEPT .
IMPORTANT
PDP-l1i40
VT11 INSTRUCTION SET
PROGRAMMING
PROGRAMMING RESTRICTIONS
AND
SCOPE
DESCRIPTION
PDP-11/40 Computer
Unibus
KD11-A Processor
KY11-D Programmer's
M F
ll-L
Power System
VT11 Graphic Display Processor .
VR17
Cathode
375
Light
Pen
LA30-S DECwriter
RK05
Disk Drives and RK11-D Disk Drive Control
BM792YB Bulk Storage Bootstrap Loader
SPECI
PDP-l1/40
VT11 Graphic Display Processor
VR17
375
LA30
R K05 Disk Drive
PDP-11/40
VR
17
LA30
R K05 Disk Drive
Circuit Breakers and
OPERATING PROCEDURES .
GT
44
GT44 Failure Procedures
Initializing the Display Processor
Display File
Application
Stop
Display File
Non-Flicker Display
Processor
CRT Display
Light
Pen
DECwriter
CRT Display
DECwriter
Circuit Breakers
Fuses
Start
Up
Duplicating the System Disk
ADDRESSES
INSTRUCTION SET .
EXAMPLES
of
and
Sync, Microcoding .
Changes
..........
AND
............
Core Memory
......
Ray
Tube
..............
and
DL
FICATIONS
.....
Monitor
.........
and
DL
and
R K
AND
...........
Monitor
...
..
. . . .
Fuses
..........
Procedures
..........
the Stop
Interrupt
.....
........
OPERATION
......
Console
..
Monitor
11
Asynchronous Line Interface
..
11
Asynchronous Line Interface
l1-D
Controller . . . . .
INDICATORS
. .
...
....
..
.
.
1
2
.
.
2
2
3
3
.
4
5
....
.
.
.......
5
5
6
6
..
.....
7
7
.
7
7
8
. . . . .
..
8
9
9
.....
.
....
.
.
.
.
..
..
10
10
12
12
12
12
12
12
12
15
15
16
17
18
20
· 20
· 20
20
20
21
· 22
.22
·
22
· 28
iii
CONTENTS (Cont)
Page
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4~8
APPENDIX A
APPENDIX B
Figure No.
1
2
3
4
5
6
7
8
9
ADVANCED
Subroutines
Light
Special Characters
Edge
GT44 SOFTWARE
CHARACTE
BM792-YB
Relationship
PDP-11/40 Programmer's Console
LA30
K05
R
Memory
Instruction Word Functions
Data Word Formats
Non-Flicker Display
Subroutining Example
PROGRAMMING TECHNIQUES
Pen
Interaction
Violations
..
R CODES
BULK
STORAGE BOOTSTRAP
ILLUSTRATIONS
of
GT44 Components
DECwriter Console
Controls and Indicators
Layout
Example
as
Determined
.........................
Title
to
the Unibus
by
Vector
LOADER
Quantity
PROGRAM LISTING
and Magnitude
.
28
28
30
30
31
31
Page
11
13
14
17
23
24
29
30
Table No.
1
2
3
RK11 Registers
Controls and
Recommended GT44 Mnemonics
Indicators
TABLES
Title
Page
6
14
26
iv
GT44 USER'S GUIDE
GT44 Graphics System
1.1
PURPOSE
This guide describes the operation of
System.
description
AND
SCOPE
The
following information
and
operation,
equipment
the
GT44
Grapnlcs
is
included: system
specifications, controls and indicators, start-up procedures, and programming
techniques.
the
functional units
System,
user, arid
more detailed sources
It
is
the
intention
that
to
present in brief, information
to
reference, where necessary, additional and
of
of
this guide
make
up
information.
to
the
GT44 Graphics
of
relevance
tie
together
to
the
1.2 GENERAL DESCRIPTION
The
DECgraphic
ful disk-based PDP-11/40
been added.
require a visual display, a high
capability, and mass data storage. With its
the
GT44 has access
any
time. Its 16K
operating system such as RT-11/GT,
room
for user programs.
combination and
interaction. Because graphic capabilities have been added
the
software system, processor
The
11/40
GT44
to
which graphic capabilities have
GT44
is
designed for applications
to
2.4
million 16-bit words
of
core memory allows use
The
the
DECwriter provide
Graphics System
order
of
two
yet
leaves adequate
CRT
monitor/light
for
and
display utilization
is
a power-
that
computation
disk drives,
of
data
at
of
an
pen
user-system
to
is
simplified.
1.3 SYSTEM DESCRIPTION
ponents:
a.
PDP-11/40
Computer
1. Unibus
2.
KD11
3. KY11-D Programmer's Console
4. MF11-L
5. Power
b.
VT11 Graphic Display Processor
c.
VR17
CRT
Display Monitor
375
d.
e.
Light Pen
LA30 DECwriter with DL
Interface
f.
Two
RK05 Disk Drives with RK11-D Control-
ler
g.
BM792YB Bulk Storage Bootstrap Loader
ROM.
Figure 1 shows
the
Unibus.
the
relationship
The
following sections briefly discuss these
components.
AND
OPERATION
Central Processor
16K
Core Memory
Supply
11
Asynchronous
of
the
GT44
components
to
RK05
DISK
DRIVE
CONTROLLER
RK11
DRIVE
PDP-11/40
CPU
RK05
DISK
DRIVE
LA30
DECwriter
DL11
A SYNC HRONOUS
LI
NE INTERFACE
UNIBUS
MF11-L
MEMORY
ROM
VT11
DPU
LIGHT
PEN
Cp-0156
Figure 1 Relationship
of
GT44
Components
to
the
Unibus
1.3.1
PDP-ll/40
The
PDP-ll/40
microprogrammed
and
instructions and
PDP-l1/40
which can directly address
memory.
(including processor, core memory, and peripherals)
performed
of
device-to-device transfers can be
2.5
peripherals are linked
and
Therefore,
also be applied
enabling peripheral device registers
the
Subsequent
tion
1.3.1.1 Unibus munication between system
data,
transfers
of
repertoire
and
interfaces. The asynchronous nature
also eases design
operations
All
the
bus concept,
million words per second. All system
all peripherals are in
processor as flexibly as memory.
of
the
address,
to
the
bus an
design
Computer
is
a 16-bit general purpose, parallel logic,
computer
contains a multiple
communication
on
a single high-speed bus,
all
instructions applied
to
paragraphs present a brief functional descrip-
PDP-ll/40.
The
and
control lines,
occur between all units
important
of
bus operations
economy,
and
is:
using single
2's
complement
word
up
among system
all
peripherals are compatible, and
accomplished
by
the
Unibus and power connectors,
the
basic system address space.
data
in
peripheral device registers,
Unibus provides high-speed com-
components.
factor
in
is
flexible enough for speed
yet
provides a fixed specification for
operation.
and
double oper-
arithmetic.
instruction processor,
to
28K
words
of
components
the
Unibus. Because
at
the
components
to
data
in
memory
to
be manipulated
With bidirectional
the
Unibus allows
on
the
bus, with control
these transfers.
of
The
repertoire
The
these operations
rate
of
The
core
and
can
data
fixed
bus
,
DATI, DATIP, DATO, DATOB - data operations
INTR, PTR (BR, NPR) - control operations
Full 16-bit words
transferred
DATI, DATIP operations transfer data into
DATO, DATOB operations transfer
When a device
requests use
make a Direct Memory Access (DMA) transfer of data
directly
processor intervention,
execution
address where an
Bus
(NPR)
INTR. A device can perform a
control
to
and force
control
for
via
on
the
a BR.
the
of
or
is
DMA
the
from
obtained
or
8-bit bytes
bus between
is
capable
bus, it
another
or
the
interrupt
or
under a Bus Request (BR) for an
of
information can be
the
master
and
slave.
The
the
master;
data
out
of
the
master.
of
becoming bus master and
is
for
one
of
two
purposes:
device
or
memory
to
INTeRrupt
processor
service
routine
under a Non-Processor Request
DMA
(lNTR) program
to
branch
is
after
without
to
a specific
located.
acquiring bus
is
of
by
to
the
Requests for
and
NPR lines. Transfer
another
which grants control
highest priority. NPRs are accorded higher priority
BRs.
Unibus data cycles, in
WAIT
completion
priority exceeds
The
operations
the
when no
The
Internal Unibus
Unibus
Unibus signals
module. A
system units
peripheral device removed
A
tions,
1.3.1.2
codes instructions; accepts, modifies, and
performs
the
sixteen hardware registers, eight
mable.
specifically used for processor operation: a program count-
er (PC)
arithmetic
and
The
of a variety
source
register,
operation
Because
modes, instruction set,
written
includes a
byte
words or bytes may be displayed on
console.
is
The
or
PDP-l1
next
bus master.
other
Unibus originates
from
complete
is
presented in
KDll-A
arithmetic
Unibus among external devices.
Two
and
autodecrement
eight non-programmable registers are used for storage
and
the
data.
of
in directly relocatable codes.
operands and provisions for
bus can be made
of
bus control from
made by
NPRs are serviced before
TRAP
/40
as
120-conductor
accumulators, index register, and
full
the
processor priority arbitration logic
of
the
addition
sequences.
of
the
current
that
of
the
processor.
processor has a special role
it performs
device has
and
the
processor
and
in
different mounting boxes
description
Processor-The
of
the
a stack
of
functions including: intermediate address,
destination
last
the
flexibility
complement
the
The
processor assumes bus control
control.
in
the
Terminator
to
17
grounds are carried
Mylar cable
from
of
the
the
PDP-11 Peripherals Handbook.
operations; and controls allocation
eight programmable registers are
pointer
registers.
data, a copy of
interrupt
of
and
DMA, PDP-11
of
at
any
time
on
the
one
device
bus
to
the
device having
and
immediately
to
specific times during
The
BRs are serviced upon
instruction
priority arbitration
processor with
module, which carries
the
the
Unibus, including specifica-
(SP);
the
vector address and console
hardware registers, address
instructions
if
the
in
next
system unit.
is
used
or
to
mounting box.
KD11-A Processor de-
outputs
The
processor contains
of
which are program-
remaining six serve as
autoincrement
the
/40
programs are
The
processor also
that
byte
swapping. Either
the
programmer's
after
requesting
bus control
to
select
the
M981
All
in
this
to
connect
connect
data;
instruction
manipulate
BR
the
than
the
56
one
to
a
of
2
Any
of
the
eight
programmable
used
to
build last-in, first-out stacks.
processor (or
This stack-handling
the
program
subroutine
reentrant
The
Unibus serves
therefore,
which
requests use
non-processor
or
to
interrupt
to
branch
granted
device-to-device
tion.
A B R
instruction
calls
codes
there
device
to
by
the
and
system)
counter
and
and
must
becomes
of
the
transfer
program
an
processor
data
is
granted
allows
stack
pointer
capability
and
status
interrupts.
automatic
the
processor
nesting
be a priority
bus master. General!y, a device
bus
for
one
of
data
directly
execution
interrupt
at
the
service
end
transfers
by
the
the
device
processor task.
The
processor recognizes
each major level
attached
on
containing
each
electrically closest
devices
processor itself
on
the
same
is
programmable
therefore, a running
permissible
Additional
structure
interrupt
identifies itself,
automatically
device polling
tines.
priority
system
The
are
18-bit
word
Thus,
references up
interrupts.
speed
through
scheme. With
and a unique
selected
and
The
device
are
independent
behavior in response
Unibus addresses
direct
byte
length
and
while
the
PDP-11/40
to
four
sublevels. Many devices
major
level,
to
the
processor given
priority
program
and
power
the
use
of
vectored
by
the
permits
interrupt
to
to
generated
addresses, even
operational
word
32K
words
levels
level.
can select
are
the
nesting
priority
allow
real-time
logic
Processor can reference addresses
bytes).
In
addition
addressing space,
are reserved
ters. ! n the basic
to
for
peripheral
the
the
uppermost
PDP~
word
length
control,
11/40 configuration,
internal registers
One
register serves as a
for
automatic
permits save
word
This
and
and
in
conjunction
feature
of
subroutines.
all peripheral devices;
structure
of
two
reasons:
to
or
from
and
force
routine.
of
bus cycles
without
processor
processor interven-
at
to
interrupt
of
hardware
with
the
the
device
priority
The
priority
within
the
hardware
the
priority
added
to
PDP-11
/40
fully
interrupts,
interrupt
service
processor. This
of
device service rou-
and
service
dynamic
adjustment
conditions.
by
the
KD11-A Processor
though
the
is
16-bit
can
only
contain
(64K
bytes),
up
to
128K
constraint
4K
words
of
status,
and
stacking.
restore
allows
to
determine
to
make
memory,
the
processor
An
NPR
and
e~d
the
current
B Rs,
that
over
level
level
the
interrupt
vectored
the
routine
eliminates
routine
PDP-11/40
word
length.
address
the
KD11-A
words
on
address
data
all
address
can
with
true
allows
of
with
can
other
of
the
levels;
device
(256K
basic
space
regis-
be
of
a
is
an
be
is
of
is
of
references
space
references
16-bit
converted
773224
can
words
detailed
A
tained
to
the
(160000-177777)
with
bits
reference
to
a full
Consequently,
•
8
address
up
to
of
I/O device registers.
description
in
the
KD11-A Processor Manual, DEC-11-H KDAA-
uppermost
16
and
to
address
18-bit
the
28K
words
of
4K
words
of
16-bit
are
converted
17
always
1732248 is
to
set
to
automatically
I/O device register address
basic PDP-11
of
the
KD11-A Processor
core
/40
configuration
memory
A-D.
1.3.1.3
Programmer's
direct
stop,
Console displays indicate processor
contents
mounted
and
The
through a microprogram
The
diodes),
for
certain
for
the
whose
Console
and
descriptions
KD11-A Processor Manual, DEC-11-HKDAA-A-D.
1.3.1.4
GT44
capacity.
mounted
is
The
used
The
from
however,
structure,
processor
operand
a true arithmetic accumulator.
KY11-0
system
interface.
load,
modify,
of
the
as
the
is
connected
programmer's
console
switches,
the
control
Unibus
DEP
and
DATI
processor
priority
operation,
indicators,
of
MF11-L
contains
The
on a double
an
8K,
16-bit
backplane
to
accomodate a third
core
memory
the
processor
is
never bus master. Because
the
or
any
instructions,
Programmer's
Console
provides
The
console allows
examine,
address
front
to
panel
the
and
of
processor
console
control
contains
and
the
only
contact
switches. Console
operations
responds
supersedes all
for
EXAM.
to
through
a Console Bus
other
including
is
presented
console
an
MF11-L
logic circuits are
Core
Memory -The
MF11-L
consists
Core
system
word
memory
has
additional
optional
uses
the
Unibus
and
other
memory
other
every
can
master
location
Console -
the
programmer
step,
or
continue
operation
data
registers.
the
processor
by
two
interacts
with
located
indicators
bounce
operation
the
For
single-step
B R priorities.
descriptions
in Paragraph
Memory
of
2 MM11-L
unit
backplane.
consisting
unused slots
MM11-L
for
data
devices.
be
The
directly
device. Because
in
core
The
the
user
The
mounting
cables.
the
in
the
(tight-emitting
filtering circuits
does
processor: DATO
Request
of
all
2.1.
contained
PDP-11/40
with
Each MM11-L
of
three
which
8K
transfers
core
of
the
addressed
can
address
full
18-bit
1.
Thus,
of
and
4K
is
con-
KY11-D
with
to
start,
a program.
and
the
console
box
processor
processor.
require
operation,
(CBR)
controls
Detailed
in
the
in
the
16K
word
memories
modules.
can be
memory.
to
and
memory,
Unibus
by
the
of
double
function
as
a
a
is
3
The memory does
it
is
always a slave device.
request use of
either a
BR
independent of
perform direct data transfers with memory
not
enter
the
The
the
Unibus,
and
or an NPR. Because
the
processor, any master device can
priority structure because
master device, however, can
thus
the
the
memory,
memory
without
through
is
completely
proces-
sor intervention.
1.3.1.4.1
graphs briefly describe
up
the
MF11-L, and MF11-LP Core Memory
MMll-L
the
MF11-L memory.
Core Memory -
the
MM11-L memories, which make
For
more detailed descriptions of
The
MM11-L and MF11-L memories, refer
following para-
to
the
MM11-S,
Systems
Manual,
DEC-11-HM F LA-B-D.
The
MM
11-L Core Memory
coincident current, magnetic core
of
900
cycle time
memory
It provides
byte
addressable.
The
memory
containing
low-order
15-08).
is
byte
Each
ns
organized
8192
(8K) 16-bit words
is
organized into 16-bit words, each word
two
8-bit bytes.
(bits
byte
is
is
a read/write, random access,
type
memory with a
and Unibus access time
in
a 3D, 3-wire planar configuration.
that
The
bytes are identified
07-00)
and
the
of
400
ns.
are
both
word and
as
high-order byte (bits
addressable and has its own address
The
the
location. Low bytes are always even numbered and high
bytes are
even-numbered locations only. When a full word
dressed,
example,
therefore,
the
000002
odd
numbered. Full words are addressed
the
the
8K
16,384
high byte
memory has
locations are assigned. Address
is
automatically included. For
8,192
first low byte, address 000001
is
the
second low byte,
000003
words
is
the
or
is
at
is
ad-
16,384
bytes;
000000
first high byte,
the
second high
byte, etc.
The
MM11-L consists of
module containing
the
channels; a G231 Hex module containing
driver logic; and an H214 Quad module containing
three
modules: a
G110
Hex
memory control logic and data
the
memory
the
memory core stack.
The
memory control logic acknowledges
master device, determines which of
tions
(DATI, DATIP,
DATa,
or DATOB)
the
request of
the
four basic opera-
is
to
the
be per-
formed, and sets up appropriate timing and control circuits
to
perform
contains
device selector logic
been addressed from
a 16-bit flip-flop storage register. During
the
desired read
the
inhibit drivers and sense amplifiers
to
the
or
write operation. It also
determine if
Unibus.
The
the
control logic includes
as
well
as
memory bank has
DATI operations,
this register stores
being read (destructive read) so
the
contents of
that
the
memory location
the
data can be written
back into memory (restored). The register
during
DATa
from
and DATOB cycles
the
Unibus lines so
that
to
store incoming data
it can be written into core
memory.
The memory driver logic includes: address selection logic
that
decodes
specifically addressed;
current flow through
proper polarity for
current generators
change
The
ferrite core memory stack consists
arranged
ferrite cores arranged
represents a single bit position
the
incoming address
the
switches and drivers
the
magnetic cores
the
desired function; and
that
provide
the
state
of
the
magnetic cores.
in
a planar configuration. Each mat contains
in a 128 X 64
to
determine
the
necessary current
of
16
matrix. Each mat
of
a word. Each ferrite core
can assume a stable magnetic state corresponding
binary 1 or binary
core,
the
core retains its state until changed by appropriate
O.
Even if power
is
removed from
control signals.
1.3.1.5
Power System -
The
PDP-11/40 power system
consists of an 861 Power Controller, an H742 Power
Supply,
three
H744 +5 V Regulators,
two
Regulators, and interconnection and power distribution
cabling.
The
861 Power Controller controls
is
the
processor cabinet.
The
controller
all
ac power
is
equipped with a
circuit breaker for overload protection and a thermos1:at for
excessive heat protection.
switched ac
for
the
outputs
entire cabinet and related peripherals.
861 Power Controller
two
controllers
display
of
The
monitor
either controller.)
H742 Power Supply takes ac
operate
may be plugged into
The
power controller provides
(uncontrolled) which provide power
is
located
in
in
parallel.
input
the
drives cabinet.
The
the
switched
pmNer
Power Controller, generates and distributes dc power and
control signals
to
the
system, and provides ac power
logic cooling fans and H744 and H745 regulators.
There are
DC
signal
synchronize
warn
processor time
three
control signals generated: a clock signal, a
La
logic signal, and an
is
used by
the
processor of imminent power failure, allowing
the
the
display.
to
perform a power-fail sequence.
AC
La
logic signal.
VT11 Graphic Display Processor
The
AC
LO
and
is
also used
the
core
that
direct
to
ensure
the
the
X and Y
to
memory mats
8192
to
either a
the
H745
-15
V
input
to
(A
second
The
DECwriter and
outputs
from
the 861
to
the
The
clock
to
DC
LO
signals
the
4
The
H744 and H745 regulators generate
outputs,
respectively, which are
distributed
Processor and MF11-L Memory backplanes and
KY11-D console. H744 +5 V also goes
to
+5
to
the
V and
-15
the
KD11-A
the
VT11 Graphic
Display Processor backplane.
1.3.2
VT11 Graphic Display Processor
The
VT11 Graphic Display Processor
GT44 Graphics System. It
displays and drives
The
VT11 processor consists
that
are
mounted
unit
is
mounted
The
VT11 interfaces with
the
on
inside
It obtains ±22 V power
power
from
the
PDP-11
The
VT11
is
a high performance display processing unit
that
operates
started by
placed
The
VT11 responds by issuing NPRs and fetching its
in
as
a peripheral
the
central processor when a valid address
the
Display Processor Program
is
the
CRT.
a 4-slot systems unit backplane.
the
PDP-11
the
system
from
/40
power supply.
of
display program from memory locations specified by
DPC. Once
the
display processor
is
VT11
of
three
/40
cabinet.
by
the
VR17 CRT
the
PDP-11
is
granted control
the
"heart"
that
of
generates
the
the
hex-height modules
The
way
of
the
Unibus.
and
+5 V
/40.
The
VT11
Counter
(DPC).
the
of
the
Unibus it can fetch its display program, and execute it
independently.
The
VT11 also issues
when it encounters an illegal character code
If
memory.
enabled by program, it will issue an
when instructed
to
interrupts
stop,
or
when
to
the
central processor
or
a light pen
unresponsive
interrupt
hit
is
sensed.
V
rather
than
the
storage
image, with excellent
motion
the
characters
clock
synchronized
The
and
line.
or
while changes are being made in
picture. A hardware blink feature
or
graphics drawn
input
to
the
to
line frequency.
VT11 includes logic for descender characters such as p
g, positioning
In
addition
type
so
that
a bright,
contrast
ratio,
is
is
on
the
screen. A separate line
display processor permits
them
to
the
correctly
96
with
respect
ASCII printing characters,
provided during
applicable
special characters are included which are addressed
the
shift-in/shift-out control codes (Appendix A). These
special characters include some Greek letters, architectural
symbols, and math symbols. Characters can be drawn
italics simply by selecting
the
feature through
instruction bit. Eight intensity levels permit
and
contrast
to
be varied so
that
the
scope can be viewed
a normally lighted room.
The
is
is
instruction
six
data
data
interpretation,
image, and allow branching
can be
interpreted
multiple tasks
core usage and
the
VT11 automatically plots
preset distances as values for
For a detailed description
Processor see
formats.
to
the
set
consists
The
in
control
set
the
any
of
five control instructions
instructions set
parameters
of
of
six
the
different
of
instruction flow. Data
formats, allowing
be accomplished efficiently from
time
standpoint.
VT11 Graphic Display
The
the X or
the
opposite
of
the
graph/plot
Y axis according
axis are recorded.
VT11 Graphic Display
Processor
DEC-11-HVTGA-A-D.
continuous
the
elements
the
VT11
to
the
the
brightness
the
the
feature
of
to
any
to
be
the
text
31
through
in
status
in
and
mode
of
displayed
both
of
to
Manual.
a
The VT11
is
a stable device
that
requires only minimum
adjustments because it employs a combination
and
analog techniques
The
vector function operates efficiently, providing a good
compromise
of
vector calculation.
vectors means
that
as
opposed
to
analog circuits alone.
speed and accuracy and assuring a precise
The
presentation and accumulation
every point
of
a vector
is
digital form.
All
beam position calculations are
plotting each vector,
updated
to
the
end-point position
the
digitally calculated values, preventing
accumulated errors or drift.
types
- solid, long dash,
possible
The
through
VT11 character generator has
standard hardware.
short
case capability with a large repertoire
characters.
The
display
is
the
done
digitally. After
is
automatically
Four
different vector
dash, and
both
dot
upper and lower
of
automatically refreshing
of
digital
of
available
dash - are
displayable
type
1.3.3
VR17
Cathode Ray
The
VR17
is
a completely self-contained
provides a
package.
information
displays. Except
all solid state circuits, utilizing high-speed magnetic deflec-
in
tion
In addition,
maintenance.
to
enhance
9.25
inch by
The
VR17
and
intensity signals
for
brightness and resolution.
the
VR17
Any
subassembly
Tube
9.25
requires
the
CRT
construction
Monitor
CRT
inch viewing area
only
analog X and Y position
to
generate sharp, bright
itself,
the
unit
is
is
modular for easy
or
major
component
replaced in minutes, using only a screwdriver.
For
a detailed description
VR14 and VR17 CRT Display
of
the
VR17
CRT
User's
DEC-12-HVCRT-D-D.
1 .3.4
375
Light Pen
The
375
Light Pen
by
the
operator
5
is
a pencil-shaped light
in
a wide range
detector
of
interactive applications.
display
that
in a compact
composed
of
can be
monitor
see
Manual,
for use
The
375
uses
a photo-sensitive transistor for high gain and
In
fast response.
matching spectral response
the
375 yields very good light pen capability, without the
normally attendant
addition, an infrareq doped phosphor and
in
the photo-detector
visual
flicker of the fast phosphor
component.
is
The 375
attached to
connected to
the
front panel of the CRT monitor; it
removed by simply unplugging it from
G840 Light Pen Amplifier
cabinet. The
VT11
output
by way of
the
the
is
of
the
light
scope cable.
VR
17 by a flexible cable
the
CRT panel. The
situated inside
pen
amplifier
the
is
fed
used
is
easily
VR17
to
in
the
DEC-OO-LA30-DD.
interface
Interface Manual,
1.3.6 R
is
K05 Disk
The GT44 Graphics System contains two R
Drives. Each R
storage device
A detailed description of the
presented
in
the DL
11
DEC-11-HDLAA-A-D.
Drives
and R K11-D Disk
K05
is
a self-contained, random-access, data
that
is
especially
well
Asynchronous Line
Drive
Control
K05
suited for
use
in
DL
Disk
small
11
or medium size computer systems, data acquisition systems,
to
K05
the disk
Disk
Drive
terminals, and other storage applications. Power
is
drives
the
controlled by
bottom of
has its own internal power
an
861
Power Controller mounted at
the
drives Cabinet. Each R
supply.
1.3.5 LA30-S
DECwriter and
DL
11
Asynchronous Line
Interface
The LA30-S DECwriter
keyboard for
use
of printing a set of
is a dot
as
a hard copy I/O terminal.
64
ASCII
matrix impact printer and
characters at speeds up
It
is
capable
to
30
characters per second on a sprocket-fed 9-7/8 inch continu-
is
ous form. Data entry
from a keyboard capable of
generating 128 characters.
LA30-S
The
uses the D L 11-A Asynchronous
it
with the Unibus. Serial information read or written by
the
LA30 DECwriter
DL
11
also formats
format required by the
that
flags
interrupt
is
a serial asynchronous device, and therefore
Li
ne
is
for parallel transfer
the
data from
I nterface
assembled or disassembled by the
to
or from
the
the
Unibus so
to
Unibus. The
that
it
LA30. The interface provides the
initiate these data transfers and causes a priority
to
indicate the availability of
the
interface
DL
is
in
the
LA30
DECwriter.
DL
11
The
transfers data
via
processor
DATI
and
DATOB
bus cycles. Although a DATO can be used, normal
operation consists of a
and
DECwriter
the
DATOB
interface handle byte rather than word
data. The interface can acquire bus control through a
and
is
normally set
DL
11
interface operates through an interrupt, no
at
the B
transfer because the LA30
R4
priority
level.
Because the
BR
NPR
hardware exists.
The R K05
disk cartridges for data storage. Data
is
a moving-head disk drive
that
is
stored on both sides
of the disk by a pair of movable heads, which are always
positioned over opposing surfaces of the same
simultaneously. Each side of the disk contains 203
tracks, each of which contains 12
storing
4008 or 256
0
data words.
1
The sector format consists of 15
in
terminating
a sync bit, followed by a one-word header,
sectors capable of
10
words of preamble
8
4008 data words, a one-word checksum, and one word of
postamble. Sector pulses signal the beginning of each
sector, and an index pulse indicates the last sector,
that
the sector following
is
sector
O.
11
The
RK11
Controller and the RK05
Disk
disk drive system, which interfaces with the
processor
K05
R
The R
via
the
Unibus. One R
Disk
Drives.
K11
contains seven 16-bit programmable hardware
K11
can control up to eight
registers, addressed from the Unibus, that provide
software interface between
1 lists these registers and their addresses.
Table
detailed discussion of R K
the R K11
11
registers
and the Unibus.
is
provided
graph 4.2).
Table 1
RK11
Registers
uses
Drives
R K03-KA
cylinder
10
form the
PDP-11/40
the
(A
more
in
Para-
DL
11
The
installed
(SPC)
decoding
generating
performs
LA30 DECwriter controls and indicators are covered
The
Paragraph 2.1.3
contained
consists of a single quad module which
in
the processor
in
a Small Peripheral Controller
slot. This module contains address selection logic for
the
incoming bus address,
the
interrupt, and receiverltransmitter logic
the
conversion and formatting functions.
..
Il.
detailed description of
in
the
LA30
DECwriter Maintenance Manual,
an
interrupt control for
that
the D EC-v-vriter
in
is
K11
R
R
K11
RK11
R Kl1
R
K11
(Current Memory Address)
R
is
K11
RK11
Name Abbreviation
Drive Status Register
Error Register
Control Status Register
Word
Count Register
Bus
Address Register
Disk Address Register
Data Buffer Register
RKDS
RKER
RKCS
RKWC
RKBA
RKDA
RKDB
Address
777400
777402
777404
777406
777410
7774i2
777416
6
Through software control,
the
RK11 can perform
four
control functions (Control Reset, Seek, Drive Reset, and
and
four
Write Lock)
Write Check,
transfer
R
KWC,
and
is
initiated by
a memory address
R KDA, and a code for
data transfer
Read Check).
the
CPU by storing a
"go"
RKCS. More detailed information
and
the
R K11-D Disk Drive Controller may be
RK05
Disk Drive Maintenance Manual (DEC-00-RK05-DB)
and
the
RKll-D
Controller Manual
1.3.7 BM792YB Bulk
The
BM792YB Bootstrap Loader
and
RKll-E
(DEC-11-HRKDA-B-D).
Storage Bootstrap Loader
matrix ROM, implemented on a
situated
program starting address
The
words
memory by
from location
assumed
The
in
the
PDP-11/40 mounting box. The BM792YB
is
773100.
actual
of
a disk
to
bootstrap
the
be
loader program, stored
is
transferred from
BM792-YB program.
0
of
the
disk and
operative
at
BM792-YB program jumps
satisfactory completion of
automatic
If
BM792-YB program,
The
bootstrap
starting
of
the
actual
error conditions occur during
the
program starts over again.
sequence
1.
of
operations used by
loader
is
as
follows:
It determines which device
by sensing an address
2.
It reads
256
words
starting with address
3.
The
loader
then
functions
For
example, a disk data
in
R KBA, a disk address
and direction (read
on
the
Moving Head Disk Drive
is
quad
size module, which
the
The
the
(Write, Read,
word
count
or
write) in
RK05 Disk Drive
found
in
a 32-word,
in
the
diode
first
disk into read-write
transfer
is
started
loaded routine
read-write memory location
to
the
transfer, so
bootstrap
set
0
of
stores
location 0
the
in
the
stored
the
the
loader program.
running
the
is
to
Switch Register.
from
disk.
256
after
that
there
of
bulk storage
be
read from
the
disk,
words
the
256
the
read-write memory sequential locations, starting with location
O.
in
in
is
O.
a
is
in
1.4
EQUIPMENT SPECIFICATIONS
Specifications
Graphics
PDP-11/40 Processor
1.4.1
to
Refer
coverage
1.4~2
VT11 Graphic Display Processor
Input
Power
+5 V at
+15
+22 V at
-22 V at
is
I nstruction Word Length
16
Raster Definition
10
Viewable Area
X =
Y =
Paper Size
12
Hardware Blink
Programmable
Hardware
8
Line
Frequency
Hardware programmable
Character
6 X 8
Characters/Line
73
of
the
components
System
of
are covered
the
PDP-11/40 Processor Handbook
in
the
PDP-11/40 specifications.
8 A
Vat
100 rnA
500
rnA
500
rnA
bits
bits
1024
raster unit (1777
1024
raster units (1777
)
8
)
8
bits
I ntensity Levels
Synchronization
Font
dot
matrix
(85 possible)
that
make up
the
GT44
following paragraphs.
for
detailed
4.
The
loader checks for errors and starts
program over if any errors occur.
5.
The
loader
then
jumps
location
bootstrap
A program listing for
provided
BM792YB
Only-Memory and
in
Appendix
bootstrap
0 for
automatic
loader program.
the
bulk storage
B.
For
a detailed description of
loader refer
MRll-DB
Bootstrap Loader Manual
(DEC-11-HBMD-D).
to
read-write memory
starting of
the
bootstrap
to
the
BM792
the
actual
loader
the
Read~
Number
of
Li
nes
42
Character
Set
96
ASCII - upper and lower case plus
31
specials
(GTeek letters, math symbols, etc.) (Refer
Appendix
A)
to
is
Control Characters
Line feed
Backspace
7
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