Digital Equipment AlphaPC64 User Manual

AlphaPC64Motherboard
User’sManual

Order Number: EC–QLJKB–TE

Revision/Update Information: This document supersedes the

AlphaPC64 Motherboard User’s Manual

(EC–QLJKA–TE).

Digital Equipment Corporation
Maynard, Massachusetts

July 1995

Possession, use, or copying of the software described in this publication is authorized only
pursuant to a valid written license from Digital or an authorized sublicensor.

While Digital believes the information included in this publication is correct as of the date of
publication, it is subject to change without notice.

Digital Equipment Corporation makes no representations that the use of its products in the
manner described in this publication will not infringe on existing or future patent rights, nor do
the descriptions contained in this publication imply the granting of licenses to make, use, or sell
equipment or software in accordance with the description.

© Digital Equipment Corporation 1995.
All rights reserved.

Printed in U.S.A.
AlphaGeneration, DEC, DECchip, DECladebug, Digital, OpenVMS, VAX, VAX DOCUMENT,

VMS, the AlphaGeneration design mark, and the DIGITAL logo are trademarks of Digital
Equipment Corporation.

Digital Semiconductor is a Digital Equipment Corporation business.
Digital UNIX Version 3.2 for Alpha is a UNIX 93 branded product.

Centronics is a trademark of Genicom Corporation.
CompuServe is a registered trademark of CompuServe, Inc.
GRAFOIL is a registered trademark of Union Carbide Corporation.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Intel and UPI are trademarks of Intel Corporation.
MACH is a trademark of Advanced Micro Devices, Inc.
Micron is a registered trademark of Micron Corporation.
Motorola is a registered trademark of Motorola, Inc.
National is a registered trademark of National Semiconductor Corporation.
Microsoft is a registered trademark, NT, and Windows NT are trademarks of Microsoft
Corporation.
OSF and OSF/1 are registered trademarks of Open Software Foundation, Inc.
PHOENIX is a registered trademark of Phoenix Technologies, Ltd.
PS/2 is a registered trademark of International Business Machines Corporation.
SPEC is a trademark of Standard Performance Evaluation Corporation.
TriQuint is a registered trademark of TriQuint Semiconductor, Inc.
UNIX is a registered trademark in the United States and other countries, licensed exclusively
through X/Open Company Ltd.

All other trademarks and registered trademarks are the property of their respective owners.

This document was prepared using VAX DOCUMENT Version 2.1.

Contents

About This Manual ........................................... vii

1 AlphaPC64 Introduction

1.1 The AlphaPC64 Motherboard . ........................... 1–1

1.2 System Components and Features........................ 1–1

1.2.1 Memory Subsystem ................................ 1–1

1.2.2 DECchip 21072 Support Chipset . . . ................... 1–4

1.2.3 PAL Control Set ................................... 1–4

1.2.4 Level 2 Cache Subsystem Overview . ................... 1–4

1.2.5 Clock Subsystem Overview .......................... 1–5

1.2.6 PCI Interface Overview . . ........................... 1–5

1.2.7 ISA Interface Overview . . ........................... 1–5

1.2.8 Software Support .................................. 1–6

1.2.9 Component Layout ................................. 1–6

1.2.10 System Summary .................................. 1–6

2 System Jumpers and Connectors

2.1 Configuration Jumpers ................................. 2–1

2.1.1 Software Configuration Jumpers . . . ................... 2–1

2.1.2 Hardware Configuration Jumpers . . ................... 2–6

2.2 AlphaPC64 Board Connectors ........................... 2–7

3 Starting and Using the AlphaPC64

3.1 Hardware Requirements ............................... 3–1

3.2 Software Requirements ................................ 3–2

3.3 Hardware Configuration ............................... 3–2

3.4 Software Configuration ................................ 3–9

3.4.1 Starting Windows NT ARC Firmware .................. 3–9

3.4.2 Going to the Debug Monitor from Windows NT ARC

Firmware ........................................ 3–9

iii

3.4.3 Returning to Windows NT ARC Firmware from the Debug

Monitor . ........................................ 3–10

4 Functional Elements

4.1 PCI Interrupts and Arbitration . . ........................ 4–1

4.1.1 System Interrupts . ................................ 4–1

4.1.2 PCI/ISA Arbitration ................................ 4–5

4.2 ISA Devices . ........................................ 4–6

4.3 dc Power Distribution . ................................ 4–7

4.4 Flash ROM (System ROM).............................. 4–9

4.4.1 Special Flash ROM Headers . ........................ 4–9

4.4.2 Flash ROM Structure............................... 4–12

4.4.3 Flash ROM Access . ................................ 4–14

5 Board Requirements and Parameters

5.1 Power Requirements . . ................................ 5–1

5.2 Environmental Characteristics . . . ........................ 5–2

5.3 Physical Board Parameters ............................. 5–2

A Supporting Vendor Products

A.1 Products Included .................................... A–1

A.2 Products Not Included . ................................ A–2

B Technical Support and Ordering Information

B.1 Technical Support .................................... B–1

B.2 Ordering Digital Semiconductor Products . . ................ B–1

B.3 Ordering Associated Literature . . ........................ B–2

B.4 Ordering Third-Party Documentation ..................... B–4

C Warranty Registration Information

iv

Index

Figures

1–1 AlphaPC64 Functional Block Diagram .................. 1–2

1–2 Maximum and Minimum SIMM Bank Layouts . .......... 1–3

1–3 AlphaPC64 Component Layout and Board Dimensions . . . . . 1–7

2–1 AlphaPC64 Board Jumpers .......................... 2–2

2–2 J3 Jumpers/Connectors . . ........................... 2–3

2–3 AlphaPC64 Board Connectors ........................ 2–8

3–1 Fan/Heat Sink Assembly . ........................... 3–4

3–2 AlphaPC64 Power Connectors ........................ 3–7

4–1 Interrupt Control and PCI Arbitration .................. 4–2

4–2 Interrupt and Interrupt Mask Registers ................ 4–5

4–3 ISA Devices . . . ................................... 4–6

4–4 dc Power Distribution . . . ........................... 4–8

4–5 Special Header Content . . ........................... 4–9

5–1 Board Component Layout ........................... 5–3

Tables

1–1 L2 Cache SIMM Sizes . . . ........................... 1–5

1–2 AlphaPC64 Summary ............................... 1–8

2–1 Jumper Position Descriptions......................... 2–4

2–2 AlphaPC64 Board Jumpers .......................... 2–6

2–3 Module Connector Descriptions ....................... 2–9

4–1 CPU Interrupt Assignment .......................... 4–3

4–2 Special Header Entry Descriptions . ................... 4–10

4–3 Higher 512KB Flash ROM Image Selection .............. 4–12

5–1 Power Supply dc Current Requirements (275 MHz)........ 5–1

5–2 Board Component Descriptions ....................... 5–4

v

This manual describes Digital’s AlphaPC64 motherboard, a module for
computing systems based on the Alpha 21064A microprocessor and the
DECchip 21072 chipset.

Audience

This guide is intended for users of the AlphaPC64 to assist them in installing
the board and populating it with memory modules and peripheral cards.

Scope

This guide describes the features, configuration, and installation of the
AlphaPC64. This guide does not include specific bus specifications (for
example, PCI or ISA buses). Additional information is available in the
appropriate vendor and IEEE specifications. See Appendix B for information
about how to obtain additional technical support and how to order additional
documentation.

Content

This guide contains the following chapters and appendixes:

About This Manual

• Chapter 1, AlphaPC64 Introduction, is an overview of the AlphaPC64,
including its components, uses, and features.

• Chapter 2, System Jumpers and Connectors, describes the user
environment configuration; board connectors and functions; jumper
functions; and identifies jumper and connector locations.

• Chapter 3, Starting and Using the AlphaPC64, lists additional hardware
and software requirements, provides information on how to configure the
hardware and software, and describes the board startup procedures.

• Chapter 4, Functional Elements, describes some of the functional elements
of the AlphaPC64, such as, interrupt assignments, flash ROM contents,
and power distribution.

vii

• Chapter 5, Board Requirements and Parameters, describes the AlphaPC64
power and environmental requirements, and identifies major board
components.

• Appendix A, Supporting Vendor Products, lists suggested vendor sources
for supporting components, such as, power supply, SIMMs, enclosure, and
so forth.

• Appendix B, Technical Support and Ordering Information, describes how to
obtain Digital Semiconductor information and technical support, and how
to order Digital Semiconductor products and associated literature.

• Appendix C, Warranty Registration Information, provides information on
how to register your AlphaPC64 motherboard and be notified of changes
and updates.

Document Conventions

This section provides the conventions used in this document.

Caution: Cautions indicate potential damage to equipment or data.
Note: Notes provide additional information.
Numbering: All numbers are decimal or hexadecimal unless otherwise

indicated. In case of ambiguity, a subscript indicates the radix of nondecimal
numbers. For example, 19 is a decimal number, but 1916and 19A are
hexadecimal numbers.

Extents: Extents are specified by a single number, or a pair of numbers in
angle brackets ( < >) separated by a colon (: ) and are inclusive. For example,
bits <7:3> specify an extent including bits 7, 6, 5, 4, and 3. Multiple bit fields
are shown as extents.

Register Figures: Register figures have bit and field position numbering
starting at the right (low-order) and increasing to the left (high-order).

Signal Names: Signal names in text are printed in boldface lowercase type.
For example, ‘‘ . . . bits data<127:0> are delivered to the Bcache SIMM
connectors . . . ’’

viii

AlphaPC64 Introduction

This chapter provides an overview of the AlphaPC64, its components, features,
and uses.

1.1 The AlphaPC64 Motherboard

The AlphaPC64 Motherboard (AlphaPC64) is a module for computing systems,
based on the Alpha 21064A microprocessor and the DECchip 21072 chipset.
The AlphaPC64 runs the Windows NT operating system. For information
on Digital UNIX or OpenVMS operating system support, contact your local
distributor or your Digital sales representative.

1.2 System Components and Features

The AlphaPC64 is implemented in industry-standard parts and uses a 21064A
microprocessor (CPU) running at 200 MHz to 275 MHz. The functional
components are shown in Figure 1–1 and are introduced in the following
subsections.

1.2.1 Memory Subsystem

The AlphaPC64 memory subsystem supports DRAM memory arrays of 16MB
to 512MB with a 128-bit data bus. The memory is contained in two banks of
four commodity single inline memory modules (SIMMs). Each SIMM is 36 bits
wide, with 32 data bits, 1 parity bit, and 3 unused bits with 70-ns or less
access. Figure 1–2 shows the maximum and minimum SIMM bank layouts.
The following SIMM sizes are supported:

1

1M x 36 2M x 36 4M x 36 8M x 36 16M x 36

AlphaPC64 Introduction 1–1

1.2 System Components and Features

Figure 1–1 AlphaPC64 Functional Block Diagram

21064A Support

- TriQuint PLL
Clock

- External Clock
Oscillator

- Serial Boot ROM

- Power Supply

- Supervisor

- System Clocking

Alpha 21064A
Microprocessor
Running at
200 MHz to
275 MHz

L2 Cache

Control

Address

21072 Chipset

DECchip 21071-DA

- PCI Bridge

PCI Devices *

PCI Arbitration

ISA Interface

*Three PCI Expansion Slots with
One Shared Expansion Slot

ISA Expansion Memory Buffering

PCI
Bus

- 208-Pin Package

L2 Cache Interface

- L2 Cache PALs

- Address Buffers

tag_adr

data<127:0>

Address

DECchip 21071-CA

- Cache/Memory
Control

- 208-Pin Package

Memory

Control

buff_

address

oe weand

Check Bits<21, 14, 7, 0>

data<15:0>

AddressISA Bus

- 512KB

- 2MB

- 8MB

- Longword Parity

DECchip 21071-BA

- 128-Bit Data Path

- Requires Four
DECchip
21071-BA Chips

Memory

data<127:0>

L2 Cache SIMMs

Memory SIMMs

- 2 or 3 Expansion
Slots

- National 87312

- Intel 8242 Mouse
and Keyboard

- System Support

- IDE

1–2 AlphaPC64 Introduction

ABT162244
Buffers

b_addr

b_mctl

- 128-bit Data Path

- Longword Parity

- 16MB to 512MB

- 2 Banks

LJ04129A.AI5

1.2 System Components and Features

Figure 1–2 Maximum and Minimum SIMM Bank Layouts

Maximum 512MB DRAM Layout - Populated with 16M x 36 SIMMs

DRAM 2 - 64MB SIMM

memData64 - 95 + Parity

DRAM 3 - 64MB SIMM

memData96 - 127 + Parity

DRAM 2 - 64MB SIMM

memData64 - 95 + Parity

DRAM 3 - 64MB SIMM

memData96 - 127 + Parity

Minimum 16MB DRAM Layout - Populated with 1M x 36 SIMMs

DRAM 2 - 4MB SIMM

memData64 - 95 + Parity

DRAM 3 - 4MB SIMM

memData96 - 127 + Parity

DRAM 2

Unpopulated

DRAM 3

Unpopulated

DRAM 0 - 64MB SIMM

J9

memData0 - 31 + Parity

DRAM 1 - 64MB SIMM

J8

memData32 - 63 + Parity

DRAM 0 - 64MB SIMM

J5

memData0 - 31 + Parity

DRAM 1 - 64MB SIMM

J4

memData32 - 63 + Parity

J9

J8

J5

J4

DRAM 0 - 4MB SIMM

memData0 - 31 + Parity

DRAM 1 - 4MB SIMM

memData32 - 63 + Parity

DRAM 0

Unpopulated

DRAM 1

Unpopulated

J11

Bank 0
256MB

J10

512MB

J7

Bank 1
256MB

J6

J11

Bank 0
16MB

J10

16MB

J7

Bank 1
0MB

J6

LJ04134A.AI

AlphaPC64 Introduction 1–3

1.2 System Components and Features

1.2.2 DECchip 21072 Support Chipset

The 21064A is supported by a DECchip 21072 ASIC chipset (21072), with a
128-bit memory interface. The chipset consists of the following three chips:

• DECchip 21071-CA (21071-CA) provides the interface from the CPU to
cache and main memory, and includes the cache and memory controller.

• DECchip 21071-BA (21071-BA) provides a 32-bit data path from the CPU
to memory and I/O. Four chips provide the 128-bit interface.

• DECchip 21071-DA (21071-DA) provides an interface from the CPU to the
peripheral component interconnect (PCI) bus.

The chipset includes the majority of functions required for a high-performance
PC or workstation, requiring minimum discrete logic on the motherboard. The
chipset provides flexible and generic functions to allow its use in a wide range
of systems.

For more information on the DECchip 21072 chipset, see the DECchip 21071
and DECchip 21072 Core Logic Chipsets Data Sheet.

1.2.3 PAL Control Set

The AlphaPC64 contains a 4-PAL control set and includes the following:

• Two 16V8-5 PALs provide L2 cache output-enable and write-enable
functions.

• One 22V10-25 PAL provides interrupt address decode functions and utility
bus (Ubus) control.

• One MACH210-20 PAL provides the PCI and ISA interrupts.

1.2.4 Level 2 Cache Subsystem Overview

The external level 2 (L2) cache subsystem supports 512KB, 2MB, or 8MB
cache sizes by using a 128-bit data bus. The L2 cache size can be reconfigured
through onboard hardware and software jumpers.

The AlphaPC64 supports the L2 cache SIMM sizes shown in Table 1–1. SIMM
types currently available and supported are 512KB @15 ns and 2MB @12 ns.
Two SIMMs are required per system. See Appendix A for ordering information.

1–4 AlphaPC64 Introduction

Table 1–1 L2 Cache SIMM Sizes

L2 Cache Size Static RAM Access Times

512KB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns
2MB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns
8MB 6 ns, 8 ns, 10 ns, 12 ns, 15 ns

1.2.5 Clock Subsystem Overview

The clock subsystem provides clocks to the 21072 chipset and PCI devices. Two
oscillators provide clocks for the ISA and combination chip functions.

1.2.6 PCI Interface Overview

The PCI interface provides a selectable PCI speed between 25 MHz and
33 MHz (based on the 21064A clock divisor). An Intel 82378ZB Saturn IO
(SIO) chip provides a PCI-to-ISA bridge.

The PCI has three dedicated slots and one shared slot with the ISA.

1.2.7 ISA Interface Overview

The ISA provides an expansion bus and the following system support functions:

1.2 System Components and Features

• Mouse and keyboard controller functions provided through an Intel 8242

chip

• A National 87312 chip used as the combination chip providing a diskette

controller; two universal asynchronous receiver–transmitters (UARTs); an
integrated device electronics (IDE) interface; a bidirectional parallel port;
and an interface to the utility bus (Ubus) for ISA interrupts and jumper
status

• A time-of-year (TOY) function provided by a Dallas Semiconductor DS1287

chip

• A 1MB flash ROM memory using the Intel 28F008SA chip
The ISA has two dedicated expansion slots and one shared expansion slot with

the PCI.

AlphaPC64 Introduction 1–5

1.2 System Components and Features

1.2.8 Software Support

Software support includes an industry-standard, 1MB flash ROM containing
Windows NT ARC firmware and debug monitor code. The debug monitor
allows you to:

• Download files through serial port, I/O diskette, and optional Ethernet
port.

• Load data from the flash ROM through the debug monitor.

• Examine and deposit the AlphaPC64 system register, 21064A internal
processor registers (IPRs), and I/O mapped registers.

• Examine and modify DRAM and I/O mapped memory.

• Disassemble CPU instructions in memory.

• Transfer control to programs in memory.

• Perform native debugging, including breakpoints and single stepping.

• Perform full source-level debugging, using DECladebug running on a host
communicating through an Ethernet connection.

Development code can be generated on a host system and loaded into the
AlphaPC64 through the serial line, optional Ethernet port, diskette, or flash
ROM. Full design database and user documentation are provided.

A serial ROM (SROM) contains the 21064A initialization code. When reset
is deasserted, the contents of the SROM are read into the Icache and are
executed to perform initialization. During initialization, code is loaded from
the flash ROM to memory. Following initialization, control is transferred to the
code in memory.

1.2.9 Component Layout

Figure 1–3 shows the AlphaPC64 board component layout and dimensions.

1.2.10 System Summary

Table 1–2 lists the physical, performance, and operating characteristics of the
AlphaPC64 motherboard.

1–6 AlphaPC64 Introduction

1.2 System Components and Features

Figure 1–3 AlphaPC64 Component Layout and Board Dimensions

22.1 cm (8.7 in ± 0.0005 in)

Scale = 90%

33.0 cm (13.0 in ± 0.0005 in)

LJ-04458.AI5

AlphaPC64 Introduction 1–7

1.2 System Components and Features

Table 1–2 AlphaPC64 Summary

Characteristic Description
Operating Systems

Supported operating
systems

Microsoft Windows NT. For information on Digital UNIX
or OpenVMS operating system support, see your local
distributor or your Digital sales representative.

System Characteristics

CPU and clock speed Alpha 21064A at 200 MHz, 233 MHz, or 275 MHz
CPU upgradable ZIF socket for Alpha 21064A upgrade
Instruction issue Up to 2 instructions issued per clock cycle
Word size 64 bits
Address size 34-bit physical address, 43-bit virtual address
Floating-point format VAX (F and G) and IEEE (S and T) data types
Memory (DRAM)

1

Minimum DRAM 16MB plus parity

Maximum DRAM 512MB plus parity
Memory (ROM) 1MB flash ROM
External L2 cache Configurable for 512KB, 2MB, 8MB (128-bit data)
Memory bus width 128 bits plus parity
Performance metrics

Alpha 21064A running
at 275 MHz

Cache SPECint92 SPECfp92

512KB @15 ns 176 217

2MB @12 ns 193 259

2MB @8 ns 205 272

1

Minimum DRAM recommended:

16MB for Windows NT
32MB for Digital UNIX
32MB for OpenVMS

1–8 AlphaPC64 Introduction

(continued on next page)

1.2 System Components and Features

Table 1–2 (Cont.) AlphaPC64 Summary

Characteristic Description
Graphics

Graphics options Refer to the Microsoft Hardware Compatibility List for

Input/Output

Input device interfaces PS/2 style keyboard and mouse
Serial Two RS423-compatible (9-position) serial communications

Parallel One parallel (Centronics compatible) communications port
Bus options Total of 6 option slots
PCI bus Supports four 5-V/32-bit PCI option slots at 33 MHz

ISA bus Supports three 16-bit ISA option slots
IDE One IDE interface supporting up to 2 drives
Diskette One 82077-compatible diskette controller supporting up to 2

Physical Characteristics

Form factor Baby-AT-size system board
Width/depth 22.1 cm (8.7 in)
Weight 840 grams (1.85 lb) with high-profile heat sink

Windows NT to determine which graphics cards are
supported. See Section B.4 for information on how to obtain
the listing.

ports

maximum–one long and three short cards

drives with 1.44MB and 2.88MB formats

2

33.0 cm (13.0 in)

(continued on next page)

AlphaPC64 Introduction 1–9

1.2 System Components and Features

Table 1–2 (Cont.) AlphaPC64 Summary

Characteristic Description
Environmental Characteristics (Operating)

Temperature 10°C to 40°C (50°F to 104°F)
Temperature change

rate (maximum)
Relative humidity

Maximum wet bulb
Minimum dew point

EMC compliance Compliance certification is the responsibility of the system

Shock and vibration Passing of shock and vibration tests is dependent on the

20°C/hr (36°F/hr)

10%–90% noncondensing

32°C (90°F)

2°C (36°F)

integrator. The AlphaPC64 was tested in industry-

representative enclosures to prove feasibility of emissions

compliance.

method used to mount the system board, the design of the

enclosure, and how the enclosure is supported. Testing is

the responsibility of the system integrator.

1–10 AlphaPC64 Introduction

System Jumpers and Connectors

The AlphaPC64 uses jumpers to implement variations in clock frequency and
L2 cache size and speed. These jumpers must be configured for the user’s
environment. Onboard connectors are provided for the I/O, memory SIMMs,
serial and parallel peripherals, integrated device electronics (IDE) devices, and
L2 cache SIMMs.

After the module is configured, you can apply power and run the debug
monitor. The debug monitor and its commands are described in the Alpha
Microprocessors Evaluation Board Debug Monitor User’s Guide. Appendix B
provides information about other software design tools.

2.1 Configuration Jumpers

The software and hardware configuration jumpers are identified in Figures 2–1
and 2–2, and are described in Tables 2–1 and 2–2.

2.1.1 Software Configuration Jumpers

The software configuration jumpers are completely programmable. Each
jumper position is described in Table 2–1.

2

The SROM code defines the software configuration jumpers sp_bit<7:0>,as
shown in Figure 2–2 (see also Chapter 4).

The board ships with the jumpers listed in Tables 2–1 and 2–2 in the default
position.

System Jumpers and Connectors 2–1

2.1 Configuration Jumpers

Figure 2–1 AlphaPC64 Board Jumpers

J16

J15

J3

2–2 System Jumpers and Connectors

Scale = 90%

LJ-04459.AI5

Figure 2–2 J3 Jumpers/Connectors

2.1 Configuration Jumpers

To Speaker

sysclkdiv

jmp_irq2
jmp_irq1
jmp_irq0

toy_clr
sp_bit0
sp_bit1
sp_bit2
sp_bit3
sp_bit4
sp_bit5
sp_bit6
sp_bit7

hd_act_l
hd_led_l

spkr

Vdd
gnd
Vdd

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2
4
6
8

gnd
reset_button

gnd
key_lock

gnd
power_led_l

LJ-04132.AI

System Jumpers and Connectors 2–3

2.1 Configuration Jumpers

Table 2–1 Jumper Position Descriptions

Select Bit

Register Bit
Name Function

sp_bit7 BOOT_OPTION Jumper out—Boot first image in flash ROM.

Jumper in (default)—Boot one of several alternate
images in flash ROM as specified by NVRAM
location 3F in TOY RAM. See Section 4.4.

sp_bit6 MINI_DEBUG Jumper out (default)—Boot selected image in

flash ROM.
Jumper in—Trap to SROM debug port (J2).

sp_bit<5:3> BC_SPEED<2:0> L2 cache speed selection is shown here.

BC_SPEED

<2> <1> <0>

J3-21 J3-19 J3-17 L2 Cache Period

1

In
In In Out

In In Reserved

2

6ns
In Out In 8 ns
In Out Out 10 ns
Out In In 12 ns (default for

21A02–A3 and 21A02–A4)
Out In Out 15 ns (default for

21A02–A5)
Out Out In Reserved
Out Out Out Reserved

1

Jumper in (logical 0)

2

Jumper out (logical 1)

2–4 System Jumpers and Connectors

(continued on next page)

2.1 Configuration Jumpers

Table 2–1 (Cont.) Jumper Position Descriptions

Select Bit

sp_bit<2:0> BC_SIZE<2:0> L2 cache size selection is shown here.

Register Bit
Name Function

<2> <1> <0>

J3-15 J3-13 J3-11 L2 Cache Size

1

In
In In Out

In Out In 1MB
In Out Out 2MB (default for

Out In In 4MB
Out In Out 8MB
Out Out In Reserved
Out Out Out Reserved

BC_SIZE

In In Disables L2 cache

2

512KB (default for
21A02–A5)

21A02–A3 and 21A02–A4)

1

Jumper in (logical 0)

2

Jumper out (logical 1)

System Jumpers and Connectors 2–5