Digilent ZYBO, ZYNQ XC7Z010-1CLG400C Reference Manual

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ZYBO™ FPGA Board Reference Manual

Revised April 11, 2016
This manual applies to the ZYBO rev. B

DOC#: 502-279

Copyright Digilent, Inc. All rights reserved.

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 26

Overview

The ZYBO (ZYnq BOard) is a feature-rich, ready-to-use, entry-level embedded software and digital circuit
development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is
based on the Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core
ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. When coupled with the
rich set of multimedia and connectivity peripherals available on the ZYBO, the Zynq Z-7010 can host a whole
system design. The on-board memories, video and audio I/O, dual-role USB, Ethernet, and SD slot will have your
design up-and-ready with no additional hardware needed. Additionally, six Pmod ports are available to put any

design on an easy growth path.

The Zynq 7010 AP SoC offers the following features:

 650Mhz dual-core Cortex-A9 processor
 DDR3 memory controller with 8 DMA channels
 High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
 Low-bandwidth peripheral controller: SPI, UART, CAN, I
 Reprogrammable logic equivalent to Artix-7 FPGA

o 4,400 logic slices, each with four 6-input LUTs and 8 flip-flops
o 240 KB of fast block RAM
o Two clock management tiles, each with a phase-locked loop (PLL) and mixed-mode clock

manager (MMCM)

o 80 DSP slices
o Internal clock speeds exceeding 450MHz
o On-chip analog-to-digital converter (XADC)

2

C

ZYBO™ FPGA Board Reference Manual

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Page 2 of 26

The ZYBO Zynq-7000 development board.

 ZYNQ XC7Z010-1CLG400C
 512MB x32 DDR3 w/ 1050Mbps bandwidth
 Dual-role (Source/Sink) HDMI port
 16-bits per pixel VGA source port
 Trimode (1Gbit/100Mbit/10Mbit) Ethernet PHY
 MicroSD slot (supports Linux file system)
 OTG USB 2.0 PHY (supports host and device)
 External EEPROM (programmed with 48-bit

globally unique EUI-48/64™ compatible
identifier)

 Audio codec with headphone out, microphone

and line in jacks

 128Mb Serial Flash w/ QSPI interface
 On-board JTAG programming and UART to USB

converter

 GPIO: 6 pushbuttons, 4 slide switches, 5 LEDs
 Six Pmod ports (1 processor-dedicated, 1 dual

analog/digital, 3 high-speed differential, 1 logic­dedicated)

The ZYBO is compatible with Xilinx's new high-performance Vivado Design Suite as well as the ISE/EDK toolset.
These toolsets meld FPGA logic design with embedded ARM software development into an easy to use, intuitive
design flow. They can be used for designing systems of any complexity, from a complete operating system running
multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs.

An accessory kit that contains a 5V/2.5A power adapter, a USB A to Micro B cable, an 8GB speed class 10 microSD
card, and a Xilinx voucher for a Vivado Design Suite license will be available to purchase separately off of the
Digilent website in the near future. The Vivado Design Suite license enables use of the Logic Analyzer tools, which
accelerate debug and testing. This license is a 1 year, device-locked license, and will only work with the Z-7010
Zynq part on the ZYBO. After the license expires, any version of Vivado Design Suite that was released during this 1
year period can continue to be used indefinitely.

ZYBO™ FPGA Board Reference Manual

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Page 3 of 26

Callout

Component Description

Callout

Component Description

1

Power Switch

15

Processor Reset Pushbutton

2

Power Select Jumper and battery header

16

Logic configuration reset Pushbutton

3

Shared UART/JTAG USB port

17

Audio Codec Connectors

4

MIO LED

18

Logic Configuration Done LED

5

MIO Pushbuttons (2)

19

Board Power Good LED

6

MIO Pmod

20

JTAG Port for optional external cable

7

USB OTG Connectors

21

Programming Mode Jumper

8

Logic LEDs (4)

22

Independent JTAG Mode Enable Jumper

9

Logic Slide switches (4)

23

PLL Bypass Jumper

10

USB OTG Host/Device Select Jumpers

24

VGA connector

11

Standard Pmod

25

microSD connector (Reverse side)

12

High-speed Pmods (3)

26

HDMI Sink/Source Connector

13

Logic Pushbuttons (4)

27

Ethernet RJ45 Connector

14

XADC Pmod

28

Power Jack

1 2 3

4

5 6 7 8 9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Table 1. ZYBO Device Diagram.

ZYBO™ FPGA Board Reference Manual

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Page 4 of 26

Power

Jack

(J15)

3.3V (III)

IC26: ADP5052

Power
Switch
(SW4)

Micro-USB
Port (J11)

VU5V0

J14

IC27: ADR127

REFVIN

1.25V (III)

Power Source Select

JP7

J14

USB WALL BATTERY

EN

PGOOD

1.5A

PVIN1-4

JP7

Power On
LED (LD11)

PVIN5

1.0V (I)

2.1A

1.5V (III)

1.2A

1.8V (II)

0.6A

1.8V (III, analog)

0.1A

IC6: ADP150

0.1AVIN

3.3V (IV, analog)

EN

R281

D13

Power-on Reset

1 Power Supplies

The ZYBO can be powered from the Digilent USB-JTAG-UART port (J11), or from an external power supply. Jumper
JP7 (near the power switch) determines which power source is used. There are three valid configurations for this
jumper corresponding to the three powering options: USB, wall wart with barrel jack, and battery pack. There is a
diagram on the board silkscreen indicating all three.

All on-board power supplies are enabled or disabled by the power switch SW4. The power indicator LED (LD11) is
on when all the supply rails reach their nominal voltage. An overview of the power circuit is shown in Fig.2

A USB 2.0 port can deliver maximum 0.5A of current according to the specifications. This should provide enough
power for lower complexity designs. An idling blank board consumes around 0.2A from the 5V input supply. As an
example, the standalone lwIP echo server sample project replying to ping requests consumes 0.38A on average.
More demanding applications, including any that drive multiple peripheral boards or other USB devices, might

require more power than the USB port can provide. In this case, power consumption will increase until it’s limited

by the USB host. This limit varies a lot between manufacturers and depends on many factors. When in current
limit, once the voltage rails dip below their nominal value, the Zynq is reset by the Power-on Reset signal and
power consumption returns to its idle value. Also, some applications may need to run without being connected to
a PC’s USB port. In these instances an external power supply or battery pack can be used.

An external power supply (wall wart) can be used by plugging into to the power jack (J15) and setting jumper JP7
to "wall". The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to

5.5VDC and at least 2.5A of current (i.e., at least 12.5W of power). Suitable supplies can be purchased from the
Digilent website or through catalog vendors like DigiKey. Power supply voltages above 6VDC might cause
permanent damage.

An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP7 and the
negative terminal to the pin labeled J14 next to JP7. The external battery pack must be limited to 5.5VDC. The
minimum voltage of the battery pack depends on the application: if the USB Host (J10) or HDMI Source (J8)
function is used, at least 4.6V need to be provided. In other cases the minimum voltage is 3.6V.

Figure 2. Power circuit overview.

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Page 5 of 26

Supply

Circuits

Device

Current (max/typical)

3.3V

FPGA I/O, USB ports, Clocks,
Ethernet, SD slot, Flash, HDMI

IC26#1: ADP5052

2.5A/0.1A to 1.5A

1.0V

FPGA, Ethernet Core

IC26#2: ADP5052

2.5A/0.2A to 2.1A

1.5V

DDR3

IC26#3: ADP5052

1.2A/0.1A to 1.2A

1.8V

FPGA Auxiliary, Ethernet I/O,
USB OTG

IC26#4: ADP5052

1.2A/0.1A to 0.6A

1.8V

XADC Analog

IC26#5: ADP5052

200mA/20mA

3.3V

Audio Analog

IC6: ADP150

150mA/50mA

1.25V

XADC Precision Reference

IC27: ADR127

5mA/50uA

Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the main power input.

Table 2 provides additional information (typical currents depend strongly on FPGA configuration and the values
provided are typical of medium size/speed designs).

Table 2. ZYBO power supplies.

The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch
(SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails

3.3V and 1.5V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels
of the ADP5052 (IC26) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply,
lighting up the power LED (LD11), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.

Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least
130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the
PS_CLK (IC22) to stabilize.

2 Zynq AP SoC Architecture

The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the Programmable Logic
(PL). Figure 3 shows an overview of the Zynq AP SoC architecture, with the PS colored light green and the PL in
yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7010
device.

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Page 6 of 26

Figure 3. Zynq AP SoC architecture.

The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses
that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series
FPGA, and it must be configured either directly by the processor or via the JTAG port.

The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9
processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and
various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called
MultiplexedI/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO
pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers
are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control

registers that are addressable in the processors’ memory space. The programmable logic is also connected to the

interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain
addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors
(connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory.

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Page 7 of 26

MIO 500 3.3 V

Peripherals

Peripherals

Peripherals

Pin

Pmod

SPI Flash

GPIO

0

JF7 1

CS

2 DQ0

3

DQ1

4 DQ2

5 DQ3

6 SCLK

7

LED4

8 SLCK FB

9 JF8

10

JF2

11

JF3

12

JF4

13

JF1

14

JF9

15

JF10

There are many aspects of the Zynq AP SoC architecture that are beyond the scope of this document. For a
complete and thorough description, refer to the Zynq Technical Reference Manual, available at www.xilinx.com.

Figure 3 depicts the external components connected to the MIO pins of the ZYBO. The Zynq Board Definition File
found on the Digilent ZYBO product page can be imported into EDK and Vivado Designs to properly configure the
PS to work with these peripherals.

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Page 8 of 26

MIO 501

1.8V

Peripherals

Pin

ENET 0

USB 0

SDIO 0

UART 1

GPIO

16

TXCK

17

TXD0

18

TXD1

19

TXD2

20

TXD3

21

TXCTL

22

RXCK

23

RXD0

24

RXD1

25

RXD2

26

RXD3

27

RXCTL

28 DATA4

29 DIR 30 STP

31 NXT

32 DATA0

33 DATA1

34 DATA2

35 DATA3

36 CLK 37 DATA5

38 DATA6

39 DATA7

40

CCLK

41

CMD

42

D0

43

D1

44

D2

45

D3

46 RESETN

47

CD

48 RXD 49 TXD 50

BTN4

51

BTN5

52

MDC

53

MDIO

Table 3. MIO Pinout.

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Page 9 of 26

3 Zynq Configuration

Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7010 are designed around the processor, which acts as
a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes
the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the
processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for
configuring the programmable logic (optional), and a user application.

The boot process is broken into three stages:

Stage 0

After the ZYBO is powered on or the Zynq is reset (in software or by pressing PS-SRST), one of the
processors (CPU0) begins executing an internal piece of read-only code called the BootROM. If and only if
the Zynq was just powered on, the BootROM will first latch the state of the mode pins into the mode
register (the mode pins are attached to JP5 on the ZYBO). If the BootROM is being executed due to a reset
event, then the mode pins are not latched, and the previous state of the mode register is used. This
means that the ZYBO needs a power cycle to register any change in the programming mode jumper (JP5).
Next, the BootROM copies an FSBL from the form of non-volatile memory specified by the mode register
to the 256 KB of internal RAM within the APU (called On-Chip Memory, or OCM). The FSBL must be
wrapped up in a Zynq Boot Image in order for the BootROM to properly copy it. The last thing the
BootROM does is hand off execution to the FSBL in OCM.

Stage 1

During this stage, the FSBL first finishes configuring the PS components, such as the DDR memory
controller. Then, if a bitstream is present in the Zynq Boot Image, it is read and used to configure the PL.
Finally, the user application is loaded into memory from the Zynq Boot Image, and execution is handed off
to it.

Stage 2

The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of
program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating
system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the Zynq
Technical Reference Manual.

The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For a tutorial on
how to build an image using these tools that properly targets the ZYBO, download the ZYBO Base System Design
from the Digilent ZYBO product page and follow the included documentation.

The ZYBO supports three different boot modes: microSD, QSPI Flash, and JTAG. The boot mode is selected using
the Mode jumper (JP5), which affects the state of the Zynq configuration pins after power-on. Figure 4 depicts how
the Zynq configuration pins are connected on the ZYBO. Note that MIO2-MIO8 are shared with the QSPI Flash and
MIO LED, but not pictured in Fig. 4.