Digilent Pegasus Board User Manual

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Revision: August 11, 2005 215 E Main Suite D | Pullman, WA 99163

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Overview

The Pegasus circuit board provides a complete
circuit development platform centered on a
Xilinx Spartan 2 FPGA. Pegasus features
include:

Power

jack

5-9VDC

2.5VDC

regulator

3.3VDC

regulator

Clock

(50MHz)

Config

ROM

Expansion Connectors

A1

A2

B1

JTAG

• a 50K-gate Xilinx Spartan 2 FPGA with

Xilinx Spartan 2 XC2S50-PQ208

50K gates and 200MHz operation (a
200K-gate version is also availabl e)

• a XCF01S Xilinx Platform Flash ROM
(XCF02S for 200K gate version)

• a collection of I/O devices including eight
LEDs, four-digit seven-segment display,
four pushbuttons, and eight slide
switches

• a 50MHz oscillator and a socket for a

8 LEDs

4 7-seg.

displays

4 buttons

8 switches

Figure 1. Pegasus circuit board block diagram

PS2

Port

VGA

Port

second oscillator

• PS/2 and VGA ports

• 96 I/O signals routed to three standard

40-pin expansion connectors

• all I/O signals have ESD and short-circuit
protection

• a JTAG programming port.

The Pegasus board has been designed to
work seamlessly with all versions of the Xilinx
ISE CA D tools, including the free WebPack
tools available from Xilinx. A growing collection
of low-cost expansion boards can be used with
the Pegasus board to add analog and digital
I/O capabilities, as well as various data ports
like Ethernet and USB. The Pegasus board
ships with a power supply and programming
cable, so designs can be implemented
immediately without the need for any additional
hardware.

Important: This reference manual is
updated for Rev. D Pegasus Boards with a
5V power supply. For a manual for a
previous Pegasus board using a 3.3V
power supply, e-mail

[e-mail]

Functional Description

The Pegasus board provides an inexpensive,
robust, and easy -to-use platform that anyone
can use to gain experience with FPGA devices
and modern design methods. The Pegasus
board is centered on the Spartan 2 FPGA, and
it contains all needed support circuits so
designs can get up and running quickly. The
large collection of on -board I/O devices allows
many designs to be completed without the
need for any other components. Three
standard expansion connectors allow designs
to grow beyond the Pegasus board, either with
user-designed boards or any one of several
analog and digital I/O boards offered by
Digilent. Each expansion connector provides
system voltages and 32 unique I/O signals,
with all I/O signals protected against damage
from ESD and short-circuit connections. JTAG
signals are routed to two expansion
connectors, allowing peripheral boards to drive
the scan chain or to be configured along with
the Spartan FPGA. The collection of on-board
I/O devices and signal protection networks
make the Pegasus board ideally suited to
educational settings.

Copyright Digilent, Inc. All rights reserved 12 pages Doc: 50 0-223

Pegasus Reference Manual Digilent, Inc. ™

JTAG Ports and Device Configuration

The Spartan 2 FPGA, the XCF01S Platform
Flash ROM, and any programmable devices
on peripheral boards attached to the Pegasus
board can be programmed through JTAG
ports. The JTAG scan chain is routed from the
primary JTAG connector (port 1) to the FPGA,
Platform Flash, and two connection ports as
shown in Figure 2. The primary configuration
port (Port 1) uses a standard 6-pin JTAG
header (J6) that can accommodate Digilent’s
JTAG3 cable (or cables from Xilinx or other
vendors). The other two bi-directional JTAG
ports are available on the A1 and B1
expansion connectors. If no peripheral boards
are present on these connectors, a buffer on
the Pegasus board removes them from the
JTAG chain. If a peripheral board with a JTAG­programmable device is attached, the scan
chain is driven out the expansion connector so
that the device can be configured. If a Digilent
port module is connected to A1 or B1, then the
port module can drive the JTAG chain to
program all devices in the scan chain. Port
modules include Ethernet, USB, EPP parallel,
and serial modules. (See www.digilentinc.com
for more information). For port modules to
drive the JTAG chain, a jumper must be
installed on the primary JTAG connector
across the TDI and TDO pins.

Port 2

A1 A2

Port 3

JTAG connector

Programming
mode select
jumpers

(Port 1)

Spartan 2E

PQ 208

Platform
Flash

B1

Figure 2. JTAG signal routing on Pegasus

To program the Pegasus board from the
primary port, first power on the Pegasus board,
then connect it to the PC with a JTAG cable,

and then run the “auto-detect” feature of the
configuration software. The configuration
software will identify all devices in the scan
chain, and then each device can be bypassed
or programmed with a suitable configuration
file. Note that both the FPGA and Platform
Flash ROM will always appear in the scan
chain. If the Platform Flash ROM is loaded with
an FPGA configuration file, the FPGA will load
that file at power-on if jumpers are loaded in all
three positions of J4 (M2, M1, and M0).

Power Supplies

The Pegasus board requires a regulated 5V
power supply (it ships with a 5V regulated wall­plug supply). If a higher voltage supply is used,
the Pegasus board may be permanently
damaged. The power supply is connected to
the Pegasus board using a 5.5mm OD, 2.5mm
ID center-positive power jack. The 5V supply
from the power jack is connected directly to the
V

supply that drives the FPGA I/O signals,

CCIO

and to a 2.5V regulator that supplies the
Spartan 2 V

CORE

voltage.

Total board current is dependant on FPGA
configuration, clock frequency, and external
connections. In test circuits with roughly 20K
gates routed, a 50MHz clock source, and all
LEDs illuminated, approximately 200mA +/­30% of supply current is drawn from the 2.5V
supply, and approximately 100mA is drawn
from the 5V supply. Required current will
increase if peripheral boards are attached.

The Pegasus board uses a four layer PCB,
with the inner layers dedicated to VCC and
GND planes. Most of the VCC plane is at 5V,
with an island under the FPGA at 2.5V. The
FPGA and the other ICs on the board all have

0.047uF bypass capacitors placed as close as
possible to each VCC pin. The power supply
routing and bypass capacitors result in a very
clean, low-noise power supply.

Oscillators

The Pegasus provides a 50MHz SMD primary
oscillator and a socket for a second oscillator.

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Pegasus Reference Manual Digilent, Inc. ™

The primary oscillator is connected to the
GLK1 input of the Spartan 2 (pin 77) and the
secondary oscillator is connected to GCLK2
(pin 182). Both clock inputs can drive a DLL on
the Spartan 2, allowing for a wide range if
internal frequencies are up to four times higher
than the external clock signals. Any 5V
oscillator in a half-size DIP package can be
loaded into the secondary oscillator socket.

Pushbuttons, Slide Switches, and LEDs

Four pushbuttons and eight slide switches are
provided for circuit inputs. Pushbutton inputs
are normally low, and they are driven high only
when the pushbutton is pressed. Slide
switches generate constant high or low inputs
depending on their position. Pushbutton inputs
use RC networks to provide nominal debounce
and ESD protection. Slide switch inputs use
only a series resistor for protection.

Eight LEDs are provided for circuit outputs.
LED anodes are driven directly from the FPGA
via 470-ohm resistors, and the cathodes are
connected directly to ground. A ninth LED is
provided as a power-on LED, and a tenth LED
indicates JTAG programming status.

3.3V

4.7K ohms
To FPGA

4.7K

ohms

Pushbuttons

3.3V

4.7K

ohms

Slide switches

0.1uF

To FPGA

Seven-Segment Display

The Pegasus board contains a four-digit
common anode seven-segment LED display.
The display is multiplexed, so only seven
cathode signals exist to drive all 28 segments
in the display. Four digit-enable signals drive
the common anodes and these signals
determine which digit the cathode signals
illuminate.

Anodes are connected via

transistors for greater current

Vdd

AN0

AN1AN2AN3

abc d e f g dp

Cathodes are connected to

Xilinx device via 100Ω resistors

Figure 4. Common anode Sseg display

The seven anodes of each digit’s LEDs are
connected together into one “common anode”
circuit node. The display has four such nodes
named AN0 – AN3, and the signals that drive
these nodes serve as digit enablers. Driving an
anode signal low enables the corresponding
digit. The cathodes of similar segments on all
four displays are connected into seven circuit
nodes labeled CA through CG. Driving cathode
signals low illuminates segments on any digit
whose digit enable is low.

Common anode

a

f

e

b

g

c

From

FPGA

LEDs

Figure 3. Pushbutton, slide switch, and LED circuits

www.digilentinc.com Page 3

390 ohms

This connection scheme creates a multiplexed
display, where driving the anode signals and
corresponding cathode patterns of each digit in

d

a f g e d c b

Figure 5. Common anode detail

Pegasus Reference Manual Digilent, Inc. ™

PS/2 Power

a repeating, continuous succession can create
the appearance of a four-digit display. Each of
the four digits will appear bright and
continuously illuminated if the digit enable
signals are driven low once every 1 to 16ms
(for a refresh frequency of 1KHz to 60Hz). For
example, in a 60Hz refresh scheme, each digit
would be illuminated for one quarter of the
refresh cycle, or 4ms. The controller must
assure that the correct cathode pattern is
present when the corresponding anode signal
is driven.

Refresh period = 1ms to 16ms

AN0

AN1

AN2

AN3

Digit 0

Digit period = Refresh / 4

Digit 1 Digit 2 Digit 3

Figure 6. Sseg signal timing

To illustrate the process, if AN0 is driven low
while CB and CC are driven low, then a “1” will
be displayed in digit position 0. Then, if AN1 is
driven low while CA, CB and CC are driven
low, then a “7” will be displayed in digit position

1. If AN0 and CB, CC are driven low for 4 ms,
and then AN1 and CA, CB, CC are driven low
for 4 ms in an endless succession, the display
will show “71” in the rightmost two digits.

Digit Cathode Signals
Shown

0
1 1 0 0 1 1 1 1
2
3
4
5
6
7
8
9

a b c d e f g

0 0 0 0 0 0 1

0 0 1 0 0 1 0
0 0 0 0 1 1 0
1 0 0 1 1 0 0
0 1 0 0 1 0 0
0 1 0 0 0 0 0
0 0 0 1 1 1 1
0 0 0 0 0 0 0
0 0 0 1 1 0 0

Figure 7. Cathode patterns for decimal digit s

PS/2 Port

The Pegasus board includes a 6-pin mini-DIN
connector that can accommodate a PS/2
mouse or keyboard connection. A jumper on
the Pegasus board (J9) can be
loaded to provide 5V to the PS/2

J9

VCC33

PS2VCC

VU

port, or an external supply can be
connected to the “PS2VCC” pin of
J9 (some PS/2 devices require 5V
to work properly).

Pin Definitions

Pin Function
1 Data
2 Reserved
3 GND
4 Vdd
5 Clock
6 Reserved

1

2

4

PS2 Connector

3

6

5

Pin 1

Pin 2

Pin 5Pin 6

Bottom-up

hole pattern

Figure 8. PS/2 connections

The PS/2 protocol uses a bi-directional two ­wire interface that includes a serial data and a
clock signal (the host -to-keyboard data
direction is used to send status LED data).
Driver circuits on both ends of the clock and
data signals use open-collector buffers with
10K pull-ups. The signals are only driven when
a key is actively pressed (or when the host is
actively sending LED status data). If the PS/2
device is only used as an input device, then
the host system can just use input buffers
(open-collector buffers are not required).

PS/2 mouse and keyboard devices use11-bit
data words that include a start bit, eight data
bits, and odd parity bit, and a stop bit. Data
timings are shown in the figure below. The
mouse and keyboard use eight-bit data
packets that are organized differently – the
keyboard sends eight-bit key scan codes, and
the mouse sends three eight-bit data elements
to define relative mouse movements.

Keyboard

Each key has a single, unique scan code that
is sent whenever the corresponding key is
pressed. If a key is continuously pressed for
more than 570ms, its scan code is repeated
each 104ms (but the time interval between first
and second transmission of the same code is

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