Digilent Nexys 3 Reference Manual

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Nexys 3™ FPGA Board Reference Manual

Revised April 11, 2016 This manual applies to the Nexys 3 rev. B

DOC#: 502-182

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 22

 Xilinx Spartan-6 LX16 FPGA in a 324-pin BGA

package

 16Mbyte Cellular RAM (x16)  16Mbytes SPI (quad mode) PCM non-volatile

memory

 16Mbytes parallel PCM non-volatile memory  10/100 Ethernet PHY  On-board USB2 port for programming & data

xfer

 USB-UART and USB-HID port (for

mouse/keyboard)

 8-bit VGA port  100MHz CMOS oscillator  72 I/Os routed to expansion connectors  GPIO includes 8 LEDs, 5 buttons,8 slide

switches and 4-digit seven-segment display

 USB2 programming cable included

Features include:

Overview

The Nexys 3 is a complete, ready-to-use digital circuit development platform based on the Xilinx Spartan-6 LX16 FPGA. The Spartan-6 is optimized for high performance logic, and offers more than 50% higher capacity, higher performance, and more resources as compared to the Nexys 2's Spartan-3 500E FPGA.

In addition to the Spartan-6 FPGA, the Nexys 3 offers an improved collection of peripherals including 32Mbytes of Micron's latest Phase Change nonvolatile memory, a 10/100 Ethernet PHY, 16Mbytes of Cellular RAM, a USBUART port, a USB host port for mice and keyboards, and an improved high-speed expansion connector. The large FPGA and broad set of peripherals make the Nexys 3 board an ideal host for a wide range of digital systems, including embedded processor designs based on Xilinx's MicroBlaze.

Nexys 3 is compatible with all Xilinx CAD tools, including ChipScope, EDK, and the free WebPack. The Nexys 3 uses Digilent's newest Adept USB2 system that offers FPGA and ROM programming, automated board tests, virtual I/O, and simplified user-data transfer facilities.

A comprehensive collection of board support IP and reference designs, and a large collection of add-on boards are available on the Digilent website. Please see the Nexys 3 page at www.digilentinc.com for more information.

Nexys 3™ FPGA Board Reference Manual

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M0 M1

JTAG Port

USB

Controller

Micron SPI Quad

mode PCM (P5Q)

1x6 JTAG Header

SPI

Port

Micro-AB USB

Connector

Adept “USB Prog” Port

Spartan6

Done

PIC24

Type A USB

Connector

Host Port

Serial Prog. Port

Micron Parallel

PCM (P8P)

BPI

Port

Programming

Mode

SLV Serial

SPI

BPI UP

M0 M1

6-pin JTAG

Header (J7)

Prog

Cellular RAM

16MByte

High-Speed

Expansion

USB HID Host

Mouse/Keyboard

Spartan-6

XC6SLX16

CSG324C

Basic I/O

LEDs, Btns, Swts

Pmod Port Expansion

USB-UART

Clock 100MHz

Adept USB2

Config & data

SPI PCM (x4)

Nonvolatile

Memory

16MByte

10/100

Ethernet PHY

Parallel PCM

Nonvolatile

Memory

16MByte

8-bit VGA

 2,278 slices each containing four 6-input LUTs

and eight flip-flops

 576Kbits of fast block RAM  two clock tiles (four DCMs & two PLLs)  32 DSP slices  500MHz+ clock speeds

Spartan-6 LX16 features include:

1 Configuration

After power-on, the Spartan-6 FPGA board must be configured (or programmed) before it can perform any functions. The FPGA can be configured in one of four ways: a PC can use the Adept "USB Prog" port to program the FPGA any time power is on; a configuration file stored in the non-volatile parallel PCM device can be transferred to the FPGA at power-on using the BPI-UP port; a file stored in the non-volatile serial (SPI) PCM device can be transferred to the FPGA using the SPI port; or a programming file can be transferred from a USB memory stick attached to the USB HID port. An on-board "mode" jumper (J8) selects between the programming modes as shown in the J8 Mode legend in the figure below. JTAG Mode can be accessed at any time without changing jumpers.

Programming files are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA's logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port.

FPGA configuration files transferred via the JTAG port use the .bin or .svf file types, files transferred from a USB stick use the .bit file type, and BPI or SPI programming files can use .bit, .bin, or .mcs types. The ISE/WebPack or EDK software from Xilinx can create bit, svf, bin, or mcs files from VHDL, Verilog, or schematic-based source files

Nexys 3™ FPGA Board Reference Manual

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Adept

USB Port

Power

Switch

USB HID

Host Port

Power

Jack

JTAG

Header

MODE

Jumper

Power

Good LED

Done

LED

Reset

Button

Power Select

Jumper

LEDs

Slide switches Push buttons

7-seg

Display

USB

UART

VGA

Port

10/100

Ethernet

Pmod

Connectors

VHDC

Conncector

(EDK is used for MicroBlaze™ embedded processor-based designs). Digilent's Adept software or Xilinx's iMPACT software can be used to program the FPGA or ROMs using the Adept USB port.

During JTAG programming, a .bit or .svf file is transferred from the PC to the FPGA using the Adept USB port. When programming a non-volatile PCM device, a .bit, .bin, or .mcs file is transferred to the in a two-step process. First, the FPGA is programmed with a circuit that can program PCM devices, and then data is transferred to the PCM device via the FPGA circuit (this complexity is hidden from the user – a simple "program ROM" interface is presented by the programming software. Note the PCM devices are next-generation Flash ROM devices, and they are often referred to as "Flash" or "ROM" memory). After the PCM device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the J8 jumper setting. Programming files stored in the PCM devices will remain until they are overwritten, regardless of powercycle events. The FPGA can be programmed from a memory stick attached to the USB-HID port if the stick contains a single .bit configuration file in the root directory, the J8 Programming Mode jumper is set to JTAG (both jumpers loaded), and board power is cycled. The FPGA will automatically reject any .bit files that are not built for the proper FPGA.

After being successfully programmed, the FPGA will cause the "Done" LED to illuminate. Pressing the Reset button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from one of the PCM devices if the J8 Mode jumper is set to BPI or SPI mode.

Nexys 3™ FPGA Board Reference Manual

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To program the Nexys 3 board using Adept, first set up the board and initialize the software:

 plug in and attach the power supply  plug in the USB cable to the PC and to

the USB port on the board

 start the Adept software  turn ON Nexys 3's power switch  wait for the FPGA to be recognized.

Use the browse function to associate the desired .bit file with the FPGA, and click on the Program button. The configuration file will be sent to the FPGA, and a dialog box will indicate whether programming was successful. The configuration "done" LED will light after the FPGA has been successfully configured.

Before starting the programming sequence, Adept ensures that any selected configuration file contains the correct FPGA ID code – this prevents incorrect .bit files from being sent to the FPGA.

In addition to the navigation bar and browse and program buttons, the Config interface provides an Initialize Chain button, console window, and status bar. The Initialize Chain button is useful if USB communications with the board have been interrupted. The console window displays current status, and the status bar shows real-time progress when downloading a configuration file.

Digilent's Adept software offers a simplified programming interface and many additional features as described below. The Adept USB port is fully compatible with all Xilinx tools, including the iMPACT programming software. The Adept features are always available, regardless of how the FPGA was programmed.

1.1 Adept System

Digilent's Adept high-speed USB2 system can be used to program the FPGA and PCM devices, run automated board tests, add PC-based virtual I/O devices (like buttons, switches, and LEDs) to FPGA designs, and exchange register-based and file-based data with the FPGA. Adept automatically recognizes the Nexys 3 board and presents a graphical interface with tabs for each of these applications. Adept also includes public APIs/DLLs so that users can write applications to exchange data with the Nexys 3 board at up to 38Mbytes/sec. The Adept application, an SDK, and reference materials are freely downloadable from the Digilent website.

1.2 Programming Interface

1.3 Memory Interface

The Memory tab allows .bin, .bit, and .mcs configuration files to be transferred to the on-board BPI (parallel) or SPI (serial) PCM devices for subsequent FPGA programming, and allows user data files to be transferred to/from the PCM devices or RAM memories at user-specified addresses. The target memory is selected by clicking one of the three radio buttons in the upper-right corner.

Nexys 3™ FPGA Board Reference Manual

Page 5 of 22

The configuration tool supports programming from any valid ROM file produced by the Xilinx tools. After programming, board power can either be cycled or the Reset button can be pressed to program the FPGA from the PCM device selected by the J8 mode jumper. If programming with a .bit file, the startup clock must be set to CCLK.

All three memory devices (the PCM's and the cellular RAM) can be fully tested by clicking the Full Test button. They can also be completely erased by clicking the Erase button.

The Read/Write tools allow data to be exchanged between files on the host PC and specified address ranges in the memory devices.

The test interface provides an easy way to verify many of the board's hardware circuits and interfaces. These are divided into two major categories: on-board memory (RAM and Flash) and peripherals. In both cases, the FPGA is configured with test and PC-communication circuits, overwriting any FPGA configuration that may have been present.

Clicking the Run RAM/Flash Test button will identify the CellularRam, SPI Flash, and BPI Flash memory by reading out and verifying the IDCODE on each memory. The memory contents will not be modified. To run a full test on a particular memory device, refer to the Full Test in the Memory Tab.

Clicking the Start Peripherals Test button will initialize GPIO and user I/O testing. Once the indicator near the Start Peripherals Test button turns green, all peripheral tests can be run.

1.4 Test Interface

The Test Shorts feature checks all discrete I/O's for shorts to Vdd, GND, and neighboring I/O pins. The switches and buttons graphics show the current states of those devices on the Nexys 3 board. Connect a VGA monitor and USB mouse to visually test the J2 VGA port and J4 USB port respectively.

Nexys 3™ FPGA Board Reference Manual

Page 6 of 22

The register I/O tab requires that a corresponding IP block, available in the Parallel Interface reference design (DpimRef.vhd) on the Adept page of the Digilent website, is included and active in the FPGA. This IP block provides an EPP-style interface, where an 8-bit address selects a register, and data read and write buttons transfer data to and from the selected address. Addresses entered into the address field must match the physical address included in the FPGA IP block.

Register I/O provides an easy way to move small amounts of data into and out of specific registers in a given design. This feature greatly simplifies passing control parameters into a design, or reading lowfrequency status information out of a design.

The File I/O tab can transfer files between the PC and the Nexys 3 FPGA. A number of bytes (specified by the Length value) can be streamed into a specified register address from a file or out of a specified register address into a file. During upload and download, the file start location can be specified in terms of bytes.

As with the Register I/O tab, File I/O also requires specific IP to be available in the FPGA. This IP can include a memory controller for writing files into the onboard Ram and Flash memories.

1.5 Register I/O

1.6 File I/O

1.7 I/O Expand

The I/O Expand tab works with an IP block in the FPGA to provide additional simple I/O beyond the physical devices found on the Nexys 3 board. Virtual I/O devices include a 24-LED light bar, 16 slide switches, 16 push buttons, 8 discrete LEDs, a 32-bit register that can be sent to the FPGA, and a 32-bit register that can be read from the FPGA.

Nexys 3™ FPGA Board Reference Manual

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The IP block, available in the Adept I/O Expansion reference design (AdeptIOExpansion.zip) on the Adept page of the Digilent website, provides a simple interface with well-defined signals. This IP block can easily be included in, and accessed from, user-defined circuits.

For more information, see the Adept documentation available at the Digilent website.

Supply

Circuits

Device

Amps (max/typ)

3.3V

FPGA I/O, USB ports, Clocks, ROM & RAM I/O, Ethernet

IC13: LTC3633

3A / 200mA

2.5V

Optional voltage for Bank0 and VHDC connector

IC14: LTC3619

800mA / 0mA

1.2V

FPGA Core

IC13: LTC3633

3A / 0.2 to 1.0A

1.8V

RAM and ROM core

IC14: LTC3619

400mA / 0.1 to 0.3A

2 Power Supplies

The Nexys 3 board can receive power from the Adept USB port or from an external power supply. Jumper JP1 (near the power jack) determines which source is used.

The USB port can deliver enough power for the vast majority of designs. It is possible that a very demanding application, including an application that drives many peripheral boards, might require more power than can be delivered by the USB port. Some applications may also need to run without being connected to a PC's USB port. In either case, an external power supply or battery pack can be used by setting JP1 to "Wall".

The main regulator on the Nexys 3 can accommodate input voltages up to 5.5VDC. An external DC wall-plug supply should provide at least five watts of input power, and use a coax center-positive 2.1mm internal-diameter plug. An external battery pack can also be used by connecting the battery's terminal leads to connector J11 (J11 is in parallel with the wall-plug power jack, so if a battery pack is connected, a wall plug should not be). An external battery pack should also be limited to 5.5VDC, and should be capable of delivering adequate power for the application.

Voltage regulator circuits from Linear Technology create the required 3.3V, 2.5V, 1.8V, and 1.2V supplies from the main power input. The table below provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).

Table 1. Nexys 3 Power Supplies.

+ 15 hidden pages

Digilent Nexys 3 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual