Digilent NetFPGA-SUME Reference Manual
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NetFPGA-SUME™ Reference Manual
Revised April 11, 2016
This manual applies to the NetFPGA-SUME rev. C
DOC#: 502-301
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 1 of 18
FPGA
Xilinx Virtex-7 XC7V690T FFG1761-3
Memory
Two 4GB DDR3 SODIMMs (MT8KTF51264Hz-
1G9E1)
64 bit wide buses clocked at
850 MHz (1700 mbps)
Three 72Mbit QDRII+ SRAMs
(CY7C25652KV18-500BZXC)
36 bit wide buses clocked at
500 MHz (1000 mbps)
Storage
Two SATA III ports (6 gbps via GTH
transceivers)
Micro-SD Card Slot
Two 512Mbit Micron StrataFlash parallel flash
modules (PC28F512G18A)
For bitfile storage only
Communication Interfaces
PCI-E Gen3 x8 supporting 8Gbps/lane
Four SFP+ interfaces supporting 10Gbps
Four globally unique MAC addresses
USB-UART
I2C Pmod port
Expansion Connectors
QTH Connector (8 GTH transceivers)
One HPC FMC Connector (10 GTH transceivers
and 68 User I/Os)
One 12-pin Pmod port (8 User I/Os)
Programming
Micro USB Connector for JTAG programming and
debugging (shared with USB-UART interface)
Xilinx CPLD XC2C512 for FPGA configuration from
parallel flash
Power Management
Two Linear Technology Power System Managers
(LTC2974)
Provide current measuring on all major
power rails
Other Features
User LEDs and Push Buttons
PROG Push Button for manual FPGA Reset
FPGA Configuration LEDs
I2C Mux (PCA9548A) for controlling all onboard
I2C buses
The NetFPGA-SUME board.
Features include:
Overview
Powered by Xilinx's Virtex-7 XC7V690T
FPGA, the NetFPGA-SUME is an ideal
platform for high-performance and
high-density networking design.
32 GTH serial transceivers have been
used to provide access to 8 lanes of
end-point PCI-E (Gen3 x8), 4 SFP+
(10Gbps) ports, 2 SATA-III ports
(6Gbps), and 18 data-rate-adjustable
GTH ports through a HPC-FMC
connector and a QTH connector.
Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB
DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.
NetFPGA-SUME™ Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 2 of 18
Figure 1. NetFPGA-SUME component callouts.
The NetFPGA-SUME is compatible with Xilinx's new high-performance Vivado® Design Suite as well as the ISE®
toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means
full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA-SUME.
Licensing information for Vivado can be found here. Academic institutes can make a request to the Xilinx
University Program for a donation of full Vivado licenses here.
A simplified block diagram that depicts the major features of the NetFPGA-SUME is displayed in Fig. 2.
NetFPGA-SUME™ Reference Manual
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Other product and company names mentioned may be trademarks of their respective owners.
Page 3 of 18
FIgure 2. NetFPGA-SUME block diagram.
1 NetFPGA Organization
This board is supported by reference designs and IP created by the NetFPGA organization. For more information on
the NetFPGA organization, go here.
2 Power
2.1 Input Supply
The NetFPGA-SUME receives power via a 2 x 4 pin PCI Express Auxiliary Power Connector. The 2x4 pin PCI Express
Auxiliary Power receptacle (header J14) can accept both 2x3 and 2x4 pin PCI Express Auxiliary Power Plugs found
on a standard ATX power supply. When installed on a PC motherboard, you can plug the 2x3 or 2x4 pin PCI Express
power supply connector directly into header J14. When used in standalone mode (without a PC motherboard),
NetFPGA-SUME™ Reference Manual
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Other product and company names mentioned may be trademarks of their respective owners.
Page 4 of 18
pins 15 and 16 of the main 20 pin connector of the standard ATX power supply must be shorted together, as
shown in Figure 3. If these pins aren't shorted together then the power supply will not turn on.
Figure 3. Pin 15 and 16 of Standard ATX power supply shorted together.
According to Revision 1.0 of the PCI Express 225 W/300 W High Power Card Electromechanical Specification, the
2x3 pin plug is guaranteed to deliver up to 75 watts of power, while the 2x4 pin plug is guaranteed to deliver up to
150 watts of power. While the board may be powered by either a 2x3 pin or a 2x4 pin PCI Express Auxiliary Power
plug, due to the potential for high power consumption, Digilent recommends using a 2x4 pin plug to provide power
whenever possible.
Figure 4. Power connector (J14).
Figure 4 describes pin-out of the power connector (header J14) when a 2x4 pin or a 2x3 pin plug is used. The
Sense0 and Sense1 pins are to be connected to GND when power is present, and left floating otherwise. Since the
2x3 pin plug does not include a Sense1 pin, it's possible to determine what type of plug is present, and thus how
much power can be consumed.
The FPGA logic can determine whether or not a 2x4 pin is present by enabling an internal pull-up on pin AW42 and
then checking the state of that pin. If logic '0' is seen on AW42, then a 2x4 plug is connected and up to 150 watts of
power can be drawn. If logic '1' is on AW42, then a 2x3 plug is connected, and the board's power consumption
should be limited to 75 watts or less.
2.2 Power Supply Topology
The high performance Virtex-7 FPGA, QDRII+ memories, and DDR3 memories featured on the NetFPGA-SUME
require several different supply voltages (supply rails) in order to function. These components also require that the
supply rails are sequenced on and off in a particular order. Table 1 lists the various supply rails, their nominal
voltages, and rated output currents.
NetFPGA-SUME™ Reference Manual
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Page 5 of 18
Supply Rail
Nominal Voltage
Rated Output Current
VCC1V0
1.0V
40A
VCC1V8
1.8V
15A
VCC2V0
2.0V
2A
MGTAVCC
1.0V
8A
MGTAVTT
1.2V
3A
VCC3V3
3.3V
15A
VCC1V5
1.5V
15A
MGTVAUX
1.8V
1A
DDRVTT
0.75V
+/- 3A
QDRVTT
0.75V
+/- 3A
Table 1. Supply rails, voltages, and currents.
These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency
switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and
QDRII+ I/O supplies are powered from the VCC1V5 rail, two ferrite beads are also included to prevent high speed
switching noise caused by one memory from affecting the other. Figure 6 shows how the various supplies are
derived from the input.
A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of
phase with any of the other clock outputs (see Fig. 5). These out of phase clocks are used as the input clocks for the
regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC).
The LTC3839, which produces the VCC1V0 supply rail, is a dual phase converter that directly utilizes the OUT1 clock
and indirectly utilizes the OUT4 clock. The use of out of phase clocks reduces the input RMS ripple current.
Figure 5. LTC6909 clock output phase relationship.
NetFPGA-SUME™ Reference Manual
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Page 6 of 18
Figure 6. Regulator topology.
2.3 Power Sequencing and Supervising
The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular
order. The NetFPGA-SUME utilizes two Linear Technology LTC2974s to ensure that these sequencing requirements
are met. Each LTC2974 supports "cascade sequence ON with time-based sequence off" and can monitor the input
voltage, four output voltages, four output currents, and four external temperatures using a 16-bit ADC.
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