Digilent Genesys 2 Reference Manual

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Genesys 2 Reference Manual

The Digilent Genesys 2 board is an advanced, high-performance, ready-to-use digital circuit development platform based on
the latest Kintex-7™ Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity, high-speed FPGA (Xilinx
part number XC7K325T-2FFG900C), fast external memories, high-speed digital video ports, and wide expansions options
make the Genesys 2 well suited for data and video processing applications. Several built-in peripherals, including Ethernet,
audio and USB 2.0, allow a wide range of other applications. The fully-bonded high-speed FMC HPC connector opens the
door to great expansion possibilities.

1)

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Features

• 50,950 logic slices (from Genesys up 7x), each with four 6-input LUTs and 8 flip-flops

• Close to 16 Mbits of fast block

• Ten clock management tiles, each with phase-locked loop (PLL)

• 840 DSP slices (up 17x)

• Internal clock speeds exceeding 450MHz

• On-chip analog-to-digital converter (XADC)

• Up to 10.3125Gbps gigabit transceivers

• 1800Mbps DDR3 data rate with 32-bit data width

• Commercial -2 speed grade

• Fully bonded 400-pin FMC HPC connector

• USB-UART Bridge

• 8 user switches, 6 buttons

•

OLED ()

• VGA connector

• Pmod for XADC signals

•Two four-lane DisplayPort connectors

• HDMI Sink and HDMI Source

• 10/100/1000 Ethernet PHY

• 1GiB 1800Mt/s on-board DDR3

• USB 2.0 Host/Device/OTG PHY

• Digilent Adept USB port for programming and data

• Ten GTX lanes available in the FMC connector

RAM () (up 7x)

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• Micro SD card connector

• Audio codec w/ four 3.5mm jacks

• Serial Flash

•Five Pmod ports

• USB HID Host for mice, keyboards and USB MSD Host for storage

The Genesys 2 can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatile Flash or
the on-board USB-JTAG programmer circuit.

The Genesys 2 is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset. Included in
the box is a voucher that unlocks the Design Edition of Vivado that is device-locked to the Genesys 2. This allows designs to
be implemented straight out of the box at no additional cost. The Design Edition of Vivado also unlocks the Logic Analyzer
tool and still includes the ability to create Microblaze soft-core processor projects.

Callout Component Description

1 USB-UART bridge

2 User-USB (bottom) & USB MSD/HID (top)

3 Ethernet RJ-45 10/100/1000

4 USB-JTAG bridge

5 PROG and user reset buttons

Callout Component Description

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6 Power LED ()

7 Digital Pmods

8 JTAG header

9 User slide switches

10 User LEDs

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12 Dual analog/digital Pmod

13 User pushbuttons

14 FMC HPC

15 Fan header

16 VADJ jumper

17 micro SD slot

18 3.5mm audio jacks

19 DisplayPort source connector

20 DisplayPort sink connector

21 VGA connector

22 HDMI source connector

OLED () display

23 FPGA configuration source jumper

24 HDMI sink connector

25 Power switch

26 Power jack 12VDC

Table 1. Genesys 2 features and connectors.

1. Quick-start

The Genesys 2 comes with an out-of-box demo design that gets loaded from the on-board QSPI flash. It exercises most of the
on-board peripherals. Just power the board with the included 12V wall supply, flick the power switch, wait for the design to
fully load and explore the following features:

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• Connecting an HDMI/DVI, VGA, or DisplayPort monitor shows a demo image with a mouse pointer.

• Connecting a USB mouse controls the mouse pointer on the display.
OLED () shows the Digilent logo and various information on several pages. Advance between pages with the

•The

BTNC button.

• The internal FPGA temperature, voltage and current readings of various power rails are shown on the

• Connecting the board to an Ethernet network will acquire link, IP address and become “pingable” at the IPv4 address

displayed on the

• Connecting the USB-UART port to a PC and opening a terminal (115200, 8, N, 1) shows status messages.

• Pushing BTNU records audio off the microphone input for five seconds and plays it back on the headphone output if

BTND is pushed, or line-out if BTNL. Similarly, BTNR starts a recording off the line-in jack.

• The LEDs are showing a scanning light bar.

• The fan starts when FPGA internal temperature reaches 60°C and stops when it drops back to 40°C.

OLED ().

OLED ().

To develop new FPGA designs for the Genesys 2, download and install the

(http://www.xilinx.com/products/design-tools/vivado.html). The tools include all the USB drivers for the board. Once installed, the USB

JTAG and USB UART ports can be connected to the PC and making the FPGA visible in Vivado Hardware Manager.

Additional resources can be found on the Genesys 2 Resource Center.

Xilinx Vivado® Design Suite

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2. Power Supplies

The Genesys 2 board can receive power from an external power supply through the center-positive barrel jack (J27). The
external supply voltage must be 12 V ±5 %. The Genesys 2 cannot be powered from the USB bus.

All Genesys 2 power supplies can be turned on and off together by a single logic-level power switch (SW8). Power supplies are
either enabled/disabled directly by the power switch or indirectly by other supplies upstream. A power-good
driven by the “power good” output of the on-board regulators, indicates that the supplies are turned on and operating
normally. An overview of the Genesys 2 power circuit is shown in Figure 1.

LED () (LD15),

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An external power supply can be used by plugging it into the power jack (J27). The supply must use a coax, center-positive

2.1mm internal-diameter plug, and deliver 12VDC ±5 %. The minimum current rating of the supply depends on the actual
design implemented in the FPGA, but at least 3A (i.e., at least 36W) is recommended. For high-power FMC applications a 60W
supply is recommended.

Voltage regulator circuits from Linear Technology create the different voltages required by the FPGA and on-board peripherals
from the main power input. Some regulators use the outputs of another regulator as input, depending on design considerations.
In some cases this chaining helps in creating the proper power-on sequence for circuits. In other cases the chaining of power
supply enables achieves the same purpose.

Table 2 provides information on maximum and typical currents for each power rail. The typical currents strongly depend on
FPGA configuration and the values provided are the current consumption of the OOB demo.

Current

Supply Circuits Device

(max/typical)

3.3 V FPGA I/O, USB, FMC, Clocks, Pmod, Ethernet, SD slot,

Flash, DisplayPort, HDMI

IC42:

LTC3855#1

6 A / 0.8 A

1.0 V FPGA Core IC30: LTC3866 14 A / 1.2 A

1.8 V FPGA Auxiliary IC36: LTC3605 5 A / 1.6 A

1.5 V DDR3 and FPGA I/O IC32: LTC3618 2 A / 0.7 A

0.75V DDR3 termination, reference IC32: LTC3618 2 A

2.0 V FPGA Auxiliary I/O for memory high data rates IC38: LT1762 150 mA

VADJ

User I/O, FMC and FPGA I/O IC37: LTM4618 5A

2)

(1.2-3.3 V)

3.3 V Audio analog supply IC12: LT1761 100 mA

5.0 V USB Host, HDMI IC42:

3 A / 0.3 A

LTC3855#2

MGT 1.0 V Gigabit Transceivers

VCC () IC41: LT3083 2 A

MGT 1.2 V Gigabit Transceivers VTT IC39: LTC3026 1.5 A

MGT 1.8 V Gigabit Transceivers AUX IC40: LT1762 150 mA

XADC 1.8 V XADC supply IC47: LT1761 100 mA

XADC 1.25 V XADC reference IC48: LT1790 5 mA

Table 2. Voltage rail power settings.

The VADJ power rail requires special attention. It is an adjustable rail that powers the FMC mezzanine connector, user push­buttons, switches, XADC Pmod connector and the FPGA banks connected to these peripherals (banks 15, 16, 17). The
feedback pin of the VADJ regulator is connected to a resistor network modifiable by jumper JP6. Changing its position
changes the resistor divider in the feedback loop, thereby changing the voltage on the regulator’s output. The possible voltages

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are listed in Figure 2. If JP6 is not set, the VADJ voltage defaults to 1.2 V. This feature enables setting the VADJ voltage to suit
a certain FMC mezzanine card or application. It is recommended to only change the JP6 position with the power switch in the
OFF position.

Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex. user push-buttons),
the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the schematic and/or the
constraints file to determine which signals are in VADJ-powered banks. The provided master UCF and XDC files assume the
default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these signals.

3. Power Monitoring

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I C-interfaced monitoring circuits, INA219 from Texas Instruments, are available on the main power rails. These allow real­time voltage, current, and power readings in the FPGA. Six such circuits share the same I C bus with different slave addresses.
These are summarized in Table 3, along with recommended configuration values.

Supply rail I2C device address Shunt resistor Configuration register Calibration register Designator

2

VCC1V0 b1000101 5 mΩ 0x0867 0x4000 IC29

VCC1V5 b1001100 IC33

VCC1V8 b1001000 IC35

VADJ b1000001 IC34

VCC3V3 b1000100 IC44

VCC5V0 b1000000 IC46

Table 3. Power monitoring circuit parameters.

The configuration and calibration registers are volatile, so they need to be initialized after power-up. After initialization is done
voltage, current, and power values can be read from dedicated registers. It is recommended to add glitch filters to the I2C
master controller to avoid spurious start or stop conditions occurring on the bus. This is especially important when using an
external I2C master connected to the J18 header (not mounted by default).

For more information on the INA219, see its

datasheet (http://www.ti.com/lit/gpn/ina219).

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The principle of operation is measuring bus and shunt voltages using a programmable-gain differential amplifier and an analog­to-digital converter. The schematic for one such circuit is shown in Figure 3. The two analog inputs are connected across a
shunt resistor placed in series between the power supply and the load. Current consumed by the load produce a voltage drop
across the shunt resistor. This voltage is measured by the INA219 and is used to calculate the current. In addition, the bus
voltage is measured on V- with respect to

GND () and is the voltage on the respective power rail. The voltage and current
measurements are used to calculate power consumption. If the INA219 is configured, it will correctly calculate all three
parameters. In its default, power-up configuration it provides bus and shunt voltage only, which can be used to calculate
current and power in the FPGA.

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4. Fan

The Genesys 2 comes with a fan and a secondary heat sink pre-installed on the FPGA package heat sink. The fan is powered
from the external 12V DC supply rail and controlled by the FPGA. Control is done by the “FAN_EN” signal. Pulling the
signal high from the FPGA opens the transistor driving the fan. This pin is pulled high by default. Feedback is obtained on the
“FAN_TACH” signal. This generates a pulse with a frequency proportional to the rotation speed of the fan. Each rotation
generates four pulses on “FAN_TACH”. The period of these pulses shortens with higher rotation speed and lengthens at
slower speeds.

The fan uses a 3-pin header for power, ground and feedback. It is recommended leaving the fan connected at all times.
Depending on FPGA design complexity and actual usage the fan might not be needed at all. In this case the enable signal can
be used to stop the fan, and start it when the FPGA internal temperature (as read by the XADC) gets above a certain limit.

5. FPGA Configuration

After power-on, the Kintex-7 FPGA must be configured (or programmed) before it can perform any functions. You can
configure the FPGA in one of four ways:

1. A PC can use the Digilent USB-JTAG circuitry (port J17, labeled “USB JTAG”) to program the FPGA any time the
power is on.

2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA.

3. A programming file can be transferred to the FPGA from a micro SD card.

4. A programming file can be transferred from a USB mass-storage device (ex. pen drive) attached to the USB HOST port.

Figure 5 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP5) and a media
selection jumper (JP4) select between the programming modes.