Digilent FX12 User Manual

FFXX1122 BBooaarrdd RReeffeerreennccee MMaannuuaall

FFeeaattuurriinngg tthhee XXiilliinnxx VViirrtteexx--44 FFPPGGAA

Revision: August 2, 2006

www.digilentinc.com

215 E Main Suite D | Pullman, WA 99163

(509) 334 6306 Voice and Fax

Overview

The Digilent FX12 board (the FX12) is an integrated circuit development platform for Xilinx’s Virtex-4 FX12 FPGA. The FX12 is based on Xilinx’s newest programmable architecture and contains a PowerPC core, dual Ethernet MACs, 32 XtremeDSP slices, 80Kbytes of block RAM, advanced clock management, and flexible I/O’s. The FX12 also features external memories, a flexible time base, power supplies, an Ethernet PHY, ports, and other I/O devices.

The FX12 provides an ideal platform for investigating a new generation of highly integrated designs made possible by Xilinx’s Virtex-4 family.

Features include:

• a Virtex-4 FX12 FPGA

• JTAG programming port that can

accommodate all Digilent and Xilinx programming cables

• XCF08S Xilinx Platform Flash ROM to store FPGA configurations

• Marvell 88E1111 “Alaska” Gigabit PHY

• 24-bit Analog Devices high-speed Video

DAC

• 64 Mbytes of ISSI DDR SDRAM

• 16 Mbytes of Micron Flash ROM

• high-current Linear Technology

switching power supplies

• Linear Technology FastDAACS connector for driving high-speed analog peripherals

• user-settable Integrated Circuit System frequency synthesizer (up to 350MHz)

• on board serial port, LCD display, buttons, switches, and LEDs

• high-speed-capable expansion connector

Doc: 502-108 page 1 of 18

FX12 Block Diagram

FX12 Reference Manual

Digilent

www.digilentinc.com

Functional Description

The FX12 showcases the many advanced features of Xilinx’s Virtex-4 FPGA, especially its ability to serve as the single device at the core of an embedded system. The FX12 includes a host of advanced features, including an embedded PowerPC core, a hard-IP MAC, XtremeDSP slices that include fast hardware multipliers, advanced clock management, Smart RAM, and other features, bringing new capabilities to highly-integrated embedded platforms. The FX12 board enhances the abilities of the FPGA by adding peripheral devices such as 64Mbytes of DDR memory, 16Mbytes of Flash ROM, and an Ethernet port, making it well suited to support a variety of embedded system designs.

The FX12 is supported by world-class design tools, including ISE, Chipscope-Pro, Embedded developers Kit (EDK), and System Generator.

JTAG Ports and Device Configuration

The FX12 can be programmed from a PC or directly from an on-board Flash ROM at power-on. PC programming requires a programming cable such as Digilent’s JTAG3 or JTAG-USB cable, or Xilinx’s PC4 or Platform USB cable. Programming files for the Virtex-4 and XCF08 Platform Flash ROM can be created using Xilinx’s ISE or EDK software, or a variety of other third-party tools. Please refer to the appropriate CAD tool reference materials for information on creating programming files.

Mode select

JTAG3 header

PC4

header

XCF08

Platform

Flash

jumper

JTAG

Virtex-4

FPGA

Slave Serial

Bypass

buffer

Hirose FX2 connector

PROG

DONE

LD14

Vdd

PROG (reset) pushbutton

Mode Select

Jumpers

JTAG3

Connector

PC4

Connector

A .bit file may be programmed into the FPGA from a PC by setting the mode jumpers to “JTAG” mode, attaching a programming cable to the PC and to one of the two programming headers (JTAG3 or PC4), and running Digilent’s Adept software or Xilinx’s iMPACT programming tool (Adept is a free download from the Digilent website and iMPACT is a free download from the Xilinx website). The configuration software will automatically identify all devices in the scan chain, and allow

Mode Select Jumper Settings

the FPGA and ROM to either be bypassed individually, or programmed individually with any available .bit or .mcs file. Note that both the FPGA and Platform Flash ROM will always appear in the scan chain. If a JTAG-aware peripheral board is attached to the Hirose FX2 expansion connector, it will appear in the scan chain between the FPGA and Platform Flash.

FX12 Reference Manual

Digilent

www.digilentinc.com

After the Platform Flash ROM has been loaded with a configuration file, the FPGA can load that file at power-on if the mode select jumpers are set in the Platform Flash position.

An FPGA system-reset button labeled PROG has been provided to allow a user-initiated FPGA reset. Pressing the PROG button will clear all configuration memory and cause the FPGA to await the next programming cycle. An LED on the DONE signal will illuminate at the end of a successful configuration.

Power Supplies

Power is delivered to the FX12 board via a 2.1mm, center-positive power connector that can be driven from any suitable 4VDC-5.5VDC source (like a

2.1mm centerpositive power jack

3.3V switching supply for FPGA I/O and peripherals (LTC3416)

2.5V switching supply for DDR (LTC3416)

wall-plug supply). Power is routed from the connector to four switching regulators and single LDO that produce all required supply voltages. Input power is also routed directly to the character LCD and high-speed expansion connector (pins A49 and A50) for use by peripheral circuits.

Current Consumption

Total board current is dependant on FPGA configuration, synthesizer clock frequency, and external connections. In test configurations using the PPC core to run DDR and Flash memory tests, with roughly 10% of the FPGA routed and a 100MHz input clock, approximately 650mA of supply current is drawn from the main power supply. Required current will increase if larger circuits are configured in the FPGA, if clock frequency is increased, and if peripheral boards are attached.

1.8V LDO for Platform Flash ROM (LTC1844)

FX12 Power Supplies

1.25V switching supply for DDR termination (LTC3413)

1.2V switching supply for FPGA core (LTC3418)

Power Distribution

The FX12 uses an eight-layer PCB, with the stack-up shown in the table. The Vdd planes are split into several localized islands to accommodate the various component’s supply voltage requirements. Bulk ceramic bypass capacitors are placed strategically around the board, and every component Vdd pin has one, two, or three local bypass caps in the .001 to .047uF range. The power supply routing and bypass capacitors result in a very clean low-noise power supply.

FX12 Stack-Up

Layer Usage Copper

1 Signal 1 oz. 2 GND .5 oz. 3 Signal .5 oz. 4 Vdd .5 oz. 5 Vdd .5 oz. 6 Signal .5 oz. 7 GND .5 oz. 8 Signal 1 oz.

Supply Details

FX12 Reference Manual

Regulator

Part

Number

Supply

Max

Current

• Hirose expansion connector

• Xilinx FPGA I/O banks 2, 4, 6, 7,

and 8

3.3V 4A LTC3416

• Micron Flash memory

• RS-232 level shifter

• Analog Devices Video DAC

• ICS frequency synthesizer

• Xilinx Platform Flash

• Xilinx FPGA I/O banks 1, 3, 5, 7,

2.5V 4A LTC3416

and 8

• ISSI DDR DRAM’s

• Marvell 88E1111 Ethernet PHY

1.8V 150mA LTC1844

1.25V 2A LTC3413

1.2V 8A LTC3418

• Xilinx Platform Flash

• DDR termination networks

• Xilinx FPGA core

• Marvell PHY core

Oscillator

The FX12 includes a 350MHz, crystal-toLVCMOS frequency synthesizer from Integrated Circuit Systems Inc (PN ICS8402). The synthesizer gets its primary frequency input from a 25MHz crystal, and then multiplies that input up to the desired output frequency. The output frequency is selected by the DIP switches at SW1, according to the table in Appendix A. The clock output from the synthesizer is delivered to the FPGA on the GCLK0 input at pin Y5.

A secondary input is also available to drive a different base frequency into the synthesizer. The socket labeled “test_clk” can accommodate any 12-40MHz LVCMOS oscillator in a half-DIP package. This secondary source will drive the synthesizer if the XTAL_SEL signal is driven high from the FPGA. The oscillator circuit is shown in the accompanying figure. Please see the ICS8402 data sheet for further information.

Digilent

www.digilentinc.com

Devices Powered Notes

Uses oversized 3.3uH inductor for stability at low current.

Uses oversized 1.5uH inductor for stability at low current.

SMA Clock Inputs to FPGA

Frequency Select Switches

SMA Clock Output

Secondary Clock Input

Frequency Synthesizer

Clock Source Select Jumper

Primary Crystal (25MHz)

FX12 Oscillator Circuit

FX12 Reference Manual

Digilent

www.digilentinc.com

Frequency Select Switches

M0 M1

IC15

XTAL_SEL

M2 M3 M4 N0

ICS8402

Frequency

Synthesizer

N1 VCO_SEL

OE1 OE2 M5

TEST_CLK

M6 M7 M8 NP_LOAD

XTAL1 XTAL2

FX12 Frequency Synthesizer Diagram

R18 (GCLK0) R18

Virtex-4

FPGA

SMA Connector

Test Clock Socket

25MHz

Crystal

DDR

The 64Mbyte DDR memory array consists of two 32Mbyte (16M x 16) ISSI IS43R16160A-6T devices connected as a 16M x 32 array. Individual byte selects for both memories are brought to the FPGA so byte, word, and long-word read/writes are possible. A differential clock is routed from the FPGA to the memories, and a length-matched clock return is routed back to the FPGA to allow for timing optimization. All data signals are delay and impedance matched (with 48-ohm trace impedance), and all DDR signals are actively terminated through 47-ohm resistors to a 1.25V supply for optimal bus performance.

UCF File

Signals routed to the DDR SDRAM should use the SSTL2_I standard as shown in the example .ucf file entry below. All VREF pins on Bank 5 (used by the DDR signal connections) should have “prohibit” constraints in the .ucf file to prohibit software from assigning these pins to other functions.

NET “DDR_D0” LOC = “P20” | IOSTANDARD = SSTL2_I ; CONFIG PROHIBIT = C17;

FX12 Reference Manual

See table

ADDR(12:0)

IC11

Digilent

www.digilentinc.com

BA1 BA0

CK CK_N CKE

Dual ISSI

IS43R16160A

DDR SDRAM’s

IC12

Virtex-4

FPGA

C18 D17

P16 P17 N16

DDRCLK LOOP

(16Mbyte x 16)

D18

F17

E18

F18

See table

IC11 only

J19 N18 A13 B13

See table

IC12 only

A15 B15 A14 B14

FX12 DDR Circuit Diagram

CS CAS RAS WE

DATA(15:0) LDQS1 UDQS1 LDM1 UDM1

DATA(31:16) LDQS2 UDQS2 LDM2 UDM2

DDR Address Pins DDR Data Pins

ADDR12 M15 DATA31 H18 DATA15 G17 ADDR11 M16 DATA30 H20 DATA14 H17 ADDR10 F16 DATA29 G20 DATA13 J17 ADDR9 K17 DATA28 G19 DATA12 J18 ADDR8 K16 DATA27 F20 DATA11 K18 ADDR7 J15 DATA26 F19 DATA10 M18 ADDR6 J16 DATA25 E20 DATA9 M17 ADDR5 H16 DATA24 D19 DATA8 N17 ADDR4 G16 DATA23 A16 DATA7 K20 ADDR3 C15 DATA22 B16 DATA6 K19 ADDR2 C16 DATA21 B17 DATA5 L20 ADDR1 D16 DATA20 A18 DATA4 M19 ADDR0 E16 DATA19 B18 DATA3 M20 DATA18 B19 DATA2 N19 DATA17 C19 DATA1 P19 DATA16 C20 DATA0 P20

+ 12 hidden pages

Digilent FX12 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual