Digilent DIO5 User Manual

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Overview

The DIO5 circuit board provides a ready-made

Connector P2Connector P1

source for many common I/O devices found in digital systems. It can be connected to Digilent system boards to create a digital development platform that is suitable for a wide range of projects. The DIO5 uses a Xilinx CoolRunner CPLD to facilitate interaction with system boards. The CLPD automatically appears in the JTAG scan chain when the DIO5 is

JTAG

XCR3128XL CoolRunner CPLD

Clock

System Bus

TQ-144

VGA

Port

Uncomitted I/O

attached to a system board, so new designs can easily be configured into the DIO5. DIO5 features include:

• A Xilinx CoolRunner XCR3128 CPLD for I/O device and system bus control;

• A 16x2 character LCD module;

• A 4-digit seven segment LED display;

• 16 LEDs in three different colors;

8 switches

16x2 LCD

DIO5 circuit board block diagram

PS2 Port

4 7-seg.

displays

16 LEDs

16 button

keypad

• A 16 button keypad;

• 8 slide switches;

• 3-bit VGA port;

• PS/2 mouse or keyboard port.

The DIO5 has been designed to work seamlessly with Digilent system boards and all versions of the Xilinx ISE CAD tools, including the free WebPack tools available from Xilinx. The CPLD on the DIO5 is configured during manufacturing with the project shown in Appendix 1, but new designs can easily be loaded into the CPLD.

Functional Description

The Digilab DIO5 can be attached to any Digilent system board to create a digital design platform that has many useful I/O devices. The DIO5 draws power from the system board, so no separate power supply is required. All I/O device signals are routed through the on-board CPLD so that a customized I/O controller can be created for any given design. For example,

if all on-board I/O devices are needed, a register-based controller can be implemented. Or, if only a subset of I/O devices are needed, a much simpler controller can be used to map device signals directly through the CPLD to the system board. Because the CPLD appears in the JTAG scan chain when the DIO5 is attached to a system board, it can easily be configured. The CPLD is programmed during manufacture with register-based controller shown in Appendix 1.

Power Supplies

The DIO5 board draws power from three pins on the 40-pin connectors: pin 37 supplies 3.3V; pin 39 provides system GND, and pin 40 supplies unregulated voltage (VU). Pin 40 (VU) is connected directly to an LM1117 5VDC LDO regulator on the DIO5. 5VDC is used by the LCD display and the PS/2 interface. The 3.3V

DIO5 Reference Manual Digilent, Inc.

supply is used to drive the CPLD and all other I/O devices on the board. During normal operation, the DIO5 consumes 10-20mA from the 5V supply, and 50-100mA from the 3.3V supply depending on how many LEDs are illuminated. The DIO5 uses a four-layer board, with two layers dedicated to 3.3V and GND, and several bulk and high-frequency decoupling capacitors to keep the supplies stable under all loads.

CPLD Configuration

The JTAG scan chain is routed through the DIO5 board on pins 1-4 of connector P1, allowing the CPLD to be configured from any Digilent system board. Jumper-shunts must be loaded on pins 1 & 2 of jumper blocks JP2 and JP3 on the DIO5 to include the CPLD in the scan chain, or across pins 2 & 3 to remove the CPLD from the scan chain.

Jumper position JP1 allows the JTAG signals on the CPLD to be reclaimed if they are inadvertently programmed as user I/O’s. Since the JTAG pins on the CPLD are used only for programming, this jumper block should not normally be loaded. The CPLD pinout is available in appendix 1.

System Board Interface

Signals from all I/O devices on the DIO5 are routed through the CPLD, with the exception of the VGA port (video data is too high bandwidth to pass through the CPLD). All I/O devices on the DIO5 can therefore be read or written via a register-based controller in the CPLD. Some device signals, including the eight slide switches, the PS/2 data and clock, and an LCD enable are also routed around the CPLD and directly to the connectors. These signals can be accessed either through the CPLD or directly from the system board.

The CPLD offers several options for moving data between the DIO5 and a system board: a memory-mapped bus interface can be defined where all devices are accessed via registers; a “direct connect” interface can be defined where

I/O signals pass directly through the CPLD without the need for a bus (in this case, not all devices on the DIO5 can be accessed); or various controllers and compression/encoding schemes can be used to transfer device data over subsets of pins.

The default DIO5 CPLD circuit defines a “system bus” to transfer data to and from a system board. The bus uses 8 bi-directional data lines, six address lines, three control signals, and a clock signal (LCLK). The three control signals, write enable (WE), output enable (OE), and chip select (CS), are used to coordinate bus traffic, and the LCLK signal provides a clock for latches and controllers on the DIO5. Four 8-bit write-only registers are used to receive LED and seven-segment display data in the CPLD, and three readable locations contain pushbutton and switch data.

DIO5 Default Circuit Memory Map

Address Read Write

000 BtnLo (buttons 0-7) LedLo (LEDs 0-7) 001 BtnHi (buttons 8-F) LedHi (LEDs 8-F) 010 Swt (slide switches) SsegLo 011 unused SsegHi

10X LCD bus LCD bus

Two read locations, BtnHi and BtnLo, arise from latches in the CPLD. Pushbutton signals are stored in these two 8-bit latches at each rising edge of LCLK. The third read location, Swt, simply passes switch signals to the system bus from the switch input pins.

The four writable registers in the CPLD all provide data to the LED devices (i.e., the seven-segment displays and discrete LEDs). The registers use rising-edge-triggered flipflops clocked by the trailing edge of the write enable signal (WE is active low). Data written to these registers appears immediately on the LED’s.

Ten additional pushbutton signals bypass the system bus, and are routed from the CPLD directly to pins on the expansion connectors. Four of these signals contain BCD codes for buttons 0-9, and six signals are simply the state of buttons A-F at the output of the

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DIO5 Reference Manual Digilent, Inc.

latches. These ten signals are always available regardless of the system bus state.

The CPLD also contains a seven-segment display controller. Binary data, in the form of four 4-bit fields spanning two bytes, can be written to the seven-segment data registers and it will be displayed as four hexadecimal characters on the seven-segment display. The display controller uses LCLK to control refresh timing.

Bi-directional LCD data transfers occur over the system bus. The default CPLD circuit synthesizes LCD control signals for bus cycles directed to the LCD memory space, but it is also possible to drive the LCD control signals directly. The “LCD” section below provides information on driving the LCD.

Write Cycle

tdoe

DB0-DB7

Read Cycle

DB0-DB7

System Bus Timing

ten

twd

System bus timings are shown below. Data is written on the rising edge of write-enable (WE). DIO5 bus drivers are enabled whenever output enable (OE) is asserted (low). The diagrams below show signal timings assumed by Digilent to create peripheral devices. Different bus and timing models can be used by modifying circuits in the FPGA and attached peripheral devices.

System Bus Timings

Symbol Parameter

ten Time to enable after CS asserted 10ns

th Hold time 1ns tdoe Disable time after OE deasserted 10ns teoe Enable time after OE asserted 15ns

tw Write strobe time 10ns

tsu Data setup time 5ns

twd Write disable time 0ns

teoe

tsu

teoe

tdoe

tsu

Read data latch time

Time

(typ)

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DIO5 Reference Manual Digilent, Inc.

LCD

The DIO5 uses a Powertip 16x2 LCD module (P/N PC1602ARS-DWA-A) with a Samsung KS0066U controller (data sheets are available at the Digilent website).

16 x 2 character LCD

Pin 1

Powertip PC1602ARS

The KS0066U contains a character-generator ROM (CGROM) with 208 preset 5x8 character patterns, a character-generator RAM (CGRAM) that can hold 8 user-defined 5x8 characters, and a display data RAM (DDRAM) that can hold 80 character codes. Character codes written into the DDRAM serve as indexes into the CGROM (or CGRAM). Writing a character code into a particular DDRAM location will cause the associated character to appear at the corresponding display location. Display positions can be shifted left or right by setting a bit in the instruction register (IR). The write-only IR directs display operations (such as clear display, shift left or right, set DDRAM address, etc). Available instructions (and the associated IR codes) are shown in the rightmost column of table 3 below. A busy flag shows whether the display has competed the last requested operation; prior to initiating a new operation, the flag can be checked to see if the previous operation has been completed.

The display has more DDRAM locations than can be displayed at any given time. DDRAM locations 00H to 27H map to the first display row, and locations 40H to 67H map to the second row. Normally, DDRAM location 00H maps to the upper left display corner, and 40H to the lower left. Shifting the display left or right can change this mapping. The display uses a temporary data register (DR) to hold data during DDRAM /CGRAM reads or writes, and an internal address register to select the RAM location. Address register contents, set via the

IR, are automatically incremented after each read or write operation. The LCD display uses ASCII character codes. Codes up through 7F are standard ASCII (which includes all “normal” alphanumeric characters). Codes above 7F produce various international characters – please see the manufacturers data sheet for more information on international codes.

The display is connected to the DIO5 board by a 16-pin connector (pins 15 and 16 are for an optional backlight, and they are not used). The 14-pin interface includes eight data signals, three control signals, and three voltage supply signals. The eight data bus signals are passed through the CPLD to/from the system bus for read/write cycles directed to the LCD memory space (address 10X). The three LCD control signals are driven from the CPLD: the RS (Register Strobe) signal clocks data into registers; the R/W signal determines bus direction; and the E signal enables the bus for read or write operations. In the standard CPLD configuration, the R/S and R/W signals are connected to ADDR0 and WE respectively. The E signal can be driven directly from the LCDEN signal available on the system connector, or if LCDEN is left at logic ‘0’, then E is driven whenever address “10X” is present on the bus, CS is asserted, and AS or DS are low. LCD bus signals and timings are shown below.

A startup sequence with specific timings ensures proper LCD operation. After power-on, at least 20ms must elapse before the functionset instruction code can be written to set the bus width, number of lines, and character patterns (8-bit interface, 2 lines, and 5x8 dots are appropriate). After the function-set instruction, at least 37us must elapse before the display-control instruction can be written (to turn the display on, turn the cursor on or off, and set the cursor to blink or no blink). After another 37us, the display-clear instruction can be issued. After another 1.52ms, the entrymode instruction can set address increment (or address decrement) mode, and display shift mode (on or off). After this sequence, data can be written into the DDRAM to cause information to appear on the display.

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DIO5 Reference Manual Digilent, Inc.

Table 3. LCD Instructions and Codes

Instruction

Clear

Display

Return

Home

Entry mode

set

Display

ON/OFF

control

Cursor or

Display shift

Function Set 0 0 0 0 1 DL N F X X

Set CGRAM

Address

Set DDRAM

address

Read busy

flag/ address Write data to

RAM

Read data

from RAM

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 X

0 0 0 0 0 0 0 1 I/D SH

0 0 0 0 0 0 1 D C B

0 0 0 0 0 1 S/C R/L X X

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address counter 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address counter 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Instruction bit assignments

Description

Clear display by writing a 20H to all DDRAM locations; set DDRAM address register to 00H; and return cursor to home. Return cursor to home (upper left corner), and set DDRAM address to 0H. DDRAM contents not changed. I/D = ‘1’ for right-moving cursor and address increment; SH = ‘1’ for display shift (direction set by I/D bit). Set display (D), cursor (C), and blinking cursor (B) on or off.

SC = ‘0’ to shift cursor right or left, ‘1’ to shift entire display right or left (R/L = ‘1’ for right). Set interface data length (DL = ‘1’ for 8 bit), number of display lines (N = ‘1’ for 2 lines), display font (F = ‘0’ for 5x 8 dots)

Read busy flag and address counter Write data into DDRAM or CGRAM, depending on which address was last set Read data from DDRAM or CGRAM, depending on which address was last set

Table 4. LCD Connector Signals

Pin No. Symbol Signal Description

1 Vss Signal ground 2 Vdd Power supply (5V) 3 Vo Operating (contrast) voltage (LCD drive, typically 100mV at 20C) 4 RS Register select: high for data transfer, low for instruction register 5 R/W Read/write signal: high for read mode, low for write mode 6 E Read/write strobe: high for read OE; falling edge writes data 7-14 Data Bus Bi-directional data bus

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DIO5 Reference Manual Digilent, Inc.

LCD Read Cycle

R/W

tsu

tr tf

tD tDH

Power On

Wait for 20ms

Function Set

Wait for 37us

Display Control Set

DB0-DB7

Wait for 37us

Display Clear

Wait for 1.52ms

OK for operati o ns

LCD startup sequence

LCD Write Cycle

R/W

tsu

tsu1 th1

DB0-DB7

Enable cycle time tc 500 ns E Enable High pulse width tw 220 ns E Enable rise/fall time tr, tf 25 ns E RS, R/W setup time tsu 40 ns RS, R/W RS, R/W hold time th 10 ns RS, R/W Read data output delay tD 60 120 ns DB0-DB7 Read data hold time tDH 20 ns DB0-DB7 Write data setup time tsu1 40 ns DB0-DB7 Write data hold time th1 10 ns DB0-DB7

Parameter Symbol Min Max Unit Test Pin

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Table 5. LCD Bus Timings

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Digilent DIO5 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual