Digilent DIO2 User Manual

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Overview

The Digilab Digital I/O board 2 (the DIO2) is one of several expansion boards designed to mate with Digilab system boards. The DIO2 board provides an assortment of frequently used digital I/O devices, many of which are controlled by an on-board Xilinx XC95108 CPLD. The CPLD also provides a bus interface

5VDC

regulator

VDD

GND

JTAG

Connector BConnector A

control

address

PS2

data

port

VGA

port

16x2 LCD

to simplify communications with Digilab system boards. DIO2 boards can be combined with Digilab system boards to implement projects ranging from basic logic designs to

XC95108

PC84

general computer systems, without the need for any other components.

DIO2 board features include:

• A XC95108 CPLD for I/O device and system bus control;

• A 16x2 character LCD with integral Samsung controller IC;

4 7-seg. displays

15 LEDs

DIO2 circuit board block diagram

8 switches

15 button

keypad

• A four digit seven-segment LED display;

• 16 individual LEDs of various colors;

• An 8-bit VGA port;

• A 15-button keypad;

• 8 slide switches;

• A PS2 mouse/keyboard port;

• An on board 5VDC regulator.

The CPLD comes pre-configured with the circuit shown in Appendix 1, but it can also be reprogrammed from any Xilinx CAD tool, including the free WebPack tools available from the Xilinx website. CPLD configuration can be accomplished using the Xilinx JTAG cable or the Digilent XC95 programming board.

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Digilab DIO2 Reference Manual Digilent, Inc.

Functional description

The DIO2 board includes many frequently used peripheral devices found in digital systems, including several output display devices and several input devices. When mated with a Digilab main board, the DIO2 board provides a highly flexible digital system development platform. The DIO2 board centers on a Xilinx XC95108 CPLD that provides a convenient interface to most of the I/O devices, as well as a control bus between an attached system board and the I/O devices. Since the CPLD on the DOI2 board is user configurable, many different I/O control and communication schemes can easily be implemented.

Although the DIO2 board has been designed as a peripheral board for various Digilab system boards, it can also be used as a CPLD demonstration/development board. Digilent produces a low cost power supply/programming board that can be connected to the DIO2 board to create a stand-alone, very low cost CPLD platform. This board, called the DXC95 board, provides a JTAG programming interface, a power supply, a clock source, and a small breadboard area (see www.digilentinc.com for more information).

This document presents the circuits, I/O devices, and interfaces in the DIO2 board. When needed, manufacturer part numbers have been provided so that further reference material can be obtained from their websites.

Signals

All named signals used on the DIO2 board are defined in the table on the right. Voltage levels for all signals arriving from an attached Digilab system board are determined by the system board, but all signals arising on the I/O board derive from the on-board 5VDC regulator (so they are all 5V CMOS signals).

The DIO2 board uses a twolayer process, so all signals are available on the top and bottom layers. Many signals are brought to a test point header for easy test and measurement equipment attachment.

Power Supplies VU Unregulated power supply voltage from attached system

board – typically 5-9VDC. Available only on J1 P40, this supply is regulated to 5VDC to supply on onboard devices.

VDD* Regulated power supply voltage (5VDC) from on-board

regulator. This supply is used by all devices on DIO2 board. GND* System ground CPLD – system board bus signals D7-D0* Bi-directional data bus between B connector and CPLD/LCD A5-A0* Address lines to select locations in CPLD CS* Chip select used for CPLD interface on DIO2 board WE* Write enable for CPLD memory locations OE* Output enable for CPLD data signals BOCI* “Button Out-Clock In” pin, used as clock input to CPLD LCD control signals D7-D0 Data bus – same as CPLD data signals LCD_RW* LCD Read/Write signal – ‘1’ for read mode LCD_RS* LCD Register Select – ‘1’ for data register, ‘0’ for instruction LCD_E LCD Enable signal – active high; falling edge latches data VGA and PS2 signals (routed directly from B connector, not through CPLD) HS* VGA Horizontal Sync signal VS* VGA Vertical Sync signal R1, R0* VGA 2-bit red data G2-G0* VGA 3-bit green data B2-B0* VGA 3-bit blue data KCLK* PS2 (Keyboard or Mouse) clock signal KDAT* PS2 (Keyboard or Mouse) data signal On board devices (routed through CPLD) BTN0-E Pushbuttons (A through E) SW1-SW8 Slide switches (1 through 8) LD0-LDF Discreet LEDs (0 through F) CA-CF Seven-segment display cathodes AN1-AN3 Seven-segment display anodes * available on test point header

Table 1. DIO2 board signal definitions

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Power Supplies

The DIO2 board receives system power from pins 39 and 40 of connector A. Pin 40 is connected directly to a 5VDC LDO regulator (an LM2940), and pin 39 is connected to ground. The regulator powers all devices on the DIO2 board, including the CPLD (all outbound data signals from the DIO2 board are 5V). The regulator requires about 400mV of dropout voltage, so a DC voltage 5.5VDC 8VDC must be applied to pin 40 of connector A for proper board operation.

Digilab system boards route unregulated voltage directly from the power supply to pin 2 of all expansion connectors. Since pin 2 on system boards mates with pin 40 on expansion boards, the DIO2 board receives power from the supply attached to the system board.

With no LED’s illuminated, the DIO2 board typically consumes about 200mA. With all LEDs illuminated (including all segments of the seven-segment display), the board can consume up to 350mA.

LCD

The LCD display is a 16 character, 2 line display from the Okaya company (Okaya part number RC1602D). The Okaya data sheet may be found on the Digilent website.

Pin 1

16 x 2 character LCD

The display uses a KS0066 Samsung controller that has a character-generator ROM (CGROM) containing 208 preset 5x8 character patterns, a character-generator RAM (CGRAM) that can hold 8 user-defined 5x8 characters, and a display data RAM (DDRAM) that can hold 80 character

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

codes. Character codes written into the DDRAM serve as indexes into the CGROM (or CGRAM). Writing a character code into a particular DDRAM location will cause the associated 5x8 character

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

DDRAM address - display postion map

pattern to appear at the corresponding display location. The display positions can be shifted left

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

or right by setting a bit in the instruction register (IR). The write-only IR is used to direct display

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

operations (such as clear display, shift left or right, set DDRAM address, etc). Available instructions are shown in the rightmost column of the table

DDRAM address - display postion map

after shift-left operation

below, together with the IR codes. A busy flag is

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E

available to indicate whether the display has competed the last requested operation; prior to initiating a new operation, the flag can be checked to see whether the previous operation has been completed.

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E

DDRAM address - display postion map

after shift-right operation

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The display has more DDRAM locations than can be displayed at any given time. DDRAM locations 00H to 27H map to the first display row, and locations 40H to 67H map to the second row. Normally, DDRAM location 00H maps to the upper left display corner, and 40H to the lower left. Shifting the display left or right can change this mapping. The display uses a temporary data register (DR) to hold data during DDRAM /CGRAM read or write operations, and an internal address register to select the RAM location. Address register contents, which can be set via the IR, are automatically incremented after each read or write operation. The LCD display uses ASCII character codes. Codes up through 7F are standard ASCII (which includes all “normal” alphanumeric characters). Codes above 7F produce various international characters – please see the manufacturers data sheet for more information on international codes.

Display Instructions and Instruction Codes

Instruction

Clear

Display

Return

Home

Entry mode

set

Display

ON/OFF

control

Cursor or

Display shift

Function Set 0 0 0 0 1 DL N F X X

Set CGRAM

Address

Set DDRAM

address

Read busy

flag/ address

Write data

to RAM

Read data

from RAM

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 X

0 0 0 0 0 0 0 1 I/D SH

0 0 0 0 0 0 1 D C B

0 0 0 0 0 1 S/C R/L X X

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address counter

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address counter

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Instruction bit assignments

Clear display by writing a 20H to all DDRAM locations; set DDRAM address register to 00H; and return cursor to home. Return cursor to home (upper left corner), and set DDRAM address to 0H. DDRAM contents not changed. I/D = ‘1’ for right-moving cursor and address increment; SH = ‘1’ for display shift (direction set by I/D bit). Set display (D), cursor (C), and blinking cursor (B) on or off.

SC = ‘0’ to shift cursor right or left, ‘1’ to shift entire display right or left (R/L = ‘1’ for right). Set interface data length (DL = ‘1’ for 8 bit), number of display lines (N = ‘1’ for 2 lines), display font (F = ‘0’ for 5x 8 dots)

Read busy flag and address counter Write data into DDRAM or CGRAM, depending on which address was last set Read data from DDRAM or CGRAM, depending on which address was last set

Description

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The display is connected to the DIO2 board by a 16-pin connector (pins 15 and 16 are for an optional backlight, and they are not connected on the DIO2 board). The eight data bus signals and three strobes are connected directly to the B connector on the DIO2 board (note the data lines are common with the CPLD data bus), so the LCD can be controlled from a Digilab system board. Bus timings are shown below. Note that the enable signal (E) serves as both output enable and write strobe (with an active falling edge) depending on the state of the Read/Write (R/W) signal.

Pin No. Symbol Signal Description

1 Vss Signal ground 2 Vdd Power supply (5V) 3 Vo Operating (contrast) voltage (LCD drive, typically 100mV at 20C) 4 RS Register select: high for data transfer, low for instruction register 5 R/W Read/write signal: high for read mode, low for write mode 6 E Read/write strobe: high for read OE; falling edge writes data 7-14 Data Bus Bi-directional data bus

LCD Read Cycle

LCD Write Cycle

R/W

DB0-DB7

R/W

tsu

tr tf

tD tDH

tsu

DB0-DB7

tsu1 th1

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Digilab DIO2 Reference Manual Digilent, Inc.

Parameter Symbol Min Max Unit Test Pin

Enable cycle time tc 500 ns E Enable High pulse width tw 220 ns E Enable rise/fall time tr, tf 25 ns E RS, R/W setup time tsu 40 ns RS, R/W RS, R/W hold time th 10 ns RS, R/W Read data output delay tD 60 120 ns DB0-DB7 Read data hold time tDH 20 ns DB0-DB7 Write data setup time tsu1 40 ns DB0-DB7 Write data hold time th1 10 ns DB0-DB7

LCD start-up sequence

The manufacturer requires that a startup sequence with specific timings be

Power On

followed to ensure proper LCD operation. After power-on, at least 20ms must elapse before the function-set instruction code can be written to set the

Wait for 20ms

bus width, number of lines, and character patterns (8-bit interface, 2 lines, and 5x8 dots are appropriate). After the function-set instruction, at least

Function Set

37us must elapse before the display-control instruction can be written (to turn the display on, turn the cursor on or off, and set the cursor to blink or no blink). Then after another 37us, the display-clear instruction can be

Wait for 37us

issued, followed by a 1.52ms delay. Finally, the entry-mode instruction code can be used to set address increment (or address decrement) mode, and

Display Control Set

display shift mode (on or off). Once this sequence is complete, data can be written into the DDRAM to cause information to appear on the display.

Wait for 37us

LEDs

Display Clear

Sixteen individual LEDs (8 red, 4 yellow, and 4 green) are provided for circuit outputs. The LED cathodes are driven directly from the CPLD, and

Wait for 1.52ms

the anodes are tied to Vdd via 270-ohm resistors (so the LED drive signals are active low). When the CPLD is configured with the code shown in the appendix, two 8-bit registers at locations x04 and x05 drive the LED cathode signals. Note the LED signals are inverted in the VHDL code, so a

OK for operati o ns

LCD startup sequence

logic “1” turns on the LEDs.

Seven-segment LED display

The DIO2 board contains a modular 4-digit, common anode, seven-segment LED display. In a common anode display, the seven anodes of the LEDs forming each digit are connected to four common circuit nodes (labeled AN1 through AN4 on the DIO2 board). Each anode, and therefore each digit, can be independently turned on and off by driving these signals to a ‘1’ or a ‘0’. The cathodes of

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Digilent DIO2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual