DIGILENT DIGIL 471-034-1 Datasheet

ZedBoard

(Zynq™ Evaluation and Development)

Hardware User’s Guide

Version 2.2

27 January 2014

Table of Contents

1 INTRODUCTION .................................................................................................................................. 2

1.1 ZYNQ BANK PIN ASSIGNMENTS ...................................................................................................... 4

2 FUNCTIONAL DESCRIPTION ............................................................................................................ 5

2.1 ALL PROGRAMMABLE SOC ............................................................................................................. 5

2.2 MEMORY ......................................................................................................................................... 5

2.2.1 DDR3 ...................................................................................................................................... 5

2.2.2 SPI Flash ................................................................................................................................ 7

2.2.3 SD Card Interface ..................................................................................................................10

2.3 USB ...............................................................................................................................................11

2.3.1 USB OTG ...............................................................................................................................11

2.3.2 USB-to-UART Bridge ............................................................................................................11

2.3.3 USB-JTAG .............................................................................................................................12

2.3.4 USB circuit protection ...........................................................................................................13

2.4 DISPLAY AND AUDIO ......................................................................................................................13

2.4.1 HDMI Output .........................................................................................................................13

2.4.2 VGA Connector......................................................................................................................16

2.4.3 I2S Audio Codec ....................................................................................................................17

2.4.4 OLED .....................................................................................................................................18

2.5 CLOCK SOURCES .............................................................................................................................18

2.6 RESET SOURCES .............................................................................................................................18

2.6.1 Power‐on Reset (PS_POR_B) ................................................................................................18

2.6.2 Program Push Button Switch .................................................................................................19

2.6.3 Processor Sub system Reset ....................................................................................................19

2.7 USER I/O ........................................................................................................................................19

2.7.1 User Push Buttons .................................................................................................................19

2.7.2 User DIP Switche s .................................................................................................................19

2.7.3 User LEDs .............................................................................................................................20

2.8 10/100/1000 ETHERNET PHY ........................................................................................................20

2.9 EXPANSION HEADERS ....................................................................................................................21

2.9.1 LPC FMC Connector .............................................................................................................21

2.9.2 Digilent Pmod™ Compatible Headers (2x6).........................................................................22

2.9.3 Agile Mixed Signaling (AMS) Connector, J2 .........................................................................23

2.10 CONFIGURATION MODES ................................................................................................................26

2.10.1 JTAG ......................................................................................................................................27

2.11 POWER ...........................................................................................................................................28

2.11.1 Primary Power Input .............................................................................................................28

2.11.2 On/Off Switch ........................................................................................................................28

2.11.3 Regulators ..............................................................................................................................28

2.11.4 Sequencing .............................................................................................................................29

2.11.5 Power Good LED ..................................................................................................................30

2.11.6 Power Estimation ..................................................................................................................30

2.11.7 Testing ...................................................................................................................................31

2.11.8 Probes ....................................................................................................................................31

3 ZYNQ-7000 AP SOC BANKS .............................................................................................................32

3.1 ZYNQ-7000 AP SOC BANK VOLTAGES ..........................................................................................33

4 JUMPER SETTINGS ............................................................................................................................34

5 MECHANICAL ....................................................................................................................................36

6 REVISION HISTORY ..........................................................................................................................37

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1 Introduction

The ZedBoard is an evaluation and development board based on the Xilinx ZynqTM-7000 All
Programmable SoC (AP SoC). Combining a dual Corex-A9 Processing System (PS) with 85,000
Series-7 Programmable Logic (PL) cells, the Zynq-7000 AP SoC can be targeted for broad use in
many applications. The ZedBoard’s robust mix of on-board peripherals and expansion
capabilities make it an ideal platform for both novice and experienced designers. The features
provided by the ZedBoard consist of:

• Xilinx® XC7Z020-1CLG484C Zynq-7000 AP SoC

o Primary configuration = QSPI Flash
o Auxiliary configuration options

 Cascaded JTAG
 SD Card

• Memory

o 512 MB DDR3 (128M x 32)
o 256 Mb QSPI Flash

• Interfaces

o USB-JTAG Programming using Digilent SMT1-equivalent circuit

 Accesses PL JTAG
 PS JTAG pins connected through PS Pmod

o 10/100/1G Ethernet
o USB OTG 2.0
o SD Card
o USB 2.0 FS USB-UART bridge
o Five Digilent Pmod™ compatible headers (2x6) (1 PS, 4 PL)
o One LPC FMC
o One AMS Header
o Two Reset Buttons (1 PS, 1 PL)
o Seven Push Buttons (2 PS, 5 PL)
o Eight dip/slide switches (PL)
o Nine User LEDs (1 PS, 8 PL)
o DONE LED (PL)

• On-board Oscillators

o 33.333 MHz (PS)
o 100 MHz (PL)

• Display/Audio

o HDMI Output
o VGA (12-bit Color)
o 128x32 OLED Display
o Audio Line-in, Line-out, headphone, microphone

• Power

o On/Off Switch
o 12V @ 5A AC/DC regulator

• Software

o ISE® WebPACK Design Software
o License voucher for ChipScope™ Pro locked to XC7Z020

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ZYNQ XC7

Z020-CLG484

DDR3

MIC In

Line In

Line Out

HdPhn Out

32

Pmods

QSPI

7

Pmod

Flash

8

14

Gbit

Enet

12

USB

OTG

8

SD

2

1 LED

,

2 buttons

USB
Cont

USB

UART

3

71

4

USB
Cont

Clk

FMC-LPC

GPIO (8 LEDs,
8

slide switches

,

5 pushbuttons)

Type A
HDMI Out

82

21

8

27

10

5

VGA (12­bit color)

128x32 OLED

PHY

1

1

33Mhz

Reset

Primary JTAG

512Mbyte

DDR3 (

x32)

Multiplexed I/O (MIO)Processing System (PS)

Programmable Logic (PL)

1

PROG

Display

DDR

PS_RST

JTAG

PS_CLK

<User
Select>

ENET/
MDIO

USBOTG

SD

USBUART

PS_GPIO

QSPI

I2

S

/ACD

GPIO

FMC

PMOD

HDMI

VGA

OLED

PROG

PHY

HDMI

transmitter

I

2S Audio

Codec

XADC

8

GPIO/VP/VN

1

DONE LEDDONE

Clk

100Mhz

1

GCLK

Figure 1 – ZedBoard Block Diagram

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1.1 Zynq Bank Pin Assignments

The following figure shows the Zynq bank pin assignments on the ZedBoard followed by a table
that shows the detailed I/O connections.

Figure 2 - Zynq Z7020 CLG484 Bank Assignments

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2 Functional Description

2.1 All Programmable SoC

The ZedBoard features a Xilinx Zynq XC7Z020-1CLG484 All Programmable SoC (AP SoC).
Initial ZedBoards were marked ‘Rev C’ and shipped with Engineering Sample "CES" grade
silicon. Later ‘Rev D’ shipments switched to production "C" grade silicon once those became
available. The Zynq-7000 AP SoC part markings indicate the silicon grade.

2.2 Memory

Zynq contains a hardened PS memory interface unit. The memory interface unit includes a
dynamic memory controller and static memory interface modules.

2.2.1 DDR3

The ZedBoard includes two Micron DDR3 128 Megabit x 16 memory components creating a 32­bit interface, totaling 512 MB.

Earlier ZedBoards used Micron MT41J128M16HA-15E:D, but
As of August 2012, this device has been marked by Micron for end-of-life. There are several

options that Micron offers for a replacement. ZedBoard will likely migrate to the
MT41K128M16JT-125 device, although this is pending validation. The DDR3 is connected to the
hard memory controller in the Processor Subsystem (PS) as outlined in the Zynq datasheet.

The multi-protocol DDR memory controller is configured for 32-bit wide accesses to a 5 12 MB
address space. The PS incorporates both the DDR controller and the associated PHY, including
its own set of dedicated I/Os. DDR3 memory interface speeds up to 533MHz (1066Mbs) are
supported.

The DDR3 uses 1.5V SSTL-compatible inputs. DDR3 Termination is utilized on the ZedBoard.
The Zynq-7000 AP SoC and DDR3 have been placed close together keeping traces short and
matched.

DDR3 on the PS was routed with 50 ohm targeted trace impedance for single-ended signals, and
DCI resistors (VRP/VRN) as well as differential clocks set to 80 ohms. Each DDR3 chip needs its
own 240-ohm pull-down on ZQ. The Xilinx Zynq-7000 All Programmable SoC PCB Design and
Pin Planning Guide (UG933) recommends using 40 ohm trace impedance for DDR3 single-ended
signals, so designers looking to duplicate the ZedBoard design may want consider this in their
own board design. See the appropriate ZedBoard Errata document for more details.

DDR-VDDQ is set to 1.5V to support the DDR3 devices selected. DDR-VTT is the termination
voltage which is ½ DDR-VDDQ. DDR-VREF is a separate buffered output that is equal to ½
nominal DDR-VDDQ. The DDR-VREF is isolated to provide a cleaner reference for the DDR
level transitions.

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Signal Name

Description

Zynq pin

DDR3 pin

Differential clock
output

Differential clock
output

DDR_CKE

Clock enable

V3

K9

DDR_CS_B

Chip select

P6

L2

RAS row address
select

RAS column address
select

DDR_WE_B

Write enable

R4

L3

DDR_BA[2:0]

Bank address

PS_DDR_BA[2:0]

BA[2:0]

DDR_A[14:0]

Address

PS_DDR_A[14:0]

A[14:0]

Output dynamic
termination

DDR_RESET_B

Reset

F3

T2

DDR_DQ[31:0]

I/O Data

PS_DDR_[31:0]

DDR3_DQ pins

DDR_DM[3:0]

Data mask

PS_DDR_DM[3:0]

LDM/UDM x2

I/O Differential data
strobe

I/O Differential data
strobe

I/O Used to calibrate
input termination

I/O Used to calibrate
input termination

I/O Reference
voltage

The PCB design guidelines outlined in Zynq datasheet must be followed for trace matching, etc.

Table 1 - DDR3 Connections

DDR_CK_P

DDR_CK_N

DDR_RAS_B

DDR_CAS_B

DDR_ODT

DDR_DQS_P[3:0]

DDR_DQS_N[3:0]

N4 J7

N5 K7

R5 J3

P3 K3

P5 K1

PS_DDR_DQS_P[3:0] UDQS/LDQS

PS_DDR_DQS_N[3:0] UDQS#/LDQS#

DDR_VRP

DDR_VRN

DDR_VREF[1:0]

For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read
data eye options in the PS Configuration Tool in Xilinx Platform Studio (XPS) or the IP Editor in
Vivado. Two entries allow for DQS to Clock Delay and Board Delay information to be specified for
each of the four byte lanes. The tools will calculate these board training details based upon
specific trace lengths for certain DDR3 signals.

The PCB lengths are contained in the ZedBoard PCB trace length reports. The DQS to CLK
Delay and Board Delay values are calculated specific to the ZedBoard memory interface PCB
design. The Xilinx tools allow for up to 4 memory devices to be configured for DDR3 4x8 flyby
topology. Note that ZedBoard is configured for DDR3 2x16 flyby routing topology. The first two
clock trace midpoint values (CLK0 and CLK1) are used to represent the Micron device electrically
furthest from the 7Z020 (IC25) and the second two clock trace midpoint values (CLK2 and CLK3)
are used to represent the Micron device electr ic al ly closest to the 7Z020 (IC26). The worksheet
calculation results are shown in the following table.

N7 N/A

M7 N/A

H7, P7 H1

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Pin Group

Length

Length

Package

Total

Propagation

Total

DQS to

Board

0.025

0.358

Table 2 - DDR3 Worksheet Calculations

(mm)

CLK0 55.77 2195.9 470 2665.9 160 0.427
CLK1 55.77 2195.9 470 2665.9 160 0.427
CLK2 41.43 1631.1 470 2101.1 160 0.336

CLK3 41.43 1631.1 470 2101.1 160 0.336
DQS0 51.00 2008.0 504 2512.0 160 0.402
DQS1 50.77 1998.8 495 2493.8 160 0.399
DQS2 41.59 1637.6 520 2157.6 160 0.345
DQS3 41.90 1649.4 835 2484.4 160 0.398

DQ[7:0] 50.63 1993.3 465 2458.3 160 0.393

DQ[15:8] 50.71 1996.4 480 2476.4 160 0.396
DQ[23:16] 40.89 1609.9 550 2159.9 160 0.346
DQ[31:24] 40.58 1597.8 780 2377.8 160 0.380

The DQS to CLK Delay fields in the PS7 DDR Configuration window should be populated using
the corresponding values from the previous table.

The configuration fields of the tool may not allow you to input a negative delay value, this is a
known problem with the 14.1 tools and scheduled for correction in the 14.2 tools release. In the
case of DQS2 and DQS3 fields for DQS to CLK Delay, simply enter a value of zero rather than
the negative delay values. This is an acceptable workaround since the calculated values are
relatively close to zero and the values provided in these fields are used as initial values for the
read/write training for DDR3. Keep in mind for LPDDR2 there is no write leveling, and for DDR2
there is no training whatsoever. In these memory use cases, the accuracy of the trace length info
is more important. This is covered in further detail in section 10.6.8 of the

UG585.

(mils)

Length
(mils)

Length
(mils)

Delay
(ps/inch)

Delay
(ns)

Xilinx Zynq TRM,

CLK
Delay
(ns)

0.028

-0.009

-0.061

Delay
(ns)

0.410

0.411

0.341

Figure 3 - DQS to Clock Delay Settings

The Board Delay fields in the PS7 DDR Configuration window should be populated using the
corresponding values from the table above.

Figure 4 - DDR3 Board Delay Settings

2.2.2 SPI Flash

The ZedBoard features a 4-bit SPI (quad-SPI) serial NOR flash. The Spansion S25FL256S is
used on this board. The Multi-I/O SPI Flash memory is used to provide non-volatile code, and
data storage. It can be used to initialize the PS subsystem as well as configure the PL
subsystem (bitstream). Spansion provides Spansion Flash File System (FFS) for use after
booting the Zynq-7000 AP SoC.

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Zynq Pin

MIO

QSPI Pin

DQ0

Data0

A2 (Bank MIO0/500)

5

DQ1

Data1

F6 (MIO Bank 0/500)

2

DQ2

Data2

E4 (MIO Bank 0/500)

3

DQ3

Data3

A3 (MIO Bank 0/500)

7

SCK

Serial Data Clock

A4 (MIO Bank 0/500)

6

CS

Chip Select

A1 (MIO Bank 0/500)

1

FB Clock

QSPI Feedback

E5 (MIO Bank 0/500)

8

N/C

The relevant device attributes are:

• 256Mbit

• x1, x2, and x4 support

• Speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz

o In Quad-SPI mode, this translates to 400Mbs

• Powered from 3.3V

The SPI Flash connects to the Zynq-7000 AP SoC supporting up to Quad-I/O SPI interface. This
requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the
Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is connected to
a 20K pull-up resistor to 3.3V. This allows a QSPI clock frequency greater than FQSPICLK2.

Note: Zynq only supports 24-bit addressing, however the full capacity of the 256Mb Flash can be
accessed via internal bank switching. As of now the S25FL256S is not supported in iMPACT.
Note: 14.x is required for in-direct QSPI Flash Programming.

Table 3 – QSPI Flash Pin Assignment and Definitions

Signal Name Description

1:6

Note: The QSPI data and clock pins are shared with the Boot Mode jumpers.

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Two packages can be used on the ZedBoard; SO-16 and WSON. For the WSON package,
there is a heat sink slug under the package that is not connec te d to an y signa l on the PCB.

Figure 5 - Overlying Packages for SPI Flash

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Signal

Name

MIO

Level Shift

Pin

SD Card

Pin

E14 (MIO Bank

1/501)

CMD

Command

C8 ((MIO Bank 1/501)

41

Pass-Thru

2

MIO Bank 1/501

D3: B9

Data Pins

1

B10 (MIO Bank

1/501)

D12 ((MIO Bank

1/501)

2.2.3 SD Card Interface

The Zynq PS SD/SDIO peripheral controls communication with the ZedBoard SD Card (A 4GB
Class 4 card is included in the ZedBoard kit.) The SD card can be used for non-volatile external
memory storage as well as booting the Zynq-7000 AP SoC. PS peripheral sd0 is connected
through Bank 1/501 MIO[40-47], including, Card Detect and Write Protect.

The SD Card is a 3.3V interface but is connected through MIO Bank 1/501 (1.8V). Therefore, a
TI TXS02612 level shifter performs this translation. The TXS02612 is a 2-port SDIO port
expander with level translation. ZedBoard only makes use of one of these parts. TI offered an
alternative TXS0206 device, but the 0.4mm pitch of that device’s packaging was too fine for our
manufacturer.

Based on the Zynq TRM, host mode is the only mode supported.
The ZedBoard SD Card is connected through a 9-pin standard SD card connector, J12, TE

2041021-1

Note: To use the SD Card, JP6 must be shorted.

. A Class 4 card or better is recommended.

27-Jan-2014

Table 4 – SD Card Pin Assignment and Definitions

Description Zynq Pin

CLK Clock

Data[3:0] Data

CD Card Detect

WP Write Protect

Figure 6 - SD Card Interface

40 Pass-Thru 5

D0: D8
D1: B11
D2: E13

10

42:45 Pass-Thru

47 Pass-Thru CD
46 Pass-Thru WP

7
8
9

MIO

TUSB1210

Pin

USB

Conn Pin

OTG_Data[8:0]

USB Data lines

MIO Bank 1/501

Data[7:0]

N/C

OTG_CLOCK

USB Clock

MIO Bank 1/501

26

N/C

OTG_DIR

ULPI DIR output signal

MIO Bank 1/501

31

N/C

OTG_STP

ULPI STP input signal

MIO Bank 1/501

29

N/C

OTG_NXT

ULPI NXT output signal

MIO Bank 1/501

2

N/C

OTG_CS

USB Chip Select

11

N/C

DP

DP pin of USB Connector

N/C

18 2 DM

DM pin of USB Connector

N/C

19

3

Identification pin of the

USB connector

OTG_RESET_B

Reset

MIO Bank 1/501

27

N/C

OTG_VBUS_OC

VBus Output Control

Bank 34

L16

TPS2051

2.3 USB

2.3.1 USB OTG

Warning: After the design of the ZedBoard was complete, a timing incompatibility

between the TUSB1210 PHY and Zynq was discovered. The TUSB1210 is not
recommended for new designs with Xilinx Zynq. Please refer to the ZedBoard Errata for
more details.

ZedBoard implements one of the two available PS USB OTG interfaces. An external PHY with
an 8-bit ULPI interface is required. A TI TUSB1210 Standalone USB Transceiver Chip is used as
the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to
480Mbs. This part is available in a 32-pin QFN package. VCCio for this device is 1.8V and
cannot be connected through level shifters. The PHY is connected to MIO Bank 1/501, which is
powered at 1.8V. Additionally the USB chip must clock the ULPI interface which requires an
oscillator. A Fox XPRESSO oscillator (767-26-31) is used on ZedBoard.

The external USB interface connects through a TE 1981584-1
The usb0 peripheral is used on the PS, connected through MIO[28-39] in MIO Bank 1/501.
This USB port will not power the board. However, ZedBoard provides 5V when in Host or OTG

modes. REFCLK pin of TUSB1210 is tied to ground as the Zynq-7000 AP SoC will drive the
CLOCK input of this part.

Table 5 - USB OTG Pin Assignment and Definitions

.

Signal Name Description Zynq Pin

28:39

ID

See the Jumper Settings section for configuring the USB interface for Host, Device and OTG
mode. The jumpers control the Vbus supply as well.

2.3.2 USB-to-UART Bridge

The ZedBoard implements a USB-to-UART bridge connected to a PS UART peripheral. A
Cypress CY7C64225 USB-to-UART Bridge device allows connection to a host computer. The
USB/UART device connects to the USB Micro B connector, J14, (TE 1981584-1) on the board.
Only basic TXD/RXD connection is implemented. If flow control is required this can be added
through Extended MIO on a PL-Pmod™.

Cypress provides royalty-free Virtual COM Port (VCP) drivers which permit the CY7C64225 USB­to-UART bridge to appear as a COM port to host computer communications application software
(for example, HyperTerm or Tera Term). Please refer to the CY7C64225 Setup Guide posted on
zedboard.org for detailed instructions for installing the driver.

N/C 23 4

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