DIGILENT DIG 410-383-5EV Instructions

10/19/2020 Genesys ZU Reference Manual [Digilent Documentation]

The black matte board you are holding in your hand is a prototyping and evaluation board
proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA
hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide
variety of expansion connectors making it a versatile computing platform.

There are two variants of the Genesys ZU mentioned in this Reference Manual: 3EG and
5EV. (The 5EV is not yet released.) These two variants are differentiated by the MPSoC
model and some peripherals. As compared to the 3EG, with the 5EV you get slightly faster
DDR4, more FPGA, a video codec, and GTH transceivers allowing HDMI Source, Sink
and SFP+ 10G.

Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it
straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC
and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login
and password are both “root”. The red button labeled “POR” always resets the MPSoC and
starts the boot process again.

Want to dive deep into development? Head over to our GitHub page

(https://github.com/Digilent) and use the repos there as a starting point. Check out our

Getting Started Guide (https://reference.digilentinc.com/reference/programmable-logic/genesys-

zu/getting-started) for a step-by-step. Build your own boot image on the SD card and boot it

like the OOB demo. Not enough? Connecting the JTAG-HS1/HS2 cable to header J28 will
allow for on-the-fly programming and debug using Xilinx Vivado and SDK.

The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC prototyping and development board. It is an advanced computing
platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals, upgrade-friendly
DDR4, Mini PCIe and microSD slots, multi-camera and high-speed expansion connectors are bound to support a wide number of use­cases. Furthermore, the Genesys ZU is available in two variants with different MPSoC options and additional features for even more
flexibility. Differences are highlighted* throughout this document.

The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor
cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort,

SFP+* and HDMI* . The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular
radio (WWAN), SSD, USB SuperSpeed and 4K video. The bundled microSD card includes an out-of-box demo that boots a Linux
image built in Petalinux and includes some test scripts for some of the peripherals.

Genesys ZU Reference Manual

TL;DR

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Feature group Sub-feature Genesys ZU -3EG Genesys ZU -5EV Zedboard

Processor APU Quad A53 Dual A9

RPU Dual R5 ✘

Main Memory DDR4, 4GB, 1866 MT/s,

upgradeable

DDR4, 4GB, 2133 MT/s,

upgradeable

DDR3, 512MB, 1066

MT/s, soldered

GPU ✔ ✘

Features

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Feature group Sub-feature Genesys ZU -3EG Genesys ZU -5EV Zedboard

Video Codec ✘ ✔ ✘

Programmable
logic

# of logic cells 154K 256K 85K

Peripheral
connectivity

USB Type-C 3.1 Gen1 Dual­Role Device

✔ ✘

MiniPCIe / mSATA dual
slot

Half-/Full-size ✘

USB 2.0 Host 2 x Type-A 1 x OTG

Network
connectivity

On-board Wi-Fi 2.4GHz ✘

Ethernet 1G w/ IEEE 1588 ✔ ✘ (w/o IEEE 1588)

WLAN / WWAN / LoRa option - MiniPCIe ✘

SFP+ 10G Ethernet ✘ ✔ ✘

Storage SD 104 MB ()/s 25 MB ()/s

SSD option - mSATA ✘

Flash ISSI 256 Mib SNOR 128 Mib

Multimedia DisplayPort 1.2a Dual-Lane ✘

Pcam 2 x Dual-Lane ✘

HDMI Source ✘ ✔ ✔

HDMI Sink ✘ ✔ ✘

Audio Codec ✔ ✔

Expansion Low speed - Pmod 4 x 5 x

Mid-speed - SYZYGY ✔ ✘

Mid-speed - FMC ✔ ✔

High-speed - FMC Gigabit ✘ ✔ ✘

User I/O LED (), Buttons, Switches ✔ ✔

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Figure I: Genesys ZU-3EG callout diagram

Callout with Description

Callout
# Description

Callout
# Description

Callout
# Description

1 6-pin PCIe power connector 13 Coin battery retainer 25 Type-C USB 3.1

2 External JTAG port 14 Pmod headers 26 Power switch

3 USB JTAG/UART port 15 Dual digital/analog Pmod 27 Zynq Ultrascale+, heat sink and

fan

4 USB 2.0 host connectors 16 User buttons 28 System Monitor header

5 Wi-Fi chip 17 User switches 29 SIM card slot (on the bottom

side)

6 4 GiB DDR4 SODIMM

module

18 Mini PCIe/mSATA slot

7 Audio jacks 19 User buttons

8 Boot mode select jumper 20 MIPI (Pcam) connectors

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Callout
# Description

Callout
# Description

Callout
# Description

9 Reset buttons 21 Wireless and SSD activity

LEDs

10 INIT, DONE, ERR and STS

Leds

22 MicroSD Card Slot

11 Zmod (SYZYGY) connector 23 Mini DisplayPort

12 FMC LPC connector 24 1G Ethernet port

Zynq UltraScale+ MPSoC platforms are well-suited to be embedded Linux targets, and the Genesys ZU is no exception. Digilent provides a
Petalinux project that was used to build the out-of-box image.

The Genesys ZU is fully compatible with Xilinx’s high-performance Vivado® Design Suite HL WebPACK™ Edition. This tool set melds
FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing
systems of any complexity, from a complete operating system running multiple server applications, down to a simple bare-metal program
that controls some LEDs. It is also possible to treat the MPSoC as a standalone FPGA for those not interested in using the processor in
their design. The two MPSoC parts the Genesys ZU is available with, XCZU3EG and XCZU5EV, are supported

(https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architecture) under Vivado's free WebPACK™ license, which means

the software is completely free to use, including the Logic Analyzer and High-level Synthesis (HLS) features. The Logic Analyzer assists with
debugging logic that is running in hardware, and the HLS tool allows C code to be directly compiled into HDL.

In the kit you will also find a free voucher for the Xilinx MIPI CSI-2 IP cores. Follow the instructions on the voucher slip to activate the
license. This is a temporary measure until Vivado 2020.1 hits, which should include a license for these IPs free of charge. See the next table
for IP-support status for other peripherals.

Table I: IP support status

Feature/Peripheral IP support Version

DDR4 memory
controller

PS hard-core, WebPACK built-in 2019.1

MIPI CSI-2/Pcam PL soft-core, MIPI CSI Controller Subsystems (https://www.xilinx.com/products/intellectual-

property/ef-di-mipi-csi-rx.html), bundled voucher

2019.1

DisplayPort controller PS hard-core, WebPACK built-in 2019.1

Ethernet 1G PS hard-core, WebPACK built-in 2019.1

USB 2.0/3.0 PS hard-core, WebPACK built-in 2019.1

PCIe Root/Mini PCIe PS hard-core, WebPACK built-in 2019.1

SATA/mSATA PS hard-core, WebPACK built-in 2019.1

On-board Wi-Fi/SPI
controller

PS hard-core, WebPACK built-in, open-source Linux driver (https://github.com/linux4wilc/driver) 2019.1

SFP+* PL soft-core, 10G/25G Ethernet Subsystem (https://www.xilinx.com/products/intellectual-

property/ef-di-25gemac.html), license required

2019.1

Software Support

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Feature/Peripheral IP support Version

HDMI 2.0

Source/Sink*

PL soft-core, HDMI Subsystem (https://www.xilinx.com/products/intellectual-property/hdmi.html),
license required

2019.1

Video PHY

Controller*

PL soft-core, WebPACK built-in, requires protocol-implementation like the HDMI Subsystem
above, supported by 5EV only

2019.1

The initial Vivado version supported by Digilent for Genesys ZU-related projects is 2019.1. Digilent currently does not provide hardware
platforms or examples for Xilinx's Vitis Unified Software Platform, however Vitis support is planned for the near future.

Design resources, example projects, and tutorials are available for download at the Genesys ZU Resource Center

(https://reference.digilentinc.com/reference/programmable-logic/genesys-zu/start).

Zynq UltraScale+ MPSoC is the Xilinx second-generation Zynq platform, combining a powerful processing system (PS) and user­programmable logic (PL) into the same device. The Zynq UltraScale+ Processing System core acts as a logic connection between the PS and
the Programmable Logic (PL) while assisting you to integrate customized and integrated IP cores with the processing system using the
Vivado IP integrator. As you may see in the picture below, the processing system features the Arm flagship Cortex -A53 64-bit quad-core
running up to 1.5GHz and Cortex-R5 dual-core real-time processor along with other interfaces such as: DDR Memory Controller, High­Connectivity, General Connectivity, System Functions etc. The Zynq UltraScale+ MPSoC Processing System wrapper instantiates the
processing system section of the Zynq UltraScale+ MPSoC for the programmable logic and external board logic. The wrapper includes
unaltered connectivity with the ones presented above.

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Figure II: Zynq UltraScale+ EG

The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user-created hardware accelerators and other
functions in the PL logic that are accessible to the processors. The interfaces between the processing system and programmable logic mainly
consist of three main groups: the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups. Besides those,
there are up to 78 Multiplexed I/O (MIO) ports available from the processing system. The 78 MIO signals are divided into three banks, and
each bank includes 26 device pins. Each bank (500, 501, and 502) has its own power pins for the hardware interface.

MIO 0-25 : Bank 500

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Zynq UltraScale+ MPSoC Architecture

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MIO
500 3.3
V

Peripherals

Pin QSPI Mini PCIe /

SATA

DDR4
SODIMM

MIO
Buttons

WI-FI UART MIO

LED
()

I

0 QSPI_SCLK0OUT

1 QSPI_D1

2 QSPI_D2

3 QSPI_D3

4 QSPI_D0

5 QSPI_SS_OUTN

6(N/C)

7 PCIE_PERSTN

8 DDR_SCL

9 DDR_SDA

10 BTN1

11 BTN0

12 WIFI_PORTEX_SCK

13

14

15 WIFI_SSN

16 WIFI_PORTEX_MISO

()

17 WIFI_PORTEX_MOSI

()

18 UART_TXD_IN

19 UART_RXD_OUT

20 PCIE_WAKEN

21 LD0

22 M

23 M

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Note: The WI-FI signals are shared by the same bus that goes through the I/O expander.

MIO 26-51 : Bank 501

MIO 501 1.8V Peripherals

Pin Ethernet SD

26 ETH_TX_CLK

27 ETH_TX_D0

28 ETH_TX_D1

29 ETH_TX_D2

30 ETH_TX_D3

31 ETH_TX_CTL

32 ETH_RX_CLK

33 ETH_RX_D0

34 ETH_RX_D1

35 ETH_RX_D2

36 ETH_RX_D3

37 ETH_RX_CTL

38 ETH_INTN_PWDNN

39 SDIO_SEL

40 SDIO_DIR_CMD

41 SDIO_DIR_DAT0

42 SDIO_DIR_DAT1_3

43 SDIO_POW_EN

44 ETH_RSTN

45 SDIO_CDN

46 SDIO_R_DAT0

47 SDIO_R_DAT1

24

25

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