Digilent DDR-2 User Manual
Opus Card – DDR-2 Interface
Reference Manual
Revision Name Date
0.02 Rick Hoover August 21, 2009
0.03 Rick Hoover – Added support for burst reads and writes September 30, 2009
0.04 Rick Hoover – Made corrections to Bus2IP_RdReq that
match ChipScope traces. Basically Bus2IP_RdReq is
active for only one clock on non-burst reads and is active
one additional clock past the de-assertion of Bus2IP_CS
for burst reads.
0.10 Rick Hoover – Added support for burst of eight quadwords. This is required for DMA accesses. Also added
configuration register for resetting the Ethernet PHY and to
control burst accesses via software.
1.00 Rick Hoover – Released December 3, 2010
Copyright © 2009-2010 by Computer Measurement Laboratory, LLC
October 6, 2009
November 16, 2009
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Reference Manual
Table of Contents
1. INTRODUCTION ..................................................................................................................................................3
1.1 DEBUG REGISTERS ACCESSIBLE BY THE CPU .....................................................................................................3
1.2 CONFIGURATION REGISTER ACCESSIBLE BY THE CPU........................................................................................3
1.3 ENDIANNESS........................................................................................................................................................3
1.4 DDR-2 MEMORY ACCESSIBLE BY THE CPU .......................................................................................................4
2. STATE MACHINE FOR WRITING DATA TO MEMORY.............................................................................5
2.1 SIGNAL DEFINITIONS...........................................................................................................................................5
2.2 WRITE STATE MACHINE......................................................................................................................................6
2.3 WAVEFORMS .......................................................................................................................................................7
2.3.1 Non-burst, 32-bit Memory Write .................................................................................................................7
2.3.2 Non-burst, 64-bit Memory Write .................................................................................................................8
2.3.3 Burst Memory Write - Four 32-bit Words ...................................................................................................9
2.3.4 Burst Memory Write - Eight 32-bit Words.................................................................................................10
2.3.5 Burst Memory Write – Two 64-bit Words..................................................................................................11
2.3.6 Burst Memory Write - Four 64-bit Words .................................................................................................12
3. STATE MACHINES FOR READING DATA FROM MEMORY..................................................................13
3.1 SIGNAL DEFINITIONS.........................................................................................................................................13
3.2 READ STATE MACHINE .....................................................................................................................................14
3.2 READ FIFO STATE MACHINE ............................................................................................................................15
3.3 WAVEFORMS .....................................................................................................................................................16
3.3.1 Non-burst, 32-bit Memory Read Clock-Aligned ........................................................................................16
3.3.2 Non-burst, 32-bit Memory Read not Clock-Aligned ..................................................................................17
3.3.3 Non-burst, 64-bit Memory Read................................................................................................................18
3.3.4 Burst Memory Read - Four 32-bit Words..................................................................................................19
3.3.5 Burst Memory Read - Eight 32-bit Words .................................................................................................20
3.3.6 Burst Memory Read - Two 64-bit Words ...................................................................................................21
3.3.7 Burst Memory Read - Four 64-bit Words..................................................................................................22
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Reference Manual
1. Introduction
This document provides the details on how DDR-2 memory on the Opus card is connected into
the PLB bus contained in the Xilinx Virtex-5 FPGA using the Embedded Design Kit (EDK).
The CML team discovered that the default Multi-Port Memory Controller (MPMC) provided
with the EDK had problems which reduced the reliability of accessing the DDR-2 memory
contained on the Opus card.
For additional details on many of the registers described here, see document DS562 from Xilinx.
This Xilinx document is titled “PLBV46 Slave Burst”. In addition, there are further details on
the DDR-2 memory controller generated using Xilinx MIG in document UG086 that is titled
“Memory Interface Solutions User Guide”.
1.1 Debug Registers Accessible by the CPU
There are several debug registers that can be read via the CPU to determine the calibrated state
of the DDR-2 PHY. These registers are detailed below:
• 0x84800000 – DQ IODELAY settings for bits 3 downto 0
• 0x84800004 – DQ IODELAY settings for bits 7 downto 4
• 0x84800008 – DQ IODELAY settings for bits 11 downto 8
• 0x8480000C – DQ IODELAY settings for bits 15 downto 12
• 0x84800010 – DQ IODELAY settings for bits 19 downto 16
• 0x84800014 – DQ IODELAY settings for bits 23 downto 20
• 0x84800018 – DQ IODELAY settings for bits 27 downto 24
• 0x8480001C – DQ IODELAY settings for bits 31 downto 28
• 0x84800020 – DQS IODELAY settings
• 0x84800024 – Gate Tap IODELAY settings
• 0x84800028 – Read Data Enable (RDEn) delay and Data Select IODELAY settings
• 0x8480002C – Gate delay settings
1.2 Configuration Register Accessible by the CPU
There is one configuration register that can be set via the CPU. This configuration register
controls the reset of the external Ethernet PHY and memory burst accesses. In big endian
format, bit 30 resets the Ethernet PHY when set to ‘1’ and bit 31 enables burst mode when set to
‘1’. Besides a hardware reset, the only way to clear these bits is by a write to the configuration
register. So, it is important to clear bit 30 by a write to the configuration register after the
required 100uS have elapsed to bring the Ethernet PHY out of reset mode.
1.3 Endianness
The PLB slave assumes a big endian interface to memory. Therefore, memory is organized in a
big endian fashion where byte 0 is in bits 0 to 7, byte 1 is in bits 8 to 15 and so forth where bit 0
is the most significant bit in a word.
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Reference Manual
1.4 DDR-2 Memory Accessible by the CPU
The DDR-2 memory is 128 MBytes in size, organized as 32-bit words. The memory is
accessible from 0x88000000 to 0x8FFFFFFF.
The C_CACHLINE_ADDR_MODE for the PLB interface in the DDR-2 memory controller
MUST be set to 1 so that cache line bursts always start at the first address in the cache line. A
setting of 0, which is the default, will not work with the current implementation of the DDR-2
memory controller.
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2. State Machine for Writing Data to Memory
This chapter covers the state machine that controls the writing of data sent via the PLB bus to the
DDR-2 Memory Controller. The write state machine supports both non-burst writes and burst
writes. Burst writes are limited to a multiple of four 32-bit words or a multiple of two 64-bit
words depending on the width of the PLB data bus and should be limited to a maximum length
of eight quad-words (128 bytes). Each burst is assumed to have consecutive addresses starting
with an address masked by 0xFFFFFFF0. Burst writes also assume that all bytes in the burst are
to be written (i.e. bus2IP_BE is all 1’s).
2.1 Signal Definitions
The table below provides details on the signals used for writing data to memory.
Name I/O Description
Bus2IP_Clk I The clock for the PLB bus (currently 100 MHz)
DDR2_Clk I The clock for the DDR-2 memory (currently 200 MHz)
Bus2IP_Reset I Reset signal for the block
App_AF_AFull I Indicates the DDR-2 address buffer is full – not currently used
App_WDF_AFull I Indicates the DDR-2 data buffer is full – not currently used
Bus2IP_Addr I Address of memory to write to
Bus2IP_CS I Indicates the DDR-2 memory is being accessed
Bus2IP_Burst I Indicates a burst read or write is occurring
Bus2IP_RNW I Indicates a write access when low
Bus2IP_WrReq I Indicates a write request
Bus2IP_BE I Indicates bytes to write to (big endian format)
Bus2IP_Data I Data to be written to memory
Rd_Send_Ack I Indicates the read from the PLB slave should be acknowledged
on the next clock cycle.
Rd_Send_Cmd I Indicates the read command and address should be sent to the
DDR-2 memory controller on the next clock cycle.
App_AF_WREn O Causes a write to the DDR-2 address buffer on the rising edge
of DDR2_Clk
App_WDF_WREn O Causes a write to the DDR-2 data buffer on the rising edge of
DDR2_Clk – must write enough data for four consecutive
addresses
App_AF_Cmd O The command to be written to the DDR-2 controller (a Write
command)
App_AF_Addr O The first address that is written to in the DDR-2 memory
App_WDF_Data O The data to be written to the DDR-2 memory
App_WDF_Mask_Data O The mask for the data being writing to the DDR-2 controller
(big endian format)
IP2Bus_RdAck O Acknowledges that the read to memory has occurred
IP2Bus_WrAck O Acknowledges that the write to memory has occurred
IP2Bus_AddrAck O Acknowledges that the address to write to has been latched
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2.2 Write State Machine
The write state machine currently has ten states to support the writing of data to memory.
Transitions from one state to the next occur on the rising edge of DDR2_Clk and the state
machine is synchronously reset to Idle when Bus2IP_Reset is ‘1’. Each state is described below:
State Description
Idle Waiting for a write from the PLB slave. A write is detected when Bus2IP_CS is
‘1’, Bus2IP_RNW is ‘0’, App_AF_AFull is ‘0’, and App_WDF_Afull is ‘0’.
The state machine transitions to Wait_Wr_Req on the next clock when these
conditions are met.
This state is also used to pass through needed commands from the read_ctrl
entitiy. The read_ctrl entity generates the Rd_Send_Ack and Rd_Send_Cmd
signals that are used to control the App_AF_Cmd, App_AF_Addr,
App_AF_WREn, IP2Bus_AddrAck, and IP2Bus_RdAck outputs when in this
state.
Wait_Wr_Req Waiting for Bus2IP_WrReq to transition to ‘1’ to indicate the data to be written
to memory is valid. The state machine transitions to the next state when
Bus2IP_WrReq is ‘1’. The next state is Wr_Word1 if Bus2IP_Burst is ‘0’.
Otherwise the next state is Save_W1.
Save_W1 Save word 1 of burst write. The next state is Wr_Word1 when the PLB slave is
configured for 64-bit data width. Otherwise the next state is Save_W2.
Save_W2 Save word 2 of burst write (32-bit PLB bus only). When Bus2IP_Clk is ‘0’, the
next state is set to Save_W3.
Save_W3 Save word 3 of burst write (32-bit PLB bus only). ). When Bus2IP_Clk is ‘0’,
the next state is set to Wr_Brst1.
Wr_Brst1 Write word 1 of burst to DDR-2. The next state is Wr_Brst2.
Wr_Brst2 Write word 2 of burst to DDR-2. The next state is Wr_BrstD.
Wr_BrstD Delay after burst write to DDR-2. The next state is Save_W1 if the burst write
is not complete (Bus2IP_Burst = ‘1’ and Bus2IP_CS = ‘1’). Otherwise the next
state is Idle.
Wr_Word1 State that writes the low order 64-bit word to memory. The state machine
transitions to Wr_Word2 on the next clock.
Wr_Word2 State that writes the high order 64-bit word to memory. The state machine
transitions to Idle on the next clock.
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Reference Manual
2.3 Waveforms
2.3.1 Non-burst, 32-bit Memory Write
The diagram below is for a non-burst memory write to a single 32-bit word. The Bus2IP_BE bus
is used to determine which bytes to write in the 32-bit word. The use of the Bus2IP_BE bus
enables the hardware controlling the PLB slave to also write eight or sixteen bit values to a 32bit memory location.
1 2 3 4 5 6 7 8 9 10 11
DDR2_ Clk
Bus2IP_Clk
Bus2IP_CS
Bus2IP_RNW
Bus2IP_Addr
Bus2IP_BE
Bus2IP_WrReq
Bus2IP_Data
IP2Bus_AddrAck
IP2Bus_WrAck
App_AF_WREn
App_AF_Cmd
App_AF_Addr
App_WDF_WREn
App_WDF_Data
App_WDF_Mask_Data
Stat e
Addre ss
Byte Enab les
32-bi t Data
Wr i t e
Address
Wo r d 1 Wo r d 2
Mask1 Mask2
Idle Wait_WrReq Wr_Word1 Wr_Word2 Idle
TimeGen
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