Digilent D2-SB User Manual
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June 4, 2004 246 East Main | Pullman, WA 99163
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www.digilentinc.com
(509) 334 6306 Voice and Fax
Overview
The Digilent D2-SB circuit board provides a
complete circuit development platform
centered on a Xilinx Spartan 2E FPGA. D2-SB
features include:
• A Xilinx XC2S200E-200 FPGA with 200K
gates and 350MHz operation;
• 143 user I/Os routed to six standard 40pin expansion connectors;
• A socket for a JTAG-programmable
18V02 configuration Flash ROM;
• Dual on-board 1.5A power regulators
(1.8V and 3.3V);
• An SMD 50MHz oscillator, and a socket
for a second oscillator;
• A JTAG programming port;
• A status LED and pushbutton for basic
I/O.
The D2-SB has been designed to work
seamlessly with all versions of the Xilinx ISE
CAD tools, including the free WebPack tools
available from the Xilinx website. A growing
collection of low-cost expansion boards can be
used with the D2-SB to add analog and digital
I/O capabilities, as well as various data ports
like Ethernet and USB. The D2-SB board ships
with a power supply and programming cable,
so designs can be implemented immediately
without the need for any additional hardware.
Functional Description
The Digilab D2-SB provides a minimal system
that can be used to rapidly implement FPGAbased circuits, or to gain exposure to Xilinx
CAD tools and Spartan 2E devices. The D2-SB
provides only the essential supporting devices
for the Spartan 2E FPGA, including clock
sources and power supplies. All available I/O
signals are routed to standard expansion
Power
jack
5-9VDC
1.8VDC
regulator
3.3VDC
regulator
Clock
(50MHz)
ND
2
Clock
Push
button
LED
Config
ROM
JTAG
Xilinx Spartan2E XC2S200E-PQ208
Expansion Connectors
JTAG
MA1 bus
System Bus
A1
B1
MB1 bus
MC1 bus
C1
PA bus
MA2 bus
A2 B2 C2
PB bus
MC2 bus
Figure 1. D2-SB Circuit Board Block Diagram
connectors that mate with 40-pin, 100 mil
spaced DIP headers available from any
catalog distributor. A pushbutton and LED are
also included for basic I/O. (See Figure 1)
The D2-SB board has been designed to serve
primarily as a host for peripheral boards. Each
of the six expansion connectors provides the
unregulated supply voltage (VU), 3.3V, GND,
and 32 FPGA I/O signals. Because there are
more connector pins than FPGA pins, the A1,
B1 and C1 connectors share an 18-pin “system
bus”, and not all pins on the B expansion
connectors are used. JTAG signals are also
routed to the A1, B1, and C1 expansion
connectors. This allows peripheral boards to
drive the scan chain, or to be configured along
with the Spartan 2E FPGA.
Application-specific peripheral boards can be
created to mate with the D2-SB, or readymade peripheral boards that offer many
PC bus
Copyright Digilent, Inc. All rights reserved 7 pages Doc: 502-023
D2-SB Reference Manual Digilent, Inc.
standard functions can be obtained from
Digilent (see www.digilentinc.com).
JTAG Ports and Device Configuration
The Spartan 2E FPGA , the 18V00 ROM on
the D2-SB, and any programmable devices on
peripheral boards attached to the D2-SB can
be programmed via the JTAG port. The JTAG
scan chain is routed to the FPGA and ROM on
the D2-SB and then around the board to four
connection ports as shown in Figure 2. The
primary configuration port (Port 1) uses a
standard 6-pin JTAG header (J7) that can
accommodate Digilent’s JTAG3 cable (or
cables from Xilinx or other vendors). The other
three JTAG programming ports are available
on the A1, B1, and C1 expansion connectors,
and these ports are bi-directional. If no
peripheral board is present, a buffer on the D2SB removes the expansion connector from the
JTAG chain. If a peripheral board with a JTAG
device is attached, the scan chain is driven out
the expansion connector so that any JTAGprogrammable parts can be configured. If a
Digilent port module is connected to one of the
three JTAG-enabled expansion connectors,
then the port module can drive the JTAG chain
to program all devices in the scan chain (port
modules include Ethernet, USB, EPP parallel,
and serial modules -- see www.digilentinc.com
for more information).
The scan chain can be driven from the primary
port by powering on the D2-SB, connecting it
to a PC with a JTAG programming cable, and
running the “auto-detect” feature of the
configuration software. The configuration
software allows devices in the scan chain to be
selectively programmed with any available
configuration file. If no programming ROM is
loaded in the IC5 socket (or if ROM is present
but is not to be included in the scan chain),
jumper-shunts must be loaded at JP1 and JP2
in the “Bypass ROM” location to route the
JTAG chain around the ROM socket. If an
18V02 (or larger) ROM is loaded in the IC5
socket, it can be included in the scan chain by
loading the JP1 and JP2 jumper-shunts in the
“Include ROM” positions.
If a programming ROM is present in the IC5
socket, the FPGA will automatically access the
ROM for configuration data if jumper shunts
are loaded in all three positions of J8 (M2, M1,
and M0).
Port modules attached to ports A1, B1, or C1
can drive the scan chain if a jumper-shunt is
installed on the primary JTAG header across
the TDI and TDO pins. In their default state,
Digilent port modules will appear as a JTAG
cable to the configuration software. Port
modules can disable their JTAG drivers; if
more than one JTAG driver is enabled on the
scan chain, programming may fail.
Port 2
ROM bypass
jumpers
JTAG
connector
Cable bypass
jumper
Programming
mode select
jumpers
A1
18V
ROM
Port 1
C2
A2
Spartan 2E
PQ 208
C1
Port 4
B1 B2
Port 3
Figure 2. JTAG Signal Routing on D2-SB
Power Supplies
The D2-SB board uses two LM317 voltage
regulators to produce a 1.8VDC supply for the
Spartan 2E core, and 3.3VDC supply for the
I/O ring. Both regulators have good bypass
capacitance, allowing them to supply up to
1.5A of current with less than 50mV of noise
(typical). Power can be supplied from a lowcost wall transformer supply. The external
supply must use a 2.1mm center-positive
connector, and it must produce between 6VDC
and 12VDC of unregulated voltage.
The D2-SB uses a four layer PCB, with the
inner layers dedicated to VCC and GND
planes. Most of the VCC plane is at 3.3V, with
an island under the FPGA at 1.8V. The FPGA
and the other ICs on the board all have
0.047uF bypass capacitors placed as close as
possible to each VCC pin.
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D2-SB Reference Manual Digilent, Inc.
Total board current is dependant on FPGA
configuration, clock frequency, and external
connections. In test circuits with roughly 50K
gates routed, a 50MHz clock source, and a
single expansion board attached (the DIO5
board), approximately 200mA +/- 30% of
supply current is drawn from the 1.8V supply,
and approximately 200mA +/- 50% is drawn
from the 3.3V supply. These currents are
strongly dependent on FPGA and peripheral
board configurations.
All FPGA I/O signals use the VCCO voltage
derived from the 3.3V supply. If other VCCO
voltages are required, the regulator output can
be modified by changing R12 according to:
VCCO = 1.25(1 + R12/R11).
Refer to the LM317 data sheet and D2-SB
schematic for further information.
Oscillators
The D2-SB provides a 50MHz SMD primary
oscillator and a socket for a second oscillator.
The primary oscillator is connected to the
GLK2 input of the Spartan 2E (pin 182), and
the secondary oscillator is connected to
GCLK3 (pin 185). Both clock inputs can drive
the DLL on the Spartan 2E, allowing for
internal frequencies up to four times higher
than the external clock signals. Any 3.3V
oscillator in a half-size DIP package can be
loaded into the secondary oscillator socket.
Pushbutton and LED
A single pushbutton and LED are provided on
the board allowing basic status and control
functions to be implemented without a
peripheral board. As examples, the LED can
be illuminated from a signal in the FPGA to
verify that configuration has been successful,
and the pushbutton can be used to provide a
basic reset function independent of other
inputs. The circuits are shown in Figure 2.
Vdd
Push
button
4.7K
4.7K
80 Ohm
Pin 187
Xilinx
Spartan 2E
PQ208
Pin 154
Figure 2. Pushbutton and LED Circuit
Expansion Connectors
The six expansion connectors labeled A1-A2,
B1-B2, and C1-C2 use 2x20 right-angle
headers with100 mil spacing. All six
connectors have GND on pin 1, VU on pin 2,
and 3.3V on pin 3. Pins 4-35 route to FPGA I/O
signals, and pins 36-40 are reserved for JTAG
and/or clock signals. (See Figure 4.)
The expansion headers provide 192 signal
connections, but the Spartan 2E-PQ208 has
only 143 available I/O signals. Thus, some
FPGA signals are routed to more than one
connector. In particular, the lower 18 pins (pins
4-21) of the A1, B1, and C1 connectors are all
connected to the same 18 FPGA pins, and
they are designated as the “system bus” (a
unique chip select signal is routed to each
connector). Other than these 18 shared
signals, all remaining FPGA signals are routed
to individual expansion connector positions.
The lower 18 pins of the A2, B2, and C2
connectors are designated as “peripheral
busses”, and each of these busses (named
PA, PB, and PC) use 18 unique signals.
The 14 upper pins of each expansion
connector (pins 22-35) have been designated
as “module busses”. The A1, A2, C1, and C2
connectors each have fully populated module
busses (named MA1, MA2, MC1, and MC2).
Insufficient FPGA pins were available to route
full module buses to the B connectors; only the
8 data pins of MB1 are routed, and no pins are
routed to the upper B2 expansion connector
(i.e., MB2 is a “no connect”).
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