Digilent D2-FT User Manual
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December 6, 2004 246 East Main | Pullman, WA 99163
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www.digilentinc.com
(509) 334 6306 Voice and Fax
Overview
The Digilent D2-FT circuit board provides the
basis for a complete circuit development
platform centered on a Xilinx Spartan 2E
FPGA. D2-FT features include:
• A Xilinx XC2S300E FPGA with 300K
gates and 350MHz operation (also
available with the XC2S400E FPGA);
• 172 user I/Os routed to six standard 40pin expansion connectors;
• A socket for a JTAG-programmable
18V02 configuration Flash ROM;
• Dual on-board 1.5A power regulators
(1.8V and 3.3V);
• An SMD 50MHz oscillator, and a socket
for a second oscillator;
• A JTAG programming port;
• A status LED and pushbutton for basic
I/O.
The D2-FT has been designed to work with all
versions of the Xilinx ISE CAD tools, including
the free WebPack tools available at Xilinx web
site. (www.xilinx.com
) A growing collection of
low-cost expansion boards can be used with
the D2-FT to add analog and digital I/O
capabilities, as well as various data ports like
Ethernet and USB. The D2-FT board ships
with a power supply and programming cable,
so designs can be implemented immediately
without the need for any additional hardware.
Functional Description
The Digilab D2-FT provides a minimal system
that can be used to rapidly implement FPGAbased circuits, or to gain exposure to Xilinx
CAD tools and Spartan 2E devices. The D2-FT
provides only the essential supporting devices
for the Spartan 2E FPGA, including clock
sources and power supplies. All available I/O
signals are routed to standard expansion
© Digilent, Inc. 7 pages Doc: 502-036
PA bus
ND
2
Clock
MB2 bus
Push
button
PB bus
Status
Configuration
LED
(flash) ROM
JTAG
PC1 bus
MC1 bus
C1 C2
JTAG
MC2 bus
Power
jack
5-9VDC
1.8VDC
regulator
3.3VDC
regulator
Xilinx Spartan2E XC2S300E-FT256
JTAG
MA1 bus
System Bus
A1 B2
MB1 bus
B1
Clock
(50MHz)
Expansion Connectors
MA2 bus
A2
Figure 1. D2-FT Circuit Board Block Diagram
connectors that mate with 40-pin, 100 mil
spaced DIP headers available from any
catalog distributor. A pushbutton and LED are
also included for basic I/O.
The D2-FT board has been designed to serve
primarily as a host for peripheral boards. Each
of the six expansion connectors provides the
unregulated supply voltage (VU), 3.3V, GND,
and 32 I/O signals from the FPGA. Because
there are more connector pins than FPGA
pins, the A1 and B1 connectors share an 18pin bus. All other connector positions are
driven by individual FPGA signals. JTAG
signals are also routed to the A1, B1, and C1
expansion connectors. This allows peripheral
boards to drive the scan chain, or to be
configured along with the Spartan 2E FPGA.
Application-specific peripheral boards can be
created to mate with the D2-FT, or ready-made
peripheral boards that offer many standard I/O
and data port functions can be obtained from
Digilent (for a current listing of available
boards, see www.digilentinc.com).
PC2 bus
D2-FT Reference Manual Digilent, Inc.
JTAG Scan Chain and Device Configuration
The Spartan 2E FPGA, the 18V00 ROM on the
D2-FT, and any programmable devices on
peripheral boards attached to the D2-FT can
be programmed via their JTAG ports. The
JTAG scan chain is routed to the FPGA, the
ROM, and around the board to four connection
ports as shown in Figure 2 below. The primary
configuration port (Port 1) uses a standard 6pin JTAG header (J7) that can accommodate
Digilent’s JTAG3 cable (or cables from Xilinx or
other vendors). The other three JTAG
programming ports are bi-directional, and they
are available on the A1, B1, and C1 expansion
connectors. If no peripheral board is present, a
buffer on the D2-FT removes the expansion
connector from the JTAG chain. If a peripheral
board with a JTAG device is attached, the scan
chain is driven out the expansion connector so
that any JTAG-programmable parts can be
configured. If a Digilent port module is
connected to one of the three JTAG-enabled
expansion connectors, then the port module
can drive the JTAG chain to program all
devices in the scan chain (port modules
include Ethernet, USB, EPP parallel, and serial
modules -- see www.digilentinc.com
for more
information).
The scan chain can be driven from the primary
port by powering on the D2-FT, connecting it to
a PC with a JTAG programming cable, and
running the “auto-detect” feature of the
configuration software. The configuration
software allows devices in the scan chain to be
selectively programmed with any available
configuration file. If no programming ROM is
loaded in the IC5 socket (or if ROM is present
but is not to be included in the scan chain),
jumper-shunts must be loaded at JP1 and JP2
in the “Bypass ROM” location to route the
JTAG chain around the ROM socket. If an
18V02 (or larger) ROM is loaded in the IC5
socket, it can be included in the scan chain by
loading the JP1 and JP2 jumper-shunts in the
“Include ROM” positions.
If a programming ROM is present in the IC5
socket, the FPGA will automatically access the
ROM for configuration data if jumper shunts
are loaded in all three positions of J8 (M2, M1,
and M0).
Port modules attached to ports A1, B1, or C1
can drive the scan chain if a jumper-shunt is
installed on the primary JTAG header across
the TDI and TDO pins. In their default state,
Digilent port modules will appear as a JTAG
cable to the configuration software. Port
modules can disable their JTAG drivers; if
more than one JTAG driver is enabled on the
scan chain, programming may fail.
Port 2
ROM bypass
jumpers
JTAG
connector
Cable bypass
jumper
Programming
mode select
jumpers
A1
18V
ROM
Port 1
C2
A2
B1 B2
Spartan 2E
FT 256
C1
Port 4
Figure 2. JTAG Signal Routing on D2-FT
Power Supplies
The D2-FT board uses two LM317 voltage
regulators to produce a 1.8VDC supply for the
Spartan 2E core, and 3.3VDC supply for the
I/O ring. Both regulators have good bypass
capacitance, allowing them to supply up to
1.5A of current with less than 50mV of noise
(typical). Power can be supplied from a lowcost wall transformer supply. The external
supply must use a 2.1mm center-positive
connector, and it must produce between 6VDC
and 12VDC of unregulated voltage.
The D2-FT uses a four layer PCB, with the
inner layers dedicated to VCC and GND
planes. Most of the VCC plane is at 3.3V, with
an island under the FPGA at 1.8V. The FPGA
and the other ICs on the board all have
0.047uF bypass capacitors placed as close as
possible to each VCC pin.
Port 3
www.digilentinc.com © Digilent, Inc. Page 2
D2-FT Reference Manual Digilent, Inc.
Total board current is dependant on FPGA
configuration, clock frequency, and external
connections. In test circuits with roughly 50K
gates routed, a 50MHz clock source, and a
single expansion board attached (the DIO5
board), approximately 200mA +/- 30% of
supply current is drawn from the 1.8V supply,
and approximately 200mA +/- 50% is drawn
from the 3.3V supply. These currents are
strongly dependent on FPGA and peripheral
board configurations.
All FPGA I/O signals use the VCCO voltage
derived from the 3.3V supply. If other VCCO
voltages are required, the regulator output can
be modified by changing R12 according to:
VCCO = 1.25(1 + R12/R11).
Refer to the LM317 data sheet and D2-FT
schematic for further information.
Oscillators
The D2-FT provides a 50MHz SMD primary
oscillator and a socket for a second oscillator.
The primary oscillator is connected to the
GLK2 input of the Spartan 2E (pin B8), and the
secondary oscillator is connected to GCLK3
(pin C8). Both clock inputs can drive the DLL
on the Spartan 2E, allowing for internal
frequencies up to four times higher than the
external clock signals. Any 3.3V oscillator in a
half-size DIP package can be loaded into the
secondary oscillator socket.
Pushbutton and LED
A single pushbutton and LED are provided on
the board allowing basic status and control
functions to be implemented without a
peripheral board. As examples, the LED can
be illuminated from a signal in the FPGA to
verify that configuration has been successful,
and the pushbutton can be used to provide a
basic reset function independent of other
inputs. The circuits are shown in Figure 3.
Vdd
Push
button
4.7K
4.7K
80 Ohm
Pin A12
Xilinx
Spartan 2E
FT 256
Pin C15
Figure 3. LED and Pushbutton Circuit
Expansion Connectors
The six expansion connectors labeled A1-A2,
B1-B2, and C1-C2 use 2x20 right-angle
headers with100 mil spacing. All six
connectors have GND on pin 1, VU on pin 2,
and 3.3V on pin 3. Pins 4-35 route to FPGA I/O
signals, and pins 36-40 are reserved for JTAG
and/or clock signals. (See Figure 4)
The expansion headers provide 192 signal
connections, and the Spartan 2E-FT256 has
172 available I/O signals. Thus, some FPGA
signals are routed to more than one connector.
The lower 18 pins (pins 4-21) of the A1and B1
connectors are connected to the same 18
FPGA pins, and they are designated as the
“system bus” (a unique chip select signal is
routed to each connector). Other than these 18
shared signals, all remaining FPGA signals are
routed to individual expansion connector
positions.
The lower 18 pins of the A2, B2, and C2
connectors are designated as “peripheral
busses”, and each of these busses (named
PA, PB, and PC) use 18 unique signals. The
14 upper pins of each expansion connector
(pins 22-35) have been designated as “module
busses”. Each connector has a fully populated
module bus (named MA1, MA2, MB1, MB2,
MC1, and MC2).
System Bus
The “system bus” is a protocol used by certain
expansion boards that mimics a simple 8-bit
microprocessor bus. It uses eight data lines,
six address lines, a write-enable (WE) strobe
that can be used by the peripheral to latch
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