Digilent Atlys Reference Manual

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Overview

The Atlys circuit board is a complete, ready­to-use digital circuit development platform
based on a Xilinx Spartan-6 LX45 FPGA.
The large FPGA and collection of high-end
peripherals like Gbit Ethernet, HDMI Video,
128MByte 16-bit DDR2 memory, and USB
and audio ports make the Atlys board an
ideal host for a wide range of digital systems,
including embedded processor designs
based on Xilinx’s MicroBlaze. Atlys is
compatible with all Xilinx CAD tools, including
ChipScope, EDK, and the free WebPack, so
designs can be completed with no extra
costs.

The Spartan-6 LX45 is optimized for high­performance logic, and offers:

• 6,822 slices each containing four 6­input LUTs and eight flip-flops

• 2.1Mbits of fast block RAM

• four clock tiles (eight DCMs & four

PLLs)

• six phased-locked loops

• 58 DSP slices

• 500MHz+ clock speeds

The Atlys board includes Digilent's newest
Adept USB2 system, which offers device
programming, real-time power supply
monitoring, automated board tests, virtual
I/O, and simplified user-data transfer
facilities.

A comprehensive collection of board support
IP and reference designs, and a large
collection of add-on boards are available on
the Digilent website. Please see the Atlys
page at www.digilentinc.com for more
information.

1300 Henley Court | Pullman, WA 99163

[phone] Voice and Fax

• Xilinx Spartan-6 LX45 FPGA, 324-pin BGA package

• 128Mbyte DDR2 with 16-bit wide data

• 10/100/1000 Ethernet PHY

• on-board USB2 ports for programming & data xfer

• USB-UART and USB-HID port (for mouse/keyboard)

• two HDMI video input ports & two HDMI output ports

• AC-97 Codec with line-in, line-out, mic, & headphone

• real-time power monitors on all power rails

• 16Mbyte x4 SPI Flash for configuration & data storage

• 100MHz CMOS oscillator

• 48 I/O’s routed to expansion connectors

• GPIO includes 8 LEDs, 6 buttons, & 8 slide switches

• ships with a 20W power supply and USB cable

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Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners.

Atlys Reference Manual

Configuration

After power-on, the
FPGA on the Atlys
board must be
configured (or
programmed) before it
can perform any
functions. The FPGA
can be configured in
one of three ways: a
USB-connected PC can
configure the board
using the JTAG port any
time power is on, a
configuration file stored
in the SPI Flash ROM
can be automatically
transferred to the FPGA
at power-on, or a
programming file can be transferred from a USB memory stick
attached to the USB HID port.

An on-board "mode" jumper (JP11) selects between JTAG/USB
and ROM programming modes. If JP11 is not loaded, the FPGA will
automatically configure itself from the ROM. If JP11 is loaded, the
FPGA will remain idle after power-on until configured from the
JTAG or Serial programming port.

Both Digilent and Xilinx freely distribute software that can be used
to program the FPGA and the SPI ROM. Programming files are
stored within the FPGA in SRAM-based memory cells. This data
defines the FPGA’s logic functions and circuit connections, and it
remains valid until it is erased by removing power or asserting the
PROG_B input, or until it is overwritten by a new configuration file.

FPGA configuration files transferred via the JTAG port use the .bin
or .svf file types, files transferred from a USB stick use the .bit file
type, and SPI programming files can use .bit, .bin, or .mcs types.
The ISE/WebPack or EDK software from Xilinx can create bit, svf,
bin, or mcs files from VHDL, Verilog, or schematic-based source
files (EDK is used for MicroBlaze™ embedded processor-based
designs). Digilent's Adept software or Xilinx's iMPACT software can
be used to program the FPGA or ROM using the Adept USB port.

During FPGA programming, a .bit or .svf file is transferred from the
PC directly to the FPGA using the USB-JTAG port. When
programming the ROM, a .bit, .bin, or .mcs file is transferred to the ROM in a two-step process. First,
the FPGA is programmed with a circuit that can program the SPI ROM, and then data is transferred to
the ROM via the FPGA circuit (this complexity is hidden from the user – a simple “program ROM”
interface is presented by the programming software). After the ROM has been programmed, it can
automatically configure the FPGA at a subsequent power-on or reset event if the JP11 jumper is

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Atlys Reference Manual

Programming Interface

unloaded. A programming file stored in the SPI ROM will remain until it is overwritten, regardless of
power-cycle events.

The FPGA can be programmed from a memory stick attached to the USB-HID port if the stick
contains a single .bit configuration file in the root directory, JP11 is loaded, and board power is cycled.
The FPGA will automatically reject any .bit files that are not built for the proper FPGA.

Adept offers a simplified programming interface and many additional features as described in the
following section. The Adept port is also compatible with Xilinx's iMPACT programming software,
provided the Adept-iMPACT plug-in software is installed on the host PC (the plug-in can be freely
downloaded from the Digilent website). The plug-in automatically translates iMPACT-generated JTAG
commands into formats compatible with the Digilent USB port, providing a seamless programming
experience without leaving the Xilinx tool environment. Once the plug-in is installed, the "third party"
programming option can be selected from with the iMPACT tools menu, and iMPACT will work as if a
Xilinx programming cable were being used. All Xilinx tools (iMPACT, ChipScope, EDK, etc.) can work
with the plug-in, and they can be used in conjunction with Adept tools (like the power supply monitor)
without interference.

Adept System

Digilent's Adept high-speed USB2 system can be used to program the FPGA and ROM, run
automated board tests, monitor the four main board power supplies, add PC-based virtual I/O
devices (like buttons, switches, and LEDs) to FPGA designs, and exchange register-based and
file-based data with the FPGA. Adept automatically recognizes the Atlys board and presents a
graphical interface with tabs for each of these applications. Adept also includes public APIs/DLLs so
that users can write applications to exchange data with the Atlys board at up to 38Mbytes/sec. The
Adept application, an SDK, and reference materials are freely downloadable from the Digilent website.

To program the Atlys board using Adept, first
set up the board and initialize the software:

• plug in and attach the power supply

• plug in the USB cable to the PC and to

the USB port on the board

• start the Adept software

• turn ON Atlys' power switch

• wait for the FPGA to be recognized.

Use the browse function to associate the
desired .bit file with the FPGA, and click on the
Program button. The configuration file will be
sent to the FPGA, and a dialog box will indicate
whether programming was successful. The
configuration “done” LED will light after the
FPGA has been successfully configured.

Before starting the programming sequence, Adept ensures that any selected configuration file
contains the correct FPGA ID code – this prevents incorrect .bit files from being sent to the FPGA.

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Atlys Reference Manual

Flash Interface

Test Interface

In addition to the navigation bar, browse and program buttons, the Config interface provides an
Initialize Chain button, console window, and status bar. The Initialize Chain button is useful if for some
reason USB communications with the board have been interrupted. The console window displays
current status, and the status bar shows real-time progress when downloading a configuration file.

The Flash programming application allows .bin,
.bit, or .mcs configuration files to be transferred
to the on-board SPI Flash ROM for FPGA
programming, and also user data files to be
transferred to/from the Flash at user-specified
addresses.

The configuration tool supports programming
from any valid ROM file produced by the Xilinx
tools. After programming, board power must be
cycled to program the FPGA from the SPI
Flash. If programming with a .bit file, the startup
clock must be set to CCLK.

The Read/Write tools allow data to be
exchanged between files on the host PC and
specified address ranges in Flash.

The test interface provides a quick and easy
way to verify many of the board's hardware
circuits and interfaces. These are divided into
two major categories: on-board memory (DDR2
and Flash) and peripherals. In both cases, the
FPGA is configured with test and PC­communication circuits, overwriting any FPGA
configuration that may have been present.
Clicking the Run RAM/Flash Test button will
perform a walking ‘1’ test on the DDR2 memory
and verify the IDCODE in the SPI Flash.
Clicking the Start Peripherals Test button will
initialize GPIO and user I/O testing. Once the
indicator near the Start Peripherals Test button
turns green, all peripheral tests can be run. The
“Test Shorts” feature checks all discrete I/O’s
for shorts to Vdd, GND, and neighboring I/O
pins. The switches and buttons graphics show
the current states of those devices on the Atlys
board. Each button press will drive a tone out
of the LINE-OUT or HP-OUT audio connectors.

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Atlys Reference Manual

Power

The power application provides highly accurate
(better than 1%) real-time current and power
readings from four on-board power-supply
monitors. The monitors are based on Linear
Technology’s LTC2481C sigma-delta analog to
digital converters that return 16-bit samples for
each channel.

Real-time current and power data is displayed
in tabular form and updated continuously when
the power meter is active (or started).

Historical data is available using the Show
Graph feature – up to 10 minutes of measured
current data can be displayed for all four power
supplies. Recorded values are also stored in a
buffer that can be saved to a file for later
analysis. The Save Buffer and Clear Buffer are
used to save and clear the historical data in the
buffer.

Register I/O

The register I/O tab requires that a
corresponding IP block, available in a
reference design on the Digilent website, is
included and active in the FPGA. This IP block
provides an EPP-style interface, where an 8-bit
address selects a register, and data read and
write buttons transfer data to and from the
selected address. Addresses entered into the
address field must match the physical address
included in the FPGA IP block.

Register I/O provides an easy way to move
small amounts of data into and out of specific
registers in a given design. This feature greatly
simplifies passing control parameters into a
design, or reading low-frequency status
information out of a design.

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Atlys Reference Manual

File I/O

The File I/O tab can transfer arbitrarily large
files between the PC and the Atlys FPGA. A
number of bytes (specified by the length value)
can be streamed into a specified register
address from a file or out of a specified register
address into a file. During upload and
download, the file start location can be
specified in terms of bytes.

As with the Register I/O tab, File I/O also
requires specific IP to be available in the
FPGA. This IP can include a memory
controller for writing files into the on-board
DDR2 and Flash memories.

A reference design demonstrating the required
IP is available on the Digilent website.

I/O Expand

The I/O Expand tab works with an IP block in
the FPGA to provide additional simple I/O
beyond the physical devices found on the Atlys
board. Virtual I/O devices include a 24-LED
light bar, 16 slide switches, 16 push buttons, 8
discrete LEDs, a 32-bit register that can be
sent to the FPGA, and a 32-bit register that can
be read from the FPGA. The IP block, available
in a reference design on the Digilent website,
provides a simple interface with well-defined
signals. This IP block can easily be included in
and accessed from user-defined circuits.

For more information, please see the Adept
documentation available at the Digilent
website.

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