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i
Contents
About This Guide ........................................................................................................................................................1
Features ..................................................................................................................................................................1
Appendix A: UCF for SP605 ..................................................................................................................................... 10
Appendix B: UCF for ML605 .................................................................................................................................... 13
Appendix C: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout ................................................................. 18
Table 2. Linear LED Connections ................................................................................................................................3
Table 8. SMA FMC Connections..................................................................................................................................7
Figure 6. SMA Schematics ..........................................................................................................................................7
ii
About This Guide
The purpose is of this document is to convey the necessary information to the designer to successfully use the
capabilities of the FMC-CE I/O expansion card.
Each feature is independently described and contains a connection table. This table includes the name of the
signal, its location on the FMC, the voltage at which it must be programmed by the FPGA, and a brief description
of its function. Where the term “any” is provided, the FPGA may provide use voltage as the FPGAs signals are
passed directly to the device and not through any level shifter.
FMC-CE Card
Overview
The FMC-CE card is meant to be used with a Xilinx demonstration/evaluation board equipped with an FMC
connector. This board extends the I/O capabilities of the base platform and provides an I/O consistency among
various platforms.
Figure 1. FMC-CE Card with Features Annotated
Features
The FMC-CE card provides the following features:
1) Linear array of 8 slide switches
2) Linear array of 8 LEDs co-located with the 8 slide switches
3) Rosetta pattern of 5 push button switches
1
4) Rosetta pattern of 5 LEDs, co-located with the push button switches
Signal Name
Pin Voltage
Description
Switch 0
G33 ≤
2.5V
Switch 1
H32 ≤
2.5V
Switch 2
H31 ≤
2.5V
Switch 3
G31 ≤
2.5V
Switch 4
G30 ≤
2.5V
Switch 5
H29 ≤
2.5V
Switch 6
H28 ≤
2.5V
Switch 7
G28 ≤
2.5V
5) A Rotary/push-button switch
6) An LCD display (2x16).
7) Headphone jack (7a), speaker jack (7b) with a volume control (7c).
1. 8 Slide switches: One side of each of the eight slide switches is tied to GND, while the other side is pulled
up to 2.5V. There is a 10K series resistor for each switch which enables these signals to be used at lower
voltages without damaging the FPGA. These switches are silkscreened SW0-SW7. SW0 is on the right
most side.
Figure 2. Slide Switch Schematics
Table 1. Slide Switch FMC connections
2. There are 8 LED's in a linear fashion, co-located with the slide switches. Each is tied to GND through a
300 Ohm resistor. LD0 is on the right most side. The LEDs illuminate with voltages as low as LVCMOS12.
2
Signal Name
Pin Voltage
Description
LED linear 0
D27 any Voltage must be sufficient to
LED linear 1
D26 any
LED linear 2
C26 any
LED linear 3
D24 any
LED linear 4
D23 any
LED linear 5
C23 any
LED linear 6
C22 any
LED linear 7
D21 any
Figure 3. Schematic of LEDs for Both the Linear Array and Rosetta Array
cross the “on” threshold –
need to verify, as this might
be changed from “any” to >=
some voltage.
Table 2. Linear LED Connections
3
Signal Name
Pin Voltage
Description
Button 0
H14 2.5V
Center
Button 1
G15 2.5V
West
Button 2
G18 2.5V
North
Button 3
H13 2.5V
East
Button 4
G12 2.5V
South
Signal Name
Pin Voltage
Description
LED Rosetta
0 H16 any Center
3. The 5 buttons are pulled to GND through a 10K resistor and pulled up to 2.5 V when pressed. When not
pressed the button is pulled up to 2.5V. A series resister (10K Ohms) bleeds off excess voltage if the
FPGA is programmed to an IO standard below 2.5V. These are marked BTN0-4.
Figure 4. Schematic for Buttons
Voltage must be sufficient to
cross the “on” threshold –
need to verify, as this might
be changed from “any” to >=
some voltage.
Table 3. Button FMC Connections
4. Then there are 5 LED's co-located with the buttons (BTN0-BTN4) in a Rosetta pattern. Each LED is pulled
to GND via a 300 Ohm resistor. The schematics are show in (2) Linear LEDs
Voltage must be sufficient to
cross the “on” threshold –
need to verify, as this might
be changed from “any” to >=
some voltage.
4
Signal Name
Pin Voltage
Description
LED Rosetta 1
G16 any West
LED Rosetta 2
G19 any North
LED Rosetta 3
H17 any East
LED Rosetta 4
G13 any So
uth
Table 4. FMC Connections for LEDs Adjacent to Push Buttons
Signal Name
Pin Voltage
Description
Rot-A G21 2.5V
Reference w
aveform
Rot-B H19 2.5V
Quadrature waveform
Rot-Switch
H20 2.5V
Activated by pressing the
Signal Name
Pin Voltage
Description
LCD Data 0
G22 2.5V
LCD Data 1
H22 2.5V
As above
LCD Data 2
H23 2.5V
As above
5. Rotary Push-button LED linear labeled ROT-1
Figure 5. Rotary Switch Schematic
knob
Table 5. Rotary Switch FMC Connections
6. LCD (ST Micro ST7066) display with LVCMOS25 inputs. This dual row 16 character per row uses an
industry standard controller (Samsung KS0066U) and sports a 4 or 8 bit data interface. No backlight is
provided for the LCD, and the contrast if fixed.
This LCD supports 5x8 and 5x10 dot matrix characters and a programmable 4 or 8 bit MPU interface.
Support for custom characters is provided as is a wide range of instruction functions such as clear,
cursor home, display on/off, cursor shift, and display shift.
Four low order bi-directional
tristate data bus pins. Used for
data transfer and receive
between the MPU and the
ST7066.
These pins are not used during
4-bit operation.
5
Signal Name
Pin Voltage
Description
LCD Data 3
G24 2.5V
As above
LCD Data 4
G25 2.5V
Four high order bi-directional
LCD Data 5
H25 2.5V
As above
LCD Data 6
H26 2.5V
As above
LCD Data 7
G27 2.5V
As above. Additionally DB7
LCD - RS
C19 2
.5V Register Select. 0: Instruction
LCD –
R/W
D20 2.5V
Read
(1)
/ Write
(0) control
LCD – E
C18 2.5V
Enable
-
Signal Name
Pin Voltage
Description
Audio DAC clo
ck left
H37 2.5V
30MHz max SPI
Audio DAC data left
G37 2.5V
16 bit frames
Audio DAC sync left
H38 2.5V
Marks start of data frame
Audio DAC clock right
H35 2.5V
30MHz max SPI
Audio DAC data right
H34 2.5V
16 bit frames
tristate data bus pins. Used for
data transfer and receive
between the MPU and the
ST7066.
can be used as a busy flag.
register (for write) and busy
flag and address counter for
read.
1: Data register for read and
write
Starts data read/write.
Table 6. LCD FMC Connections
7. Both the (a and b) stereo head set jack and a mono speaker jack are controlled via potentiometer
volume control (7c). Dual DAC121S101s (12-bit) digital to analog converters (DACs) provide stereo input
into a LM4838 2W Stereo Audio Amplifier. Each 12-bit DAC supports a data rate of up to 30MHz and is
compatible with SPI, QSPI, NICROWIRE, and DSP interfaces. The effective conversion rate is has a
conversion frequency of about 1.75MHz – well above the audio range. Both DAC outputs (right and left
channels) are then fed in the Audio Amplifier and are available through a mono speaker connector (left
channel only) on J5, and a stereo headphone connector on J6. Both output volumes are controlled via
the potentiometer R47, which is clearly labeled on the board.
Key specifications for part DAC121S101 from National Semiconductor:
DNL: +0.25, -0.15 LSB (typ)
Output Settling Time: 8 us (typ)
Zero Code Error: 4mV
Full Scale Error: -0.06%
6
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