Digilent 410-308P User Manual
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Pullman, WA 99163
509.334.6306
www.digilentinc.com
JTAG-SMT2-NC Programming Module for Xilinx® FPGAs
Revised March 2. 2015
DOC#: 502-308
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 1 of 14
1
2
3
4 8
9
10
11
5
6
7
GND
TCK
TDI
TMS
GPIO1
GPIO2
GPIO0
TDO
VREF
GND
Vdd (3.3V)
12
13
DM
DP
The JTAG-SMT2-NC
Small, complete, all-in-one JTAG programming/debugging
solution for Xilinx FPGAs
Compatible with all Xilinx Tools
Compatible with IEEE 1149.7-2009 Class T0 – Class T4
(includes 2-Wire JTAG)
GPIO pin allows debugging software to reset the processor
core of Xilinx’s Zynq® platform
Single 3.3V supply
Separate Vref drives JTAG signal voltages; Vref can be any
voltage between 1.8V and 5V.
High-Speed USB2 port that can drive JTAG/SPI bus at up to
30Mbit/sec (frequency settable by user)
SPI programming solution (modes 0 and 2 up to 30Mbit/sec,
modes 1 and 3 up to 2Mbit/sec)
Small form-factor surface-mount module can be directly
loaded on target boards
USB D+ and D- signals routed to pads, allowing USB connector
to be placed anywhere on the host PCB
Features include:
Overview
The Joint Test Action Group (JTAG)-SMT2-NC is a compact, complete, and fully self-contained surface-mount
programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from
all Xilinx Tools, including iMPACT, ChipScope™, and EDK. Users can load the module directly onto a target board
and reflow it like any other component.
The JTAG-SMT2-NC uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG
signals use high speed 24mA three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds up to
30MBit/sec. The JTAG bus can be shared with other devices as the SMT2-NC signals are held at high impedance,
except when actively driven during programming. The SMT2-NC module is CE certified and fully compliant with EU
RoHS and REACH directives. The module routes the USB D+ (DP) and D- (DM) signals out to pads, providing the
system designer with the ability to choose the type of USB connector and its location on the system board.
Users can connect JTAG signals directly to the corresponding FPGA signals, as shown in Fig. 1. For best results,
mount the module over a ground plane on the host PCB. Although users may run signal traces on top of the host
PCB beneath the SMT2-NC, Digilent recommends keeping the area immediately beneath the SMT2-NC clear.
Note: Keep the impedance between the SMT2-NC and FPGA below 100 Ohms to operate the JTAG at maximum
speed.
JTAG-SMT2-NC Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 2 of 14
TCK
JTAG-SMT2-NC FPGA
TMS
TDI
TDO
GND
VREF
VIO
TMS
TCK
TDI
TDO
3.3V
V
IO
GND
Vdd
USB2
Port
2
4
3
8
1
9
11
Chip Select
Signal
Port
Number
SPI
Mode
Shift
LSB
First
Shift MSB
First
Selectable
SCK
Frequency
Max SCK
Frequency
Min SCK
Frequency
Inter-byte
Delay
TMS/CS0
0
0
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
2
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
1
0
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
1
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
2
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
3
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
GPIO0/CS1
2
0
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
2
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
3
0
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
1
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
2
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
3
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
GPIO1/CS2
4
0
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
2
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
5
0
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
1
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
2
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
3
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
GPIO2/CS3
6
0
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
2
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
7
0
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
1
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
2
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
3
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
Figure 2. SMT2 SPI port connections.
The SMT2-NC improves upon the SMT1 with the addition of three general purpose I/O pins (GPIO0 – GPIO2) and
support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes.
In addition to supporting JTAG, the JTAG-SMT2-NC also features eight highly configurable Serial Peripheral
Interface (SPI) ports that allow communication with virtually any SPI peripheral (see Fig. 2). All eight SPI ports
share the same SCK, MOSI, and MISO pins, so users may enable only one port at any given time. Table 1
summarizes the features supported by each port. The SMT2-NC supports SPI modes 0, 1, 2, and 3.
JTAG-SMT2-NC Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 3 of 14
TMS
TDI
TCK
TDO
Host
+
JTAG-SMT2-NC
(DTS)
TMS
TDI
TCK
TDO
Target
System 0
TMS
TDI
TCK
TDO
Target
System 1
TMS
TDI
TCK
TDO
Target
System N
Figure 3. 4-Wire series topology.
Note: The Xilinx Tools expect GPIO2/CS3 to be connected to the SRST_B pin on a Zynq chip. As a result, SPI ports 6
and 7 may not be used for SPI communication if the Xilinx Tools are going to be used to communicate with the
SMT2.
Software Support
The JTAG-SMT2-NC has been designed to work seamlessly with Xilinx’s ISE® (iMPACT, ChipScope, EDK) and Vivado
tool suites. The most recent versions of ISE and Vivado include all of the drivers, libraries, and plugins necessary to
communicate with the JTAG-SMT2-NC. At the time of writing, the following Xilinx software included support for
the SMT2-NC: Vivado 2014.1+, Vivado 2013.1+, and ISE 14.1+.
The SMT2-NC is also compatible with ISE 13.1 – 13.4. However, these versions of ISE do not include all of the
libraries, drivers, and plugins necessary to communicate with the SMT2-NC. In order to use the JTAG-SMT2-NC
with these versions of ISE, version 2.5.2 or higher of the Digilent Plugin for Xilinx Tools package must be
downloaded from the Digilent website and the ISE13 plugin must be manually installed as described in the
included documentation.
In addition to working seamlessly with all Xilinx tools, Digilent’s Adept software and the Adept software
development kit (SDK) support the SMT2-NC module. For added convenience, customers may freely download the
SDK from Digilent’s website. This Adept software includes a full-featured programming environment and a set of
public application programming interfaces (API) that allow user applications to directly drive the JTAG chain.
With the Adept SDK, users can create custom applications that will drive JTAG ports on virtually any device. Users
may utilize the APIs provided by the SDK to create applications that can drive any SPI device supporting those
modes. Please see the Adept SDK reference manual for more information.
IEEE 1149.7-2009 Compatibility
The JTAG-SMT2-NC supports several scan formats, including the JScan0-JScan3, MScan, and OScan0 - OScan7. It is
capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0 – T4 JTAG Target Systems (TS)
(see Figs. 3 & 4).
JTAG-SMT2-NC Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 4 of 14
VREF
Output Pin
(TMS, TDI, TCK)
100K
JtagEN
VREF
Input Pin
(TDO)
100K
2-Wire Star Topology
TMSC
TDIC
TCKC
TDOC
Target
System 0
Target
System 1
Target
System N
TMSC
TDIC
TCKC
TDOC
TMSC
TDIC
TCKC
TDOC
TMS
TDI
TCK
TDO
Host
+
JTAG-SMT2-NC
(DTS)
TMSC
TDIC
TCKC
TDOC
Target
System 0
Target
System 1
Target
System N
4-Wire Star Topology
TMSC
TDIC
TCKC
TDOC
TMSC
TDIC
TCKC
TDOC
TMS
TDI
TCK
TDO
Host
+
JTAG-SMT2-NC
(DTS)
Figure 4. 4-Wire and 2-Wire star topology.
Figure 5. Pull-ups on TMS, TDI, TDO, and TCK signals.
The IEEE 1149.7-2009 specification requires any device that functions as a debug and test system (DTS) to provide
a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-SMT2-NC features weak pullups (100K ohm) on the TMS, TDI, TDO, and TCK signals. Though not required in the specifications, the pull-ups on
the TDI and TCK signals ensure that neither signal floats while another source is not driving them (see Fig. 5).
Users should place a current limiting resistor between the TMS pin of the SMT2-NC and the TMSC pin of the TS
when using the JTAG-SMT2-NC to interface with a 1149.7 compatible TS. If a drive conflict occurs, this resistor
should prevent damage to components by limiting the amount of current flowing between the pins of each device.
A 200 ohm resistor will limit the maximum current to 16.5mA when using a 3.3V reference (see Figs. 6 & 7). While
this level of resistance should be sufficient for most applications, the value of the resistor may need to be adjusted
to meet the requirements of the TS.
JTAG-SMT2-NC Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 5 of 14
VIO
1149.7
Target
System
TDOC
TMSC
TDIC
TCKC
GND
VDD
VREF
TDO
JTAG-
SMT2-NC
GND
TMS
TDI
TCK
VIO
3.3V
VIO
200
VIO
1149.7
Target
System
TDOC
TMSC
TDIC
TCKC
GND
VDD
VREF
TDO
JTAG-
SMT2-NC
GND
TMS
TDI
TCK
VIO
3.3V
VIO
200
IO Pin
(GPIO0, GPIO1, GPIO2)
100K
VREF
OEGPIOx
Figure 6. Adding a current limiting resistor.
Figure 7. 200 Ohm resistor limiting current flow.
Figure 8. GPIO signals.
In most cases, users can avoid a drive conflict by having applications that use the SMT2-NC communicate with the
TS in two-wire mode. Use the applications to reconfigure the TS to use the JScan0, JScan1, JScan2, or JScan3 scan
format prior to disabling the SMT2-NC’s JTAG port.
The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP
controller using the MScan, OScan0, and OScan1 scan formats.
GPIO Pins
The JTAG-SMT2-NC has three general purpose I/O pins that are useful for a variety of different applications (GPIO0,
GPIO1, and GPIO2). Each pin features high speed three-state input and output buffers. At power up, the JTAGSMT2-NC disables these output buffers and places the signals in a high-impedance state. Each signal remains in a
high-impedance state until a host application enables DPIO port 0 and configures the applicable pin as an output.
When the host application disables DPIO port 0, all GPIO pins revert to a high-impedance state. Weak pull-ups
(100K ohm) ensure that the GPIO signals do not float while not being actively driven (see Fig. 8).
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