Digilent 410-292P User Manual

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Nexys4 DDR™ FPGA Board Reference Manual

Revised September 11, 2014 This manual applies to the Nexys4 DDR rev. C

DOC#: 502-292

Other product and company names mentioned may be trademarks of their respective owners.

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 16 user switches

 16 user LEDs

 Two 4-digit 7-segment displays

 USB-UART Bridge

 Two tri-color LEDs

 Micro SD card connector

 12-bit VGA output

 PWM audio output

 PDM microphone

 3-axis accelerometer

 Temperature sensor

 10/100 Ethernet PHY

 128MiB DDR2

 Serial Flash

 Four Pmod ports

 Pmod for XADC signals

 Digilent USB-JTAG port for FPGA

programming and communication

 USB HID Host for mice, keyboards

and memory sticks

The Nexys4 DDR

1 Overview

The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx®. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of designs without needing any other components.

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. Artix-7 100T features include:

 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops  4,860 Kbits of fast block RAM  Six clock management tiles, each with phase-locked loop (PLL)  240 DSP slices  Internal clock speeds exceeding 450 MHz  On-chip analog-to-digital converter (XADC)

The Nexys4 DDR also offers an improved collection of ports and peripherals, including:

The Nexys4 DDR is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. Xilinx offers free WebPACK™ versions of these toolsets, so designs can be implemented at no additional cost. The Nexys4 DDR is not supported by the Digilent Adept Utility.

Nexys4 DDR™ FPGA Board Reference Manual

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Callout

Component Description

Callout

Component Description

Power select jumper and battery header

FPGA configuration reset button

Shared UART/ JTAG USB port

CPU reset button (for soft cores)

External configuration jumper (SD / USB)

Analog signal Pmod connector (XADC)

Pmod connector(s)

Programming mode jumper

Microphone

Audio connector

Power supply test point(s)

VGA connector

LEDs (16)

FPGA programming done LED

Slide switches

Ethernet connector

Eight digit 7-seg display

USB host connector

JTAG port for (optional) external cable

PIC24 programming port (factory use)

Five pushbuttons

Power switch

Temperature sensor

Power jack

Figure 1. Nexys4 DDR board features.

A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent website. See the Nexys4 DDR page at www.digilentinc.com for more information.

Nexys4 DDR™ FPGA Board Reference Manual

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Power

Jack

(J13)

3.3V

IC17: ADP2118

Power Switch (SW16)

Power On LED (LD22)

Micro-USB Port (J6)

VU5V0

J12

IC23: ADP2138

800 mA

VIN

IC22: ADP2118

PGOOD

VIN

1.8V

1.0V

Power Source Select

JP3 J12

USB WALL BATTERY

PGOOD

VIN

JP3

Audio

3.3V

150mA

VIN

R287

D16

1.1 Migrating from Nexys4

The Nexys4 DDR is an incremental update to the Nexys4 board. The major improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations. See the Nexys4 DDR page at www.digilentinc.com for updates.

Furthermore, to accommodate the new memory, the pin-out of the FPGA banks has changed as well. The constraints file of existing projects will need to be updated.

The audio output (AUD_PWM) needs to be driven open-drain as opposed to push-pull on the Nexys4.

2 Power Supplies

The Nexys4 DDR board can receive power from the Digilent USB-JTAG port (J6) or from an external power supply. Jumper JP3 (near the power jack) determines which source is used.

All Nexys4 DDR power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good

LED (LD22), driven by the “power good” output of the ADP2118 supply, indicates that the supplies are turned on

and operating normally. An overview of the Nexys4 DDR power circuit is shown in Figure 2.

The USB port can deliver enough power for the vast majority of designs. Our out-of-box demo draws ~400mA of current from the 5V input rail. A few demanding applications, including any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some applications may need to run without being connected to a PC’s USB port. In these instances, an external power supply or battery pack can be used.

An external power supply can be used by plugging into to the power jack (JP3) and setting jumper J13 to “wall”. The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to 5.5VDC and at

Figure 2. Nexys4 DDR power circuit.

Nexys4 DDR™ FPGA Board Reference Manual

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Supply

Circuits

Device

Current (max/typical)

3.3V

FPGA I/O, USB ports, Clocks, RAM I/O, Ethernet, SD slot, Sensors, Flash

IC17: ADP2118

3A/0.1 to 1.5A

1.0V

FPGA Core

IC22: ADP2118

3A/ 0.2 to 1.3A

1.8V

DDR2, FPGA Auxiliary and RAM

IC23: ADP2138

0.8A/ 0.5A

least 1A of current (i.e., at least 5W of power). Many suitable supplies can be purchased from Digilent, through Digi-Key, or other catalog vendors.

An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP3 and the

negative terminal to the pin labeled J12, directly below JP3. Since the main regulator on the Nexys4 DDR cannot accommodate input voltages over 5.5VDC, an external battery pack must be limited to 5.5VDC. The minimum voltage of the battery pack depends on the application: if the USB Host function (J5) is used, at least 4.6V needs to be provided. In other cases, the minimum voltage is 3.6V.

Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, and 1.0V supplies from the main power input. Table 1 provides additional information. Typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs.

Table 1. Nexys4 DDR power supplies.

2.1 Power protection

The Nexys4 DDR features overcurrent and overvoltage protection on the input power rail. A 3.5A fuse (R287) and a 5V Zener diode (D16) provide a non-resettable protection for other on-board integrated circuits, as displayed in Figure 2. Applying power outside of the specs outlined in this document is not covered by warranty. If this happens, either or both might get permanently damaged. The damaged parts are not user-replaceable.

3 FPGA Configuration

After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways:

1. A PC can use the Digilent USB-JTAG circuitry (portJ6, labeled “PROG”) to program the FPGA any time the

power is on.

2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.

3. A programming file can be transferred to the FPGA from a micro SD card.

4. A programming file can be transferred from a USB memory stick attached to the USB HID port.

Nexys4 DDR™ FPGA Board Reference Manual

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M0 M1

JTAG Port

USB

Controller

SPI Quad mode

Flash

1x6 JTAG Header

SPI

Port

Micro-AB USB

Connector (J6)

USB-JTAG/UART Port

Artix-7

Done

PIC24

Type A USB Host

Connector (J5)

Serial Prog. Port

6-pin JTAG

Header (J10)

Prog

Micro SD

Connector (J1)

Media Select

(JP2)

User I/O

Mode (JP1)

Programming Mode

JP2 JP1

SPI Flash

NA JTAG

USB

MicroSD

Figure 3. Nexys4 DDR configuration options.

Figure 3 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a media selection jumper (JP2) select between the programming modes.

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs).

Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port.

An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to program the Nexys4 can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.

After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG”

button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from whatever method has been selected by the programming mode jumpers.

The following sections provide greater detail about programming the Nexys4 DDR using the different methods available.

3.1 JTAG Configuration

The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J10. You can perform JTAG programming any time after the Nexys4 DDR has been powered on, regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG

Nexys4 DDR™ FPGA Board Reference Manual

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setting (seen in Figure 3) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs.

Programming the Nexys4 DDR with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Lab Tools version of Vivado. The demonstration project available at www.digilentinc.com gives an in-depth tutorial on how to program your board.

3.2 Quad-SPI Configuration

Since the FPGA on the Nexys4 DDR is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To that effect, a configuration file needs to be downloaded first to the flash. When programming a nonvolatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). This is called indirect programming. After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting (see Figure 3). Programming files stored in the flash device will remain until they are overwritten, regardless of powercycle events.

Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Nexys4 DDR supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for Quad-SPI programming.

Quad-SPI programming can be done using the iMPACT tool included with ISE or the Lab Tools version of Vivado.

3.3 USB Host and Micro SD Programming

You can program the FPGA from a pen drive attached to the USB Host port (J5) or a microSD card inserted into J1 by doing the following:

1. Format the storage device (Pen drive or microSD card) with a FAT32 file system.

2. Place a single .bit configuration file in the root directory of the storage device.

3. Attach the storage device to the Nexys4 DDR.

4. Set the JP1 Programming Mode jumper on the Nexys4 DDR to “USB/SD”.

5. Select the desired storage device using JP2.

6. Push the PROG button or power-cycle the Nexys4 DDR.

The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Artix-7 device will be rejected by the FPGA.

The Auxiliary Function Status, or “BUSY” LED, gives visual feedback on the state of the configuration process when the FPGA is not yet programmed:

 When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration

medium (microSD or pen drive) and downloading a bitstream to the FPGA.

 A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.

Nexys4 DDR™ FPGA Board Reference Manual

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Setting

Value

Memory type

DDR2 SDRAM

Max. clock period

3000ps (667Mbps data rate)

Recommended clock period (for easy clock generation)

3077ps (650Mbps data rate)

Memory part

MT47H64M16HR-25E

Data width

Data mask

Enabled

Chip Select pin

Enabled

Rtt (nominal) – On-die termination

50ohms

Internal Vref

Enabled

Internal termination impedance

50ohms

 In case of an error during configuration, the LED will blink rapidly.

When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.

4 Memory

The Nexys4 DDR board contains two external memories: a 1Gib (128MiB) DDR2 SDRAM and a 128Mib (16MiB) non-volatile serial Flash device. The DDR2 modules are integrated on-board and connect to the FPGA using the industry standard interface. The serial Flash is on a dedicated quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and external memories are shown below.

4.1 DDR2

The Nexys4 DDR includes one Micron MT47H64M16HR-25:H DDR2 memory component, creating a single rank, 16bit wide interface. It is routed to a 1.8V-powered HR (High Range) FPGA bank with 50 ohm controlled single-ended trace impedance. 50 ohm internal terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side, on-die terminations (ODT) are used for impedance matching.

For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. There are two recommended ways to do that, which are outlined below and differ in complexity and design flexibility.

The straightforward way is to use the Digilent-provided DDR-to-SRAM adapter module which instantiates the memory controller and uses an asynchronous SRAM bus for interfacing with user logic. This module provides backward compatibility with projects written for older Nexys-line boards featuring a CellularRAM instead of DDR2. It trades memory bandwidth for simplicity.

More advanced users or those who wish to learn more about DDR SDRAM technology may want to use the Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard. Depending on the tool used (ISE, EDK or Vivado), the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of several DDR parameters optimized for the particular application. Table 2 below lists the MIG Wizard settings optimized for the Nexys4 DDR.

Table 2. DDR2 settings for the Nexys4 DDR.

Although the FPGA, memory IC, and the board itself are capable of the maximum data rate of 667Mbps, the limitations in the clock generation primitives restrict the clock frequencies that can be generated from the 100 MHz system clock. Thus, for simplicity, the next highest data rate of 650Mbps is recommended.

Nexys4 DDR™ FPGA Board Reference Manual

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CS#

SDI/DQ0

SDO/DQ1

K18

K17

L13

SPI Flash

WP#/DQ2 HLD#/DQ3

L14

M14

SCK

Artix-7

SPI Flash

The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the process.

For more details on the Xilinx memory interface solutions, refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586)1.

4.2 Quad-SPI Flash

FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL128S), and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just less than four MiB (mebibyte) of memory, leaving about 77% of the flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data.

The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2.

NOTE: Refer to the manufacturer’s data sheets2 and Xilinx user guides3 for more information.

Figure 4. Nexys4 DDR SPI flash pin-out.

5 Ethernet PHY

The Nexys4 DDR board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8720A) paired with an RJ45 Ethernet jack with integrated magnetics. The SMSC PHY uses the RMII interface and supports 10/100 Mb/s. Figure 5 illustrates the pin connections between the Artix-7 and the Ethernet PHY. At power-on reset, the PHY is set to the following defaults:

 RMII mode interface  Auto-negotiation enabled, advertising all 10/100 mode capable  PHY address=00001

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf

http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

Nexys4 DDR™ FPGA Board Reference Manual

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C11

Artix-7

B3 RESET#

INT#/REFCLK0

CRS_DV/MODE2

TXEN

MDIO

MDC

D10

RXD1/MODE1

TXD0

SMSC LAN8720A

RJ-45 with

magnetics

Link/Status LEDs (x2)

TXD1

RXD0/MODE0 RXERR/PHYAD0

CLKIND5

A10

C10

Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details.

EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also, a 50 MHz clock needs to be generated for the mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, with the external PHY clock having a 45 degree phase shift relative to the mii_to_rmii Ref_Clk. An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys4 DDR product page at www.digilentinc.com.

ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core.

NOTE: Refer to the LAN8720A data sheet4 for further information.

Figure 5. Pin connections between the Artix-7 and the Ethernet PHY.

6 Oscillators/Clocks

The Nexys4 DDR board includes a single 100 MHz crystal oscillator connected to pin E3 (E3 is a MRCC input on bank

35). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 100 MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.

Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these

http://ww1.microchip.com/downloads/en/DeviceDoc/8720a.pdf

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