Digilent 410-274P User Manual

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Nexys4™ FPGA Board Reference Manual

Nexys4 rev. B; Revised November 19, 2013

DOC#:502-274

Other product and company names mentioned may be trademarks of their respective owners.

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 16 user switches

 16 user LEDs

 Two 4-digit 7-segment displays

 USB-UART Bridge

 Two tri-color LEDs

 Micro SD card connector

 12-bit VGA output

 PWM audio output

 PDM microphone

 3-axis accelerometer

 Temperature sensor

 10/100 Ethernet PHY

 16Mbyte CellularRAM

 Serial Flash

 Four Pmod ports

 Pmod for XADC signals

 Digilent USB-JTAG port for

FPGA programming and communication

 USB HID Host for mice,

keyboards and memory sticks

Overview

The Nexys4 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and a lot of I/O devices allow the Nexys4 to be used for a wide range of designs without needing any other components.

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more resources than earlier designs. Artix-7 100T features include:

 15,850 logic slices, each with four 6-input LUTs and 8 flip-flops  4,860 Kbits of fast block RAM  Six clock management tiles, each with phase-locked loop (PLL)  240 DSP slices  Internal clock speeds exceeding 450MHz  On-chip analog-to-digital converter (XADC)

The Nexys4 also offers an improved collection of ports and peripherals, including:

Nexys4™ FPGA Board Reference Manual

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192021

Callout

Component Description

Callout

Component Description

Power select jumper and battery header

FPGA configuration reset button

Shared UART/ JTAG USB port

CPU reset button (for soft cores)

External configuration jumper (SD / USB)

Analog signal Pmod connector (XADC)

Pmod connector(s)

Programming mode jumper

Microphone

Audio connector

Power supply test point(s)

VGA connector

LEDs (16)

FPGA programming done LED

Slide switches

Ethernet connector

Eight digit 7-seg display

USB host connector

JTAG port for (optional) external cable

PIC24 programming port (factory use)

Five pushbuttons

Power switch

Temperature sensor

Power jack

The Nexys4 is compatible with Xilinx’s new high-performance Vivado ® Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Xilinx offers free “Webpack” versions of these toolsets, so

designs can be implemented at no additional cost.

Figure 1. Nexys4 board features

Nexys4™ FPGA Board Reference Manual

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Power

Jack

(J13)

3.3V

IC17: ADP2118

Power Switch (SW16)

Power On LED (LD22)

Micro-USB Port (J6)

VU5V0

J12

IC23: ADP2138

800 mA

VIN

IC22: ADP2118

PGOOD

VIN

1.8V

1.0V

Power Source Select

JP3 J12

USB WALL BATTERY

PGOOD

VIN

JP3

Figure 2. Nexys4 Power Circuit

A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent website. See the Nexys4 page at www.digilentinc.com for more information.

1 Power Supplies

The Nexys4 board can receive power from the Digilent USB-JTAG port (J6) or from an external power supply. Jumper JP3 (near the power jack) determines which source is used.

All Nexys4 power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good LED

(LD22), driven by the “power good” output of the ADP2118 supply, indicates that the supplies are turned on and

operating normally. An overview of the Nexys4 power circuit is shown in Fig 2.

The USB port can deliver enough power for the vast majority of designs. A few demanding applications, including any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some

applications may need to run without being connected to a PC’s USB port. In these instances an external power

supply or battery pack can be used.

An external power supply can be used by plugging into to the power jack (JP3) and setting jumper J13 to “wall”. The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to 5.5VDC and at least 1A of current (i.e., at least 5W of power). Many suitable supplies can be purchased through Digikey or other catalog vendors.

An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP3 and the

negative terminal to the pin labeled J12 directly below JP3. Since the main regulator on the Nexys4 cannot accommodate input voltages over 5.5VDC, an external battery pack must be limited to 5.5VDC. The minimum voltage of the battery pack depends on the application -if the USB Host function (J5) is used, at least 4.6V needs to be provided. In other cases the minimum voltage is 3.6V.

Nexys4™ FPGA Board Reference Manual

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JTAG Port

USB

Controller

SPI Quad mode

Flash

1x6 JTAG

Header

SPI

Port

Micro-AB USB

Connector (J6)

USB-JTAG/UART Port

Artix-7

Done

PIC24

Type A USB Host

Connector (J5)

Serial Prog. Port

6-pin JTAG

Header (J10)

Prog

Micro SD

Connector (J1)

Media Select

(JP2)

User I/O

Mode (JP1)

Programming Mode

JP2 JP1

SPI Flash

NA JTAG

USB

MicroSD

Supply

Circuits

Device

Current (max/typical)

3.3V

FPGA I/O, USB ports, Clocks, RAM I/O, Ethernet, SD slot, Sensors, Flash

IC17: ADP2118

3A/0.1 to 1.5A

1.0V

FPGA Core

IC22: ADP2118

3A/ 0.2 to 1.3A

1.8V

FPGA Auxiliary and Ram

IC23: ADP2138

800mA/ 0.05 to 0.15A

Table 2. Nexys4 Power Supplies

Figure 3. Nexys4 Configuration Options

Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, and 1.0V supplies from the main power input. Table 2 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).

2 FPGA Configuration

After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways:

1. A PC can use the Digilent USB-JTAG circuitry (portJ6, labeled “PROG”) to program the FPGA any time the

power is on.

2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.

3. A programming file can be transferred to the FPGA from a micro SD card.

4. A programming file can be transferred from a USB memory stick attached to the USB HID port.

Figure 3 Shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a media selection jumper (JP2) select between the programming modes.

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs).

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Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port.

An Artix-7 100T bitstream is typically 30,606,304 bits and can take a long time to transfer. The time it takes to program the Nexys4 can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitsream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.

After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG”

button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from whatever method has been selected by the programming mode jumpers.

The following sections provide greater detail about programming the Nexys4 using the different methods available.

2.1 JTAG Programming

The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J6) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J10. You can perform JTAG programming any time after the Nexys4 has been powered on, regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting (seen in Fig 3) is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs.

Programming the Nexys4 with an uncompressed bitstream using the on-board USB_JTAG circuitry usually takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the labtools version of Vivado. The demonstration project available at digilentinc.com gives an in depth tutorials on how to program your board.

2.2 Quad-SPI Programming

When programming a nonvolatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting (see Fig 3). Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.

Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written however, FPGA configuration can be very fast-- less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilnx tools that can affect configuration speed.

Nexys4™ FPGA Board Reference Manual

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Quad-SPI programming can be done using the iMPACT tool included with ISE or the labtools version of Vivado.

2.3 USB Host and Micro SD Programming

You can program the FPGA from a pen drive attached to the USB-HID port (J5) or a microSD card inserted into J1 by doing the following:

1. Format the storage device (Pen drive or microSD card) with a FAT32 file system.

2. Place a single .bit configuration file in the root directory of the storage device.

3. Attach the storage device to the Nexys4.

4. Set the JP1 Programming Mode jumper on the Nexys4 to “USB/SD”.

5. Select the desired storage device using JP2.

6. Push the PROG button or power-cycle the Nexys4.

The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not built for the proper Artix-7 device will be rejected by the FPGA.

The Auxiliary Function Status, or “BUSY” LED, gives visual feedback on the state of the configuration process when the FPGA is not yet programmed:

 When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration

medium (microSD or pen drive) and downloading a bitstream to the FPGA.

 A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.  In case of an error during configuration the LED will blink rapidly.

When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.

3 Memory

The Nexys4 board contains two external memories: a 128Mbit Cellular RAM (pseudo-static DRAM) and a 128Mbit non-volatile serial Flash device. The Cellular RAM has an SRAM interface, and the serial Flash is on a dedicated quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and external memories are shown in Fig 4 and Table 3.

The 16Mbyte Cellular RAM (Micron part number M45W8MW16) has a 16-bit bus that supports 8 or 16 bit data access. It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns, or as a synchronous memory with a 104MHz bus. When operated as an asynchronous SRAM, the Cellular RAM automatically refreshes its internal DRAM arrays, allowing for a simplified memory controller (similar to any SRAM controller). When operated in synchronous mode, continuous transfers of up to 104MHz are possible.

FPGA configuration files can be written to the Quad SPI Flash (Spansion part number S25FL128S), and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data.

NOTE: Refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website for more

information about the memory devices.

Nexys4™ FPGA Board Reference Manual

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ADDR(22:0)

DATA(15:0)

Cellular RAM

CellRAM

CRE

LB#

UB#

CE#

WE#

OE#

CLK

WAIT

ADV#

CS# SDI/DQ0 SDO/DQ1

K18

K17

L13

SPI Flash

WP#/DQ2 HLD#/DQ3

L14

M14

SCK

Artix-7

H14 R11

T15 T13 T14

L18

J13 J15 J14

See Table

SPI Flash

Figure 4. Nexys4 External Memories

Address Bus

Data Bus

ADDR22: U13

ADDR13: U16

ADDR4: H16

DATA15: P17

DATA6: T18

ADDR21: M16

ADDR12: P14

ADDR3: J17

DATA14: N17

DATA5: R17

ADDR20: T10

ADDR11: V12

ADDR2: H15

DATA13: P18

DATA4: U18

ADDR19: U17

ADDR10: V14

ADDR1: H17

DATA12: M17

DATA3: R13

ADDR18: V17

ADDR9: U14

ADDR0: J18

DATA11: M18

DATA2: U12

ADDR17: M13

ADDR8: V16

DATA10: G17

DATA1: T11

ADDR16: N16

ADDR7: N15

DATA9: G18

DATA0: R12

ADDR15: N14

ADDR6: K13

DATA8: F18

ADDR14: R15

ADDR5: K15

DATA7: R18

Table 3. CellRAM Address and Data Bus Pin Assignments

4 Ethernet PHY

The Nexys4 board includes an SMSC 10/100 Ethernet PHY (SMSC part number LAN8720A) paired with an RJ-45 Ethernet jack with integrated magnetics. The SMSC PHY uses the RMII interface and supports 10/100 Mb/s. Figure 5 illustrates the pin connections between the Artix-7 and the Ethernet PHY. At power-on reset, the PHY is set to the following defaults:

 RMII mode interface  Auto-negotiation enabled, advertising all 10/100 mode capable  PHY address=00001

Nexys4™ FPGA Board Reference Manual

Page 8 of 29

D10

Artix-7

B3 RESET#

INT#/REFCLK0

CRS_DV/MODE2

TXEN

MDIO

MDC

C11

RXD1/MODE1

TXD0

SMSC LAN8720A

RJ-45 with

magnetics

Link/Status LEDs (x2)

TXD1

RXD0/MODE0 RXERR/PHYAD0

CLKIND5

A10

C10

Figure 5. Pin connections between the Artix-7 and the Ethernet PHY

Two on-board LEDs (LD23 = LED2, LD24 = LED1) connected to the PHY provide link status and data activity feedback. See the PHY datasheet for details.

EDK-based designs can access the PHY using either the axi_ethernetlite (AXI EthernetLite) IP core or the axi_ethernet (Tri Mode Ethernet MAC) IP core. A mii_to_rmii core (Ethernet PHY MII to Reduced MII) needs to be inserted to convert the MAC interface from MII to RMII. Also, a 50 MHz clock needs to be generated for the mii_to_rmii core and the CLKIN pin of the external PHY. To account for skew introduced by the mii_to_rmii core, generate each clock individually, with the external PHY clock having a 45 degree phase shift relative to the mii_to_rmii Ref_Clk. An EDK demonstration project that properly uses the Ethernet PHY can be found on the Nexys4 product page at www.digilentinc.com.

ISE designs can use the IP Core Generator wizard to create an Ethernet MAC controller IP core.

NOTE: Refer to the LAN8720A data sheet on the www.smsc.com website for further information.

5 Oscillators/Clocks

The Nexys4 board includes a single 100MHz crystal oscillator connected to pin E3 (E3 is a MRCC input on bank 35). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 100MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.

Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these

Nexys4™ FPGA Board Reference Manual

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TXD C4

Micro-USB

(J6)

RXD

Artix-7FT2232

CTS RTS

JTAG

D4 D3 E5

Figure 6. Nexys4 FT2232HQ connections

clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the

Project Navigator or Core Generator tools.

6 USB-UART Bridge (Serial Port)

The Nexys4 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that allows you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) and optional hardware flow control (RTS/CTS). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the C4 and D4 FPGA pins.

Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD20) and the receive LED (LD19). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.

The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two features into a single device allows the Nexys4 to be programmed, communicated with via UART, and powered from a computer attached with a single Micro USB cable.

The connections between the FT2232HQ and the Artix-7 are shown in Figure 6.

7 USB HID Host

The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the Nexys4 with USB HID host capability. After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application mode, which is USB HID Host in this case. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J5 labeled "USB Host.” Hub support is not currently available, so only a single mouse or a single keyboard can be used. The PIC24 drives several signals into the FPGA – two are used to implement a standard PS/2 interface for communication with a mouse or keyboard, and the others are connected to the FPGA’s two-wire serial programming port, so the FPGA can be programmed from a file stored on a USB pen drive or microSD card.

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