Digilent 410-249P User Manual
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509.334.6306
www.digilentinc.com
JTAG-HS2™ Programming Cable for Xilinx® FPGAs
Revised January 22, 2015
DOC#: 502-249
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 1 of 6
The JTAG-HS2.
Small, complete, all-in-one JTAG programming solution for
Xilinx FPGAs
Compatible with all Xilinx tools
Compatible with IEEE 1149.7-2009 Class T0 - Class T4
(includes 2-Wire JTAG)
Separate Vref drives JTAG/SPI signal voltages; Vref can be
any voltage between 1.8V and 5V.
High-Speed USB2 port that can drive JTAG/SPI bus at up to
30Mbit/sec
JTAG/SPI frequency settable by user
Uses micro-AB USB2 connector
SPI programming solution (modes 0 and 2 up to
30Mbit/sec, modes 1 and 3 up to 2Mbit/sec)
Fully supported by the Adept SDK, allowing custom
JTAG/SPI applications to be created
Features include:
Overview
The Joint Test Action Group (JTAG)-HS2 programming cable is a high-speed programming solution for Xilinx fieldprogrammable gate arrays (FPGAs). The cable is fully compatible will all Xilinx tools and can be seamlessly driven
from iMPACT, Chipscope™, and EDK. The HS2 attaches to target boards using Digilent's 6-pin, 100-mil spaced
programming header or Xilinx's 2×7, 2mm connector and the included adaptor.
The PC powers the JTAG-HS2 through the USB port and will recognize it as a Digilent programming cable when
connected to a PC, even if the cable is not attached to the target board. The HS2 has a separate Vdd pin to supply
the JTAG signal buffers. The high speed 24mA three-state buffers allow target boards to drive the HS2 with signal
voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. To function correctly, the HS2's Vdd pin must be tied
to the same voltage supply that drives the JTAG port on the FPGA (see Fig. 1).
The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance except when
actively driven during programming. The HS2 comes with a standard Type-A to Micro-USB cable that attaches to
the end of the module opposite the system board connector. The system board connector should hold the small
and light HS2 firmly in place (see Fig. 2).
JTAG-HS2™ Programming Cable for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 2 of 6
VIO: 5V to 1.8V
USB2
Port
TMS
TDI
TDO
TCK
SS
MOSI
MISO
SCK
SPI DeviceJTAG-HS2
GND
VDD (VREF)
GND
VIO
Port
Number
SPI Mode
Shift
LSB
First
Shift
MSB
First
Selectable
SCK
Frequency
Max SCK
Frequency
Min SCK
Frequency
Inter-byte
Delay
0
0
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
2
Yes
Yes
Yes
30 MHz
8 KHz
0 – 1000 µS
1
0
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
1
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
2
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
3
Yes
Yes
Yes
2.066 MHz
485 KHz
0 – 1000 µS
Figure 1. Diagram of signal voltages and connections.
Figure 3. JTAG-HS2 SPI Device Connections.
Figure 2. Xilinx JTAG headers.
Table 1. Features supported by each port.
In addition to supporting JTAG, the JTAG-HS2 also features two highly configurable serial peripheral interface (SPI)
ports that allow communication with virtually any SPI peripheral. Both SPI ports share the same pins and only one
port may be enabled at any given time (see Fig. 3). Table 1 summarizes the features supported by each port. The
HS2 supports SPI modes 0, 1, 2, and 3.
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