Digilent 410-205P User Manual
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JTAG-HS1™ Programming Cable for Xilinx® FPGAs
Revised January 22, 2015
DOC#: 502-205
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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The JTAG-HS1.
Small, complete, all-in-one JTAG programming solution
for Xilinx FPGAs
Separate Vref drives JTAG/SPI signal voltages; Vref can
be any voltage between 1.8V and 5V.
High-Speed USB2 port that can drive JTAG/SPI bus at up
to 30Mbit/sec
JTAG/SPI frequency settable by user
Compatible with all Xilinx tools
Uses micro-AB USB2 connector
SPI programming solution (modes 0 and 2 supported)
Fully supported by the Adept SDK, allowing custom
JTAG/SPI applications to be created
Features include:
Overview
The joint test action group (JTAG)-HS1 programming cable is a high-speed programming solution for Xilinx fieldprogrammable gate arrays (FPGAs). It is fully compatible will all Xilinx tools, and can be seamlessly driven from
iMPACT, Chipscope™, and EDK. The HS1 attaches to target boards using Digilent's 6-pin, 100-mil spaced
programming header, or Xilinx's 2x7, 2mm connector (using the included adaptor).
The JTAG-HS1 is powered from a PC's USB port, and will be recognized as a Digilent programming cable when
connected to a PC, whether or not it is attached to the target board. A separate Vdd pin is provided on the HS1 to
supply JTAG signal buffers. The high speed, 24mA, three-state buffers allow target boards to drive the HS1 with
signal voltages from 1.8V to 5V, with bus speeds of up to 30MBit/sec. The HS1's Vdd pin must be tied to the same
voltage supply that drives the JTAG port on the FPGA (see Fig. 1).
JTAG signals are held in high-impedance except when actively driven during programming, so the JTAG bus can be
shared with other devices. The HS1 uses a standard Type-A to Micro-USB cable (included with the HS1) that
attaches to the end of the module opposite the system board connector. The HS1 is small and light, allowing it to
be held firmly in place by the system board connector (see Fig. 2).
JTAG-HS1™ Programming Cable for Xilinx® FPGAs
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 2 of 4
VIO: 5V to 1.8V
USB2
Port
TMS
TDI
TDO
TCK
SS
MOSI
MISO
SCK
SPI DeviceJTAG-HS1
GND
VDD
GND
VIO
Figure 1. Diagram of signal voltages and connections.
Figure 2. Xilinx JTAG headers.
Figure 3. JTAG-HS1 SPI Device Connections.
Software Support
In addition to working seamlessly with all Xilinx tools, the HS1 is supported by Digilent's Adept software and the
Adept SDK (the SDK can be freely downloaded from Digilent's website). Adept includes a full-featured
programming environment, and a set of public APIs that allow user applications to directly drive the JTAG chain.
Using the Adept SDK, custom applications can be created to drive JTAG ports on virtually any device. The HS1 also
supports SPI modes 0 and 2. Users may utilize the APIs provided by the SDK to create applications that can drive
any SPI device supporting those modes. Please see the Adept SDK reference manual for more information.
The HS1 is also supported by Digilent's AVR programmer that can target any AVR device
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