Digilent 410-183P User Manual
1300 Henley Court
• 16 user switches
• 16 user LEDs
• 5 user pushbuttons
4-digit 7-segment display
•
•
12-bit VGA output
• USB-UART Bridge
• Serial Flash
communication
• USB HID Host for mice, keyboards
The Basys3.
Pullman, WA 99163
509.334.6306
www.digilentinc.com
Basys3™ FPGA Board Reference Manual
Revised August 12, 2014
This manual applies to the Basys3 rev. C
Overview
The Basys3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix®-7
Field Programmable Gate Array (FPGA) from Xilinx®. With its high-capacity FPGA (Xilinx part number XC7A35T1CPG236C), low overall cost, and collection of USB, VGA, and other ports, the Basys3 can host designs ranging from
introductory combinational circuits to complex sequential circuits like embedded processors and controllers. It
includes enough switches, LEDs, and other I/O devices to allow a large number of designs to be completed without
the need for any additional hardware, and enough uncommitted FPGA I/O pins to allow designs to be expanded
using Digilent Pmods or other custom boards and circuits.
The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more
resources than earlier designs. Artix-7 35T features include:
• 33,280 logic cells in 5200 slices (each slice contains four
6-input LUTs and 8 flip-flops)
• 1,800 Kbits of fast block RAM
• Five clock management tiles, each with a phase-locked
loop (PLL)
• 90 DSP slices
• Internal clock speeds exceeding 450MHz
• On-chip analog-to-digital converter (XADC)
The Basys3 also offers an improved collection of ports and peripherals, including:
•
•
• Digilent USB-JTAG port for
FPGA programming and
The Basys3 works with Xilinx’s new high-performance Vivado™ Design Suite. Vivado includes many new tools and
design flows that facilitate and enhance the latest design methods. It runs faster, allows better use of FPGA
resources, and allows designers to focus their time evaluating design alternatives. The System Edition includes an
on-chip logic analyzer, high-level synthesis tool, other cutting-edge tools, and the free WebPACK™ version allows
Basys3 designs to be created at no additional cost.
DOC#: 502-183
Three Pmod connectors
Pmod for XADC signals
and memory sticks
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Copyright Digilent, Inc. All rights reserved.
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Basys3™ FPGA Board Reference Manual
2
15
2
14
13
3
4
5
6
8
7
11
9
12
2
10
1
16
Figure 1. Basys3 FPGA board with callouts.
Callout Component Description Callout Component Description
1 Power good LED 9 FPGA configuration reset button
2 Pmod connector(s) 10 Programming mode jumper
3 Analog signal Pmod connector (XADC) 11 USB host connector
4 Four digit 7-segment display 12 VGA connector
5 Slide switches (16) 13 Shared UART/ JTAG USB port
6 LEDs (16) 14 External power connector
7 Pushbuttons (5) 15 Power Switch
8 FPGA programming done LED 16 Power Select Jumper
A growing collection of board support IP, reference designs, and add-on boards are available on the Digilent
website. See the Basys3 page at www.digilentinc.com
Table 1. Basys3 Callouts and component descriptions.
for more information.
1 Power Supplies
The Basys3 board can receive power from the Digilent USB-JTAG port (J4) or from a 5V external power supply.
Jumper JP3 (near the power switch) determines which source is used.
All Basys3 power supplies can be turned on and off by a single logic-level power switch (SW16). A power-good LED
(LD20), driven by the “power good” output of the LTC3633 supply, indicates that the supplies are turned on and
operating normally. An overview of the Basys3 power circuit is shown in Fig. 2
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.
Page 2 of 19
Basys3™ FPGA Board Reference Manual
VU5V0
1.8V
1.0V
3.
3
V
VIN1
VIN2
EN1
EN
2
PGOOD1
PGOOD2
1A
2
A
IC10: LTC3633
IC11: LTC3621
EN
PGOOD
300 mA
VIN
+
-
ON/OFF
Type A USB Host
Connector (J2)
JP2
J6
5
V External
Supply
Micro-USB
Port (J4)
Power Source Select
JP2
USB EXTERNAL
Power On
LED (LD20)
Power
Switch
(SW
16
)
FPGA I/O, USB ports, Clocks,
Flash, PMODs
Figure 2. Basys3 power circuit.
The USB port can deliver enough power for the vast majority of designs. A few demanding applications, including
any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some
applications may need to run without being connected to a PC’s USB port. In these instances an external power
supply or battery pack can be used.
An external power supply can be used by plugging into the external power header (J6) and setting jumper JP2 to
“EXT”. The supply must deliver 4.5VDC to 5.5VDC and at least 1A of current (i.e., at least 5W of power). Many
suitable supplies can be purchased through Digi-Key or other catalog vendors.
An external battery pack can be used by connecting the battery’s positive terminal to the “EXT” pin of J6 and the
negative terminal to the “GND” pin of J6. The power provided to USB devices that are connected to Host connector
J2 is not regulated. Therefore, it is necessary to limit the maximum voltage of an external battery pack to 5.5V DC.
The minimum voltage of the battery pack depends on the application; if the USB Host function (J2) is used, at least
4.6V needs to be provided. In other cases, the minimum voltage is 3.6V.
Voltage regulator circuits from Linear Technology create the required 3.3V, 1.8V, and 1.0V supplies from the main
power input. Table 2 provides additional information (typical currents depend strongly on FPGA configuration and
the values provided are typical of medium size/speed designs).
Supply Circuits Device Current (max/typical)
3.3V
1.0V FPGA Core IC10: LTC3633 2A/ 0.2 to 1.3A
1.8V FPGA Auxiliary and Ram IC11: LTC3621 300mA/ 0.05 to 0.15A
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Table 2. Basys3 power supplies.
IC10: LTC3633 2A/0.1 to 1.5A
Page 3 of 19
Basys3™ FPGA Board Reference Manual
M0
M1
JTAG
Port
USB
Controller
SPI Quad mode
Flash
1x6 JTAG
Header
SPI
Port
Micro-AB USB
Connector (J4)
USB-JTAG/UART Port
Artix-7
Done
PIC24
Type A USB Host
Connector (J2)
Serial
Prog. Port
2
6-pin JTAG
Header (J5)
Prog
M2
Mode (JP1)
Programming Mode
JP1
SPI Flash
JTAG
USB
2 FPGA Configuration
After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You
can configure the FPGA in one of three ways:
1. A PC can use the Digilent USB-JTAG circuitry (portJ4, labeled “PROG”) to program the FPGA any time the
power is on.
2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
3. A programming file can be transferred from a USB memory stick attached to the USB HID port.
Figure 3 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) selects
between the programming modes.
Figure 3. Basys3 configuration options.
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado
software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files.
Bitstreams are stored in SRAM-based memory cells within the FPGA. This data defines the FPGA’s logic functions
and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset
button attached to the PROG input, or by writing a new configuration file using the JTAG port.
An Artix-7 35T bitstream is typically 17,536,096 bits and can take a long time to transfer. The time it takes to
program the Basys3 can be decreased by compressing the bitstream before programming, and then allowing the
FPGA to decompress the bitsream itself during configuration. Depending on design complexity, compression ratios
of 10x can be achieved. Bitstream compression can be enabled within the Xilinx Tools (Vivado) to occur during
generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG”
button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately
attempt to reprogram itself from whatever method has been selected by the programming mode jumper.
The following sections provide greater detail about programming the Basys3 using the different methods available.
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Page 4 of 19
Basys3™ FPGA Board Reference Manual
2.1 JTAG Programmi ng
The Xilinx Tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture,
commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using
the onboard Digilent USB-JTAG circuitry (port J4) or an external JTAG programmer, such as the Digilent JTAG-HS2
attached to port J5 (located below port JA). You can perform JTAG programming any time after the Basys3 has
been powered on regardless of what the mode jumper (JP1) is set to. If the FPGA is already configured, then the
existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to
the JTAG setting (seen in Fig. 3) is useful to prevent the FPGA from being configured from any other bitstream
source until a JTAG programming occurs.
Programming the Basys3 with an uncompressed bitstream using the on-board USB_JTAG circuitry usually takes
around five seconds. JTAG programming can be done using the hardware server in Vivado. The demonstration
project available at digilentinc.com provides an in-depth tutorial on how to program your board.
2.2 JTAG Programming
When programming a nonvolatile flash device, a bitstream file is transferred to the flash in a two-step process.
First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the
flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx Tools). After the flash device
has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as
determined by the mode jumper setting (see Fig. 3). Programming files stored in the flash device will remain until
they are overwritten, regardless of power-cycle events.
Programming the flash can take as long as one or two minutes, which is mostly due to the lengthy erase process
inherent to the memory technology. Once written, however, FPGA configuration can be very fast – less than a
second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx Tools that
can affect configuration speed.
Quad-SPI programming can be performed using Vivado.
2.3 USB Host Programming
You can program the FPGA from a pen drive attached to the USB-HID port (J2) by doing the following:
1. Format the storage device (Pen drive) with a FAT32 file system.
2. Place a single .bit configuration file in the root directory of the storage device.
3. Attach the storage device to the Basys3.
4. Set the JP1 Programming Mode jumper on the Basys3 to “USB”.
5. Push the PROG button or power-cycle the Basys3.
The FPGA will automatically be configured with the .bit file on the selected storage device. Any .bit files that are
not built for the proper Artix-7 device will be rejected by the FPGA.
The Auxiliary Function Status, or “BUSY” LED (LD16), gives visual feedback on the state of the configuration process
when the FPGA is not yet programmed:
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Page 5 of 19
Basys3™ FPGA Board Reference Manual
CS#
SDI
/DQ0
SDO
/DQ1
C11
D19
D18
K19
SPI Flash
WP
#/DQ
2
HLD
#/DQ3
G18
F18
SCK
Artix-7
SPI Flash
• When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration
medium (pen drive) and downloading a bitstream to the FPGA.
• A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
• In case of an error during configuration, the LED will blink rapidly.
When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a
USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard.
3 Memory
The Basys3 board contains a 32Mbit non-volatile serial Flash device, which is attached to the Artix-7 FPGA using a
dedicated quad-mode (x4) SPI bus. The connections and pin assignments between the FPGA and the serial flash
device are shown in Fig. 4.
FPGA configuration files can be written to the Quad SPI Flash (Spansion part number S25FL032), and mode settings
are available to cause the FPGA to automatically read a configuration from this device at power on. An Artix-7 35T
configuration file requires just over two Mbytes of memory, leaving approximately 48% of the flash device
available for user data.
NOTE: Refer to the manufacturer’s data sheets and the reference designs posted on Digilent’s website for more
information about the memory devices.
Figure 4. Basys3 external memory.
4 Oscillators/Clocks
The Basys3 board includes a single 100 MHz oscillator connected to pin W5 (W5 is a MRCC input on bank 34). The
input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase
relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven
by the 100 MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking
resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.
Xilinx offers the LogiCORE™ Clocking Wizard IP to help users generate the different clocks required for a specific
design. This wizard properly instantiates the needed MMCMs and PLLs based on the desired frequencies and phase
relationships specified by the user. The wizard will then output an easy to use wrapper component around these
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Page 6 of 19
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