Spartan-3E Starter Kit
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Board User Guide
UG230 (v1.0) March 9, 2006
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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate
on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,
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Inc. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
03/09/06 1.0
Spartan-3E Starter Kit Board User Guide www.xilinx.com UG230 (v1.0) March 9, 2006
a Initial release.
Table of Contents
Preface: About This Guide
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 1: Introduction and Overview
Choose the Starter Kit Board for Your Needs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Spartan-3E FPGA Features and Embedded Processing Functions. . . . . . . . . . . . . . . . 11
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics . . . . . . . . . . . . 11
Advanced Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . 11
Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2: Switches, Buttons, and Knob
Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rotary Push-Button Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Push-Button Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Rotary Shaft Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Discrete LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: Clock Sources
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SMA Clock Input or Output Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 4: FPGA Configuration Options
Configuration Mode Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PROG Push Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DONE Pin LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming the FPGA, CPLD, or Platform Flash PROM via USB . . . . . . . . . . . 28
Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming via iMPACT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Programming Platform Flash PROM via USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Generating the FPGA Configuration Bitstream File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Generating the PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programming the Platform Flash PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Chapter 5: Character LCD Screen
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Character LCD Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interaction with Intel StrataFlash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CG ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CG RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clear Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Return Cursor Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Entry Mode Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Display On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Cursor and Display Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Function Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Set CG RAM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Set DD RAM Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read Busy Flag and Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Write Data to CG RAM or DD RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Read Data from CG RAM or DD RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transferring 8-Bit Data over the 4-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power-On Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Disabling the Unused LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 6: VGA Display Port
Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Chapter 7: RS-232 Serial Ports
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 8: PS/2 Mouse/Keyboard Port
Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 9: Digital to Analog Converter (DAC)
SPI Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . . . . 68
SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Specifying the DAC Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DAC Outputs A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DAC Outputs C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 10: Analog Capture Circuit
Digital Outputs from Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Programmable Pre-Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Programmable Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . 79
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Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
StrataFlash Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Xilinx XC2C64A CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SPI Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 12: SPI Serial Flash
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Configuring from SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Setting the Configuration Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Formatting an SPI Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Download and Install the XSPI Programming Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Attach a JTAG Parallel Programming Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Insert Jumper on JP8 and Hold PROG_B Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Programming the SPI Flash with the XSPI Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Additional Design Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Shared SPI Bus with Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Other SPI Flash Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Variant Select Pins, VS[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Jumper Block J11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Programming Header J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Multi-Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Chapter 13: DDR SDRAM
DDR SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Chapter 14: 10/100 Ethernet Physical Layer Interface
Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 15: Expansion Connectors
Hirose 100-pin FX2 Edge Connector (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Connector Pinout and FPGA Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Mating Receptacle Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Differential I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Using Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Using Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Header J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Header J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Header J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Connectorless Debugging Port Landing Pads (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Chapter 16: XC2C64A CoolRunner-II CPLD
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
FPGA Connections to CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Chapter 17: DS2432 1-Wire SHA-1 EEPROM
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Appendix A: Schematics
FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header . . . . 132
RS-232 Ports, VGA Port, and PS/2 Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Ethernet PHY, Magnetics, and RJ-11 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Voltage Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG
Connections
FPGA I/O Banks 0 and 1, Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
FPGA I/O Banks 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
XC2C64A CoolRunner-II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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Linear Technology ADC and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM . . . 152
Buttons, Switches, Rotary Encoder, and Character LCD . . . . . . . . . . . . . . . . . . . . . 154
DDR SDRAM Series Termination and FX2 Connector Differential Termination 156
Appendix B: Example User Constraints File (UCF)
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About This Guide
This user guide provides basic information on the Spartan-3E Starter Kit board
capabilities, functions, and design. It includes general information on how to use the
various peripheral functions included on the board. For detailed reference designs,
including VHDL or Verilog source code, please visit the following web link.
• Spartan™-3E Starter Kit Board Reference Page
http://www.xilinx.com/s3estarter
Acknowledgements
Xilinx wishes to thank the following companies for their support of the Spartan-3E Starter
Kit board:
Preface
• Intel Corporation for the 128 Mbit StrataFlash memory
• Linear Technology for the SPI-compatible A/D and D/A converters, the
• Micron Technology, Inc. for the 32M x 16 DDR SDRAM
• SMSC for the 10/100 Ethernet PHY
• STMicroelectronics for the 16M x 1 SPI serial Flash PROM
• Texas Instruments Incorporated for the three-rail TPS75003 regulator supplying most
• Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM
• Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner™-II CPLD
Guide Contents
This manual contains the following chapters:
• Chapter 1, “Introduction and Overview,” provides an overview of the key features of
• Chapter 2, “Switches, Buttons, and Knob,” defines the switches, buttons, and knobs
• Chapter 3, “Clock Sources,” describes the various clock sources available on the
• Chapter 4, “FPGA Configuration Options,” describes the configuration options for
programmable pre-amplifier, and the power regulators for the non-FPGA
components
of the FPGA supply voltages
and their support for the embedded USB programmer
the Spartan-3E Starter Kit board.
present on the Spartan-3E Starter Kit board.
Spartan-3E Starter Kit board.
the FPGA on the Spartan-3E Starter Kit board.
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Preface:
About This Guide
• Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD
• Chapter 6, “VGA Display Port,” describes the functionality of the VGA port.
• Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports.
• Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2
• Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the
• Chapter 10, “Analog Capture Circuit,” describes the functionality of the A/D
• Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” describes the functionality
• Chapter 12, “SPI Serial Flash,” describes the functionality of the SPI Serial Flash
• Chapter 13, “DDR SDRAM,” describes the functionality of the DDR SDRAM.
• Chapter 14, “10/100 Ethernet Physical Layer Interface,” describes the functionality of
• Chapter 15, “Expansion Connectors,” describes the various connectors available on
• Chapter 16, “XC2C64A CoolRunner-II CPLD” describes how the CPLD is involved in
• Chapter 17, “DS2432 1-Wire SHA-1 EEPROM” provides a brief introduction to the
• Appendix A, “Schematics,” lists the schematics for the Spartan-3E Starter Kit board.
• Appendix B, “Example User Constraints File (UCF),” provides example code from a
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screen.
mouse and keyboard port.
DAC.
converter with a programmable gain pre-amplifier.
of the StrataFlash PROM.
memory.
the 10/100Base-T Ethernet physical layer interface.
the Spartan-3E Starter Kit board.
FPGA configuration when using Master Serial and BPI mode.
SHA-1 secure EEPROM for authenticating or copy-protecting FPGA configuration
bitstreams.
UCF.
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
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Introduction and Overview
Thank you for purchasing the Xilinx Spartan™-3E Starter Kit. You will find it useful in
developing your Spartan-3E FPGA application.
Choose the Starter Kit Board for Your Needs
Depending on specific requirements, choose the Xilinx development board that best suits
your needs.
Spartan-3E FPGA Features and Embedded Processing Functions
Chapter 1
The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA
family and provides a convenient development board for embedded processing
applications. The board highlights these features:
• Spartan-3E specific features
♦ Parallel NOR Flash configuration
♦ MultiBoot FPGA configuration from Parallel NOR Flash PROM
♦ SPI serial Flash configuration
• Embedded development
♦ MicroBlaze™ 32-bit embedded RISC processor
♦ PicoBlaze™ 8-bit embedded controller
♦ DDR memory interfaces
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics
The Spartan-3E Starter Kit board is more advanced and complex compared to other
Spartan development boards. To learn the basics of Xilinx FPGA or CPLD design and how
to use the Xilinx ISE development software, consider using the High Volume Starter Kit
Bundle, which includes both a Spartan-3 FPGA development board and a Xilinx
CoolRunner™-II/XC9500XL CPLD development board at a very affordable price.
• High Volume Starter Kit Bundle (HW-SPAR3-CPLD-DK)
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?
key=HW-SPAR3-CPLD-DK
Advanced Spartan-3 Generation Development Boards
The Spartan-3E Starter Kit board demonstrates the basic capabilities of the MicroBlaze
embedded processor and the Xilinx Embedded Development Kit (EDK). For more
Spartan-3E Starter Kit Board User Guide www.xilinx.com 11
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Chapter 1:
Introduction and Overview
advanced development on a board with additional peripherals and FPGA logic, consider
the SP-305 Development Board:
• Spartan-3 SP-305 Development Board (HW-SP305-xx)
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=
HW-SP305-US
Also consider the capable boards offered by Xilinx partners:
• Spartan-3 and Spartan-3E Board Interactive Search
http://www.xilinx.com/products/devboards/index.htm
Key Components and Features
The key features of the Spartan-3E Starter Kit board are:
• Xilinx XC3S500E Spartan-3E FPGA
♦ Up to 232 user-I/O pins
♦ 320-pin FBGA package
♦ Over 10,000 logic cells
• Xilinx 4 Mbit Platform Flash configuration PROM
• Xilinx 64-macrocell XC2C64A CoolRunner CPLD
• 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
• 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
♦ FPGA configuration storage
♦ MicroBlaze code storage/shadowing
• 16 Mbits of SPI serial Flash (STMicro)
♦ FPGA configuration storage
♦ MicroBlaze code shadowing
• 2-line, 16-character LCD screen
• PS/2 mouse or keyboard port
• VGA display port
• 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
• Two 9-pin RS-232 ports (DTE- and DCE-style)
• On-board USB-based FPGA/CPLD download/debug interface
• 50 MHz clock oscillator
• SHA-1 1-wire serial EEPROM for bitstream copy protection
• Hirose FX2 expansion connector
• Three Digilent 6-pin expansion connectors
• Four-output, SPI-based Digital-to-Analog Converter (DAC)
• Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain
pre-amplifier
• ChipScope™ SoftTouch debugging port
• Rotary-encoder with push-button shaft
• Eight discrete LEDs
• Four slide switches
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• Four push-button switches
• SMA clock input
• 8-pin DIP socket for auxiliary clock oscillator
Design Trade-Offs
A few system-level design trade-offs were required in order to provide the Spartan-3E
Starter Kit board with the most functionality.
Configuration Methods Galore!
A typical FPGA application uses a single non-volatile memory to store configuration
images. To demonstrate new Spartan-3E capabilities, the starter kit board has three
different configuration memory sources that all need to function well together. The extra
configuration functions make the starter kit board more complex than typicalSpartan-3E
applications.
The starter kit board also includes an on-board USB-based JTAG programming interface.
The on-chip circuitry simplifies the device programming experience. In typical
applications, the JTAG programming hardware resides off-board or in a separate
programming module, such as the Xilinx Platform USB cable.
Design Trade-Offs
Voltages for all Applications
The Spartan-3E Starter Kit board showcases a triple-output regulator developed by Texas
Instruments, the T
regulator is sufficient for most stand-alone FPGA applications. However, the starter kit
board includes DDR SDRAM, which requires its own high-current supply. Similarly, the
USB-based JTAG download solution requires a separate 1.8V supply.
Related Resources
• Xilinx MicroBlaze Soft Processor
http://www.xilinx.com/microblaze
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• Xilinx Embedded Development Kit
http://www.xilinx.com/ise/embedded_design_prod/platform_studio.htm
• Xilinx software tutorials
http://www.xilinx.com/support/techsup/tutorials/
• Texas Instruments TPS75003
http://focus.ti.com/docs/prod/folders/print/tps75003.html
PS75003 specifically to power Spartan-3 and Spartan-3E FPGAs. This
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Chapter 1:
Introduction and Overview
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Switches, Buttons, and Knob
Slide Switches
Locations and Labels
The Spartan-3E Starter Kit board has four slide switches, as shown in Figure 2-1. The slide
switches are located in the lower right corner of the board and are labeled SW3 through
SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.
Chapter 2
Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic
Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board.
UCF Location Constraints
SW3
(N17)
Figure 2-1:
SW2
(H18)
SW1
(L14)
Four Slide Switches
SW0
(L13)
HIGH
LOW
UG230_c2_01_021206
Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin
assignment and the I/O standard used. The PULLUP resistor is not required, but it defines
the input value when the switch is in the middle of a transition.
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Chapter 2:
Switches, Buttons, and Knob
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL |
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL |
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL |
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PULLUP ;
PULLUP ;
PULLUP ;
Push-Button Switches
Locations and Labels
The Spartan-3E Starter Kit board has four momentary-contact push-button switches,
shown in Figure 2-3. The push buttons are located in the lower left corner of the board and
are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The FPGA pins
that connect to the push buttons appear in parentheses in Figure 2-3 and the associated
UCF appears in Figure 2-5.
BTN_WEST
(D18)
Figure 2-2:
UCF Constraints for Slide Switches
Rotary Push Button Switch
BTN_NORTH
(V4)
ROT_A: (K18)
ROT_B: (G18)
ROT_CENTER: (V16)
Requires an internal pull-up
Requires an internal pull-up
Requires an internal pull-down
BTN_EAST
(H13)
BTN_SOUTH
(K17)
Notes:
1. All BTN_* push-button inputs require an internal pull-down resistor.
2. BTN_SOUTH is also used as a soft reset in some FPGA applications.
Figure 2-3:
Four Push-Button Switches Surround Rotary Push-Button Switch
UG230_c2_02_021206
Operation
Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 2-4.
Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the
button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the
UCF. There is no active debouncing circuitry on the push button.
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Rotary Push-Button Switch
3.3V
Figure 2-4:
Push-Button Switches Require an Internal Pull-Down Resistor in FPGA
In some applications, the BTN_SOUTH push-button switch is also a soft reset that
selectively resets functions within the FPGA.
UCF Location Constraints
Figure 2-5 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
Figure 2-5:
Push Button
FPGA I/O Pin
Input Pin
UCF Constraints for Push-Button Switches
BTN_* Signal
UG230_c2_03_021206
Rotary Push-Button Switch
Locations and Labels
The rotary push-button switch is located in the center of the four individual push-button
switches, as shown in Figure 2-3. The switch produces three outputs. The two shaft
encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.
Operation
The rotary push-button switch integrates two different functions. The switch shaft rotates
and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a
push-button switch.
Push-Button Switch
Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to
3.3V, as shown in Figure 2-6. Use an internal pull-down resistor within the FPGA pin to
generate a logic Low. Figure 2-9 shows how to specify a pull-down resistor within the UCF.
There is no active debouncing circuitry on the push button.
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Chapter 2:
Switches, Buttons, and Knob
Rotary / Push Button
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3.3V
Figure 2-6:
Push-Button Switches Require Internal Pull-up Resistor in FPGA Input
FPGA I/O Pin
ROT_CENTER Signal
UG230_c2_05_021206
Pin
Rotary Shaft Encoder
In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft.
Rotating the shaft then operates two push-button switches, as shown in Figure 2-7.
Depending on which way the shaft is rotated, one of the switches opens before the other.
Likewise, as the rotation continues, one switch closes before the other. However, when the
shaft is stationary, also called the detent position, both switches are closed.
A pull-up resistor in each input pin
generates a ‘1’ for an open switch.
See the UCF file for details on
specifying the pull-up resistor.
A=‘0’
FPGA
Vcco
Vcco
Rotary Shaft
Encoder
GND
Figure 2-7:
B=‘1’
Basic example of rotary shaft encoder circuitry
UG230_c2_06_030606
Closing a switch connects it to ground, generating a logic Low. When the switch is open, a
pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints
in Figure 2-9 describe how to define the pull-up resistor.
The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the
mechanical switching noise on the inputs, also called chatter. As shown in Figure 2-8, the
chatter can falsely indicate extra rotation events or even indicate rotations in the opposite
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Discrete LEDs
direction! See the Rotary Encoder Interface reference design in“Related Resources” for an
example.
Rotating RIGHT
A
B
UCF Location Constraints
Detent
Figure 2-8:
Rising edge on ‘A’ when ‘B’ is Low indicates RIGHT (clockwise) rotation
Detent
Switch closing chatter on ‘B’
injects false “clicks” to the LEFT
(’B’ rising edge when ‘A’ is Low)
Switch opening chatter on ‘A’
injects false “clicks” to the RIGHT
UG230_c2_07_030606
Outputs from Rotary Shaft Encoder May Include Mechanical Chatter
Figure 2-9 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
Figure 2-9:
UCF Constraints for Rotary Push-Button Switch
Discrete LEDs
Locations and Labels
The Spartan-3E Starter Kit board has eight individual surface-mount LEDs located above
the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through LED0.
LED7 is the left-most LED, LED0 the right-most LED.
LED7: (F9)
LED6: (E9)
LED5: (D11)
LED4: (C11)
LED3: (F11)
LED2: (E11)
LED1: (E12)
LED0: (F12)
Figure 2-10:
UG230_c2_04_021206
Eight Discrete LEDs
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UG230 (v1.0) March 9, 2006
Chapter 2:
Switches, Buttons, and Knob
Operation
Each LED has one side connected to ground and the other side connected to a pin on the
Spartan-3E device via a 390Ω current limiting resistor. To light an individual LED, drive
the associated FPGA control signal High.
UCF Location Constraints
Figure 2-11 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment, the I/O standard used, the output slew rate, and the output drive
current.
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
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Related Resources
• Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design)
http://www.xilinx.com/s3estarter
Figure 2-11:
UCF Constraints for Eight Discrete LEDs
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Clock Sources
Overview
As shown in Figure 3-1, the Spartan-3E Starter Kit board supports three primary clock
input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo.
• The board includes an on-board 50 MHz clock oscillator.
• Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA
can generate clock signals or other high-speed signals on the SMA-style connector.
• Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket.
Chapter 3
Bank 0, Oscillator Voltage
Controlled by Jumper JP9
On-Board 50 MHz Oscillator
CLK_50MHz: (C9)
Figure 3-1:
Available Clock Inputs
8-Pin DIP Oscillator Socket
CLK_AUX: (B8)
SMA Connector
CLK_SMA: (A10)
UG230_c3_01_030306
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UG230 (v1.0) March 9, 2006
Chapter 3:
Clock Sources
Clock Connections
Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the
top of the FPGA. As shown in Ta bl e 3 -1 , each of the clock inputs also optimally connects to
an associated DCM.
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Table 3-1:
Clock Input FPGA Pin Global Buffer Associated DCM
CLK_50MHZ C9 GCLK10 DCM_X0Y1
Clock Inputs and Associated Global Buffers and DCMs
CLK_AUX B8 GCLK8 DCM_X0Y1
CLK_SMA A10 GCLK7 DCM_X1Y1
Vol tage Control
The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set
for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5V.
50 MHz On-Board Oscillator
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to
±2500 Hz or ±50 ppm.
Auxiliary Clock Oscillator Socket
The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this
socket if the FPGA application requires a frequency other than 50 MHz. Alternatively, use
the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other frequencies from
the on-board 50 MHz oscillator.
SMA Clock Input or Output Connector
To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.
UCF Constraints
The clock input sources require two different types of constraints. The location constraints
define the I/O pin assignments and I/O standards. The period constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.
Location
Figure 3-2 provides the UCF constraints for the three clock input sources, including the
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set
for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.
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NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
Related Resources
Clock Period Constraints
The Xilinx ISE development software uses timing-driven logic placement and routing. Set
the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which
equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to
60%.
# Define clock period for 50 MHz oscillator
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
Related Resources
• Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/
prog_oscillators/go/Resources/TestC2/SG8002JF
Figure 3-2:
Figure 3-3:
UCF Location Constraints for Clock Sources
UCF Clock PERIOD Constraint
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Chapter 3:
Clock Sources
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FPGA Configuration Options
The Spartan-3E Starter Kit board supports a variety of FPGA configuration options:
• Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB interface. The on-board USB-JTAG logic also provides in-system
programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD.
SPI serial Flash and StrataFlash programming are performed separately.
• Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then
configure the FPGA from the image stored in the Platform Flash PROM using Master
Serial mode.
• Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then
configure the FPGA from the image stored in the SPI serial Flash PROM using SPI
mode.
• Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI
Down configuration modes. Further, an FPGA application can dynamically load two
different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode. See the
Spartan-3E data sheet (DS312
) for additional details on the MultiBoot feature.
Chapter 4
Figure 4-1 indicates the position of the USB download/programming interface and the on-
board non-volatile memories that potentially store FPGA configuration images.Figure 4-2
provides additional details on configuration options.
16 Mbit ST Micro SPI Serial Flash
Serial Peripheral Interface (SPI) mode
USB-based Download/Debug Port
Uses standard USB cable
Figure 4-1:
Configuration Options
PROG_B button, Platform Flash PROM, mode pins
128 Mbit Intel StrataFlash
Parallel NOR Flash memory
Byte Peripheral Interface (BPI) mode
UG230_c4_01_022006
Spartan-3E Starter Kit FPGA Configuration Options
Spartan-3E Starter Kit Board User Guide www.xilinx.com 25
UG230 (v1.0) March 9, 2006
Chapter 4:
FPGA Configuration Options
Configuration Mode Jumper Settings (Header J30)
Select between three on-board configuration sources
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DONE Pin LED
Lights up when FPGA successfully configured
4 Mbit Xilinx Platform Flash PROM
Configuration storage for Master Serial mode
PROG_B Push Button Switch
Press and release to restart configuration
64 Macrocell Xilinx XC2C64A CoolRunner CPLD
Controller upper address lines in BPI mode and
Platform Flash chip select (User programmable)
UG230_c4_02_030906
Figure 4-2:
Detailed Configuration Options
The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is userprogrammable.
Configuration Mode Jumpers
As shown in Tab le 4-1 , the J30 jumper block settings control the FPGA’s configuration
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA’s configuration mode and associated configuration memory
source.
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PROG Push Button
Table 4-1:
Spartan-3E Configuration Mode Jumper Settings (Header J30 in
Figure 4-2)
Configuration
Mode
Master Serial 0:0:0 Platform Flash PROM
SPI
(see
Chapter 12,
“SPI Serial
Flash”)
BPI Up
(see
Chapter 11,
“Intel
StrataFlash
Parallel NOR
Flash
PROM”)
Mode Pins
M2:M1:M0 FPGA Configuration Image Source Jumper Settings
1:1:0 SPI Serial Flash PROM starting at
address 0
0:1:0 StrataFlash parallel Flash PROM,
starting at address 0 and
incrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
M0
M1
M2
J30
M0
M1
M2
J30
M0
M1
M2
J30
BPI Down
(see
Chapter 11,
“Intel
StrataFlash
Parallel NOR
Flash
PROM”)
JTAG 0:1:0 Downloaded from host via USB-
PROG Push Button
The PROG push button, shown in Figure 4-2, page 26, forces the FPGA to reconfigure from
the selected configuration memory source. Press and release this button to restart the
FPGA configuration process at any time.
DONE Pin LED
0:1:1 StrataFlash parallel Flash PROM,
starting at address 0x1FF_FFFF and
decrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
JTAG port
M0
M1
M2
J30
M0
M1
M2
J30
The DONE pin LED, shown in Figure 4-2, page 26, lights whenever the FPGA is
successfully configured. If this LED is not lit, then the FPGA is not configured.
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Chapter 4:
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FPGA Configuration Options
Programming the FPGA, CPLD, or Platform Flash PROM via USB
As shown in Figure 4-1, page 25, the Spartan-3E Starter Kit includes embedded USB-based
programming logic and an USB endpoint with a Type B connector. Via a USB cable
connection with the host PC, the iMPACT programming software directly programs the
FPGA, the Platform Flash PROM, or the on-board CPLD. Direct programming of the
parallel or serial Flash PROMs is not presently supported.
Connecting the USB Cable
The kit includes a standard USB Type A/Type B cable, similar to the one shown in
Figure 4-3. The actual cable color might vary from the picture.
USB Type B Connector
Connects to Starter Kit's USB connecto
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USB Type A Connector
Connects to computer's USB connector
UG230_c4_04_030306
Figure 4-3:
Standard USB Type A/Type B Cable
The wider and narrower Type A connector fits the USB connector at the back of the
computer.
After installing the Xilinx software, connect the square Type B connector to the Spartan-3E
Starter Kit board, as shown in Figure 4-4. The USB connector is on the left side of the board,
immediately next to the Ethernet connector. When the board is powered on, the Windows
operating system should recognize and install the associated driver software.
UG230_c4_05_030306
Figure 4-4:
When the USB cable driver is successfully installed and the board is correctly connected to
Connect the USB Type B Connector to the Starter Kit Board Connector
the PC, a green LED lights up, indicating a good connection.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Programming via iMPACT
After successfully compiling an FPGA design using the Xilinx development software, the
design can be downloaded using the iMPACT programming software and the USB cable.
To begin programming, connect the USB cable to the starter kit board and apply power to
the board. Then, double-click Configure Device (iMPACT) from within Project
Navigator, as shown in Figure 4-5.
UG230_c4_06_022406
Figure 4-5:
If the board is connected properly, the iMPACT programming software automatically
recognizes the three devices in the JTAG programming file, as shown in Figure 4-6. If not
already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it.
Right-click the FPGA and select Assign New Configuration File. Select the desired
FPGA configuration file and click OK.
Double-Click to Invoke iMPACT
UG230_c4_07_022406
Figure 4-6:
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UG230 (v1.0) March 9, 2006
Right-Click to Assign a Configuration File to the Spartan-3E FPGA
Chapter 4:
FPGA Configuration Options
If the original FPGA configuration file used the default StartUp clock source, CCLK,
iMPACT issues the warning message shown in Figure 4-7. This message can be safely
ignored. When downloading via JTAG, the iMPACT software must change the StartUP
clock source to use the TCK JTAG clock source.
Figure 4-7:
To start programming the FPGA, right-click the FPGA and select Program. The iMPACT
software reports status during programming process. Direct programming to the FPGA
takes a few seconds to less than a minute, depending on the speed of the PC’s USB port and
the iMPACT settings.
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UG230_c4_08_022406
iMPACT Issues a Warning if the StartUp Clock Was Not CCLK
UG230_c4_09_022406
Figure 4-8:
Right-Click to Program the Spartan-3E FPGA
When the FPGA successfully programs, the iMPACT software indicates success, as shown
in Figure 4-9. The FPGA application is now executing on the board and the DONE pin LED
(see Figure 4-2) lights up.
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Figure 4-9:
Programming the FPGA, CPLD, or Platform Flash PROM via USB
UG230_c4_10_022406
iMPACT Programming Succeeded, the FPGA’s DONE Pin is High
Programming Platform Flash PROM via USB
The on-board USB-JTAG circuitry also programs the Xilinx XCF04S serial Platform Flash
PROM. The steps provided in this section describe how to set up the PROM file and how
to download it to the board to ultimately program the FPGA.
Generating the FPGA Configuration Bitstream File
Before generating the PROM file, create the FPGA bitstream file. The FPGA provides an
output clock, CCLK, when loading itself from an external PROM. The FPGA’s internal
CCLK oscillator always starts at its slowest setting, approximately 1.5 MHz. Most external
PROMs support a higher frequency. Increase the CCLK frequency as appropriate to reduce
the FPGA’s configuration time. The Xilinx XCF04S Platform Flash supports a 25 MHz
CCLK frequency.
Right-click Generator Programming File in the Processes pane, as shown in
Figure 4-10. Left-click Properties.
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Chapter 4:
FPGA Configuration Options
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UG230_c4_11_022706
Figure 4-10:
Set Properties for Bitstream Generator
Click Configuration Options as shown in Figure 4-11. Using the Configuration
Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately
25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK
when finished.
UG230_c4_12_022706
Figure 4-11:
Set CCLK Configuration Rate under Configuration Options
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
To regenerate the programming file, double-click Generate Programming File, as
shown in Figure 4-12.
UG230_c4_13_022706
Figure 4-12:
Double-Click Generate Programming File
Generating the PROM File
After generating the program file, double-click Generate PROM, ACE, or JTAG File
to launch the iMPACT software, as shown in Figure 4-13.
UG230_c4_14_022706
Figure 4-13:
Double-Click Generate PROM, ACE, or JTAG File
After iMPACT starts, double-click PROM File Formatter, as shown in Figure 4-14.
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Chapter 4:
FPGA Configuration Options
Figure 4-14:
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UG230_c4_15_022706
Double-Click PROM File Formatter
Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any
of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of
the directory and the PROM File Name. Click Next > when finished.
UG230_c4_16_022706
Figure 4-15:
Choose the PROM Target Type, the, Data Format, and File Location
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s
from the drop list, as shown in Figure 4-16. Click Add, then click Next >.
UG230_c4_17_022706
Figure 4-16:
Choose the XCF04S Platform Flash PROM
The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish.
UG230_c4_18_022706
Figure 4-17:
Click Finish after Entering PROM Formatter Settings
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 4-18, click OK to start selecting files. Select an FPGA bitstream file
(*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
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Chapter 4:
FPGA Configuration Options
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UG230_c4_19_022706
Figure 4-18:
Enter FPGA Configuration Bitstream File(s)
When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA
bitstream stored in an XCF04S Platform Flash PROM.
UG230_c4_20_022706
Figure 4-19:
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PROM Formatting Completed
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
To generate the actual PROM file, click Operations Æ Generate File as shown in
Figure 4-20.
UG230_c4_21_022706
Figure 4-20:
Click Operations Æ Generate File to Create the Formatted PROM File
The iMPACT software indicates that the PROM file was successfully created, as shown in
Figure 4-21.
UG230_c4_22_022706
Figure 4-21:
PROM File Formatter Succeeded
Programming the Platform Flash PROM
To program the formatted PROM file into the Platform Flash PROM via the on-board USBJTAG circuitry, follow the steps outlined in this subsection.
Place the iMPACT software in the JTAG Boundary Scan mode, either by choosing
Boundary Scan in the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on
the Boundary Scan tab.
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Chapter 4:
FPGA Configuration Options
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UG230_c4_23_022706
Figure 4-22:
Switch to Boundary Scan Mode
Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in
Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File.
Select a previously generated PROM format file and click OK.
UG230_c4_24_022806
Figure 4-23:
Assign the PROM File to the XCF04S Platform Flash PROM
To start programming the PROM, right-click the PROM icon and then click Program..
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
UG230_c4_25_022806
Figure 4-24:
Program the XCF04S Platform Flash PROM
The programming software again prompts for the PROM type to be programmed. Select
xcf04s and click OK, as shown in Figure 4-25.
UG230_c4_26_022806
Figure 4-25:
Select XCF04S Platform Flash PROM
Before programming, choose the programming options available in Figure 4-26. Checking
the Erase Before Programming option erases the Platform Flash PROM completely
before programming, ensuring that no previous data lingers. The Verify option checks
that the PROM was correctly programmed and matches the downloaded configuration
bitstream. Both these options are recommended even though they increase overall
programming time.
The Load FPGA option immediately forces the FPGA to reconfigure after programming
the Platform Flash PROM. The FPGA’s configuration mode pins must be set for Master
Serial mode, as defined in Tab l e 4 -1, p a ge 2 7. Click OK when finished.
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Chapter 4:
FPGA Configuration Options
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UG230_c4_27_022806
Figure 4-26:
PROM Programming Options
The iMPACT software indicates if programming was successful or not. If programming
was successful and the Load FPGA option was left unchecked, push the PROG_B pushbutton switch shown in Figure 4-2, page 26 to force the FPGA to reconfigure from the
newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE
LED, also shown in Figure 4-2, lights up.
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Character LCD Screen
Overview
The Spartan-3E Starter Kit board prominently features a 2-line by 16-character liquid
crystal display (LCD). The FPGA controls the LCD via the 4-bit data interface shown in
Figure 5-1. Although the LCD supports an 8-bit data interface, the Starter Kit board uses a
4-bit data interface to remain compatible with other Xilinx development boards and to
minimize total pin count.
Spartan-3E FPGA Character LCD
Chapter 5
(M15)
(P17)
(R16)
(R15)
(M18)
(L18)
(L17)
SF_D<11>
SF_D<10>
SF_D<9>
SF_D<8>
LCD_E
LCD_RS
LCD_RW
390Ω
390Ω
390Ω
390Ω
DB7
DB6
DB5
DB4
DB[3:0]
E
RS
R/W
Four-bit data
interface
Unused
Intel StrataFlash
D[11:8]
Figure 5-1:
‘1’
Character LCD Interface
CE0SF_CE0
UG230_c5_01_022006
Once mastered, the LCD is a practical way to display a variety of information using
standard ASCII and custom characters. However, these displays are not fast. Scrolling the
display at half-second intervals tests the practical limit for clarity. Compared with the
50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently
controls display timing plus the actual content of the display.
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Chapter 5:
Character LCD Screen
Character LCD Interface Signals
Ta bl e 5 -1 shows the interface character LCD interface signals.
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Table 5-1:
Signal Name FPGA Pin Function
SF_D<11> M15 Data bit DB7 Shared with StrataFlash pins
SF_D<10> P17 Data bit DB6
SF_D<9> R16 Data bit DB5
SF_D<8> R15 Data bit DB4
LCD_E M18 Read/Write Enable Pulse
LCD_RS L18 Register Select
LCD_RW L17 Read/Write Control
Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V.
However, the FPGA’s output levels are recognized as valid Low or High logic levels by the
LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs
provided by the FPGA meet the 5V TTL voltage level requirements.
Character LCD Interface
SF_D<11:8>
0: Disabled
1: Read/Write operation enabled
0: Instruction register during write operations. Busy
Flash during read operations
1: Data for read or write operations
0: WRITE, LCD accepts data
1: READ, LCD presents data
The 390Ω series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a writeonly peripheral and never read from from the display.
Interaction with Intel StrataFlash
As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data
lines SF_D<11:8>. As shown in Tab le 5 -2, the LCD/StrataFlash interaction depends on the
application usage in the design. When the StrataFlash memory is disabled (SF_CE0 =
High), then the FPGA application has full read/write access to the LCD. Conversely, when
LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full
read/write access to the StrataFlash memory
Table 5-2:
SF_CE0 SF_BYTE LCD_RW Operation
1 X X StrataFlash disabled. Full read/write access to LCD.
X X 0 LCD write access only. Full access to StrataFlash.
X 0 X StrataFlash in byte-wide (x8) mode.
Notes:
1. ‘X’ indicates a don’t care, can be either 0 or 1.
LCD/StrataFlash Control Interaction
Upper data lines
are not used. Full access to both LCD and StrataFlash.
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If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA
application has full simultaneous read/write access to both the LCD and the StrataFlash
memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data
lines.
UCF Location Constraints
Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin
assignment and the I/O standard used.
NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# The LCD four-bit data interface is shared with the StrataFlash.
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
UCF Location Constraints
LCD Controller
Memory Map
DD RAM
Figure 5-2:
UCF Location Constraints for the Character LCD
The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is
functionally equivalent with the following devices.
• Samsung S6A0069X
or KS0066U
• Hitachi HD44780
• SMOS SED1278
The controller has three internal memory regions, each with a specific purpose. The
display must be initialized before accessing any of these memory regions.
The Display Data RAM (DD RAM) stores the character code to be displayed on the screen.
Most applications interact primarily with DD RAM. The character code stored in a DD
RAM location references a specific character bitmap stored either in the predefined CG
ROM character set or in the user-defined CG RAM character set.
Figure 5-3shows the default address for the 32 character locations on the display. The
upper line of characters is stored between addresses 0x00 and 0x0F. The second line of
characters is stored between addresses 0x40 and 0x4F.
Character Display Addresses
1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 … 27
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 … 67
2
1234567891011121314151617…40
Figure 5-3:
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DD RAM Hexadecimal Addresses (No Display Shifting)
Undisplayed
Addresses
Chapter 5:
Character LCD Screen
Physically, there are 80 total character locations in DD RAM with 40 characters available
per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other
non-display data. Alternatively, these locations can also store characters that can only
displayed using controller’s display shifting functions.
The Set DD RAM Address command initializes the address counter before reading or
writing to DD RAM. Write DD RAM data using the Write Data to CG RAM or DD RAM
command, and read DD RAM using the Read Data from CG RAM or DD RAM command.
The DD RAM address counter either remains constant after read or write operations, or
auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
Mode Set command.
CG ROM
The Character Generator ROM (CG ROM) contains the font bitmap for each of the
predefined characters that the LCD screen can display, shown in Figure 5-4. The character
code stored in DD RAM for each character location subsequently references a position with
the CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM
location displays the character ‘S’. The upper nibble of 0x53 equates to DB[7:4]=”0101”
binary and the lower nibble equates to DB[3:0] = “0011” binary. As shown in Figure 5-4, the
character ‘S’ appears on the screen.
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English/Roman characters are stored in CG ROM at their equivalent ASCII code address.
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LCD Controller
Lower Data Nibble
DB7
Upper Data Nibble
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Figure 5-4:
LCD Character Set
UG230_c5_02_030306
The character ROM contains the ASCII English character set and Japanese kana characters.
The controller also provides for eight custom character bitmaps, stored in CG RAM. These
eight custom characters are displayed by storing character codes 0x00 through 0x07 in a
DD RAM location.
CG RAM
The Character Generator RAM (CG RAM) provides space to create eight custom character
bitmaps. Each custom character location consists of a 5-dot by 8-line bitmap, as shown in
Figure 5-5.
The Set CG RAM Address command initializes the address counter before reading or
writing to CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM
command, and read CG RAM using the Read Data from CG RAM or DD RAM command.
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Chapter 5:
Character LCD Screen
The CG RAM address counter can either remain constant after read or write operations, or
auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
Mode Set command.
Figure 5-5 provides an example, creating a special checkerboard character. The custom
character is stored in the fourth CG RAM character location, which is displayed when a
DD RAM location is 0x03. To write the custom character, the CG RAM address is first
initialized using the Set CG RAM Address command. The upper three address bits point to
the custom character location. The lower three address bits point to the row address for the
character bitmap. The Write Data to CG RAM or DD RAM command is used to write each
character bitmap row. A ‘1’ lights a bit on the display. A ‘0’ leaves the bit unlit. Only the
lower five data bits are used; the upper three data bits are don’t care positions. The eighth
row of bitmap data is usually left as all zeros to accommodate the cursor.
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
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Upper Nibble Lower Nibble
Write Data to CG RAM or DD RAM
Table 5-3:
Character Address Row Address
011000
011001
011010
011011
011100
011101
011110
011111
Figure 5-5:
Example Custom Checkerboard Character with Character Code 0x03
Command Set
Ta bl e 5 -3 summarizes the available LCD controller commands and bit definitions. Because
the display is set up for 4-bit operation, each 8-bit command is sent as two 4-bit nibbles.
The upper nibble is transferred first, followed by the lower nibble.
LCD Character Display Command Set
Function
LCD_RS
LCD_RW
Don’t Care Character Bitmap
- - -01010
- - - 10101
- - -01010
- - - 10101
- - -01010
- - - 10101
- - -01010
- - - 00000
Upper Nibble Lower Nibble
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Clear Display 000000 0 0 0 1
Return Cursor Home 000000 0 0 1
Entry Mode Set 000000 0 1I/DS
Display On/Off 000000 1 D C B
Cursor and Display Shift 000001S/CR/L
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-
- -
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LCD Controller
Table 5-3:
Function Set 000010 1 0 - -
Set CG RAM Address 0001A5A4A3A2A1A0
Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 A0
Read Busy Flag and Address 0 1 BF A6 A5 A4 A3 A2 A1 A0
Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0
Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0
LCD Character Display Command Set
Function
LCD_RS
(Continued)
DB7
LCD_RW
Upper Nibble Lower Nibble
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Disabled
If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.
Clear Display
Clear the display and return the cursor to the home position, the top-left corner.
This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM
addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option
settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode
Set command.
Execution Time: 82 μs – 1.64 ms
Return Cursor Home
Return the cursor to the home position, the top-left corner. DD RAM contents are
unaffected. Also returns the display being shifted to the original position, shown in
Figure 5-3.
The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its
original status if it was shifted. The cursor or blink move to the top-left character location.
Execution Time: 40 μs – 1.6 ms
Entry Mode Set
Sets the cursor move direction and specifies whether or not to shift the display.
These operations are performed during data reads and writes.
Execution Time: 40 μs
Bit DB1: (I/D) Increment/Decrement
0 Auto-decrement address counter. Cursor/blink moves to left.
1 Auto-increment address counter. Cursor/blink moves to right.
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Chapter 5:
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This bit either auto-increments or auto-decrements the DD RAM and CG RAM address
counter by one location after each Write Data to CG RAM or DD RAM or Read Data from
CG RAM or DD RAM command. The cursor or blink position moves accordingly.
Bit DB0: (S) Shift
0Shifting disabled
1 During a DD RAM write operation, shift the entire display value in the direction
controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant
and the display moves.
Display On/Off
Display is turned on or off, controlling all characters, cursor and cursor position character
(underscore) blink.
Execution Time: 40 μs
Bit DB2: (D) Display On/Off
0 No characters displayed. However, data stored in DD RAM is retained
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1 Display characters stored in DD RAM
Bit DB1: (C) Cursor On/Off
The cursor uses the five dots on the bottom line of the character. The cursor appears as a
line under the displayed character.
0 No cursor
1Display cursor
Bit DB0: (B) Cursor Blink On/Off
0 No cursor blinking
1 Cursor blinks on and off approximately every half second
Cursor and Display Shift
Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor
position or display to the right or left without writing or reading display data.
This function positions the cursor in order to modify an individual character, or to scroll
the display window left or right to reveal additional data stored in the DD RAM, beyond
the 16th character on a line. The cursor automatically moves to the second line when it
shifts beyond the 40th character location of the first line. The first and second line displays
shift at the same time.
When the displayed data is shifted repeatedly, both lines move horizontally. The second
display line does not shift into the first display line.
Execution Time: 40 μs
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LCD Controller
Table 5-4:
DB3
(S/C)
0 0 Shift the cursor position to the left. The address counter is decremented by one.
0 1 Shift the cursor position to the right. The address counter is incremented by one.
10
11
Shift Patterns According to S/C and R/L Bits
DB2
(R/L)
Shift the entire display to the left. The cursor follows the display shift. The
address counter is unchanged.
Shift the entire display to the right. The cursor follows the display shift. The
address counter is unchanged.
Operation
Function Set
Sets interface data length, number of display lines, and character font.
The Starter Kit board supports a single function set with value 0x28.
Execution Time: 40 μs
Set CG RAM Address
Set the initial CG RAM address.
After this command, all subsequent read or write operations to the display are to or from
CG RAM.
Execution Time: 40 μs
Set DD RAM Address
Set the initial DD RAM address.
After this command, all subsequentsubsequent read or write operations to the display are
to or from DD RAM. The addresses for displayed characters appear in Figure 5-3.
Execution Time: 40 μs
Read Busy Flag and Address
Read the Busy flag (BF) to determine if an internal operation is in progress, and read the
current address counter contents.
BF = 1 indicates that an internal operation is in progress. The next instruction is not
accepted until BF is cleared or until the current instruction is allowed the maximum time to
execute.
This command also returns the present value of address counter. The address counter is
used for both CG RAM and DD RAM addresses. The specific context depends on the most
recent Set CG RAM Address or Set DD RAM Address command issued.
Execution Time: 1 μs
Write Data to CG RAM or DD RAM
Write data into DD RAM if the command follows a previous Set DD RAM Address
command, or write data into CG RAM if the command follows a previous Set CG RAM
Address command.
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Chapter 5:
Character LCD Screen
Operation
Four-Bit Data Interface
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After the write operation, the address is automatically incremented or decremented by 1
according to the Entry Mode Set command. The entry mode also determines display shift.
Execution Time: 40 μs
Read Data from CG RAM or DD RAM
Read data from DD RAM if the command follows a previous Set DD RAM Address
command, or read data from CG RAM if the command follows a previous Set CG RAM
Address command.
After the read operation, the address is automatically incremented or decremented by 1
according to the Entry Mode Set command. However, a display shift is not executed
during read operations.
Execution Time: 40 μs
LCD_RS
SF_D[11:8]
LCD_RW
LCD_E
The board uses a 4-bit data interface to the character LCD.
Figure 5-6 illustrates a write operation to the LCD, showing the minimum times allowed
for setup, hold, and enable pulse length relative to the 50 MHz clock (20 ns period)
provided on the board.
CLOCK
0 = Command, 1 = Data
Valid Data
230 ns
Upper
4 bits
LCD_RS
SF_D[11:8]
LCD_RW
LCD_E
40 ns 10 ns
Lower
4 bits
1 μs 40 μs
Figure 5-6:
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The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write
(LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E
goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12
or more clock cycles at 50 MHz.
In many applications, the LCD_RW signal can be tied Low permanently because the FPGA
generally has no reason to read information from the display.
Transferring 8-Bit Data over the 4-Bit Interface
After initializing the display and establishing communication, all commands and data
transfers to the character display are via 8 bits, transferred using two sequential 4-bit
operations. Each 8-bit transfer must be decomposed into two 4-bit transfers, spaced apart
by at least 1 μs, as shown in Figure 5-6. The upper nibble is transferred first, followed by
the lower nibble. An 8-bit write operation must be spaced least 40 μs before the next
communication. This delay must be increased to 1.64 ms following a Clear Display
command.
Initializing the Display
After power-on, the display must be initialized to establish the required communication
protocol. The initialization sequence is simple and ideally suited to the highly-efficient 8bit PicoBlaze
for more complex control or computation beyond simply driving the display.
embedded controller. After initialization, the PicoBlaze controller is available
Operation
Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use the
four-bit data interface to the LCD as follows:
• Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
• Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
• Wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
• Wait 4 0 μs or longer, which is 2,000 clock cycles at 50 MHz.
• Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
• Wait 4 0 μs or longer, which is 2,000 clock cycles at 50 MHz.
Display Configuration
After the power-on initialization is completed, the four-bit interface is now established.
The next part of the sequence configures the display:
• Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3E Starter Kit board.
• Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
• Issue a Display On/Off command, 0x0C, to turn the display on and disables the
cursor and blinking.
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Chapter 5:
Character LCD Screen
• Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles)
after issuing this command.
Writing Data to the Display
To write data to the display, specify the start address, followed by one or more data values.
Before writing any data, issue a Set DD RAM Address command to specify the initial 7-bit
address in the DD RAM. See Figure 5-3 for DD RAM locations.
Write data to the display using a Write Data to CG RAM or DD RAM command. The 8-bit
data value represents the look-up address into the CG ROM or CG RAM, shown in
Figure 5-4. The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to
represent the associated character.
If the address counter is configured to auto-increment, as described earlier, the application
can sequentially write multiple character codes and each character is automatically stored
and displayed in the next available location.
Continuing to write characters, however, eventually falls off the end of the first display
line. The additional characters do not automatically appear on the second line because the
DD RAM map is not consecutive from the first line to the second.
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Disabling the Unused LCD
If the FPGA application does not use the character LCD screen, drive the LCD_E pin Low
to disable it. Also drive the LCD_RW pin Low to prevent the LCD screen from presenting
data.
Related Resources
• Initial Design for Spartan-3E Starter Kit (Reference Design)
http://www.xilinx.com/s3estarter
• PowerTip PC1602-D Character LCD (Basic Electrical and Mechanical Data)
http://www.powertipusa.com/pdf/pc1602d.pdf
• Sitronix ST7066U Character LCD Controller
http://www.sitronix.com.tw/sitronix/product.nsf/Doc/ST7066U?OpenDocument
• Detailed Data Sheet on PowerTip Character LCD
http://www.rapidelectronics.co.uk/images/siteimg/57-0910e.PDF
• Samsung S6A0069X Character LCD Controller
http://www.samsung.com/Products/Semiconductor/DisplayDriverIC/MobileDDI/BWSTN
/S6A0069X/S6A0069X.htm
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VGA Display Port
The Spartan-3E Starter Kit board includes a VGA display port via a DB15 connector.
Connect this port directly to most PC monitors or flat-panel LCDs using a standard
monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along
the top of the board.
Chapter 6
1
2
3
4
5
6
7
8
9
10
Pin 5
Pin 10
Pin 15
DB15
Connector
11
12
13
14
15
DB15 VGA Connector
(front view)
Red
Green
Blue
Horizontal Sync
Vertical Sync
Pin 1
Pin 6
Pin 11
270Ω
270Ω
270Ω
82.5Ω
82.5Ω
(H14)
VGA_RED
(H15)
VGA_GREEN
(G15)
VGA_BLUE
(F15)
VGA_HSYNC
(F14)
VGA_VSYNC
(xx) = FPGA pin number
GND
Figure 6-1:
The Spartan-3E FPGA directly drives the five VGA signals via resistors. Each color line has
a series resistor, with one bit each for VGA_RED, VGA_GREEN, and VGA_BLUE. The
series resistor, in combination with the 75Ω termination built into the VGA cable, ensures
that the color signals remain in the VGA-specified 0V to 0.7V range. The VGA_HSYNC
and VGA_VSYNC signals using LVTTL or LVCMOS33 I/O standard drive levels. Drive
the VGA_RED, VGA_GREEN, and VGA_BLUE signals High or Low to generate the eight
colors shown in Ta bl e 6 - 1.
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VGA Connections from Spartan-3E Starter Kit Board
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Chapter 6:
VGA Display Port
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Table 6-1:
3-Bit Display Color Codes
VGA_RED VGA_GREEN VGA_BLUE Resulting Color
00 0
00 1
01 0 Green
01 1
10 0 Red
10 1 Magenta
11 0
11 1 White
VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics
Standards Association (VESA). The following VGA system and timing information is
provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode.
For more precise information or for information on higher VGA frequencies, refer to
documents available on the VESA website or other electronics websites (see “Related
Resources,” page 57).
Signal Timing for a 60 Hz, 640x480 VGA Display
Black
Blue
Cyan
Yel lo w
CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode
rays) to display information on a phosphor-coated screen. LCDs use an array of switches
that can impose a voltage across a small amount of liquid crystal, thereby changing light
permittivity through the crystal on a pixel-by-pixel basis. Although the following
description is limited to CRT displays, LCDs have evolved to use the same signal timings
as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs.
Within a CRT display, current waveforms pass through the coils to produce magnetic fields
that deflect electron beams to transverse the display surface in a raster pattern, horizontally
from left to right and vertically from top to bottom. As shown in Figure 6-2, information is
only displayed when the beam is moving in the forward direction—left to right and top to
bottom—and not during the time the beam returns back to the left or top edge of the
display. Much of the potential display time is therefore lost in blanking periods when the
beam is reset and stabilized to begin a new horizontal or vertical display pass.
54 www.xilinx.com Spartan-3E Starter Kit Board User Guide
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Signal Timing for a 60 Hz, 640x480 VGA Display
Current
through the
horizontal
deflection
coil
pixel 0,0
pixel 0,639
640 pixels are displayed each
time the beam traverses the screen
VGA Display
pixel 479,0 pixel 479,639
Stable current ramp: Information is
displayed during this time
Retrace: No
information
is displayed
during
this time
time
HS
To tal horizontal time
Horizontal display time
"front porch"
Horizontal sync signal
retrace time
"front porch"
"back porch"
sets the retrace frequency
UG230_c6_02_021706
Figure 6-2:
CRT Display Timing Example
The display resolution defines the size of the beams, the frequency at which the beam
traces across the display, and the frequency at which the electron beam is modulated.
Modern VGA displays support multiple display resolutions, and the VGA controller
dictates the resolution by producing timing signals to control the raster patterns. The
controller produces TTL-level synchronizing pulses that set the frequency at which current
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The Spartan-3E Starter Kit board uses three bits per pixel, producing
one of the eight possible colors shown in Ta bl e 6 -1 . The controller indexes into the video
data buffer as the beams move across the display. The controller then retrieves and applies
video data to the display at precisely the time the electron beam is moving across a given
pixel.
Spartan-3E Starter Kit Board User Guide www.xilinx.com 55
UG230 (v1.0) March 9, 2006
Chapter 6:
VGA Display Port
As shown in Figure 6-2, the VGA controller generates the horizontal sync (HS) and vertical
sync (VS) timings signals and coordinates the delivery of video data on each pixel clock.
The pixel clock defines the time available to display one pixel of information. The VS signal
defines the refresh frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display’s phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal retrace frequency.
VGA Signal Timing
The signal timings in Ta b le 6 -2 are derived for a 640-pixel by 480-row display using a
25 MHz pixel clock and 60 Hz ± 1 refresh. Figure 6-3 shows the relation between each of
the timing symbols. The timing for the sync pulse width (T
intervals (T
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
) and front and back porch
and TBP) are based on observations from various VGA displays. The front
FP
PW
R
Table 6-2:
640x480 Mode VGA Timing
Vertical Sync Horizontal Sync
Symbol Parameter
Time Clocks Lines Time Clocks
T
Sync pulse time 16.7 ms 416,800 521 32 µs 800
S
T
Display time 15.36 ms 384,000 480 25.6 µs 640
DISP
T
Pulse width 64 µs 1,600 2 3.84 µs 96
PW
T
Front porch 320 µs 8,000 10 640 ns 16
FP
T
Back porch 928 µs 23,200 29 1.92 µs 48
BP
T
S
T
disp
T
pw
Figure 6-3:
VGA Control Timing
T
fp
T
bp
UG230_c6_03_021706
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
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UCF Location Constraints
Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin
assignment, the I/O standard used, the output slew rate, and the output drive current.
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
UCF Location Constraints
Related Resources
• VESA
http://www.vesa.org
• VGA timing information
http://www.epanorama.net/documents/pc/vga_timing.html
Figure 6-4:
UCF Constraints for VGA Display Port
Spartan-3E Starter Kit Board User Guide www.xilinx.com 57
UG230 (v1.0) March 9, 2006
Chapter 6:
VGA Display Port
R
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RS-232 Serial Ports
Overview
As shown in Figure 7-1, the Spartan-3E Starter Kit board has two RS-232 serial ports: a
female DB9 DCE connector and a male DTE connector. The DCE-style port connects
directly to the serial port connector available on most personal computers and
workstations via a standard straight-through serial cable. Null modem, gender changers,
or crossover cables are not required.
Use the DTE-style connector to control other RS-232 peripherals, such as modems or
printers, or perform simple loopback testing with the DCE connector.
Chapter 7
Standard
9-pin serial cable
DCE
DCE
Female DB9
12345
J9 J10
GND
6789
GND
Standard
9-pin serial cable
DTE
Pin 5
Pin 9
DTE
Male DB9
RS-232 Peripheral
TALK/DATA
DB9 Serial Port Connector
(front view)
12345
6789
RS-232 Voltage Translator (IC2)
TALK
RS CS TR RD TD CD
Pin 1
Pin 6
RS232_DCE_RXD
RS232_DCE_TXD
RS232_DTE_TXD
RS232_DTE_RXD
(M13)(U8)(M14)(R7)
Spartan-3E FPGA
UG230_c7_01_022006
Figure 7-1:
RS-232 Serial Ports
Spartan-3E Starter Kit Board User Guide www.xilinx.com 59
UG230 (v1.0) March 9, 2006
Chapter 7:
RS-232 Serial Ports
Figure 7-1 shows the connection between the FPGA and the two DB9 connectors. The
FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device,
which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,
the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A
series resistor between the Maxim output pin and the FPGA’s RXD pin protects against
accidental logic conflicts.
Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR
signals connect together, as shown in Figure 7-1. Similarly, the port’s RTS and CTS signals
connect together.
UCF Location Constraints
Figure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports,
respectively, including the I/O pin assignment and the I/O standard used.
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
R
Figure 7-2:
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
Figure 7-3:
UCF Location Constraints for DTE RS-232 Serial Port
UCF Location Constraints for DCE RS-232 Serial Port
60 www.xilinx.com Spartan-3E Starter Kit Board User Guide
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PS/2 Mouse/Keyboard Port
The Spartan-3E Starter Kit board includes a PS/2 mouse/keyboard port and the standard
6-pin mini-DIN connector, labeled J14 on the board. Figure 8-1 shows the PS/2 connector,
and Table 8-1 shows the signals on the connector. Only pins 1 and 5 of the connector attach
to the FPGA.
270Ω
Chapter 8
PS2_DATA: (G13)
2
4
6
Ta bl e 8-1:
PS/2 DIN Pin Signal FPGA Pin
PS/2 Connector Pinout
1 DATA (PS2_DATA) G13
2 Reserved G13
3 GND GND
1
3
5
Figure 8-1:
270Ω
PS2_CLK: (G14)
UG230_c8_01_021806
PS/2 Connector Location and Signals
4 +5V —
5 CLK (PS2_CLK) G14
6 Reserved G13
Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a
host device, the Spartan-3E FPGA in this case. The PS/2 bus includes both clock and data.
Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit
words that include a start, stop and odd parity bit. However, the data packets are
Spartan-3E Starter Kit Board User Guide www.xilinx.com 61
UG230 (v1.0) March 9, 2006
Chapter 8:
PS/2 Mouse/Keyboard Port
organized differently for a mouse and keyboard. Furthermore, the keyboard interface
allows bidirectional data transfers so the host device can illuminate state LEDs on the
keyboard.
The PS/2 bus timing appears in Tab le 8-2 and Figure 8-2. The clock and data signals are
only driven when data transfers occur; otherwise they are held in the idle state at logic
High. The timing defines signal requirements for mouse-to-host communications and
bidirectional keyboard communications. As shown in Figure 8-2, the attached keyboard or
mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.
R
Keyboard
Ta bl e 8-2:
Symbol Parameter Min Max
T
CK
T
SU
T
HLD
PS/2 Bus Timing
Clock High or Low Time 30 μs 50 μs
Data-to-clock Setup Time 5 μs 25 μs
Clock-to-data Hold Time 5 μs 25 μs
T
T
CK
Edge 0 Edge 10
CK
CLK (PS2C)
T
T
SU
HLD
DATA (PS2D)
'1' stop bit
UG230_c8_02_021806
Figure 8-2:
'0' start bit
PS/2 Bus Timing Waveforms
The keyboard uses open-collector drivers so that either the keyboard or the host can drive
the two-wire bus. If the host never sends data to the keyboard, then the host can use simple
input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all
keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent
whenever the corresponding key is pressed. The scan codes for most keys appear in
Figure 8-3.
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends an “F0” key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different shift and non-shift characters and regardless whether the Shift key is pressed or
not. The host determines which character is intended.
Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore,
they might send more than one scan code. When an extended key is released, an “E0 F0”
key-up code is sent, followed by the scan code.
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Keyboard
ESC
76
` ~
0E
TA B
0D
Caps Lock
58
Shift
12
Ctrl
14
F105F206F304F4
0C
1 !162 @1E3 #264 $255 %
2E
Q
15W1DE24R2DT2C
A
1CS1BD23F2BG34
Z
1ZX22C21V2AB32
Alt
11
Figure 8-3:
F503F60BF783F8
0A
6 ^367 &3D8 *
9 (460 )45- _4E= +
3E
Y
35U3CI43O44P4D
H
33J3BK42L4B
N
, <41> .49/ ?
31M3A
Space
29
PS/2 Keyboard Scan Codes
F901F1009F1178F12
07
Back Space
; :
4C
55
[ {54] }
' "
52
5B
66
\ |
5D
Enter
5A
Shift
4A
Alt
E0 11
59
Ctrl
E0 14
UG230_c8_03_021806
The host can also send commands and data to the keyboard. Ta b le 8 -3 provides a short list
of some often-used commands.
Ta bl e 8-3:
Command Description
Common PS/2 Keyboard Commands
ED Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an
“ED” command by replying with an “FA”, after which the host sends another byte to set LED status. The
bit positions for the keyboard LEDs are shown below. Write a ‘1’ to the specific bit to illuminate the
associated keyboard LED.
E0 75
E0 74
E0 6B
E0 72
765432 1 0
Ignored Caps Lock Num Lock Scroll Lock
EE Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”.
F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after
which the host sends a second byte to set the repeat rate.
FE Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.
FF Reset. Resets the keyboard.
The keyboard sends commands or data to the host only when both the data and clock lines
are High, the Idle state.
Because the host is the bus master, the keyboard checks whether the host is sending data
before driving the bus. The clock line can be used as a clear to send signal. If the host pulls
the clock line Low, the keyboard must not send any data until the clock is released.
The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by
eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’
stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to
30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8-2.
Spartan-3E Starter Kit Board User Guide www.xilinx.com 63
UG230 (v1.0) March 9, 2006
Chapter 8:
Mouse
PS/2 Mouse/Keyboard Port
A mouse generates a clock and data signal when moved; otherwise, these signals remain
High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit
words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits
(LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data
transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21,
and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in
Figure 8-4. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.
Mouse status byte X direction byte Y direction byte
R
L R 0 1 XS YS XV YV P X0 X1 X2 X3 X4 X5 X6 X7 P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P
0 11
Idle state Idle state
Start bit
10 10
Stop bit Stop bit Stop bit
Start bit
Figure 8-4:
Start bit
UG230_c8_04_021806
PS/2 Mouse Transaction
A PS/2-style mouse employs a relative coordinate system (see Figure 8-5), wherein
moving the mouse to the right generates a positive value in the X field, and moving to the
left generates a negative value. Likewise, moving the mouse up generates a positive value
in the Y field, and moving it down represents a negative value. The XS and YS bits in the
status byte define the sign of each value, where a ‘1’ indicates a negative value.
+Y values
(XS=1) (XS=0)
(YS=0)
+X values-X values
Figure 8-5:
-Y values
The Mouse Uses a Relative Coordinate System to Track Movement
(YS=1)
UG230_c8_05_021806
The magnitude of the X and Y values represent the rate of mouse movement. The larger the
value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when
the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates
when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat
every 50 ms or so.
The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates
that the associated mouse button is being pressed.
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Vol tage Supply
The PS/2 port on the Spartan-3E Starter Kit board is powered by 5V. Although the
Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using
series current-limiting resistors, as shown in Figure 8-1.
UCF Location Constraints
Figure 8-6 provides the UCF constraints for the PS/2 port connecting, including the I/O
pin assignment and the I/O standard used.
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
Voltage Supply
Related Resources
• PS/2 Mouse/Keyboard Protocol
http://www.computer-engineering.org/ps2protocol/
• PS/2 Keyboard Interface
http://www.computer-engineering.org/ps2keyboard/
• PS/2 Mouse Interface
http://www.computer-engineering.org/ps2mouse/
Figure 8-6:
UCF Location Constraints for PS/2 Port
Spartan-3E Starter Kit Board User Guide www.xilinx.com 65
UG230 (v1.0) March 9, 2006
Chapter 8:
PS/2 Mouse/Keyboard Port
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Chapter 9
Digital to Analog Converter (DAC)
The Spartan-3E Starter Kit board includes an SPI-compatible, four-channel, serial Digitalto-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC
with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header,
which uses the Digilent 6-pin Peripheral Module
located immediately above the Ethernet RJ-45 connector, as shown in Figure 9-1.
6-pin DAC Header (J5)
format. The DAC and the header are
Linear Tech LTC2624 Quad DAC
SPI_MOSI: (T4)
SPI_MISO: (N10)
SPI_SCK: (U16)
DAC_CS: (N8)
DAC_CLR: (P8)
UG230_c9_01_030906
Figure 9-1:
Digital-to-Analog Converter and Associated Header
SPI Communication
As shown in Figure 9-2, the FPGA uses a Serial Peripheral Interface (SPI) to communicate
digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous,
character-oriented channel employing a simple four-wire interface. A bus master—the
FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data
(SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus
slave provides serial data (SPI_MISO) back to the bus master.
Spartan-3E Starter Kit Board User Guide www.xilinx.com 67
UG230 (v1.0) March 9, 2006
Chapter 9:
Digital to Analog Converter (DAC)
R
Spartan-3E FPGA
(N10) (T4)
Interface Signals
3.3V
2.5V
SPI_MOSI
(N8)
(U16)
DAC_CLR
(P8)
SPI_MISO
Figure 9-2:
LTC 2624 DAC
REF A
DAC A
REF B
12
DAC B
REF C
12
DAC C
REF D
12
DAC D
12
DAC_CS
SPI_SCK
SDI
CS/LD
SCK
SPI Control Interface
CLR
Digital-to-Analog Connection Schematics
VOUTA
VOUTB
VOUTC
VOUTD
SDO
Header J5
A
B
C
D
GND
VCC
(3.3V)
UG230_c9_02_021806
Ta bl e 9 -1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 9-1:
DAC Interface Signals
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆDAC Serial data: Master Output, Slave Input
DAC_CS N8 FPGAÆDAC Active-Low chip-select. Digital-to-analog
conversion starts when signal returns High.
SPI_SCK U16 FPGAÆDAC Clock
DAC_CLR P8 FPGAÆDAC Asynchronous, active-Low reset input
SPI_MISO N10 FPGAÅDAC Serial data: Master Input, Slave Output
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the DAC to avoid bus contention.
Ta bl e 9 -2 provides the signals and logic values required to disable the other devices.
Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared
with the SPI_MISO signal.
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SPI Communication
Table 9-2:
SPI_SS_B SPI serial Flash 1
AMP_CS Programmable pre-amplifier 1
AD_CONV Analog-to-Digital Converter (ADC) 0
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1
Disabled Devices on the SPI Bus
Signal Disabled Device Disable Value
SPI Communication Details
Figure 9-3 shows a detailed example of the SPI bus timing. Each bit is transmitted or
received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks
rate up to the maximum of 50 MHz. However, check all timing parameters using the
LTC2624 data sheet if operating at or close to the maximum speed.
DAC_CS
SPI_MOSI
31 30 29
SPI_SCK
SPI_MISO Previous 31
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.
Communication Protocol
Figure 9-4 shows the communications protocol required to interface with the LTC2624
DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit
command word consists of a command, an address, followed by data value. As a new
command enters the DAC, the previous 32-bit command word is echoed back to the
master. The response from the DAC can be ignored although it is a useful to confirm
correct communication.
Figure 9-3:
Previous 30 Previous 29
UG230_c9_03_021806
SPI Communication Waveforms
Spartan-3E Starter Kit Board User Guide www.xilinx.com 69
UG230 (v1.0) March 9, 2006
Chapter 9:
Master
Spartan-3E
FPGA
Digital to Analog Converter (DAC)
SPI_MISO
SPI_MOSI
DAC_CS
SPI_SCK
xxxx
Don’t Care
Slave: LTC2624 DAC
12-bit Unsigned
DATA
910
msblsb
a
11876543210
0a1a2a3c0
c
c2c
1
3
COMMAND
Don’t Care
R
3
10
xxxxxxxx
a3a2a1a
0000
0001
0010
0011
1111
Figure 9-4:
SPI Communications Protocol to LTC2624 DAC
The FPGA first sends eight dummy or “don’t care” bits, followed by a 4-bit command. The
most commonly used command with the board is COMMAND[3:0] = “0011”, which
immediately updates the selected DAC output with the specified data value. Following the
command, the FPGA selects one or all the DAC output channels via a 4-bit address field.
Following the address field, the FPGA sends a 12-bit unsigned data value that the DAC
converts to an analog value on the selected output(s). Finally, four additional dummy or
don’t care bits pad the 32-bit command word.
Specifying the DAC Output Voltage
As shown in Figure 9-2, each DAC output level is the analog equivalent of a 12-bit
unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.
The voltage on a specific output is generally described in Equation 9-1. The reference
voltage, V
REFERENCE
3.3V reference voltage and Channels C and D use a 2.5V reference. The reference voltages
themselves have a ±5% tolerance, so there will be slight corresponding variances in the
output voltage.
, is different between the four DAC outputs. Channels A and B use a
ADDRESS
0
DAC A
DAC B
DAC C
DAC D
All
UG230_c9_04_021806
V
OUT
-------------------- -
4096,
V
×=
REFERENCE
Equation 9-1
D 11:0[]
DAC Outputs A and B
Equation 9-2 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 3.3V ± 5%.
D 11:0[]
V
OUTA
-------------------- -
4096,
3.3V 5%±()×=
Equation 9-2
DAC Outputs C and D
Equation 9-3 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 2.5V ± 5%.
D 11:0[]
V
OUTC
70 www.xilinx.com Spartan-3E Starter Kit Board User Guide
-------------------- -
4096,
2.5V 5%±()×=
UG230 (v1.0) March 9, 2006
Equation 9-3
R
UCF Location Constraints
Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin
assignment and the I/O standard used.
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
UCF Location Constraints
Related Resources
• LTC2624 Quad DAC Data Sheet
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170
• PicoBlaze Based D/A Converter Control for the Spartan-3E Starter Kit (Reference
Design)
http://www.xilinx.com/s3estarter
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• Digilent, Inc. Peripheral Modules
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral
Figure 9-5:
UCF Location Constraints for the DAC Interface
Spartan-3E Starter Kit Board User Guide www.xilinx.com 71
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Chapter 9:
Digital to Analog Converter (DAC)
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Analog Capture Circuit
The Spartan-3E Starter Kit board includes a two-channel analog capture circuit, consisting
of a programmable scaling pre-amplifier and an analog-to-digital converter (ADC), as
shown in Figure 10-1. Analog inputs are supplied on the J7 header.
Chapter 10
6-pin ADC Header (J7)
Figure 10-1:
Linear Tech LTC1407A-1 Dual A/D
SPI_SCK: (U16)
AD_CONV: (P11)
SPI_MISO: (N10)
Linear Tech LTC6912-1 Dual Amp
SPI_MOSI: (T4)
AMP_CS: (N7)
SPI_SCK: (U16)
AMP_SHDN: (P7)
AMP_DOUT: (E18)
UG230_c10_01_030306
Two-Channel Analog Capture Circuit
The analog capture circuit consists of a Linear Technology LTC6912-1 programmable preamplifier that scales the incoming analog signal on header J7 (see Figure 10-2). The output
of pre-amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier
and the ADC are serially programmed or controlled by the FPGA.
Spartan-3E Starter Kit Board User Guide www.xilinx.com 73
UG230 (v1.0) March 9, 2006
Chapter 10:
REFAB
(3.3V)
REFCD
(2.5V)
Analog Capture Circuit
Header J7
LTC 6912-1 AMP
R
LTC 1407A-1 ADC
VINA
VINB
GND
VCC
(3.3V)
Spartan-3E FPGA
(N10) (T4)
(E18)
(N7)
(U16)
(P7)
(P11)
REF = 1.65V
SPI_MOSI
AMP_CS
SPI_SCK
AMP_SHDN
AD_CONV
AMP_DOUT
SPI_MISO
Figure 10-2:
A
B
DIN
A GAIN B GAIN
CS/LD
SCK
SPI Control Interface
SHDN
DOUT
32103210 130 ... 130 ...
Detailed View of Analog Capture Circuit
A/D
Channel 0
A/D
Channel 1
CHANNEL 1 CHANNEL 0
SCK
SPI Control Interface
CONV
14
14
SDO
UG230_c10_02_022306
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by Equation 10-1.
1.65V–()
V
IN
----------------------------------- -
D 13:0[]GAIN
× 8192×=
1.25V
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in Table 10-2.
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in Figure 10-2. Consequently, 1.65V is subtracted from the input voltage on
VINA or VINB.
The maximum range of the ADC is ±1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
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Equation 10-1
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Programmable Pre-Amplifier
Finally, the ADC presents a 14-bit, two’s complement digital output. A 14-bit, two’s
complement number represents values between -2
13
scaled by 8192, or 2
.
See “Programmable Pre-Amplifier” to control the GAIN settings on the programmable
pre-amplifier.
The reference design files provide more information on converting the voltage applied on
VINA or VINB to a digital representation (see “Related Resources,” page 79).
Programmable Pre-Amplifier
The LTC6912-1 provides two independent inverting amplifiers with programmable gain.
The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it
maximizes the conversion range of the DAC, namely 1.65 ± 1.25V.
Interface
Ta bl e 1 0- 1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
AMP_CS signal is the active-Low slave select input to the amplifier.
Table 10-1:
Signal FPGA Pin Direction Description
AMP Interface Signals
13
and 213-1. Therefore, the quantity is
SPI_MOSI T4 FPGAÆAD Serial data: Master Output, Slave Input.
AMP_CS N7 FPGAÆAMP Active-Low chip-select. The amplifier gain is
SPI_SCK U16 FPGAÆAMP Clock
AMP_SHDN P7 FPGAÆAMP Active-High shutdown, reset
AMP_DOUT E18 FPGAÅAMP Serial data. Echoes previous amplifier gain
Programmable Gain
Each analog channel has an associated programmable gain amplifier (see Figure 10-2).
Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative
to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage
supply.
The gain of each amplifier is programmable from -1 to -100, as shown in Tab le 1 0- 2 .
Table 10-2:
Gain
Presents 8-bit programmable gain settings, as
defined in Table 10-2.
set when signal returns High.
settings. Can be ignored in most applications.
Programmable Gain Settings for Pre-Amplifier
A3 A2 A1 A0 Input Voltage Range
B3 B2 B1 B0 Minimum Maximum
0 0000
-100010.42.9
-200101.0252.275
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Chapter 10:
Analog Capture Circuit
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Table 10-2:
Programmable Gain Settings for Pre-Amplifier
Gain
-500111.41.9
-1001001.5251.775
-2001011.58751.7125
-5001101.6251.675
-10001111.63751.6625
SPI Control Interface
Figure 10-3 highlights the SPI-based communications interface with the amplifier. The gain
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The
most-significant bit, B3, is sent first.
(Continued)
A3 A2 A1 A0 Input Voltage Range
B3 B2 B1 B0 Minimum Maximum
AMP_DOUT
Spartan-3E
FPGA
Master
SPI_MOSI
AMP_CS
SPI_SCK
Slave: LTC2624-1
0
A1A2A
A
0
3
A Gain B Gain
B
0
B1B2B
7
3
AMP_CS
SPI_SCK
SPI_MOSI
(from FPGA)
AMP_DOUT
(from AMP)
UG230_c10_03_030306
Figure 10-3:
SPI Serial Interface to Amplifier
The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 10-4). The
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
30
30
765432
85 max
Previous 7
Figure 10-4:
65432
All timing is minimum in nanoseconds unless otherwise noted.
SPI Timing When Communicating with Amplifier
5050
UG230_c10_04_022306
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The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
UCF Location Constraints
Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
Analog to Digital Converter (ADC)
Figure 10-5:
UCF Location Constraints for the DAC Interface
Analog to Digital Converter (ADC)
The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.
Interface
Ta bl e 1 0- 3 lists the interface signals between the FPGA and the ADC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 10-3:
Signal FPGA Pin Direction Description
SPI_SCK U16 FPGAÆADC Clock
AD_CONV P11 FPGAÆADC Active-High shutdown and reset.
SPI_MISO N10 FPGAÅADC Serial data: Master Input, Serial Output. Presents
ADC Interface Signals
the digital representation of the sample analog
values as two 14-bit two’s complement binary
values.
SPI Control Interface
Figure 10-6 provides an example SPI bus transaction to the ADC.
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s
complement binary value.
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Chapter 10:
Spartan-3E
FPGA
Master
AD_CONV
Analog Capture Circuit
SPI_MISO
D1D2D
AD_CONV
SPI_SCK
Sample
point
D
0
Z
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
3
Slave: LTC1407A-1 A/D Converter
D5D6D
D
4
Channel 1 Channel 0
7
D
8
D9D10D
D13D
11
12
D
0
D1D2D
D
3
4
Z
D5D6D
7
D
8
D9D10D
Sample
point
R
D13D
11
12
Z
SPI_SCK
SPI_MISO
AD_CONV
SPI_SCK
SPI_MISO
4ns min
3ns
Channel 0 Channel 0Channel 1
Figure 10-6:
Analog-to-Digital Conversion Interface
1313
00
13
UG230_c10_05_030306
Figure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communication to the other SPI peripherals. As shown in Figure 10-6, use a 34-cycle
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
19.6ns min
12
High-Z
AD_CONV
3
Channel 0
13
4
8ns
5
12 11
6
45ns min
SPI_SCK
SPI_MISO
Channel 1
3
32
333130
6ns
2 10
34
High-Z
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
UG230_c10_06_022306
Figure 10-7:
Detailed SPI Timing to ADC
UCF Location Constraints
Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
Figure 10-8:
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UCF Location Constraints for the ADC Interface
UG230 (v1.0) March 9, 2006
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Disable Other Devices on the SPI Bus to Avoid Contention
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the AMP or ADC to avoid bus
contention. Table 10-4 provides the signals and logic values required to disable the other
devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is
shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if
the FPGA is set up for Master Serial mode configuration.
Table 10-4:
SPI_SS_B SPI Serial Flash 1
AMP_CS Programmable Pre-Amplifier 1
DAC_CS DAC 1
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1
Disable Other Devices on SPI Bus
Signal Disabled Device Disable Value
Connecting Analog Inputs
Connect AC signals to VINA or VINB via a DC blocking capacitor.
Related Resources
• Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference
Design)
http://www.xilinx.com/s3estarter
• Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
• LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359
• LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295
Spartan-3E Starter Kit Board User Guide www.xilinx.com 79
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Chapter 10:
Analog Capture Circuit
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Chapter 11
Intel StrataFlash Parallel NOR Flash PROM
As shown in Figure 11-1, the Spartan-3E Starter Kit boards includes a 128 Mbit (16 Mbyte)
Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash
connections are shared with other components on the board.
Intel StrataFlash
SPI Serial Flash
Q
ADC
SDO
DAC
SDO
Platform Flash
D0
Spartan-3E FPGA
LDC0
LDC1
HDC
LDC2
User I/O
User I/O
User I/O
D[7:1] D[7:1]
D[0]
User I/O
A[19:0]
A[23:20]
SF_CE0
SF_OE
SF_WE
SF_BYTE
SF_STS
SF_D<15:12>
SF_D<11:8>
SF_D<7:1>
SPI_MISO
SF_A<24:20>
SF_A<19:0>
CE2
CE1
CE0
OE#
WE#
BYTE#
STS
D[15:12]
D[11:8]
D[0]
A[24:20]
A[19:0]
CoolRunner-II CPLD
Figure 11-1:
[7:4]
Connections to Intel StrataFlash Flash Memory
Character LCD
DB[7:4]
UG230_c11_01_030206
The StrataFlash PROM provides various functions:
• Stores a single FPGA configuration in the StrataFlash device.
• Stores two different FPGA configurations in the StrataFlash device and dynamically
switch between the two using the Spartan-3E FPGA’s MultiBoot feature.
• Stores and executes MicroBlaze processor code directly from the StrataFlash device.
Spartan-3E Starter Kit Board User Guide www.xilinx.com 81
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Chapter 11:
Intel StrataFlash Parallel NOR Flash PROM
• Stores MicroBlaze processor code in the StrataFlash device and shadows the code into
the DDR memory before executing the code.
• Stores non-volatile data from the FPGA.
StrataFlash Connections
Ta bl e 11 -1 shows the connections between the FPGA and the StrataFlash device.
Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration
image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit
StrataFlash. The Spartan-3E Starter Kit board ships with a 128 Mbit device. Address line
SF_A24 is not used.
In general, the StrataFlash device connects to the XC3S500E to support Byte Peripheral
Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not
connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins
during configuration. As described in Ta bl e 11 -1 and Shared Connections, some of the
StrataFlash connections are shared with other components on the board.
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StrataFlash Connections
Table 11-1:
Category
Address
FPGA-to-StrataFlash Connections
StrataFlash
Signal Name
FPGA Pin
Number Function
SF_A24 A11 Shared with XC2C64A CPLD. The CPLD
SF_A23 N11
SF_A22 V12
SF_A21 V13
actively drives these pins during FPGA
configuration, as described in Chapter 16,
“XC2C64A CoolRunner-II CPLD”. Also
connects to FPGA user-I/O pins. SF_A24 is the
same as FX2 connector signal FX2_IO<32>.
SF_A20 T12
SF_A19 V15 Connects to FPGA pins A[19:0] to support the
SF_A18 U15
BPI configuration.
SF_A17 T16
SF_A16 U18
SF_A15 T17
SF_A14 R18
SF_A13 T18
SF_A12 L16
SF_A11 L15
SF_A10 K13
SF_A9 K12
SF_A8 K15
SF_A7 K14
SF_A6 J17
SF_A5 J16
SF_A4 J15
SF_A3 J14
SF_A2 J12
SF_A1 J13
SF_A0 H17
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Chapter 11:
Intel StrataFlash Parallel NOR Flash PROM
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Table 11-1:
Category
Data
FPGA-to-StrataFlash Connections
StrataFlash
Signal Name
FPGA Pin
Number Function
SF_D15 T8 Upper 8 bits of a 16-bit
SF_D14 R8
SF_D13 P6
SF_D12 M16
SF_D11 M15 Signals SF_D<11:8>
SF_D10 P17
halfword when
StrataFlash is
configured for x16
data
(SF_BYTE=High).
Connects to FPGA
user I/O.
-
connect to character
LCD pins DB[7:4].
SF_D9 R16
SF_D8 R15
SF_D7 N9 Upper 7 bits of a data byte or lower 8 bits of a
SF_D6 M9
16-bit halfword. Connects to FPGA pins D[7:1]
to support the BPI configuration.
SF_D5 R9
SF_D4 U9
SF_D3 V9
SF_D2 R10
SF_D1 P10
SPI_MISO N10 Bit 0 of data byte and 16-bit halfword.
Connects to FPGA pin D0/DIN to support the
BPI configuration. Shared with other SPI
peripherals and Platform Flash PROM.
SF_CE0 D16 StrataFlash Chip Enable. Connects to FPGA
pin LDC0 to support the BPI configuration.
SF_WE D17 StrataFlash Write Enable. Connects to FPGA
pin HDC to support the BPI configuration.
SF_OE C18 StrataFlash Chip Enable. Connects to FPGA
pin LDC1 to support the BPI configuration.
Control
SF_BYTE C17 StrataFlash Byte Enable. Connects to FPGA pin
LDC2 to support the BPI configuration.
0: x8 data
1: x16 data
SF_STS B18 StrataFlash Status signal. Connects to FPGA
user-I/O pin.
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Shared Connections
Besides the connections to the FPGA, the StrataFlash memory shares some connections to
other components.
Character LCD
The character LCD uses a four-bit data interface. The display data connections are also
shared with the SF_D<11:8> signals on the StrataFlash PROM. As shown in Ta bl e 11 -2 , the
FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and
LCD_RW signals.
Shared Connections
Table 11-2:
SF_CE0 LCD_RW Function
FPGA Control for StrataFlash and LCD
1 1 The FPGA reads from the character LCD.
0 0 The FPGA accesses the StrataFlash PROM.
Xilinx XC2C64A CPLD
The Xilinx XC2C64A CoolRunner CPLD controls the five upper StrataFlash address lines,
SF_A<24:20> during configuration. The four upper BPI-mode address lines from the
FPGA, A<23:20> are not connected. Instead, four FPGA user-I/O pins connect to the
StrataFlash PROM upper address lines SF_A<23:0>. See Chapter 16, “XC2C64A
CoolRunner-II CPLD” for more information.
The most-significant address line, SF_A<24>, is not physically used on the 16 Mbyte
StrataFlash PROM. It is provided for upward migration to a larger StrataFlash PROM in
the same package footprint. Likewsie, the SF_A<24> signal is also connected to the
FX2_IO<32> signal on the FX2 expansion connector.
SPI Data Line
The least-significant StrataFlash data line, SF_D<0>, is shared with data output signals
from serial SPI peripherals, SPI_MISO, and the serial output from the Platform Flash
PROM as shown in Ta bl e 11- 3. To avoid contention, the FPGA application must ensure that
only one data source is active at any time.
Table 11-3:
Condition Function
FPGA_M2 = Low
FPGA_M1 = Low
FPGA_M0 = Low
INIT_B = High
SF_CE0 = Low
SF_OE = Low
AD_CONV = High
SPI_SCK
DAC_CS = Low
SPI_SCK
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UG230 (v1.0) March 9, 2006
Possible Contention on SPI_MISO (SF_D<0>) Data
Platform Flash outputs data on D0.
StrataFlash outputs data.
Serial data is clocked out of the A/D converter
DAC outputs previous command in response to SPI_SCK transitions.
Chapter 11:
Intel StrataFlash Parallel NOR Flash PROM
UCF Location Constraints
Address
Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the
I/O pin assignment and the I/O standard used.
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
"SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>"
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
R
LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
Data
Figure 11-2:
UCF Location Constraints for StrataFlash Address Inputs
Figure 11-3 provides the UCF constraints for the StrataFlash data pins, including the I/O
pin assignment and the I/O standard used.
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
"SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW ;
Figure 11-3:
UCF Location Constraints for StrataFlash Data I/Os
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Control
Setting the FPGA Mode Select Pins
Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the
I/O pin assignment and the I/O standard used.
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
Figure 11-4:
UCF Location Constraints for StrataFlash Control Pins
Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Ta bl e 11 -4 . See
Table 11-4:
Figure 4-2)
Configuration
Mode
BPI Up 0:1:0 FPGA starts at address 0 and
BPI Down 0:1:1 FPGA starts at address 0xFF_FFFF
Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Mode Pins
M2:M1:M0
FPGA Configuration Image in
increments through address space.
The CPLD controls address lines
A[24:20] during BPI configuration.
and decrements through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
StrataFlash Jumper Settings
M0
M1
M2
J30
M0
M1
M2
J30
Related Resources
• Intel J3 StrataFlash Data Sheet
http://www.intel.com/design/flcomp/products/j3/techdocs.htm#datasheets
• Application Note 827, Intel StrataFlash
®
Memory (J3) to Xilinx Spartan-3E FPGA
Design Guide
http://www.intel.com/design/flcomp/applnots/307257.htm
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Chapter 11:
Intel StrataFlash Parallel NOR Flash PROM
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SPI Serial Flash
The Spartan-3E Starter Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial
Flash, useful in a variety of applications. The SPI Flash provides an alternative means to
configure the FPGA—a new feature of Spartan-3E FPGAs as shown in Figure 12-1. The SPI
Flash is also available to the FPGA after configuration for a variety of purposes, such as:
• Simple non-volatile data storage
• Storage for identifier codes, serial numbers, IP addresses, etc.
• Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM.
Chapter 12
Figure 12-1:
Table 12-1:
Signal FPGA Pin Direction Description
SPI_MOSI T4 FPGAÆSPI Serial data: Master Output, Slave Input
SPI_MISO N10 FPGAÅSPI Serial data: Master Input, Slave Output
SPI_SCK U16 FPGAÆSPI Clock
SPI_SS_B U3 FPGAÆSPI Asynchronous, active-Low slave select input
Spartan-3E FPGAs Have an Optional SPI Flash Configuration Interface
SPI Flash Interface Signals
UCF Location Constraints
Figure 12-2 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.
Spartan-3E FPGA
MOSI/CSI_B
DIN/D0
CCLK
CSO_B
(T4)
(N10)
(U16)
(U3)
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SS_B
STMicro M25P16
SPI Serial Flash
D
Q
C
S
UG230_c15_01_030206
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
Figure 12-2:
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UCF Location Constraints for SPI Flash Connections
Chapter 12:
SPI Serial Flash
Configuring from SPI Flash
To configure the FPGA from SPI Flash, the FPGA mode select pins must be set
appropriately and the SPI Flash must contain a valid configuration image.
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Select SPI Mode using Jumper Settings
Remove the top jumper, insert the bottom two as shown
DONE Pin LED
Lights up when FPGA successfully configured
Jumper JP8 (XSPI)
When programming SPI Flash using XSPI
utility, insert jumper to hold PROG_B pin Low
Header J12 (XSPI Programming)
Jumper J11
PROG_B Push Button Switch
Press and release to restart configuration
UG230_c15_02_030906
Figure 12-3:
Configuration Options for SPI Mode
Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for SPI mode, as shown in Figure 12-4. The location
of the configuration mode jumpers (J30) appears in Figure 12-3.
M0
M1
M2
J30
UG230_c15_03_030206
Figure 12-4:
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Creating an SPI Serial Flash PROM File
The following steps describe how to format an FPGA bitstream for an SPI Serial Flash
PROM.
Setting the Configuration Clock Rate
The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI
serial Flash. Set the Properties for Generate Programming File so that the
Configuration Rate is 12, as shown in Figure 12-5. See “Generating the FPGA
Configuration Bitstream File” in the FPGA Configuration Options chapter for a
more detailed description.
Regenerate the FPGA bitstream programming file with the new settings.
Configuring from SPI Flash
UG230_c15_04_030206
Figure 12-5:
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Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash
Chapter 12:
SPI Serial Flash
Formatting an SPI Flash PROM File
After generating the program file, double-click Generate PROM, ACE, or JTAG File
to launch the iMPACT software, as shown in Figure 12-6.
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UG230_c15_05_030206
Figure 12-6:
Double-Click Generate PROM, ACE, or JTAG File
After iMPACT starts, double-click PROM File Formatter, as shown in Figure 12-7.
UG230_c15_06_030206
Figure 12-7:
Double-Click PROM File Formatter
Choose 3rd Party SPI PROM as the target PROM type, as shown in Figure 12-8. Select
from any of the PROM File Formats; the Intel Hex format (MCS) is popular. The PROM
Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the mostsignificant bit (MSB) first. Enter the Location of the directory and the PROM File Name.
Click Next > when finished.
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Configuring from SPI Flash
UG230_c15_07_030206
Figure 12-8:
Choose the PROM Target Type, the, Data Format, and File Location
The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the
drop list, as shown in Figure 12-9. Click Next >.
UG230_c15_08_030206
Figure 12-9:
Choose 16M
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Chapter 12:
SPI Serial Flash
The PROM Formatter then echoes the settings, as shown in Figure 12-10. Click Finish.
Figure 12-10:
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UG230_c15_09_030206
Click Finish after Entering PROM Formatter Settings
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 12-11, click OK to start selecting files. Select an FPGA bitstream file
(*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
UG230_c15_10_030206
Figure 12-11:
Enter FPGA Configuration Bitstream File(s)
When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 12-12 shows an example for a single XC3S500E FPGA
bitstream stored in an XCF04S Platform Flash PROM.
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Figure 12-12:
PROM Formatting Completed
Configuring from SPI Flash
UG230_c15_11_030206
To generate the actual PROM file, click Operations Æ Generate File as shown in
Figure 12-13.
UG230_c15_12_030206
Figure 12-13:
Click Operations Æ Generate File to Create the Formatted PROM File
As shown in Figure 12-14, the iMPACT software indicates that the PROM file was
successfully created. The PROM Formatter creates an output file based on the settings
shown in Figure 12-8. In this example, the output file is called MySPIFlash.mcs.
UG230_c15_13_030206
Figure 12-14:
PROM File Formatter Succeeded
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Chapter 12:
SPI Serial Flash
Downloading the Design to SPI Flash
There multiple methods to program the SPI Flash, as listed below.
• Use the XSPI programming software provided with XAPP445. Download the SPI
Flash via the parallel port using a JTAG parallel programming cable (not provided
with the kit).
• Use the PicoBlaze based SPI Flash programmer reference designs. Use a terminal
emulator, such as Hyperlink, to download SPI Flash programming data via the PC’s
serial port to the FPGA. The embedded PicoBlaze processor then programs the
attached SPI serial Flash. See “Related Resources,” page 102.
• Via the FPGA’s JTAG chain, use a JTAG tool to program the SPI Flash connected to the
FPGA. See the link to the Universal Scan SPI Flash programming tutorial in “Related
Resources,” page 102.
• Additional programming support will be provided in the ISE 8.2i software.
Downloading the SPI Flash using XSPI
The following steps describe how to download the SPI Flash PROM using the XSPI
programming utility.
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Download and Install the XSPI Programming Utility
Download application note XAPP445 and the associated XSPI programming software (see
“Related Resources,” page 102). Unzip the XSPI software onto the PC.
Attach a JTAG Parallel Programming Cable
The XSPI programming utility uses a JTAG parallel programming cable, such as:
• Xilinx Parallel Cable IV
• Digilent JTAG3 programming cable
These cables are not provided with the Spartan-3E Starter Kit board but can be purchased
separately, either from the Xilinx Online Store or from Digilent, Inc. (see “Related
Resources,” page 102).
First, turn off the power on the Spartan-3E Starter Kit board.
If the USB cable is attached to the board, disconnect it. Simultaneously connecting both the
USB cable and the parallel cable to the PC confuses the iMPACT software.
Connect one end of the JTAG parallel programming cable to the parallel printer port of the
PC.
Connect the JTAG end of the cable to Header J12, as shown in Figure 12-15a. The physical
location of Header J12 is more clearly shown in Figure 12-3, page 90. The J12 header
connects directly to the SPI Flash pins; it is not connected to the JTAG chain.
with flying leads
The JTAG3 cable directly mounts to Header J12. The labels on the JTAG3 cable face toward
the J11 jumpers. If using flying leads, they must be connected as shown in Figure 12-15b
and Ta bl e 1 2- 2. Note the color coding for the leads. The gray INIT lead is left unconnected.
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a) JTAG3 Parallel Connector b) Parallel Cable III or Parallel Cable IV
with Flying Leads
Figure 12-15:
Attaching a JTAG Parallel Programming Cable to the Board
Configuring from SPI Flash
UG230_c15_14_030206
Table 12-2:
Cable Connections to J12 Header
Cable and Labels Connections
J12 Header Label SEL SDI SDO SCK GND VCC
JTAG3 Cable Label TMS TDI TDO TCK GND VCC
Flying Leads Label
TMS/
PROG
TDI/
DIN
TDO/
DONE
TCK/
CCLK
GND/
GND
Insert Jumper on JP8 and Hold PROG_B Low
The JTAG parallel programming cable directly accesses the SPI Flash pins. To avoid signal
contention with the FPGA, ensure that the connecting FPGA pins are high-impedance.
Force the FPGA’s PROG_B pin Low by installing a jumper on JP8, next to the PROG push
button, as shown in Figure 12-16. See Figure 12-3, page 90 to locate jumper JP8 and
surrounding landmarks.
PROG
GND
JP8
DEFAULT
NO JUMPER
PROG
PROG
GND
JP8
DEFAULT
NO JUMPER
PROG
VREF/
VREF
a) No Jumper: FPGA Operational (default) b) Jumper Installed: FPGA Held in
Configuration State, I/Os in High Impedance
UG230_c15_15_030206
Figure 12-16:
Installing the JP8 Jumper Holds the FPGA in Configuration State
Re-apply power to the Spartan-3E Starter Kit board.
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Chapter 12:
SPI Serial Flash
Programming the SPI Flash with the XSPI Software
Open a command prompt or DOS box and change to the XSPI installation directory.
The XSPI installation software also includes a short user guide, in addition to XAPP445.
Ty pe xspi at the prompt to view quick help.
Type the following command at the prompt to program the SPI Flash using the SPIformatted Flash file generated earlier. This verifies that the SPI Flash is indeed an M25P16
SPI Flash and then erases, programs, and finally verifies the Flash.
C:\xspi>xspi -spi_dev m25p16 -spi_epv -mcs -i MySPIFlash.mcs -o output.txt
A disclaimer notice appears on the screen. Press the Enter key to continue. The entire
programming process takes slightly longer than a minute, as shown in Figure 12-17.
-==< Press ENTER to accept notice and continue >==-
Start : Mon Feb 27 13:37:07 2006
==> Checking SPI device [STMicro_M25P16_ver_00100] ID code(s)
- density = [2097152] bytes
= [16777216] bits
- mfg_code = [0x20]
- memory_type = [0x20]
- density_code = [0x15]
+-----------------------------------------+
| Device ID code(s) check ====> [ OK ] |
+-----------------------------------------+
=> Operation: Erase
=> Operation: Program and Verify using file [MySPIFlash.mcs]
Programmed [283776] of [283776] bytes (w/ polling)
Verified [283776] of [283776] bytes (0 errors)
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--> Total byte mismatches [0] (see [temp.txt])
Finish : Mon Feb 27 13:38:22 2006
Elapsed clock time (00:01:15) = 75 seconds
Figure 12-17:
Programming the M25P16 SPI Flash with the XSPI Programming
Utility
After programming the SPI Flash, remove jumper JP8, as shown in Figure 12-16a. If
properly programmed, the FPGA then configures itself from the SPI Flash PROM and the
DONE LED lights. The DONE LED is shown in Figure 12-3.
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Additional Design Details
Figure 12-18 provides additional details of the SPI Flash interface used on the Spartan-3E
Starter Kit board. In most applications, this interface is as simple as that shown in
Figure 12-1. The Spartan-3E Starter Kit board, however, supports of variety of
configuration options and demonstrates additional Spartan-3E capabilities.
Additional Design Details
3.3V
SF_A<17>
SF_A<18>
SF_A<19>
Spartan-3E FPGA
VS2/A17
(T16)
VS1/A18
(U15)
(V15)
VS0/A19
Figure 12-18:
SPI_MOSI
MOSI/CSI_B
DIN/D0
CCLK
CSO_B
User-I/O
(T4)
(N10)
(U16)
(U3)
(R12)
SPI_MISO
SPI_SCK
SPI_SS_B
SPI_ALT_CS_JP11
Jumper J11
Programming
Header J12
SEL
SEL
CSO_B
SDI
SCK
SDO
Additional SPI Flash Interface Design Details
ROM_CS
GND
CSO_B
3.3V
STMicro M25P16
SPI Serial Flash
D
Q
C
S
DAC
AMP
ADC
Platform
Flash
Strata-
Flash
W
HLD
UG230_c15_17_030306
Other devices share SPI bus
Shared SPI Bus with Peripherals
After configuration, the SPI Flash configuration pins are available to the application. On
the Spartan-3E Starter Kit board, the SPI bus is shared by other SPI-capable peripheral
devices, as shown in Figure 12-18. To access the SPI Flash memory after configuration, the
FPGA application must disable the other devices on the shared PCI bus. Table 12-3 shows
the signal names and disable values for the other devices.
Table 12-3:
DAC_CS Digital-to-Analog Converter (DAC) 1
AMP_CS Programmable Pre-Amplifier 1
AD_CONV Analog-to-Digital Converter (ADC) 0
SF_CE0 StrataFlash Parallel Flash PROM 1
FPGA_INIT_B Platform Flash PROM 1
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Disable Other Devices on SPI Bus
Signal Disabled Device Disable Value
Chapter 12:
SPI Serial Flash
Other SPI Flash Control Signals
The M25P16 SPI Flash has two additional control inputs. The active-Low write protect
input (W) and the active-Low bus hold input (HLD) are unused and pulled High via an
external pull-up resistor.
Variant Select Pins, VS[2:0]
When in SPI configuration mode, the FPGA samples the value on three pins, labeled
VS[2:0], to determine which SPI read command to issue to the SPI Flash. For the M25P16
Flash, VS[2:0]=<1:1:1> issues the correct command sequence. The VS[2:0] pins are pulled
High externally via pull-up resistors to 3.3V. The VS[2:0] pins are also parallel NOR Flash
address lines A[19:17] in the FPGA’s BPI configuration mode and these signals also
connect to the StrataFlash parallel Flash PROM. After SPI configuration, the VS[2:0] pins
become user-programmable I/O pins, allowing full access to the StrataFlash PROM,
despite that the FPGA configured from SPI Flash.
Jumper Block J11
In SPI configuration mode, the FPGA selects the attached SPI Flash by asserting the CSO_B
pin Low. On the Spartan-3E Starter Kit board, the CSO_B pin drives into the jumper J11
block. This jumper block provides the option to move the on-board SPI Flash to a different
select line (SPI_ALT_CS_JP11). This way, a different SPI Flash device can be tested by
changing the JP11 jumper settings and connecting the alternate SPI Flash on Header JP12.
By default, both jumpers are inserted on jumper block header J11.
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Programming Header J12
As shown in Figure 12-15, page 97, Header J12 accepts a JTAG parallel programming cable
to program the on-board SPI Flash.
Multi-Package Layout
STMicroelectronics was rather clever when they defined the package layout for the
M25Pxx SPI serial Flash family. The Spartan-3E Starter Kit board supports all three of the
package types used for the 16 Mbit device, as shown in Figure 12-19. By default, the board
ships with the 8-lead, 8x6 mm MLP package. The multi-package layout also supports the 8pin SOIC package and the 16-pin SOIC package. Pin 1 for the 8-pin SOIC and MLP
packages is located in the top-left corner. However, pin 1 for the 16-pin SOIC package is
located in the top-right corner, because the package is rotated 90
package also have four pins on each side that do not connect on the board. These pins must
be left floating. Why support multiple packages? In a word, flexibility. The multi-package
layout provides ...
• Density migration between smaller- and larger-density SPI Flash PROMs. Not all
SPI Flash densities are available in all packages. The SPI Flash migration strategy
follows nicely with the pinout migration provided by Xilinx FPGAs.
• Consistent configuration PROM layout when migrating between FPGA densities.
The Spartan-3E FPGA’s FG320 package footprint supports the XC3S500E, the
XC3S1200E, and the XC3S1600E FPGA devices without modification. The SPI Flash
multi-package layout allows comparable flexibility in the associated configuration
PROM. Ship the optimally-sized SPI Flash memory for the FPGA mounted on the
board.
°. The 16-pin SOIC
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