Digilent 410-044-10P User Manual

Spartan-3
Starter Kit Board
User Guide

UG130 (v1.1) May 13, 2005

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Spartan-3 Starter Kit Board User Guide
UG130 (v1.1) May 13, 2005

The following table shows the revision history for this document.

Version Revision

04/26/04 1.0 Initial Xilinx release.

06/07/04 1.0.1 Minor modifications for printed release.

07/21/04 1.0.2 Added information on auxiliary serial port connections to Chapter 7.

05/13/05 1.1 Clarified that SRAM IC10 shares eight lower data lines with A1 connector.

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Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: Introduction

Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Component Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 2: Fast, Asynchronous SRAM

Address Bus Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Write Enable and Output Enable Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SRAM Data Signals, Chip Enables, and Byte Enables. . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 3: Four-Digit, Seven-Segment LED Display
Chapter 4: Switches and LEDs

Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 5: VGA Port

Signal Timing for a 60Hz, 640x480 VGA Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Chapter 6: PS/2 Mouse/Keyboard Port

Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 7: RS-232 Port
Chapter 8: Clock Sources
Chapter 9: FPGA Configuration Modes and Functions

FPGA Configuration Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Program Push Button/DONE Indicator LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Chapter 10: Platform Flash Configuration Storage

Platform Flash Jumper Options (JP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

“Default” Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

“Flash Read” Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

“Disable” Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 11: JTAG Programming/Debugging Ports

JTAG Header (J7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5). . . . . . . . . . . . . . . . . . 42

Chapter 12: Power Distribution

AC Wall Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Voltage Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter 13: Expansion Connectors and Boards

Expansion Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

A1 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

A2 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

B1 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Expansion Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Appendix A: Board Schematics
Appendix B: Reference Material for Major Components

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About This Guide

This user guide describes the components and operation of the Spartan™-3 Starter Kit
Board.

Guide Contents

This manual contains the following chapters:

• Chapter 1, “Introduction”

• Chapter 2, “Fast, Asynchronous SRAM”

• Chapter 3, “Four-Digit, Seven-Segment LED Display”

• Chapter 4, “Switches and LEDs”

• Chapter 5, “VGA Port”

• Chapter 6, “PS/2 Mouse/Keyboard Port”

• Chapter 7, “RS-232 Port”

• Chapter 8, “Clock Sources”

• Chapter 9, “FPGA Configuration Modes and Functions”

• Chapter 10, “Platform Flash Configuration Storage”

• Chapter 11, “JTAG Programming/Debugging Ports”

• Chapter 12, “Power Distribution”

• Chapter 13, “Expansion Connectors and Boards”

• Appendix A, “Board Schematics”

• Appendix B, “Reference Material for Major Components”

Preface

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Preface:

About This Guide

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Introduction

The Xilinx Spartan-3 Starter Kit provides a low-cost, easy-to-use development and
evaluation platform for Spartan-3 FPGA designs.

Key Components and Features

Figure 1-1 shows the Spartan-3 Starter Kit board, which includes the following

components and features:

Chapter 1

• 200,000-gate Xilinx Spartan-3

package (XC3S200FT256)

♦ 4,320 logic cell equivalents
♦ Twelve 18K-bit block RAMs (216K bits)
♦ Twelve 18x18 hardware multipliers
♦ Four Digital Clock Managers (DCMs)
♦ Up to 173 user-defined I/O signals

• 2Mbit Xilinx XCF02S Platform Flash

PROM

♦ 1Mbit non-volatile data or application code storage available after FPGA

2

XC3S200 FPGA in a 256-ball thin Ball Grid Array

1

, in-system programmable configuration

configuration

♦ Jumper options allow FPGA application to read PROM data or FPGA

configuration from other sources

3

• 1M-byte of Fast Asynchronous SRAM (bottom side of board, see Figure 1-3)

♦ Two 256Kx16 ISSI IS61LV25616AL-10T 10 ns SRAMs
♦ Configurable memory architecture

- Single 256Kx32 SRAM array, ideal for MicroBlaze

code images

- Two independent 256Kx16 SRAM arrays

♦ Individual chip select per device
♦ Individual byte enables

• 3-bit, 8-color VGA display port

• 9-pin RS-232 Serial Port

♦ DB9 9-pin female connector (DCE connector)
♦ RS-232 transceiver/level translator
♦ Uses straight-through serial cable to connect to computer or workstation serial

6

5

7

port

♦ Second RS-232 transmit and receive channel available on board test points

4

8

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Chapter 1:

Introduction

2

XCF02S 2Mbit

Configuration

PROM

3

Platform Flash

Option Jumpers

256Kx16

10ns SRAM

4

256Kx16

10ns SRAM

5

8-color

VGA Port

6

RS-232 Port

Serial Port

9

PS/2 Port

10

4 Character

7-Segment LED

11

8 Slide Switches

Parallel Cable IV

MutliPro Desktop Tool

JTAG Connector

XC3S200

Spartan-3

7

RS-232

Driver

Digilent Low-Cost

Parallel Port to JTAG

Low-Cost JTAG

Download Cable

1

FPGA

Cable

Connector

23

Included

2224

A1 Expansion

Header

A2 Expansion

Header

B1 Expansion

Header

Configuration

DONE LED

PROGRAM

Push Button

Configuration

Mode Select

Jumpers

Auxiliary

Oscillator Socket

50 MHz

Oscillator

4 Push Buttons

8 LEDs

21

20

19

18

17

16

15

14

13

12

VCCO

Power On

LED

26

Figure 1-1:

Regulator

Xilinx Spartan-3 Starter Kit Board Block Diagram

• PS/2-style mouse/keyboard port

• Four-character, seven-segment LED display

• Eight slide switches

• Eight individual LED outputs

• Four momentary-contact push button switches

27 28 29

3.3V

2.5V

Regulator

5 VDC, 2A Supply

100-240V AC Input

50-60 Hz

11

12

1.2V

Regulator

AC Wall Adapter

Included

25

9

UG130_c1_01_042504

10

13

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Component Locations

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• 50 MHz crystal oscillator clock source (bottom side of board, see Figure 1-3)

• Socket for an auxiliary crystal oscillator clock source

• FPGA configuration mode selected via jumper settings

15

16

14

• Push button switch to force FPGA reconfiguration (FPGA configuration happens

automatically at power-on)

• LED indicates when FPGA is successfully configured

17

18

• Three 40-pin expansion connection ports to extend and enhance the Spartan-3 Starter

Kit Board

♦ See www.xilinx.com/s3boards for compatible expansion cards
♦ Compatible with Digilent, Inc. peripheral boards

https://digilent.us/Sales/boards.cfm#Peripheral

♦ FPGA serial configuration interface signals available on the A2 and B1 connectors

19 20 21

- PROG_B, DONE, INIT_B, CCLK, DONE

• JTAG port for low-cost download cable

• Digilent JTAG download/debugging cable connects to PC parallel port

22 23

23

• JTAG download/debug port compatible with the Xilinx Parallel Cable IV and

MultiPRO Desktop Tool

24

• AC power adapter input for included international unregulated +5V power

supply

• Power-on indicator LED

• On-board 3.3V , 2.5V , and 1.2V regulators

25

26

27 28 29

Component Locations

Figure 1-2 and Figure 1-3 indicate the component locations on the top side and bottom side

of the board, respectively.

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Chapter 1:

Introduction

21

5

VGA

POWER

6

RS-232

20

A1 Expansion Connector A2 Expansion Connector

22

24

2

2Mbit

PlatformFlash

XILINX

XC3S200

FPGA

1

15

10

11

27

3.3V

17

PROG

25

POWER

RS-232

8

Figure 1-2:

31

16

18

DONE

26

7

12

13

Xilinx Spartan-3 Starter Kit Board (Top Side)

3

30

PS/2

9

ug130_c1_02_042704

19

B1 Expansion Connector

14

50

MHz

Figure 1-3:

4

2.5V

SRAM

256Kx16

SRAM

256Kx16

28

29

1.2V

Xilinx Spartan-3 Starter Kit Board (Bottom Side)

5

6

ug130_c1_03_042704

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Fast, Asynchronous SRAM

The Spartan-3 Starter Kit board has a megabyte of fast asynchronous SRAM, surface­mounted to the backside of the board. The memory array includes two 256Kx16 ISSI

IS61LV25616AL-10T

appears in Figure A-8.

10 ns SRAM devices, as shown in Figure 2-1. A detailed schematic

Chapter 2

ISSI

256Kx16 SRAM

(10 ns)

(see Table 2-3)

(see T ab le 2-3)

CE1

UB1

LB1

Spartan-3

FPGA

(see Table 2-4)

(see T ab le 2-4)

(see Table 2-1)

(see T ab le 2-1)

CE2

UB2

LB2

WE

OE

(P7)
(T4)
(P6)

(N5)
(R4)
(P5)
(G3)
(K4)

I/O[15:0]

A[17:0]

CE

IC10

UB
LB
WE
OE

ISSI

256Kx16 SRAM

(10 ns)

I/O[15:0]

A[17:0]

CE

IC11

UB
LB
WE
OE

(xx) = FPGA pin number

UG130_c2_01_042604

Figure 2-1:

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FPGA to SRAM Connections

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The SRAM array forms either a single 256Kx32 SRAM memory or two independent
256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable
(OE#), and address (A[17:0]) signals. However, each device has a separate chip select
enable (CE#) control and individual byte-enable controls to select the high or low byte in
the 16-bit data word, UB and LB, respectively.

The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions. However, it
alternately provides high-density data storage for a variety of applications, such as digital
signal processing (DSP), large data FIFOs, and graphics buffers.

Address Bus Connections

Both 256Kx16 SRAMs share 18-bit address control lines, as shown in Tab le 2-1. These
address signals also connect to the A1 Expansion Connector (see “Expansion Connectors,”

page 47).

Chapter 2:

Fast, Asynchronous SRAM

Table 2-1:

External SRAM Address Bus Connections to Spartan-3 FPGA

Address Bit FPGA Pin A1 Expansion Connector Pin

A17 L3 35

A16 K5 33

A15 K3 34

A14 J3 31

A13 J4 32

A12 H4 29

A11 H3 30

A10 G5 27

A9 E4 28

A8 E3 25

A7 F4 26

A6 F3 23

A5 G4 24

A4 L4 14

A3 M3 12

A2 M4 10

A1 N3 8

A0 L5 6

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Write Enable and Output Enable Control Sign als

Write Enable and Output Enable Control Signals

Both 256Kx16 SRAMs share common output enable (OE#) and write enable (WE#) control
lines, as shown in Ta bl e 2- 2. These control signals also connect to the A1 Expansion
Connector (refer to “Expansion Connectors,” page 47).

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Table 2-2:

External SRAM Control Signal Connections to Spartan-3 FPGA

Signal FPGA Pin A1 Expansion Connector Pin

OE# K4 16

WE# G3 18

SRAM Data Signals, Chip Enables, and Byte Enables

The data signals, chip enables, and byte enables are dedicated connections between the
FPGA and SRAM. Tab l e 2- 3 shows the FPGA pin connections to the SRAM designated
IC10 in Figure A-8. Tab l e 2- 4 shows the FPGA pin connections to SRAM IC11. To disable an
SRAM, drive the associated chip enable pin High.

Table 2-3:

SRAM IC10 Connections

Signal FPGA Pin A1 Expansion Connector Pin

IO15 R1

IO14 P1

IO13 L2

IO12 J2

IO11 H1

IO10 F2

IO9 P8

IO8 D3

IO7 B1 19

IO6 C1 17

IO5 C2 15

IO4 R5 13

IO3 T5 11

IO2 R6 9

IO1 T8 7

IO0 N7 5

CE1 (chip enable IC10) P7

UB1 (upper byte enable IC10) T4

LB1 (lower byte enable IC10) P6

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Chapter 2:

Fast, Asynchronous SRAM

Table 2-4:

SRAM IC11 Connections

Signal FPGA Pin

IO15 N1

IO14 M1

IO13 K2

IO12 C3

IO11 F5

IO10 G1

IO9 E2

IO8 D2

IO7 D1

IO6 E1

IO5 G2

IO4 J1

IO3 K1

IO2 M2

IO1 N2

IO0 P2

CE2 (chip enable IC11) N5

UB2 (upper byte enable IC11) R4

LB2 (lower byte enable IC11) P5

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Chapter 3

Four-Digit, Seven-Segment LED Display

The Spartan-3 Starter Kit board has a four-character, seven segment LED display
controlled by FPGA user-I/O pins, as shown in Figure 3-1. Each digit shares eight common
control signals to light individual LED segments. Each individual character has a separate
anode control input. A detailed schematic for the display appears in Figure A-2.

The pin number for each FPGA pin connected to the LED display appears in parentheses.
To light an individual signal, drive the individual segment control signal Low along with
the associated anode control signal for the individual character. In Figure 3-1, for example,
the left-most character displays the value ‘2’. The digital values driving the display in this
example are shown in blue. The AN3 anode control signal is Low, enabling the control
inputs for the left-most character. The segment control inputs, A through G and DP, drive
the individual segments that comprise the character. A Low value lights the individual
segment, a High turns off the segment. A Low on the A input signal, lights segment ‘a’ of
the display. The anode controls for the remaining characters, AN[2:0] are all High, and
these characters ignore the values presented on A through G and DP.

AN3 (E13) AN2 (F14) AN1 (G14) AN0 (D14)

0

(E14)

a

A

0
0

B
C

1

D

0

E

0

F

1

G

0

DP

1

f

(F13)

(R16)

e c

(N16)

g

d

(P15)

b

(G13)

(N15)

dp dp dp dp

(P16)

f

e c

Figure 3-1:

111

a

b

g

d

a

f

g

e c

d

a

b

f

g

e c

d

UG130_c3_01_042704

b

Seven-Segment LED Digit Control

Ta bl e 3- 1 lists the FPGA connections that drive the individual LEDs comprising a seven-

segment character. Tab le 3- 2 lists the connections to enable a specific character. Ta bl e 3- 3
shows the patterns required to display hexadecimal characters.

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Chapter 3:

Four-Digit, Seven-Segment LED Display

Table 3-1:

FPGA Connections to Seven-Segment Display (Active Low)

Segment FPGA Pin

AE14

BG13

CN15

DP15

ER16

FF13

GN16

DP P16

Table 3-2:

Digit Enable (Anode Control) Signals (Active Low)

Anode Control AN3 AN2 AN1 AN0

FPGA Pin E13 F14 G14 D14

Table 3-3:

Display Characters and Resulting LED Segment Control Values

Character a b c d e f g

0 0000001

1 1001111

2 0010010

3 0000110

4 1001100

5 0100100

6 0100000

7 0001111

8 0000000

9 0000100

A 0001000

b 1100000

C 0110001

d 1000010

E 0110000

F 0111000

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The LED control signals are time-multiplexed to display data on all four characters, as
shown in Figure 3-2. Present the value to be displayed on the segment control inputs and
select the specified character by driving the associated anode control signal Low. Through
persistence of vision, the human brain perceives that all four characters appear
simultaneously, similar to the way the brain perceives a TV display.

AN3

AN2

AN1

AN0

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{A,B,C,D,E,F,G,DP}

Figure 3-2:

Drive Anode Input Low to Light an Individual Character

DISP3 DISP2 DISP1 DISP0

UG130_c3_02_042404

This “scanning” technique reduces the number of I/O pins required for the four
characters. If an FPGA pin were dedicated for each individual segment, then 32 pins are
required to drive four 7-segment LED characters. The scanning technique reduces the
required I/O down to 12 pins. The drawback to this approach is that the FPGA logic must
continuously scan data out to the displays—a small price to save 20 additional I/O pins.

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Chapter 3:

Four-Digit, Seven-Segment LED Display

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Switches and LEDs

Slide Switches

Chapter 4

The Spartan-3 Starter Kit board has eight slide switches, indicated as in Figure 1-2. The
switches are located along the lower edge of the board, toward the right edge. The switches
are labeled SW7 through SW0. Switch SW7 is the left-most switch, and SW0 is the right­most switch. The switches connect to an associated FPGA pin, as shown in Ta bl e 4 -1 . A
detailed schematic appears in Figure A-2.

Table 4-1:

Switch SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0

FPGA Pin K13 K14 J13 J14 H13 H14 G12 F12

When in the UP or ON position, a switch connects the FPGA pin to V
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic
Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board. A 4.7KΩ series resistor provides nominal input protection.

Push Button Switches

The Spartan-3 Starter Kit board has four momentary-contact push button switches,
indicated as in Figure 1-2. These push buttons are located along the lower edge of the
board, toward the right edge. The switches are labeled BTN3 through BTN0. Push button
switch BTN3 is the left-most switch, BTN0 the right-most switch. The push button
switches connect to an associated FPGA pin, as shown in Ta bl e 4- 2. A detailed schematic
appears in Figure A-2.

Slider Switch Connections

13

11

, a logic High.

CCO

Table 4-2:

Push Button BTN3 (User Reset) BTN2 BTN1 BTN0

FPGA Pin L14 L13 M14 M13

Pressing a push button generates a logic High on the associated FPGA pin. Again, there is
no active debouncing circuitry on the push button.

The left-most button, BTN3, is also the default User Reset pin. BTN3 electrically behaves
identically to the other push buttons. However, when applicable, BTN3 resets the provided
reference designs.

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LEDs

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Chapter 4:

Switches and LEDs

The Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above
the push button switches, indicated by in Figure 1-2. The LEDs are labeled LED7

12

through LED0. LED7 is the left-most LED, LED0 the right-most LED. Tab le 4 -3 shows the
FPGA connections to the LEDs.

Table 4-3:

LED Connections to the Spartan-3 FPGA

LED LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

FPGA Pin P11 P12 N12 P13 N14 L12 P14 K12

The cathode of each LED connects to ground via a 270Ω resistor. To light an individual
LED, drive the associated FPGA control signal High, which is the opposite polarity from
lighting one of the 7-segment LEDs.

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