Digilent 210-299P User Manual
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JTAG-HS3 Programming Cable for Xilinx® FPGAs
Revised June 30 , 2014
DOC#: 502-299
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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The JTAG-HS3
Small, complete, all-in-one JTAG
programming/debugging solution for Xilinx FPGAs and
SoCs
Plugs directly into standard Xilinx JTAG header
Separate Vref drives JTAG signal voltages; Vref can be
any voltage between 1.8V and 5V
High-Speed USB2 port that can drive JTAG bus up to
30Mbit/sec (frequency adjustable by user)
Compatible with Xilinx ISE® 14.1 and newer, Xilinx
Vivado 2013.3 and newer
Uses micro_AB USB2 connector
Open drain buffer on pin 14 allows debugging software
to reset the processor core of Xilinx’s Zynq® platform
Figure 2. Xilinx JTAG header. Dual row, 2mm, 14 pin.
Figure 1. Diagram of signal voltages and connections.
VIO: 5V to 1.8V
USB2
Port
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
FPGAJTAG-HS3
GND
VREF
GND
VIO
Features include:
Overview
The JTAG-HS3 programming cable is a high-speed programming/debugging solution for Xilinx FPGAs and SoCs. It is
fully compatible will all Xilinx Tools, and can be seamlessly driven from iMPACT, ChipScope™, EDK, and Vivado™.
The HS3 attaches to target boards using Xilinx’s 2x7, 2mm programming header.
The PC powers the JTAG-HS3 through the USB port and will recognize it as a Digilent programming cable when
connected, even if the cable is not attached to the target board. The HS3 has a separate Vref pin to supply the
JTAG signal buffers. The high speed 24mA three-state buffers allow the HS3 to drive target boards with signal
voltages from 1.8V to 5V and bus speeds up to 30MBit/sec (see Fig. 1). To function correctly, the HS3’s Vref pin
must be tied to the same voltage supply (VCCO_0) that drives the JTAG port on the FPGA.
The JTAG bus can be shared with other devices as the HS3 signals are held in high-impedance, except when
actively driven during programming. The HS3 uses a standard Type-A to Micro-USB cable that attaches to the end
of the module opposite the system board connector. The HS3 is small and light, allowing it to be held firmly in
place by the system board connector (see Fig. 2).
JTAG-HS3 Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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1
3
5
7
9
11
13
2
4
6
8
10
12
14
GND
GND
GND
GND
GND
GND
GND
VREF
TMS
TCK
TDO
TDI
----
SRST
1
3
5
7
9
11
13
2
4
6
8
10
12
14
GND
GND
GND
GND
GND
GND
GND
VCCO_0
TMS
TCK
TDO
TDI
----
PS_SRST_B
Figure 3. JTAG-HS3 pinout.
Figure 4. Xilinx system board header.
Software Support
The JTAG-HS3 has been designed to work seamlessly with Xilinx’s ISE (iMPACT, ChipScope, EDK) and Vivado tool
suites. The most recent versions of ISE and Vivado include all of the drivers, libraries, and plugins necessary to
communicate with the JTAG-HS3. At the time of writing, the following Xilinx software included support for the HS3:
Vivado 2014.1+, Vivado 2013.3+, and ISE 14.1+.
The HS3 is also compatible with ISE 13.1 – 13.4. However, these versions of ISE do not include all of the libraries,
drivers, and plugins necessary to communicate with the HS3. In order to use the JTAG-HS3 with these versions of
ISE, version 2.5.2 or higher of the Digilent Plugin for Xilinx Tools package must be downloaded from the Digilent
website, and the ISE13 plugin must be manually installed as described in the included documentation. The JTAGHS3 is not compatible with Xilinx Vivado 2013.1 or Vivado 2013.2.
In addition to working with the Xilinx Tools, the HS3 is also supported by Digilent’s Adept software and the Adept
SDK (the SDK is available to download free from Digilent’s website). Adept includes a full-featured programming
environment and a set of public APIs that allow user applications to directly drive the JTAG chain. Using the Adept
SDK, custom applications can be created to drive JTAG ports on virtually any device. Please see the Adept SDK
reference manual for more information.
Xilinx Zynq-7000 and SoC Support
The Xilinx Tools occasionally require the processor core of the Zynq-7000 to be reset during debug operations. The
Zynq platform processor has a pin dedicated for this purpose (PS_SRST_B). Driving the PS_SRST_B pin low causes
the processor to reset while maintaining any existing break points and watch points. The JTAG-HS3 is capable of
driving this pin low under the instruction of Xilinx’s SDK during debugging operations. In order for this to work, pin
14 of Xilinx JTAG header on the target board must be connected to the PS_SRST_B pin of the Zynq (see Figs. 3 & 4).
The JTAG-HS3 uses an open drain buffer to drive pin 14 of the Xilinx JTAG header (see Fig. 5). This allows the HS3 to
drive the PS_SRST_B pin when VCC_MIO1 is referenced to a different voltage than VCCO_0 (see Fig. 6).
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