Digilent 210-179P User Manual

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Revision: July 19, 2011
Note: This document applies to REV C of the board.

Overview

The VmodCAM board provides digital imaging
capabilities for any Digilent FPGA system
board with a VHDCI connector. It features two
Aptina MT9D112 2-megapixel CMOS digital
image sensors. The sensors can provide frame
rates from 15 FPS upwards, depending on the
resolution.

Its system-on-a-chip design integrates an
image flow processor and enables selectable
output formats, scaling, and special effects.
The integrated PLL (phase-locked loop) and
microprocessor offer a flexible serial control
interface. The output data is sent on a parallel
bus in processed YCrCb, RGB, or raw Bayer
formats.

Features include:

• two independent Aptina MT9D112 2­megapixel CMOS digital image sensors

• 1600x1200 maximum resolution at 15
FPS

• 63mm inter-camera spacing (stereo
baseline)

• 10-bit raw color depth

• I2C control bus

• Bayer, RGB, YCrCb output formats

• automatic exposure, gain, and white

balance

• powerful image correction algorithms

• image scaling

• output FIFO

• 68-pin female VHDCI connector

Functional Description

The two MT9D112 cameras can be controlled
independently and can acquire two separate,
simultaneous image feeds. They are controlled
by a two-wire interface.

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Each camera has a 2 megapixel color sensor
array in Bayer color filter arrangement. The
sensor readout is 10-bit and supports skipping
or binning rows/columns.

The integrated PLL can generate an internal
clock from the master clock and supports a
wide range of resolutions and frame rates.

The integrated image flow processor applies
correction algorithms to improve image quality.
It can process raw sensor data into RGB or
YCrCb output formats, and crop or scale the
image.

Since some of the processing algorithms
output data in bursts, the parallel output
interface can use a FIFO buffer to provide
constant data rate.

The camera also features a sequencer to
coordinate events triggered by the user.

Operation

The camera systems first need to be properly
configured. This includes not only setting
imaging parameters like resolution or output
format, but PLL configuration and
microprocessor sequencing too. The order in
which these steps are performed is very
important.

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VmodCAM Reference Manual

First, you must set up the power-up and reset
sequence. Then you need to understand the
control interface in order to configure the
cameras. The following sections describe this
in detail.

Power-Up and Reset Sequence

The VmodCAM should only be attached to the
system board once the signals driven by the
system board are defined.

The camera uses the analog and digital supply
voltage rails provided on-board. The power
supplies are on by default, but can be turned
off, by driving the VDD-EN signal low (see
Table 3.)

The power supplies are used by both cameras.
While the cameras do power-on reset
themselves, it’s always a good idea to do a full
reset as part of the controller routine.

Figure 1 Power-Up Sequence

Figure 2 Reset Sequence

The MCLK is important. If the PLL in the
camera is enabled, MCLK should be stable.
Stopping MCLK without respecting the reset
sequence might leave the camera in an
undefined state. This could be the case when
the FPGA is re-configured. Performing a
power-cycle in the first stages of the controller
is recommended.

Description Min Max Unit

t1 VDD-EN negative

100

ms

pulse width

t2 VDD-EN high to

75 us

first MCLK pulse

t3

ROM read time

t6

until first control

6000 MCLK

cycles

byte

t4 Active MCLK

before/after #RST

10 MCLK

cycles

edge

t5 #RST negative

pulse width

Table 1 Power-Up/Reset Timing

30 MCLK

cycles

Control Interface

The two-wire serial interface (SDA, SCL) can
be used to control various parts of the camera.
The camera acts as a slave device.

A typical register write consists of:

• start condition

• 8-bit device address (0x78 for the

MT9D112) + acknowledge bit

• upper byte of 16-bit register address +
acknowledge bit

• lower byte of register address +
acknowledge bit

• upper byte of the 16-bit data +
acknowledge bit

• lower data byte + acknowledge bit

• stop condition.

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