The MC13192 is a short range, low power, 2.4 GHz ISM band transceiver which contains a
complete 802.15.4 physical layer (PHY) modem designed for the IEEE 802.15.4 wireless
standard supporting star and mesh networking.
When combined with an appropriate microcontroller (MCU), the MC13192 provides a cost
effective solution for short-range data links and networks. In terface with t he MCU is
accomplished utilizing a four wire serial peripheral interface (SPI) connection which allows
for the use of a variety of processors. The software and processor can be scaled to fit
applications ranging from simple point-to-point systems, through complete ZigBee™
networking.
For more detailed information on MC13192 operation, refer to the MC13192 Reference Manual, part number MC13192RM/D.
Applications include, but are not limited to, the following:
•Remote control and wire replacement in industrial systems such as wireless sensor
networks
•Factory automation and motor cont rol
•Heating and cooling
•Inventory management and RF ID tagging
Potential consumer applications include:
•Home automation and control
•Human interface devices
•Remote entertainment control
Features
•Wireless toys
The transceiver includes a low noise amplifier, 1.0 mW PA, VCO, full spread-spectrum encoding and
decoding. The device supports 250 kbps O-QPSK data in 5.0 MHz channels, per the IEEE 802.15.4
specification. A Serial Peripheral Interface (SPI) is used for RX and TX data transfer and control.
Freescale Semiconductor, Inc.
1 Features
•Recommended power supply range: 2.0 to 3.4 V
•16 Channels
•0 dBm (Typical), up to 3.6 dBm maximum output power
•Buffered Transmit and Receive D ata Packets for Simplified Use with Low Cost Microcontrollers
•Supports 250 kbps O-QPSK Data in 5.0 MHz Channels and Full Spread-Spectrum Encode and
Decode (Compatible with IEEE Standard 802.15.4)
•Three Power Down Modes for Power Conservation:
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— < 1 µA Off Current
— 3.0 µ A Typical Hibernate Current
— 40 µA Typical Doze Current
•RX sensitivity of -92 dBm (Typical) at 1.0% Packet Error Rate
•Four internal timer comparators are available to reduce MCU resource requirements
•Clock output is available for use by MCU
•Seven General Purpose Input/Output ports (GPIO) are available
Figure 1 shows a simplified block diagram of the MC13192. The MC13192 is an IEEE 802.15.4
transceiver that provides most of the functions required in the Physical Layer (PHY) specification.
Figure 2 shows the basic sy stem bl ock dia gram for the MC1319 2 in an appl icat ion. I nterf ace wit h the I C is
accomplished through a 4-wire Serial Peripheral Interface (SPI). The Medium Access Control (MAC),
drivers, and Network and Application software as required reside on the host processor. The host can be
anything from a simple 8-bit device up to a sophisticated 32-bit processor depending on application
requirements.
3 Data Transfer Modes
The MC13192 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word by word
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When using the Motorola 802.15.4 MAC, only the streaming mode can be used. For proprietary
applications, packet mode is used to conserve MCU resources.
3.1 Packet Structure
Figure 3 shows the packet structure of the MC13192. Payloads of up to 125 bytes are supported. The
MC13192 adds a four byte preamble, a one byte start of frame delimiter (SFD), and a one byte frame
length indicator before the data. A Frame Check Sequence (FCS) is calculated and appended to the end of
the data.
3.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down conversion stages. A Clear Channel Assessment (CCA) can be performed based on the
baseband energy integrated over a specific time interval. The digital back end performs Differential Chip
Detection (DCD), the correlator “de spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK
(O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and frame length are parsed and used. A two-byte FCS is calculated and compar ed to
the FCS value appended to the transmitted data, generating a Cyclical Redundancy Check (CRC) result.
Link Quality is measured over a 64 µs period after the packet preamble and stored in ROM.
If the MC13192 is in packet mode, the data is processed as an entire packet. The MCU is notified that an
entire packet has been received via an interrupt.
If the MC13192 is in streaming mode, the MCU is notified by an interrupt on a word by word basis.
3.3 Transmit Path Description
The transmit path is t he exact r everse of the recei ve path. The data stor ed in RAM is ret rieved or clocked i n
via the SPI, formed into packets per the 802.15.4 PHY, spread, and then up converted to the transmit
frequency.
If the MC13192 is in packet mode, data is processed as an entire packet. The data is loaded into the TX
buffer. The MCU then requests that the MC13192 transmit the data. The MCU is notified that the whole
packet has successfully been transmitted via an interrupt.
MOTOROLAMC13192 Product Preview3
Data Transfer Modes
Freescale Semiconductor, Inc.
In streaming mode, the data is fed to the MC13192 on a word by word basis with an interrupt serving as a
notification that the MC13192 is ready for more data. This continues until the whole packet is transmitted.
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RFIN+
RFIN-
VDDLO2
Crystal1
Crystal2
VDDLO1
PAO+
PAO-
1st IF M ixe r
LNA
IF = 65 MHz
256MHz
Crystal
Osc illator
16MHz
PA
MC13192
Analog Receiver
Frequency
Generation
Analog
Transmitter
2nd IF Mixer
IF = 1 M H z
÷4
Phase Shift Modulator
PMA
Decimation
Filter
AGC
Synthesizer
Baseband
2.45GHz
VCO
Mixer
Programmable
Matched
Filter
Prescaler
MUX
CCA
Transmit
Packet RAM 2
Transmit
Packet RAM 1
FCS
Generation
DCD
Receive
Packet RAM
24 Bit Event Timer
4 Programmable
Timer Comparators
Transmit RAM
Header
Generation
Correlator
Arbiter
Symbol
Synch & Det
Packet
Processor
Receive RAM
Arbiter
Symbol
Generation
Figure 1. MC13192 Simplified Block Diagram
Microcontroller
Control
Logic
Digital Transceiver
IRQ Arbiter
and GPIO
RAM Arbiter
SPI
SPI
Timer
Analog
Power-Up
Control
Logic
Sequence
Manager
(Control Logic)
Regulator
Digital
Regulator L
Digital
Regulator H
Crystal
Regulator
VCO
Regulator
SERIAL
PERIPHERAL
IRQ
Arbiter
Rom (Flash)
RAM
CPUA/D
Application
Network
VDDA
VBATT
VDDINT
VDDD
VDDVCO
RXTXEN
CE
MOSI
MISO
SPICLK
(SPI)
INTERFACE
ATTN
RST
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
IRQ
CLKO
Timer
Voltage
Regulators
Power Up
Management
Buffer RAM
MAC
PHY Driver
Figure 2. System Level Block Diagram
4MC13192 Product PreviewMOTOROLA
Freescale Semiconductor, Inc.
Electrical Characteristics
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4 bytes
Preamble
1 byte1 byte
Start of
Frame
Delimiter
Figure 3. MC13192 Packet Structure
Frame
Length
125 bytes Max
PayloadFCS
4 Electrical Characteristics
4.1 Maximum Ratings
Table 1. Maximum Ratings
RatingSymbolValueUnit
Power Supply VoltageV
Junction Temperature T
Storage Temperature RangeT
BATT, VDDINT
stg
2 bytes
3.6Vdc
J
125°C
-55 to 125°C
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Note: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
or Recommended Operating Conditions tables.
Note: Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFin = 100 V MM,
PAout = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF pins have no ESD protection including PAO+
and PAO -.