Rabbit® 5000 Microprocessor
User’s Manual
019-0168_E
Rabbit 5000 Microprocessor User’s Manual
Part Number 019-0168 • Printed in the U.S.A.
Digi International Inc. © 2013 • All rights reserved.
Digi International Inc. reserves the right to make changes and
improvements to its products without providing notice.
Trademarks
Rabbit® and Dynamic C® are registered trademarks of Digi International Inc.
Windows
The latest revision of this manual is available at www.digi.com.
®
is a registered trademark of Microsoft Corporation.
TABLE OF CONTENTS
Chapter 1. The Rabbit 5000 Processor 13
1.1 Introduction.........................................................................................................................................13
1.2 Features...............................................................................................................................................14
1.3 Block Diagram....................................................................................................................................16
1.4 Basic Specifications............................................................................................................................17
1.5 Comparing Rabbit Microprocessors ...................................................................................................18
Chapter 2. Clocks 21
2.1 Overview.............................................................................................................................................21
2.1.1 Block Diagram ...........................................................................................................................22
2.1.2 Registers .....................................................................................................................................22
2.2 Dependencies ......................................................................................................................................23
2.2.1 I/O Pins ......................................................................................................................................23
2.2.2 Other Registers ...........................................................................................................................23
2.3 Operation ............................................................................................................................................24
2.3.1 Main Clock .................................................................................................................................24
2.3.2 Spectrum Spreader .....................................................................................................................25
2.3.3 Clock Doubler ............................................................................................................................27
2.3.4 32 kHz Clock .............................................................................................................................30
2.4 Register Descriptions ..........................................................................................................................32
Chapter 3. Reset and Bootstrap 37
3.1 Overview.............................................................................................................................................37
3.1.1 Block Diagram ...........................................................................................................................38
3.1.2 Registers .....................................................................................................................................38
3.2 Dependencies ......................................................................................................................................39
3.2.1 I/O Pins ......................................................................................................................................39
3.2.2 Clocks .........................................................................................................................................39
3.2.3 Other Registers ...........................................................................................................................39
3.2.4 Interrupts ....................................................................................................................................39
3.3 Operation ............................................................................................................................................40
3.3.1 Asynchronous Serial Bootstrap ..................................................................................................42
3.3.2 Serial Flash Bootstrap ................................................................................................................42
3.3.3 Parallel Bootstrap .......................................................................................................................43
3.4 Register Descriptions ..........................................................................................................................44
Chapter 4. System Management 45
4.1 Overview.............................................................................................................................................45
4.1.1 Block Diagram ...........................................................................................................................46
4.1.2 Registers .....................................................................................................................................47
4.2 Dependencies ......................................................................................................................................48
4.2.1 I/O Pins ......................................................................................................................................48
4.2.2 Clocks .........................................................................................................................................48
4.2.3 Interrupts ....................................................................................................................................48
Table of Contents
4.3 Operation............................................................................................................................................ 49
4.3.1 Periodic Interrupt ....................................................................................................................... 49
4.3.2 Real-Time Clock ....................................................................................................................... 49
4.3.3 Watchdog Timer ........................................................................................................................ 50
4.3.4 Secondary Watchdog Timer ...................................................................................................... 50
4.4 Register Descriptions ......................................................................................................................... 51
Chapter 5. Memory Management 57
5.1 Overview ............................................................................................................................................ 57
5.1.1 Block Diagram ........................................................................................................................... 60
5.1.2 Registers .................................................................................................................................... 61
5.2 Dependencies ..................................................................................................................................... 62
5.2.1 I/O Pins ...................................................................................................................................... 62
5.2.2 Clocks ........................................................................................................................................ 62
5.2.3 Other Registers .......................................................................................................................... 62
5.2.4 Interrupts .................................................................................................................................... 62
5.3 Operation............................................................................................................................................ 63
5.3.1 Memory Management Unit (MMU) .......................................................................................... 63
5.3.2 Memory Bank Operation ........................................................................................................... 64
5.3.3 Memory Modes ......................................................................................................................... 66
5.3.4 Separate Instruction and Data Space ......................................................................................... 68
5.3.5 Memory Protection .................................................................................................................... 68
5.3.6 Stack Protection ......................................................................................................................... 69
5.4 Register Descriptions ......................................................................................................................... 70
Chapter 6. Interrupts 81
6.1 Overview ............................................................................................................................................ 81
6.2 Operation............................................................................................................................................ 82
6.3 Interrupt Tables .................................................................................................................................. 82
Chapter 7. External Interrupts 85
7.1 Overview ............................................................................................................................................ 85
7.2 Block Diagram ................................................................................................................................... 85
7.2.1 Registers .................................................................................................................................... 86
7.3 Dependencies ..................................................................................................................................... 86
7.3.1 I/O Pins ...................................................................................................................................... 86
7.3.2 Clocks ........................................................................................................................................ 86
7.3.3 Interrupts .................................................................................................................................... 86
7.4 Operation............................................................................................................................................ 86
7.4.1 Example ISR .............................................................................................................................. 87
7.5 Register Descriptions ......................................................................................................................... 88
Chapter 8. Parallel Port A 89
8.1 Overview ............................................................................................................................................ 89
8.1.1 Block Diagram ........................................................................................................................... 89
8.1.2 Registers .................................................................................................................................... 89
8.2 Dependencies ..................................................................................................................................... 90
8.2.1 I/O Pins ...................................................................................................................................... 90
8.2.2 Clocks ........................................................................................................................................ 90
8.2.3 Other Registers .......................................................................................................................... 90
8.2.4 Interrupts .................................................................................................................................... 90
8.3 Operation............................................................................................................................................ 90
8.4 Register Descriptions ......................................................................................................................... 91
Rabbit 5000 Microprocessor User’s Manual
Chapter 9. Parallel Port B 93
9.1 Overview.............................................................................................................................................93
9.1.1 Block Diagram ...........................................................................................................................94
9.1.2 Registers .....................................................................................................................................94
9.2 Dependencies ......................................................................................................................................94
9.2.1 I/O Pins ......................................................................................................................................94
9.2.2 Clocks .........................................................................................................................................94
9.2.3 Other Registers ...........................................................................................................................94
9.2.4 Interrupts ....................................................................................................................................95
9.3 Operation ............................................................................................................................................95
9.4 Register Descriptions ..........................................................................................................................95
Chapter 10. Parallel Port C 97
10.1 Overview...........................................................................................................................................97
10.1.1 Block Diagram .........................................................................................................................98
10.1.2 Registers ...................................................................................................................................98
10.2 Dependencies ....................................................................................................................................99
10.2.1 I/O Pins ....................................................................................................................................99
10.2.2 Clocks .......................................................................................................................................99
10.2.3 Other Registers .........................................................................................................................99
10.2.4 Interrupts ..................................................................................................................................99
10.3 Operation ..........................................................................................................................................99
10.4 Register Descriptions......................................................................................................................100
Chapter 11. Parallel Port D 105
11.1 Overview.........................................................................................................................................105
11.1.1 Block Diagram .......................................................................................................................107
11.1.2 Registers .................................................................................................................................108
11.2 Dependencies ..................................................................................................................................109
11.2.1 I/O Pins ..................................................................................................................................109
11.2.2 Clocks .....................................................................................................................................109
11.2.3 Other Registers .......................................................................................................................109
11.2.4 Interrupts ................................................................................................................................109
11.3 Operation ........................................................................................................................................110
11.4 Register Descriptions......................................................................................................................111
Chapter 12. Parallel Port E 123
12.1 Overview.........................................................................................................................................123
12.1.1 Block Diagram .......................................................................................................................125
12.1.2 Registers .................................................................................................................................126
12.2 Dependencies ..................................................................................................................................126
12.2.1 I/O Pins ..................................................................................................................................126
12.2.2 Clocks .....................................................................................................................................126
12.2.3 Other Registers .......................................................................................................................127
12.2.4 Interrupts ................................................................................................................................127
12.3 Operation ........................................................................................................................................127
12.4 Register Descriptions......................................................................................................................128
Chapter 13. Parallel Port H 143
13.1 Overview.........................................................................................................................................143
13.1.1 Block Diagram .......................................................................................................................144
13.1.2 Registers .................................................................................................................................144
13.2 Dependencies ..................................................................................................................................145
13.2.1 I/O Pins ..................................................................................................................................145
13.2.2 Clocks .....................................................................................................................................145
13.2.3 Other Registers .......................................................................................................................145
13.2.4 Interrupts ................................................................................................................................145
13.3 Operation ........................................................................................................................................145
Table of Contents
13.4 Register Descriptions ..................................................................................................................... 146
Chapter 14. Timer A 149
14.1 Overview ........................................................................................................................................ 149
14.1.1 Block Diagram ....................................................................................................................... 151
14.1.2 Registers ................................................................................................................................ 152
14.2 Dependencies ................................................................................................................................. 152
14.2.1 I/O Pins .................................................................................................................................. 152
14.2.2 Clocks .................................................................................................................................... 152
14.2.3 Other Registers ...................................................................................................................... 152
14.2.4 Interrupts ................................................................................................................................ 153
14.3 Operation........................................................................................................................................ 153
14.3.1 Handling Interrupts ................................................................................................................ 153
14.3.2 Example ISR .......................................................................................................................... 153
14.4 Register Descriptions ..................................................................................................................... 154
Chapter 15. Timer B 157
15.1 Overview ........................................................................................................................................ 157
15.1.1 Block Diagram ....................................................................................................................... 157
15.1.2 Registers ................................................................................................................................ 158
15.2 Dependencies ................................................................................................................................. 158
15.2.1 I/O Pins .................................................................................................................................. 158
15.2.2 Clocks .................................................................................................................................... 158
15.2.3 Other Registers ...................................................................................................................... 158
15.2.4 Interrupts ................................................................................................................................ 158
15.3 Operation........................................................................................................................................ 159
15.3.1 Handling Interrupts ................................................................................................................ 159
15.3.2 Example ISR .......................................................................................................................... 159
15.4 Register Descriptions ..................................................................................................................... 160
Chapter 16. Timer C 163
16.1 Overview ........................................................................................................................................ 163
16.1.1 Block Diagram ....................................................................................................................... 164
16.1.2 Registers ................................................................................................................................ 165
16.2 Dependencies ................................................................................................................................. 166
16.2.1 I/O Pins .................................................................................................................................. 166
16.2.2 Clocks .................................................................................................................................... 166
16.2.3 Other Registers ...................................................................................................................... 166
16.2.4 Interrupts ................................................................................................................................ 166
16.3 Operation........................................................................................................................................ 167
16.3.1 Handling Interrupts ................................................................................................................ 167
16.3.2 Example ISR .......................................................................................................................... 167
16.4 Register Descriptions ..................................................................................................................... 168
Chapter 17. Serial Ports A – D 171
17.1 Overview ........................................................................................................................................ 171
17.1.1 Block Diagram ....................................................................................................................... 173
17.1.2 Registers ................................................................................................................................ 174
17.2 Dependencies ................................................................................................................................. 175
17.2.1 I/O Pins .................................................................................................................................. 175
17.2.2 Clocks .................................................................................................................................... 175
17.2.3 Other Registers ...................................................................................................................... 176
17.2.4 Interrupts ................................................................................................................................ 176
17.3 Operation........................................................................................................................................ 177
17.3.1 Asynchronous Mode ..............................................................................................................177
17.3.2 Clocked Serial Mode ............................................................................................................. 178
Rabbit 5000 Microprocessor User’s Manual
17.4 Register Descriptions......................................................................................................................180
Chapter 18. Serial Ports E – F 187
18.1 Overview.........................................................................................................................................187
18.1.1 Block Diagram .......................................................................................................................188
18.1.2 Registers .................................................................................................................................189
18.2 Dependencies ..................................................................................................................................190
18.2.1 I/O Pins ..................................................................................................................................190
18.2.2 Clocks .....................................................................................................................................190
18.2.3 Other Registers .......................................................................................................................190
18.2.4 Interrupts ................................................................................................................................191
18.3 Operation ........................................................................................................................................192
18.3.1 Asynchronous Mode ..............................................................................................................192
18.3.2 HDLC Mode ..........................................................................................................................192
18.3.3 More on Clock Synchronization and Data Encoding .............................................................193
18.4 Register Descriptions......................................................................................................................197
Chapter 19. Slave Port 203
19.1 Overview.........................................................................................................................................203
19.1.1 Block Diagram .......................................................................................................................204
19.1.2 Registers .................................................................................................................................204
19.2 Dependencies ..................................................................................................................................205
19.2.1 I/O Pins ..................................................................................................................................205
19.2.2 Clocks .....................................................................................................................................205
19.2.3 Interrupts ................................................................................................................................205
19.3 Operation ........................................................................................................................................206
19.3.1 Master Setup ..........................................................................................................................207
19.3.2 Slave Setup .............................................................................................................................207
19.3.3 Master/Slave Communication ................................................................................................208
19.3.4 Slave/Master Communication ................................................................................................208
19.3.5 Handling Interrupts ................................................................................................................208
19.3.6 Example ISR ..........................................................................................................................208
19.3.7 Other Configurations ..............................................................................................................209
19.3.8 Timing Diagrams ...................................................................................................................210
19.4 Register Descriptions......................................................................................................................212
Chapter 20. Analog Components 215
20.1 Overview.........................................................................................................................................215
20.2 Block Diagram................................................................................................................................218
20.2.1 Registers .................................................................................................................................219
20.3 Dependencies ..................................................................................................................................219
20.3.1 I/O Pins ..................................................................................................................................219
20.3.2 Clocks .....................................................................................................................................219
20.4 Operation ........................................................................................................................................220
20.4.1 Fast A/D Converter ................................................................................................................220
20.4.2 Fast D/A Converter ................................................................................................................220
20.4.3 Slow A/D Converter ...............................................................................................................220
20.5 Sample Circuits...............................................................................................................................221
20.6 Register Descriptions......................................................................................................................223
Chapter 21. DMA Channels 229
21.1 Overview.........................................................................................................................................229
21.1.1 Block Diagram .......................................................................................................................232
21.1.2 Registers .................................................................................................................................233
21.2 Dependencies ..................................................................................................................................234
21.2.1 I/O Pins ..................................................................................................................................234
21.2.2 Clocks .....................................................................................................................................234
21.2.3 Interrupts ................................................................................................................................234
21.3 Operation ........................................................................................................................................235
Table of Contents
21.3.1 Handling Interrupts ................................................................................................................ 236
21.3.2 Example ISR .......................................................................................................................... 236
21.3.3 DMA Priority with the Processor .......................................................................................... 236
21.3.4 DMA Channel Priority .......................................................................................................... 238
21.3.5 Buffer Descriptor Modes ....................................................................................................... 238
21.3.5.1 Single Buffer .................................................................................................................. 239
21.3.5.2 Buffer Array ................................................................................................................... 239
21.3.5.3 Linked List ..................................................................................................................... 240
21.3.5.4 Circular Queue ............................................................................................................... 241
21.3.5.5 Linked Array .................................................................................................................. 241
21.3.6 DMA with Peripherals ........................................................................................................... 242
21.3.6.1 DMA with HDLC Serial Ports ......................................................................................242
21.3.6.2 DMA with Ethernet ....................................................................................................... 242
21.3.6.3 DMA with Wi-Fi ........................................................................................................... 242
21.3.6.4 DMA with PWM and Timer C ...................................................................................... 242
21.4 Register Descriptions ..................................................................................................................... 243
Chapter 22. 10/100Base-T Ethernet 257
22.1 Overview ........................................................................................................................................ 257
22.1.1 Block Diagram ....................................................................................................................... 259
22.1.2 Registers ................................................................................................................................ 260
22.2 Dependencies ................................................................................................................................. 262
22.2.1 I/O Pins .................................................................................................................................. 262
22.2.2 Clocks .................................................................................................................................... 262
22.2.3 Other Registers ...................................................................................................................... 262
22.2.4 Interrupts ................................................................................................................................ 263
22.3 Operation........................................................................................................................................ 263
22.3.1 Setup ...................................................................................................................................... 264
22.3.2 Transmit ................................................................................................................................. 264
22.3.3 Receive .................................................................................................................................. 264
22.3.4 Handling Interrupts ................................................................................................................ 265
22.3.5 Multicast Addressing ............................................................................................................. 266
22.4 Register Descriptions ..................................................................................................................... 267
Chapter 23. 802.11b/g Wireless 281
23.1 Overview ........................................................................................................................................ 281
23.1.1 Block Diagram ....................................................................................................................... 282
23.1.2 Registers ................................................................................................................................ 283
23.2 Dependencies ................................................................................................................................. 285
23.2.1 I/O Pins .................................................................................................................................. 285
23.3 Clocks............................................................................................................................................. 286
23.3.1 Other Registers ...................................................................................................................... 286
23.3.2 Interrupts ................................................................................................................................ 286
23.4 Operation........................................................................................................................................ 286
Chapter 24. Input Capture 287
24.1 Overview ........................................................................................................................................ 287
24.1.1 Block Diagram ....................................................................................................................... 288
24.1.2 Registers ................................................................................................................................ 289
24.2 Dependencies ................................................................................................................................. 290
24.2.1 I/O Pins .................................................................................................................................. 290
24.2.2 Clocks .................................................................................................................................... 290
24.2.3 Other Registers ...................................................................................................................... 290
24.2.4 Interrupts ................................................................................................................................ 290
24.3 Operation........................................................................................................................................ 291
24.3.1 Input-Capture Channel .......................................................................................................... 291
24.3.2 Handling Interrupts ................................................................................................................ 291
24.3.3 Example ISR .......................................................................................................................... 291
24.3.4 Capture Mode ........................................................................................................................ 292
Rabbit 5000 Microprocessor User’s Manual
24.3.5 Count Mode ............................................................................................................................292
24.4 Register Descriptions......................................................................................................................293
Chapter 25. Quadrature Decoder 299
25.1 Overview.........................................................................................................................................299
25.1.1 Block Diagram .......................................................................................................................301
25.1.2 Registers .................................................................................................................................301
25.2 Dependencies ..................................................................................................................................302
25.2.1 I/O Pins ..................................................................................................................................302
25.2.2 Clocks .....................................................................................................................................302
25.2.3 Other Registers .......................................................................................................................302
25.2.4 Interrupts ................................................................................................................................302
25.3 Operation ........................................................................................................................................303
25.3.1 Handling Interrupts ................................................................................................................303
25.3.2 Example ISR ..........................................................................................................................303
25.4 Register Descriptions......................................................................................................................304
Chapter 26. Pulse Width Modulator 307
26.1 Overview.........................................................................................................................................307
26.1.1 Block Diagram .......................................................................................................................309
26.1.2 Registers .................................................................................................................................309
26.2 Dependencies ..................................................................................................................................310
26.2.1 I/O Pins ..................................................................................................................................310
26.2.2 Clocks .....................................................................................................................................310
26.2.3 Other Registers .......................................................................................................................310
26.2.4 Interrupts ................................................................................................................................310
26.3 Operation ........................................................................................................................................311
26.3.1 Handling Interrupts ................................................................................................................311
26.3.2 Example ISR ..........................................................................................................................311
26.4 Register Descriptions......................................................................................................................312
Chapter 27. External I/O Control 315
27.1 Overview.........................................................................................................................................315
27.1.1 External I/O Bus .....................................................................................................................315
27.1.2 I/O Strobes .............................................................................................................................316
27.1.3 I/O Handshake ........................................................................................................................317
27.1.4 Block Diagram .......................................................................................................................318
27.1.5 Registers .................................................................................................................................318
27.2 Dependencies ..................................................................................................................................319
27.2.1 I/O Pins ..................................................................................................................................319
27.2.2 Clocks .....................................................................................................................................319
27.2.3 Other Registers .......................................................................................................................319
27.2.4 Interrupts ................................................................................................................................319
27.3 Operation ........................................................................................................................................320
27.3.1 External I/O Bus .....................................................................................................................320
27.3.2 I/O Strobes .............................................................................................................................320
27.3.3 I/O Handshake ........................................................................................................................320
27.4 Register Descriptions......................................................................................................................321
Chapter 28. Breakpoints 331
28.1 Overview.........................................................................................................................................331
28.1.1 Block Diagram .......................................................................................................................332
28.1.2 Registers .................................................................................................................................333
28.2 Dependencies ..................................................................................................................................334
28.2.1 I/O Pins ..................................................................................................................................334
28.2.2 Clocks .....................................................................................................................................334
28.2.3 Other Registers .......................................................................................................................334
28.2.4 Interrupts ................................................................................................................................334
28.3 Operation ........................................................................................................................................334
Table of Contents
28.3.1 Handling Interrupts ................................................................................................................ 334
28.3.2 Example ISR .......................................................................................................................... 335
28.4 Register Descriptions ..................................................................................................................... 336
Chapter 29. Low-Power Operation 339
29.1 Overview ........................................................................................................................................ 339
29.1.1 Registers ................................................................................................................................ 340
29.2 Operation........................................................................................................................................ 341
29.2.1 Unused Pins ........................................................................................................................... 341
29.2.2 Clock Rates ............................................................................................................................ 341
29.2.3 Short Chip Selects ................................................................................................................. 342
29.2.4 Self-Timed Chip Selects ........................................................................................................ 347
29.3 Register Descriptions ..................................................................................................................... 348
Chapter 30. System/User Mode 351
30.1 Overview ........................................................................................................................................ 351
30.1.1 Registers ................................................................................................................................ 352
30.2 Dependencies ................................................................................................................................. 353
30.2.1 I/O Pins .................................................................................................................................. 353
30.2.2 Clocks .................................................................................................................................... 353
30.2.3 Other Registers ...................................................................................................................... 353
30.2.4 Interrupts ................................................................................................................................ 354
30.3 Operation........................................................................................................................................ 355
30.3.1 Memory Protection Only ....................................................................................................... 355
30.3.2 Mixed System/User Mode Operation .................................................................................... 356
30.3.3 Complete Operating System .................................................................................................. 356
30.3.4 Enabling the System/User Mode ........................................................................................... 357
30.3.5 System/User Mode Instructions ............................................................................................ 358
30.3.6 System Mode Violation Interrupt .......................................................................................... 359
30.3.7 Handling Interrupts in the System/User Mode ...................................................................... 360
30.4 Register Descriptions ..................................................................................................................... 362
Chapter 31. Specifications 369
31.1 DC Characteristics.......................................................................................................................... 369
31.2 AC Characteristics.......................................................................................................................... 371
31.3 Memory Access Times................................................................................................................... 372
31.3.1 Memory Reads ....................................................................................................................... 372
31.3.2 Memory Writes ...................................................................................................................... 372
31.3.3 External I/O Reads ................................................................................................................ 375
31.3.4 External I/O Writes ................................................................................................................ 375
31.3.5 Memory Access Times .......................................................................................................... 378
31.4 Clock Speeds .................................................................................................................................. 381
31.4.1 Recommended Clock/Memory Configurations ..................................................................... 381
31.5 Power and Current Consumption ................................................................................................... 385
31.5.1 Sleepy Mode Current Consumption ...................................................................................... 386
31.5.2 Battery-Backed Clock Current Consumption ........................................................................ 387
Chapter 32. Package Specifications and Pinout 389
32.1 Ball Grid Array Packages............................................................................................................... 389
32.1.1 Pinout 17 × 17 Ethernet Option ............................................................................................. 389
32.1.2 Pinout 17 × 17 Wi-Fi Option ................................................................................................. 390
32.1.3 Mechanical Dimensions and Land Pattern ............................................................................ 391
32.2 Rabbit Pin Descriptions.................................................................................................................. 393
Appendix A. Parallel Port Pins with Alternate Functions 397
A.1 Alternate Parallel Port Pin Outputs ................................................................................................. 397
A.2 Alternate Parallel Port Pin Inputs.................................................................................................... 399
Rabbit 5000 Microprocessor User’s Manual
Appendix B. Rabbit 5000 Errata 401
B.1 Errata ................................................................................................................................................401
Index 405
Table of Contents
Rabbit 5000 Microprocessor User’s Manual
1. THE RABBIT 5000 PROCESSOR
1.1 Introduction
Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in
small- and medium-scale single-board computers. The first microprocessors were the
Rabbit 2000, Rabbit 3000, and the Rabbit 4000. The latest microprocessor is the Rabbit
5000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and
HD64180 microprocessors in small single-board computers. The Rabbit microprocessors
share a similar architecture and a high degree of compatibility with these microprocessors,
but represent a vast improvement.
The Rabbit 5000 is a high-performance microprocessor with low electromagnetic interference (EMI), and is designed specifically for embedded control, communications, and network connectivity. Extensive integrated features and glueless architecture facilitate rapid
hardware design, while a C-friendly instruction set promotes efficient development of
even the most complex applications.
The Rabbit 5000 is the first Rabbit microprocessor to have a full 16-bit internal bus architecture, providing significant performance improvements when used with external 16-bit
memory devices. It also has the ability to support both 8-bit and 16-bit external memory
devices.
The Rabbit 5000 is also the fastest microprocessor from Rabbit, now a Digi International
brand, running at up to 100 MHz, with compact code and support for up to 16 MB of
memory. Operating with a 1.8 V core and 3.3 V I/O, the Rabbit 5000 boasts eight channels
of DMA, six serial ports with IrDA, 48+ digital I/O, quadrature decoder, PWM outputs,
and pulse capture and measurement capabilities. It also features a battery-backable realtime clock, glueless memory and I/O interfacing, and ultra-low power modes. Four levels
of interrupt priority allow fast response to real-time events. Its compact instruction set and
high clock speeds give the Rabbit 5000 exceptionally fast math, logic, and I/O performance.
The Rabbit 5000 contains 128 KB of internal high-speed 16-bit SRAM, which can be used
for code and/or data. It is capable of booting off of a standard serial flash, so a microcontroller application with no external parallel memory is possible.
The Rabbit 5000 provides two options for network connectivity — a full 10/100Base-T
Ethernet MAC with a standard MII PHY interface, and a wireless 802.11b/g MAC
compatible with several standard Wi-Fi transceivers. The two network interfaces share both
internal resources and I/O pins, and so only one can be enabled at a time.
Chapter 1 The Rabbit 5000 Processor 13
1.2 Features
The Rabbit 5000 has several powerful design features that practically eliminate EMI problems, which is essential for OEMs who need to pass CE and regulatory radio-frequency
emissions tests. The amplitude of any electromagnetic radiation is reduced by the internal
spectrum spreader, by gated clocks (which prevent unnecessary clocking of unused registers), and by separate power planes for the processor core and I/O pins (which reduce
noise crosstalk). An external I/O bus can be used by designers to enable separate buses for
I/O and memory, or to limit loading the memory bus to reduce EMI and ground bounce
problems when interfacing external peripherals to the processor. The external I/O bus
accomplishes this by duplicating the Rabbit's data bus on Parallel Port A, and uses Parallel
Port B to provide the processor's six or eight least significant address lines for interfacing
with external peripherals.
The high-performance instruction set offers both greater efficiency and execution speed of
compiler-generated C code. Instructions include numerous single-byte opcodes that execute
in two clock cycles, 16-bit and 32-bit loads and stores, 16-bit and 32-bit logical and arithmetic operations, 16 × 16 multiply (executes in 12 clocks), long jumps and returns for
accessing a full 16 MB of memory, and one-byte prefixes to turn memory-access instructions into internal and external I/O instructions. Hardware-supported breakpoints ease
debugging by trapping on code execution or data reads and writes.
The Rabbit 5000 requires no external memory driver or interface-logic. Its 24-bit address
bus, 8-bit or 16-bit data bus, three chip-select lines, two output-enable lines, and two
write-enable lines can be interfaced directly with up to six memory devices. Up to 1 MB
of memory can be accessed directly via the Dynamic C development software, and up to
16 MB can be interfaced with additional software development. The Rabbit 5000 also
contains 128 KB of internal high-speed 16-bit SRAM, which can be used in addition to
any external memory devices.
A built-in slave port allows the Rabbit 5000 to be used as master or slave in multi-processor
systems, permitting separate tasks to be assigned to dedicated processors. An 8-line data
port and five control signals simplify the exchange of data between devices. A remote cold
boot enables startup and programming via a serial port, a slave port, or from a standard
external serial flash device.
The Rabbit 5000 features six 8-bit parallel ports, yielding a total of 48 digital I/O. Six
CMOS-compatible serial ports are available. All six are configurable as asynchronous
(including output pulses in IrDA format), while four are configurable as clocked serial
(SPI) and two are configurable as SDLC/HDLC. The various internal peripherals share the
parallel port’s I/O pins.
The Rabbit 5000 also offers many specialized peripherals. Two input-capture channels
each have a 16-bit counter, clocked by the output of an internal timer, that can be used to
capture and measure pulses. These measurements can be extended to a variety of functions
such as measuring pulse widths or for baud-rate autodetection. Two Quadrature Decoder
channels each have two inputs, as well as an 8- or 10-bit up/down counter. Each quadrature
14 Rabbit 5000 Microprocessor User’s Manual
decoder channel provides a direct interface to optical encoder units. Four independent pulsewidth modulator (PWM) outputs, each based on a 1024-pulse frame, are driven by the output of a programmable internal timer. The PWM outputs can be filtered to create a 10-bit
D/A converter or they can be used directly to drive devices such as motors or solenoids.
Two external interrupt vectors can multiplex inputs from up to six external pins.
The Rabbit 5000 has three timer systems. Timer A consists of ten 8-bit counters, each of
which has a programmed time constant. Six of them can be cascaded from the primary
Timer A counter. Timer B contains a 10-bit counter, two match registers, and two step
registers. An interrupt can be generated or the output pin can be updated when the counter
reaches a match value, and the match value can then be incremented automatically by the
step value. Timer C is a 16-bit counter that counts up to a programmable limit. It contains
eight match registers so that up to four PWM (both synchronous and variable-phase) or
quadrature decoder signals can be created.
The Rabbit 5000 also provides support for protected operating systems. Support for two
levels of operation, known as system and user modes, allow application-critical code to
operate in safety while user code is prevented from inadvertently disturbing the setup of
the processor. Memory blocks as small as 4 KB can be write-protected against accidental
writes by user code, and stack over/underflows can be trapped by high-priority interrupts.
Security features are also available in the Rabbit 5000. Portions of the new instruction set
were introduced to increase encryption algorithm speeds dramatically, and 32 bytes of
battery-backed RAM can store an encryption key away from prying eyes.
The Rabbit 5000 supports eight channels of DMA access to internal or external memory,
internal I/O addresses, and the external I/O bus. Directing a DMA channel to or from an
internal peripheral such as a serial port or the Ethernet port automatically connects DMA
enable signals. Burst size, priority, and guaranteed cycles for the processor are all under
program control.
The Rabbit 5000 contains an 802.11b/g wireless MAC peripheral, also designed to operate
with the DMA peripheral. It includes support for all standard Wi-Fi features, including infrastructure and ad-hoc modes. The high-speed internal A/D converter and D/A converter
and clocked-serial control port provide a generic interface to several common Wi-Fi
transceivers. A low-speed A/D converter is also available to monitor the transmit signal
strength if desired. The two A/D converters and single D/A converter are available for
customer use when the Wi-Fi peripheral is disabled.
The Rabbit 5000 also contains a full-featured 10/100Base-T Ethernet MAC peripheral.
Designed to operate with the DMA peripheral, the Ethernet peripheral is fully compliant
with the 802.3 Ethernet standard, including support for auto-negotiation, link detection,
multicast filtering, and broadcast addresses. An industry-standard MII interface is used to
connect to an external PHY device.
Chapter 1 The Rabbit 5000 Processor 15
1.3 Block Diagram
/RESET
/IOWR
/IORD
/BUFEN
SMODE0
SMODE1
STATUS
/WDTOUT
CLK
RESOUT
Data
Buffer
Memory
Management/
Control
Address
Buffer
Memory Chip
Interface
Parallel Ports
Port A
Port B
Port C
Port D
Port E
Port H
Global Power
Save & Clock
Distribution
Fast
Clock
Timer A
Timer C
Real-Time
Clock
32.768 kHz
Clock Input
Watchdog
Timer
Periodic
Interrupt
External I/O
Chip Interface
External
Interrupts
DATA BUS
(16 bits)
D[7:0]
(8-bit mode)
or
D[15:0]
(16-bit mode)
A[23:0]
CLKI
CLKIEN
CLK32K
INT0A, INT1A
INT0B, INT1B
/CS2, /CS1, /CS0
/OE1, /OE0
/WE1, /WE0
PA [7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
TXA, RXA, CLKA,
ATXA, ARXA
TXB, RXB, CLKB,
ATXB, ARXB
TXC, RXC, CLKC
TXD, RXD, CLKD
ADDRESS BUS
(15 bits)
Asynch
Serial
Synch
Serial
Asynch
Bootstrap
Synch
Bootstrap
Serial Port A
Asynch Serial IrDA
Serial Ports
B,C,D
Asynch Serial IrDA
Asynch
Serial
Synch
Serial
Serial Ports
E, F
Asynch Serial IrDA
Asynch
Serial
HDLC
SDLC
HDLC/SDLC IrDA
TXE, RXE
TCLKE, RCLKE
Slave Port
Slave Interface
SD[7:0]
SA[1:0],
/SCS, /SRD, /SWR,
/SLAVEATTN
Bootstrap Interface
TXF, RXF
TCLKF, RCLKF
Spectrum
Spreader
Clock
Doubler
Pulse Width
Modulation
PWM[3:0]
Quadrature
Decoder
QD1A, QD1B
QD2A, QD2B
AQD1A, AQD1B
AQD2A, AQD2B
Input
Capture
PC[7,5,3,1]
PD[7,5,3,1]
PE[7,5,3,1]
IrDA Bootstrap
Timer B
DMA
(8 channels)
25 MHz
DREQ0[B:A]
DREQ1[B:A]
TIMER C[3:0]
Secondary
Watchdog
VBAT RAM
(32 bytes)
battery-
backable
WAIT
ID[7:0]
IA[7:0]
I[7:0]
PH[7:0]
External Interface
CPU
SYSTEM/USER
128K
SRAM
10-bit High-Speed
DAC
20 MHz
10-bit High-Speed
ADC
10-bit slow ADC
802.11a/b/g
Wi-Fi
10/100Base-T
Ethernet
25
shared I/O
{
16 Rabbit 5000 Microprocessor User’s Manual
1.4 Basic Specifications
Two versions of the Rabbit 5000 are available—the standard 289-ball BGA and a compact
196-ball BGA for specialty Wi-Fi applications. The larger package is intended for most
Rabbit applications; the smaller package has specific features and limitations, and is not
presently offered for sale. If you need further information, please contact your Rabbit sales
representative.
Table 1-1. Rabbit 5000 Specifications and Features
Package 289-ball BGA 196-ball BGA
Package Size 15 mm × 15 mm × 1.4 mm 12 mm × 12 mm × 1.2 mm
Operating Voltage 1.8 V DC core, 3.3 V DC I/O ring
Operating Current
Operating Temp. -40°C to +85°C
Maximum Clock Speed 100 MHz
Digital I/O
Network Interfaces
Serial Ports 6 CMOS-compatible 2 CMOS-compatible
Baud Rate Clock speed/8 max. asynchronous
Address Bus 20/24-bit 8-bit
Data Bus 8/16-bit 8/16-bit
Timers
Real-Time Clock Yes, battery-backable
RTC Oscillator Circuitry External
Watchdog Timer/Supervisor Yes
48+ (arranged in
802.11b/g Wi-Fi
0.57 mA/MHz @ 1.8 V/3.3 V
(Wi-Fi and Ethernet diabled)
six 8-bit ports)
10/100Base-T
Ten 8-bit, one 10-bit with 2 match registers,
and one 16-bit with 8 match registers
19
802.11b/g Wi-Fi
Clock Modes 1×, 2×, /2, /3, /4, /6, /8
Power-Down Modes
External I/O Bus 8 data, 8 address lines No
A/D Converters
D/A Converters 10-bit, 2 synchronous channels, up to 40 megasamples/s
Chapter 1 The Rabbit 5000 Processor 17
Sleepy (32 kHz)
Ultra-Sleepy (16, 8, 2 kHz)
10-bit, 2 synchronous channels, up to 40 megasamples/s
10-bit, single channel, up to 300 ksamples/s
1.5 Comparing Rabbit Microprocessors
The Rabbit 2000, Rabbit 3000, Rabbit 4000, and Rabbit 5000 features are compared
below.
Feature Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000
Maximum Clock Speed, industrial
Maximum Clock Speed,
commercial
Maximum Crystal Frequency
Main Oscillator (may be doubled
internally up to maximum clock
speed)
32.768 kHz Crystal Oscillator External External External Internal
Operating Voltage, core
Operation Voltage, I/O
Maximum I/O Input Voltage 3.6 V 3.6 V 5.5 V 5.5 V
Current Consumption
Number of Package Pins 289/196 128 128 100
Size of Package, LQFP/PQFP
Spacing Between Package Pins
100 MHz
100 MHz
100 MHz 60 MHz 30 MHz 30 MHz
1.8 V ± 10%
3.3 V ± 10%
0.57 mA/MHz
@ 1.8 V/3.3 V
(Wi-Fi and
Ethernet
disabled)
N/A
60 MHz
60 MHz
1.8 V ± 10%
3.3 V ± 10%
0.35 mA/MHz
@ 3.3 V
× 16 ×
16
0.4 mm (16 mils)
1.5 mm
55.5 MHz
58.8 MHz
3.3 V ± 10% 5.0 V ± 10%
2 mA/MHz
@ 3.3 V
16 × 16 × 1.5 mm
0.4 mm (16 mils)
30 MHz
30 MHz
4 mA/MHz
@ 5 V
× 18 ×
24
0.65 mm (26 mils)
3 mm
15
× 15 ×
Size of Package, BGA (mm)
Spacing Between Package Pins
Separate Power and Ground for
I/O Buffers (EMI reduction)
Clock Spectrum Spreader Yes Yes Yes Rabbit 2000B/C
Clock Modes
Powerdown Modes, sleepy
Powerdown Modes, ultra sleepy
Low-Power Memory Control
Extended Memory Timing for
High-Frequency Operation
Number of 8-bit I/O Ports 6575
18 Rabbit 5000 Microprocessor User’s Manual
12
1×, 2×, /2, /3,
16, 8, 4, 2 kHz
Short and
Self-Timed
Chip Selects
1.4
× 12 ×
1.2
0.8 mm
Ye s Ye s Ye s N o
/4, /6, /8
32 kHz
Ye s Ye s Ye s N o
× 10 ×
10
1×, 2×, /2, /3,
16, 8, 4, 2 kHz
Short and
Self-Timed
Chip Selects
1.2
0.8 mm
/4, /6, /8
32 kHz
10 × 10 × 1.2
0.8 mm
1x, 2x, /2, /3
/4, /6, /8
32 kHz
16, 8, 4, 2 kHz
Short and
Self-Timed
Chip Selects
Not available
1x, 2x, /4, /8
32 kHz
None
Feature Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000
Auxiliary I/O Data/Address Bus Yes Yes Yes None
Number of Serial Ports 6664
Serial Ports Capable of SPI/
Clocked Serial
Serial Ports Capable of SDLC/
HDLC
Asynch Serial Ports With Support
for IrDA Communication
4 (A, B, C, D) 4 (A, B, C, D) 4 (A, B, C, D) 2 (A, B)
2 (E, F) 2 (E, F) 2 (E, F) None
666None
Serial Ports with Support for
SDLC/HDLC IrDA
222None
Communication
Maximum Asynchronous Baud
Rate
Clock Speed/8 Clock Speed/8 Clock Speed/8 Clock Speed/32
Ethernet Port 10/100Base-T 10Base-T None None
Wi-Fi Yes No No No
PWM Outputs 4 4 4 None
Variable-Phase PWM Outputs
(PPM)
4 4 None None
Input Capture Units 2 2 2 None
Quadrature Decoders 2 channels 2 channels 2 channels None
Chapter 1 The Rabbit 5000 Processor 19
20 Rabbit 5000 Microprocessor User’s Manual
2. CLOCKS
2.1 Overview
The Rabbit 5000 supports up to three separate clocks at once—the main clock, the 32 kHz
clock, and the 20 MHz Wi-Fi clock. The main clock is used to drive the processor clock
and the peripheral clock inside the processor. The 32 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog
timers.
The Rabbit 5000 has a spectrum spreader on the main clock that shortens and lengthens
clock cycles. This has the net effect of reducing the peak energy of clock harmonics by
spreading the spectral energy into nearby frequencies, which reduces EMI and facilitates
government-mandated EMI testing. Gated clocks are used whenever possible to avoid
clocking unused portions of the processor, and separate power-supply pins for the core and
I/O ring further reduce EMI from the Rabbit 5000.
The main clock can be doubled or divided by 2, 4, 6, or 8 to reduce EMI and power
consumption. The 32 kHz clock (which can be divided by 2, 4, 8, or 16) can be used
instead of the main clock to generate processor and peripheral clocks as low as 2 kHz for
significant power savings. Note that dividing the 32 kHz clock only affects the processor
and peripheral clocks; the full 32 kHz signal is still provided to the real-time clock and
watchdog timer peripherals that use it directly. The periodic interrupt is disabled automatically since there is not enough time to process it when running off the 32 kHz clock.
There is also a 25 MHz Ethernet clock that is provided to the external PHY chip if you are
using the Ethernet option, but this Ethernet clock is not applied directly to the Rabbit
5000. The Ethernet clock can be driven by the processor clock, the processor clock
divided by 2, or by the input on PE6. The Ethernet clock needs to be 25 MHz to conform to
the 10/100Base-T specification. See Chapter 22 for more details on the Ethernet clock.
Chapter 2 Clocks 21
2.1.1 Block Diagram
Wi-Fi
Clock
GCSR
CPU Clock
Peripheral Clock
GOCR
Divide
by 2
CLK Pin
Divide by
2, 4, 6, 8
Clock
Doubler
Spectrum
Spreader
CLKI
Divide by
2, 4, 8, 16
CLK32K
Clock
Disable
CLKIEN
CLK_IN
GCMxR
GCDR GCSR
GPSCR
Real-Time Clock
Periodic Interrupt
Asynch. Serial Bootstrap
Watchdog Timer
MAIN CLOCK
GCSR
PLL
2.1.2 Registers
Register Name Mnemonic I/O Address R/W Reset
Global Control/Status Register GCSR 0x0000 R/W 11000000
Global Clock Modulator 0 Register GCM0R 0x000A W 00000000
Global Clock Modulation 1 Register GCM1R 0x000B W 00000000
Global Clock Double Register GCDR 0x000F R/W 00000000
22 Rabbit 5000 Microprocessor User’s Manual
2.2 Dependencies
2.2.1 I/O Pins
The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to
mitigate any noise problems associated with slowly transitioning signals.
The main clock disable output is on the CLKIEN pin. Its state is changed by one of the bit
combinations of bits 4:2 in GCSR. The CLKIEN pin will output low to disable an external
main oscillator when the 32 kHz mode with main oscillator disabled is selected, and will
output high for all other clock modes
The 32 kHz clock input is on the CLK32K pin. There is an internal Schmitt trigger on this
pin as well.
The peripheral clock or peripheral clock divided by 2 may be optionally output on the
CLK pin by enabling it via bits 7:6 in GOCR.
The 20 MHz Wi-Fi clock input is located on the CLK_IN pin; a PLL multiplies clocks up
to the 80 MHz required for the Wi-Fi peripheral.
2.2.2 Other Registers
Register Function
GOCR Used to set up the CLK output pin.
Chapter 2 Clocks 23
2.3 Operation
2.3.1 Main Clock
The main clock is input on the CLKI pin, and is optionally sent through the spectrum
spreader and then the clock doubler. Both of these are described in greater detail below.
Different main clock modes may be selected via the GCSR, as shown in Table 2-1. Note
that one GCSR setting slows the processor clock while the peripheral clock operates at full
speed; this allows some power reduction while keeping settings like serial baud rates and
the PWM at their desired values.
Table 2-1. Clock Modes
GCSR Setting Processor Clock Peripheral Clock
xxx010xx Main clock Main clock
xxx011xx Main clock / 2 Main clock / 2
xxx110xx Main clock / 4 Main clock / 4
xxx111xx Main clock / 6 Main clock / 6
xxx000xx Main clock / 8 Main clock / 8 (default on startup)
xxx001xx Main clock / 8 Main clock
xxx100xx 32 kHz clock (possibly divided)
32 kHz clock (possibly divided);
xxx101xx
main clock disabled via CLKIEN
output signal
32 kHz clock (possibly divided
via GPSCR)
32 kHz clock (possibly divided
via GPSCR)
When the 32 kHz clock is enabled in GCSR, it can be further divided by 2, 4, 6, or 8 to
generate even lower frequencies by enabling those modes in bits 0–2 of GPSCR. See
Table 2-4 for more details.
24 Rabbit 5000 Microprocessor User’s Manual
2.3.2 Spectrum Spreader
FREQUENCY (MHz)
AMPLITUDE (dB)
400
405
410 415 420 425 430 435 4
-10
-20
-30
-40
-50
Spectrum Spreader
Disabled
Spectrum Spreader
Enabled (normal setting)
When enabled, the spectrum spreader stretches and compresses the main clock in a complex
pattern that spreads the energy of the clock harmonics over a wider range of frequencies.
There are three settings that correspond to normal and strong spreading in the 0–50 MHz
and >50 MHz main clock range. Each setting will affect the clock cycle differently; the
maximum cycle shortening (at 1.8 V and 25°C) is shown in Table 2-2 below.
0–50 MHz > 50 MHz
Normal Strong 0x00
Strong — 0x80
Chapter 2 Clocks 25
Figure 2-1. Effects of Spectrum Spreader
Table 2-2. Spectrum Spreader Settings
GCM0R
Value
— Normal 0x40
Normal spreading of frequencies over
50 MHz
Normal spreading of frequencies up to
50 MHz; strong spreading of
frequencies over 50 MHz
Strong spreading of frequencies up to
50 MHz; normal spreading of
frequencies over 50 MHz
Description
Max. Cycle
Shortening
2.3 ns
3 ns
4.5 ns
The spectrum spreader either stretches or shrinks the low plateau of the clock by a maximum
15
10
5
10050 200150 250
350
300
Normal Spreading
Strong Spreading
Frequency (MHz)
Harmonics (dB)
of 3 ns for the normal spreading and up to 4.5 ns for the strong spreading. If the clock
doubler is used, this will cause an additional asymmetry between alternate clock cycles.
Both normal and strong modes reduce clock harmonics by approximately 15 dB for frequencies above 100 MHz; for lower frequencies the strong setting has a greater effect in
reducing the peak spectral strength as shown in Figure 2-2.
Figure 2-2. Peak Spectral Amplitude Reduction by Spectrum Spreader
Two registers control the clock spectrum spreader. These registers must be loaded in a specific manner with proper time delays. GCM0R is only read by the spectrum spreader at the
moment when the spectrum spreader is enabled by storing 0x080 in GCM1R. If GCM1R
is cleared (when disabling the spectrum spreader), there is up to a 500-clock delay before
the spectrum spreader is actually disabled. The proper procedure is to clear GCM1R, wait
for 500 clocks, set GCM0R, and then enable the spreader by storing 0x080 in GCM1R.
The spectrum spreader is applied to the main clock before the clock doubler, so if both are
enabled there will be additional asymmetry between alternate clock cycles.If the clock
doubler is used, the spectrum spreader affects every other cycle and reduces the clock high
time. If the doubler is not used, then the spreader affects every clock cycle, and the clock
low time is reduced.
26 Rabbit 5000 Microprocessor User’s Manual
2.3.3 Clock Doubler
The clock doubler allows a lower frequency crystal to be used for the main oscillator and
to provide an added range over which the clock frequency can be adjusted. The clock
doubler is controlled via the Global Clock Double Register (GCDR).
The clock doubler uses an on-chip delay circuit that must be programmed by the user at
startup if there is a need to double the clock. Table 2-3 lists the recommended delays in
GCDR for various oscillator or crystal frequencies.
Table 2-3. Recommended Delays Set In GCDR for Clock Doubler
Recommended GCDR Value Frequency Range
0x0F 7.3728 MHz
0x0B 7.3728–11.0592 MHz
0x09 11.0592–16.5888 MHz
0x06 16.5888–20.2752 MHz
0x03 20.2752–52.8384 MHz
0x01 52.8384–77.4144 MHz
0x00 >77.4144 MHz
Chapter 2 Clocks 27
When the clock doubler is used and there is no subsequent division of the clock, the output
Oscillator
Oscillator delayed
and inverted
Doubled clock
Delay
time
48% 52%
P
0.48P 0.52P 0.48P 0.52P
Data out
Example
Write
Cycle
Write pulse
Early write pulse
option
Address / CS
Address / CS
Output enb
Early output enb
option
Data out from mem
Example
Read
Cycle
clock will be asymmetric, as shown in Figure 2-3.
Figure 2-3. Effect of Clock Doubler
The doubled-clock low time is subject to wide (50%) variation since it depends on process
parameters, temperature, and voltage. The times given above are for a core supply voltage
of 1.8 V and a temperature of 25°C. The values increase or decrease by 1% for each 5°C
increase or decrease in temperature. The doubled clock is created by xor’ing the delayed
and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then
alternate clocks will have a slightly different length. Since the duty cycle of the built-in
oscillator can be as asymmetric as 52%/48%, the clock generated by the clock doubler will
exhibit up to a 4% variation in period on alternate clocks. The memory access time is not
affected because the memory bus cycle is 2 clocks long and includes both a long and a short
28 Rabbit 5000 Microprocessor User’s Manual
clock, resulting in no net change due to asymmetry. However, if an odd number of wait
states is used, then the memory access time will be affected slightly
The maximum allowed clock speed must be reduced slightly if the clock is supplied via the
clock doubler. The only signals clocked on the falling edge of the clock are the memory
and I/O write pulses, and the early option memory output enable. See Chapter 5 for more
information on the early output enable and write enable options.
The power consumption is proportional to the clock frequency, and for this reason power
can be reduced by slowing the clock when less computing activity is taking place. The
clock doubler provides a convenient method of temporarily speeding up or slowing down
the clock as part of a power management scheme.
Chapter 2 Clocks 29
2.3.4 32 kHz Clock
C1 values may vary or
C1 may be eliminated
R2
R1
R1 and R2 control the
power consumed by the
unbuffered inverter.
VBAT
R
s
C1
C2
32.768 kHz
CL = 5-12 pF
R
p
C
in
U1A
U2A
SN74AHC1GU04
NC7SP14
The 32.768 kHz clock is used to drive the asynchronous serial bootstrap, the real-time
clock, the periodic interrupt, and the watchdog timers. If these features are not used in a
design, the use of the 32 kHz clock is optional.
A simplified version of the recommended oscillator circuit for the Rabbit 5000 is shown
below. The values of resistors and capacitors may need to be adjusted for various frequencies and crystal load capacitances. Technical Note TN235, “External 32.768 kHz Oscillator Circuits“, is available on the Rabbit Web site and goes into this circuit in detail.
Figure 2-4. Basic 32.768 kHz Oscillator Circuit
The 32.768 kHz circuit consumes microampere-level currents and has a very high impedance, making it susceptible to noise, moisture, and environmental contaminants. It is
strongly recommended to conformally coat this circuit to limit the effects of humidity and
dust on the oscillation frequency. Details about this requirement are available in Technical
Note TN303, “Conformal Coating”, from the Rabbit Web site.
The 32.768 kHz oscillator is slow to start oscillating after power-on. The startup delay
may be as much as 5 seconds. For this reason, a wait loop in the BIOS waits until this
oscillator is oscillating regularly before continuing the startup procedure. If the clock is
battery-backed, there will be no startup delay since the oscillator is already oscillating.
Crystals with low series resistance (R < 35 k) will start faster.
30 Rabbit 5000 Microprocessor User’s Manual
The 32 kHz oscillator can be used to drive the processor and the peripheral clock to provide
significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided
by 2, 4, 8, or 16 to provide clock speeds as low as 2.048 kHz. Special self-timed chip
selects are available to keep the memory devices enabled for as short a time as possible
when an ultra-sleepy mode is enabled; see Chapter 29 for more details on reducing power
consumption.
Table 2-4. Ultra-Sleepy Clock Modes
GPSCR
Setting
xxxxx000 32.768 kHz
xxxxx100 16.384 kHz
xxxxx101 8.192 kHz
xxxxx110 4.096 kHz
xxxxx111 2.048 kHz
Processor and
Peripheral Clock
When the 32 kHz clock is enabled, the periodic interrupt is disabled automatically. The
real-time clock and watchdog timers keep running, and use the full 32 kHz clock speed
even when the processor and peripheral clocks use a divider on the 32 kHz clock.
Chapter 2 Clocks 31
2.4 Register Descriptions
Global Control/Status Register (GCSR) (Address = 0x0000)
Bit(s) Value Description
7:6 00 No reset or watchdog timer timeout since the last read.
(rd-only) 01 The watchdog timer timed out. These bits are cleared by a read of this register.
10 This bit combination is not possible.
11 Reset occurred. These bits are cleared by a read of this register.
5 0 No effect on the periodic interrupt. This bit will always be read as zero.
1 Force a periodic interrupt to be pending.
4:2 000
001
010
011
100
101
110
111
1:0 00 Periodic interrupts are disabled.
Processor clock from the main clock, divided by 8.
Peripheral clock from the main clock, divided by 8.
Processor clock from the main clock, divided by 8.
Peripheral clock from the main clock.
Processor clock from the main clock.
Peripheral clock from the main clock.
Processor clock from the main clock, divided by 2.
Peripheral clock from the main clock, divided by 2.
Processor clock from the 32 kHz clock, optionally divided via GPSCR.
Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
Processor clock from the 32 kHz clock, optionally divided via GPSCR.
Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
The main clock is disabled.
Processor clock from the main clock, divided by 4.
Peripheral clock from the main clock, divided by 4.
Processor clock from the main clock, divided by 6.
Peripheral clock from the main clock, divided by 6.
01 Periodic interrupts use Interrupt Priority 1.
10 Periodic interrupts use Interrupt Priority 2.
11 Periodic interrupts use Interrupt Priority 3.
32 Rabbit 5000 Microprocessor User’s Manual
Global Clock Modulator 0 Register (GCM0R) (Address = 0x000A)
Bit(s) Value Description
7:6 00
Clock dither in 1 ns steps, from 0 ns to 26 ns. Do not modify while the dither
function is enabled.
01 Clock dither in 0.5 ns steps, from 0 ns to 13 ns.
10 Clock dither in 2 ns steps, from 0 ns to 52 ns.
11 This bit combination is reserved and must not be used.
5:0 These bits are reserved and should be written with zeros.
Global Clock Modulator 1 Register (GCM1R) (Address = 0x000B)
Bit(s) Value Description
70
Disable the clock dither function. The disable does not take effect until the dither
pattern has returned to the 0 ns base delay value.
1 Enable the clock dither function.
6:0 These bits are reserved and should be written with zeros.
Chapter 2 Clocks 33
Global Clock Double Register (GCDR) (Address = 0x000F)
Bit(s) Value Description
7:5 These bits are reserved and should be written with zeros.
4:0 00000 The clock doubler circuit is disabled.
00001 6 ns nominal low time.
00010 7 ns nominal low time.
00011 8 ns nominal low time.
00100 9 ns nominal low time.
00101 10 ns nominal low time.
00110 11 ns nominal low time.
00111 12 ns nominal low time.
01000 13 ns nominal low time.
01001 14 ns nominal low time.
01010 15 ns nominal low time.
01011 16 ns nominal low time.
01100 17 ns nominal low time.
01101 18 ns nominal low time.
01110 19 ns nominal low time.
01111 20 ns nominal low time.
10001 3 ns nominal low time.
10010 4 ns nominal low time.
10011 5 ns nominal low time.
other Any bit combination not listed is reserved and must not be used.
34 Rabbit 5000 Microprocessor User’s Manual
Global Output Control Register (GOCR) (Address = 0x000E)
Bit(s) Value Description
7:6 00 CLK pin is driven with peripheral clock.
01 CLK pin is driven with peripheral clock divided by 2.
10 CLK pin is low.
11 CLK pin is high.
5:4 00 STATUS pin is active (low) during a first opcode byte fetch.
01 STATUS pin is active (low) during an interrupt acknowledge.
10 STATUS pin is low.
11 STATUS pin is high.
3:2 00 /WDTOUT pin functions normally.
01 Enable /WDTOUT for test mode. Rserved for internal use only.
10 /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz).
11 This bit combination is reserved and should not be used.
1:0 00 /BUFEN pin is active (low) during external I/O cycles.
01 /BUFEN pin is active (low) during data memory accesses.
10 /BUFEN pin is low.
11 /BUFEN pin is high.
Chapter 2 Clocks 35
36 Rabbit 5000 Microprocessor User’s Manual
3. RESET AND BOOTSTRAP
3.1 Overview
The Rabbit 5000’s /RESET pin initializes everything in the processor except for the realtime clock registers and the contents of the battery-backed onchip-encryption RAM. If a
write cycle is in progress, it waits until the write cycle is completed to avoid potential
memory corruption.
After reset, the Rabbit 5000 checks the state of the SMODE and SYSCFG pins. Depending
on the state of the SMODE pins, it either begins normal operation by fetching instruction
bytes from memory bank zero, which is mapped to either /CS0 or /CS3 depending on the
state of the SYSCFG0 pin, or it enters a special bootstrap mode where it fetches bytes
from either Serial Port A or the slave port. In this mode, bytes can be written to internal
registers to set up the Rabbit 5000 for a particular configuration, or to memory to load a
program. The processor can begin normal operation once the bootstrap operation is
completed.
Chapter 3 Reset and Bootstrap 37
3.1.1 Block Diagram
Reset
Delay
/RESET
Reset
CPU
Clock
Rabbit
5000
Master Reset
Bootstrap
Selection
SMODE0
Bootstrap
SMODE1
Asynch Serial Bootstrap
Serial Flash Bootstrap
Slave Port Bootstrap
Normal Operation
SPCR
SRAM
Chip
Select
SYSCFG0
Internal SRAM is on /CS0
Internal SRAM is on /CS3
3.1.2 Registers
Register Name Mnemonic I/O Address R/W Reset
Slave Port Control Register SPCR 0x0024 R/W 0xx00000
38 Rabbit 5000 Microprocessor User’s Manual
3.2 Dependencies
3.2.1 I/O Pins
SMODE0, SMODE1 — When the Rabbit 5000 is first powered up or when it is reset, the
state of the SMODE0 and SMODE1 pins controls its operation.
SYSCFG0 — When the Rabbit 5000 is first powered up or when it is reset, the state of
this pin controls whether memory bank zero is mapped to /CS0 or the internal SRAM
(/CS3).
SYSCFG1 — This pin should always be tied to ground.
/RESET — Pulling the /RESET pin low will initialize everything in the Rabbit 5000
except for the real-time clock registers and the onchip-encryption RAM.
/CS1 — During reset the impedance of the /CS1 pin is high, and all other memory and I/O
control signals are held high. The special behavior of /CS1 allows an external RAM to be
powered by the same source as the VBATIO pin (which powers /CS1). In this case, a pullup resistor is required on /CS1 to keep the RAM deselected during powerdown.
RESOUT — The RESOUT pin, which is powered by the backup battery, is high during
reset and powerdown as long as VBAT and VBATIO are present, but low at all other
times, and can be used to control an external power switch to disconnect VDDIO from
VBATIO when the main power source is removed.
3.2.2 Clocks
The processor requires a 32 kHz clock input to generate the 2400 bps internal clock
required for asynchronous serial bootstrap, which is used when booting via Dynamic C
and the Rabbit Field Utility. No 32 kHz clock is required for either clocked serial or slave
port bootstrap.
When the processor comes out of reset, the CPU clock and peripheral clocks are both in
divide-by-8 mode.
3.2.3 Other Registers
Register Function
SPCR
Enable/disable processor monitoring of SMODE
pins; read current state of SMODE pins.
3.2.4 Interrupts
There are no interrupts associated with reset or bootstrap.
Chapter 3 Reset and Bootstrap 39
3.3 Operation
Pulling the /RESET pin low will initialize everything in the Rabbit 5000 except for the
real-time clock registers and the onchip-encryption RAM. The reset of the Rabbit 5000 is
delayed until any write cycles in progress are completed; the reset takes effect as soon as
no write cycles are occurring. The reset sequence requires a minimum of 128 cycles of the
main clock to complete in either case.
During reset, the impedance of the /CS1 pin is high and all other memory and I/O control
signals are held high. The special behavior of /CS1 allows an external RAM to be powered
by the same source as the VBATIO pin (which powers /CS1). In this case, a pullup resistor
is required on /CS1 to keep the RAM deselected during powerdown. The RESOUT pin,
which is powered by the backup battery, is high during reset and powerdown as long as
VBAT and VBATIO are present, but low at all other times, and can be used to control an
external power switch to disconnect VDDIO from VBATIO when the main power source
is removed.
Table 3-1 lists the condition of the processor after reset takes place. The state of all registers
after reset is provided in the chapter describing the specific peripheral.
Table 3-1. Rabbit 5000 Condition After Reset
Function Operation After Reset
CPU Clock,
Peripheral Clock
Clock Doubler,
Clock Dither
Memory Bank 0
Control Register
Memory Advanced
Control Register
CPU Registers:
PC, SP, IIR, EIR,
SU, HTR
Interrupt Priority
(IP Register)
Watchdog Timer Enabled (2 seconds)
Secondary
Watchdog Timer
Divide-by-8 mode
Disabled
/CS0, /OE0, write-protected,
4 wait states
8-bit interface
0x0000
0xFF (Priority 3)
Disabled
40 Rabbit 5000 Microprocessor User’s Manual
The processor checks the SMODE and SYSCFG0 pins after the /RESET signal is inactive.
Table 3-2 summarizes what happens.
Table 3-2. SMODE Pin Settings
SMODE Pins [1,0] SYSCFG0 Operation
00 0
00 1
01 x Bootstrap from the slave port.
10 x Bootstrap from Serial Port A, serial flash mode.
11 x Bootstrap from Serial Port A, asynchronous mode.
No bootstrap; code is fetched from address 0x0000
on /CS0, /OE0.
No bootstrap; code is fetched from address 0x0000
on /CS3, /OE0. The internal SRAM is enabled as a
16-bit memory device.
If both SMODE pins are zero, the Rabbit 5000 begins fetching instructions from the
memory device mapped into memory bank 0. When SYSCFG0 is low, memory bank 0 is
set to /CS0 and /OE0. If SYSCFG0 is high, memory bank 0 is set to /CS3 and /OE0, and
the internal SRAM is selected in 16-bit mode. If a 16-bit memory is used in memory bank 0,
the first section of code must immediately select the 16-bit bus mode. Chapter 5 provides
a short sample program to do this.
If either of the SMODE pins is high, the processor will enter the bootstrap mode and
accept triplets from Serial Port A, the serial flash bootstrap port, or the slave port, depending on the SMODE pin selection. It is good practice to place pulldown resistors on the
SMODE pins to ensure the proper operation of your design.
In the bootstrap mode, the processor inhibits the normal memory fetch, and instead fetches
instructions from a small internal boot ROM. This program reads triplets of three bytes
from the selected peripheral. The first byte is the most-significant byte of a 16-bit address,
the second byte is the least-significant byte of the address, and the third byte is the data to
be written. If the uppermost bit of the address is 1, then the address is assumed to be an
internal register address instead of a memory address, and the data are written to the
appropriate register instead. For example, a triplet of (0x04, 0x34, 0x5A) will write 0x5A
to logical memory address 0x0434, while a triplet of (0x80, 0x34, 0x5A) will write 0x5A
to processor register 0x34. Processor registers with addresses above 0xFF are not accessible in the bootstrap mode.
The boot ROM program waits for data to be available; each byte received automatically
resets the watchdog timer with a 2-second timeout. Bytes must be received quickly
enough to prevent timeout (or the watchdog must be disabled).
The device checks the state of the SMODE pins each time it jumps back to the start of the
ROM program and responds according to the current state. In addition, by setting bit 7 of
Chapter 3 Reset and Bootstrap 41
the Slave Port Control Register (SPCR) high, the processor can be told to ignore the state
of the SMODE pins and continue normal operation.
Note that the processor can be told to re-enter bootstrap mode at any time by setting bit 7
of SPCR low; once this occurs and the least significant four bits of the current PC address
are zero, the processor will sample the state of the SMODE pins and respond accordingly.
This feature allows in-line downloading from the selected bootstrap port; once the download is complete, bit 7 of SPCR can be set high and the processor will continue operating
from where it left off.
As a security feature, any attempt to enter the bootstrap mode from either the SMODE
pins or by writing to bit 7 of the SPCR will erase the data stored in the onchip-encryption
RAM. This prevents loading a small program in memory to read out the data.
3.3.1 Asynchronous Serial Bootstrap
When the asynchronous serial bootstrap mode is selected by the SMODE pins, the Rabbit
5000 will being accepting triplets at 2400 bps on Serial Port A. The baud rate is generated
from the 32 kHz clock input, so a 32 kHz clock is required for this mode.
3.3.2 Serial Flash Bootstrap
When the serial flash bootstrap mode is selected by the SMODE pins, the Rabbit 5000
will enable the SPI serial flash bootstrap port on pins PD4, PD5, PD6, and PB0; the pins’
functionality is listed in Table 3-3 below. Note that these pins can be used for Serial Port B
in normal operation, so the serial flash may use the serial port as a regular serial port if
desired.
Table 3-3. Serial Flash Bootstrap Pin Functions
Pin SPI Signal Operation
PD4 MOSI Rabbit data transmit (to serial flash)
PD5 MISO Rabbit data receive (from serial flash)
PD6 CS Chip select (to serial flash)
PB0 SCK Serial clock (output to serial flash)
The Rabbit 5000 divides the main clock by 64 to provide the SPI clock for the serial flash
bootstrap. Once this mode is entered, the Rabbit 5000 will send the byte sequence "0x03
0x00 0x00 0x00", which is an industry-standard command that enables continuous read
mode starting at serial flash address 0x0. Figure 3-1 provides a sample timing diagram.
The Rabbit 5000 will then read triplets out of the serial flash until the bootstrap mode is
exited.
42 Rabbit 5000 Microprocessor User’s Manual
Figure 3-1. SPI Timing Diagram for Serial Flash Bootstrap Mode
012345678
15
16 23 24
31 32
39 40 47 487055 56
63
64
CE#
SCK
SI
SO
MODE 3
MODE 0
MSB
MSB
HIGH IMPEDANCE
MSB
O3
ADD ADD ADD
D
OUTDOUTDOUTDOUTDOUT
N
N + 1
N + 2 N + 3
N + 4
3.3.3 Parallel Bootstrap
When the parallel bootstrap mode is selected by the SMODE pins, the Rabbit 5000 will
enable the parallel slave port interface on Parallel Ports A and B, and will wait for triplets
to be sent to that interface. See Chapter 19 for more details on the operation of the slave
port.
Chapter 3 Reset and Bootstrap 43
3.4 Register Descriptions
Slave Port Control Register (SPCR) (Address = 0x0024)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
1 Ignore the SMODE pins program fetch function.
6:5 Read These bits report the state of the SMODE pins.
Write These bits are ignored and should be written with zero.
4:2 000 Disable the slave port. Parallel Port A is a byte-wide input port.
001 Disable the slave port. Parallel Port A is a byte-wide output port.
010 Enable the slave port, with /SCS from Parallel Port E bit 7.
011
100 This bit combination is reserved and should not be used.
101 This bit combination is reserved and should not be used.
110 Enable the slave port, with /SCS from Parallel Port B bit 6.
111
1:0 00 Slave port interrupts are disabled.
01 Slave port interrupts use Interrupt Priority 1.
10 Slave port interrupts use Interrupt Priority 2.
11 Slave port interrupts use Interrupt Priority 3.
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel
Port B[7:2] is used for the address bus.
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel
Port B[7:0] is used for the address bus.
44 Rabbit 5000 Microprocessor User’s Manual
4. SYSTEM MANAGEMENT
4.1 Overview
There are a number of basic system peripherals in the Rabbit 5000 processor, some of
which are covered in later chapters. The peripherals covered in this chapter are the periodic
interrupt, the real-time clock, the watchdog timers, the battery-backed onchip-encryption
RAM, and some of the miscellaneous output pins and their control and processor registers
that provide the processor ID and revision numbers.
The periodic interrupt, when enabled, is generated every 16 clocks of the 32 kHz clock
(every 488 µs, or 2.048 kHz). This interrupt can be used to perform periodic tasks.
The real-time clock (RTC) consists of a 48-bit counter that is clocked by the 32 kHz clock.
It is powered by the VBAT pin, and so can be battery-backed. The value in the counter is
not affected by reset, and can only be set to zero by writing to the RTC control register.
The 48-bit width provides a 272-year span before rollover occurs.
There are two watchdog timers in the Rabbit 5000, both clocked by the 32 kHz clock. The
main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the processor if not reloaded within that time. Its purpose is to restart the processor when it
detects that a program gets stuck or disabled.
The secondary watchdog timer can time out from 30.5 µs up to 7.8 ms, and generates a
Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary
use for the secondary watchdog is to act as a safety net for the periodic interrupt — if the
secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the
periodic interrupt stops occurring. In addition, it can be used as a periodic interrupt on its
own.
The battery-backed onchip-encryption RAM consists of 32 bytes of memory that are
powered by the VBAT pin. Their values are not affected by reset, but are erased if the state
of the SMODE pins changes. These 32 bytes are intended for storing sensitive data (such
as an encryption key) somewhere other than an external memory device. The “tamperprotection” erase feature prevents loading a program into the onchip-encryption RAM via
the programming port and reading out the bytes.
The following other registers are also described in this chapter.
• Global Output Control Register (GOCR), which controls the behavior of the CLK,
STATUS, /WDT, and /BUFEN pins
• Global CPU Register (GCPU), which holds the identification number of the processor.
• Global Revision Register (GREV), which hold the revision number of the processor.
Chapter 4 System Management 45
4.1.1 Block Diagram
Basic System Peripherals
Periodic Interrupt
(488 µs)
32 kHz Clock
Interrupt
Request
GCSR
Interrupt
Generation
Real-Time Clock
RTCxR
RTCCR
Watchdog
Timer
Secondary
Watchdog Timer
WDTCR
WDTTR
WDTCR
SWDTR
Interrupt
Request
Interrupt
Generation
Master Reset
/WDTOUT Pin
46 Rabbit 5000 Microprocessor User’s Manual
4.1.2 Registers
Register Name
Mnemonic I/O Address R/W
Reset
Global Control/Status Register GCSR 0x0000 R/W 11000000
Real-Time Clock Control Register RTCCR 0x0001 W 00000000
Real-Time Clock Byte 0 Register RTC0R 0x0002 R/W xxxxxxxx
Real-Time Clock Byte 1 Register RTC1R 0x0003 R xxxxxxxx
Real-Time Clock Byte 2 Register RTC2R 0x0004 R xxxxxxxx
Real-Time Clock Byte 3 Register RTC3R 0x0005 R xxxxxxxx
Real-Time Clock Byte 4 Register RTC4R 0x0006 R xxxxxxxx
Real-Time Clock Byte 5 Register RTC5R 0x0007 R xxxxxxxx
Watchdog Timer Control Register WDTCR 0x0008 W 00000000
Watchdog Timer Test Register WDTTR 0x0009 W 00000000
Secondary Watchdog Timer Register SWDTR 0x000C W 11111111
Global Output Control Register GOCR 0x000E R/W 00000000
Global ROM Configuration Register GROM 0x002C R 0xx00000
Global RAM Configuration Register GRAM 0x002D R 0xx00000
Global CPU Configuration Register GCPU 0x002E R 0xx00010
Global Revision Register GREV 0x002F R 0xx00000
Battery-Backed Onchip-Encryption RAM Byte
00–1F
VRAM00–
VRAM1F
0x0600–0x061F R/W xxxxxxxx
Chapter 4 System Management 47
4.2 Dependencies
4.2.1 I/O Pins
The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of
these pins can be used as general-purpose outputs by driving them high or low.
• The CLK pin can output the peripheral clock, the peripheral clock divided by two, or be
driven high or low.
• The STATUS pin can be active low during the first byte of each opcode fetch, active
low during an interrupt acknowledge, or driven high or low.
• The /WDTOUT pin can be active low whenever the watchdog timer resets the device or
driven low.
• The /BUFEN pin can be active low during external I/O cycles, active low during data
memory cycles, or driven high or low.
The values in the battery-backed onchip-encryption RAM bytes are cleared if the signal
on the SMODE pins changes state.
4.2.2 Clocks
The periodic interrupt, real-time clock, watchdog timer, and secondary watchdog timer
require the 32 kHz clock.
4.2.3 Interrupts
The periodic interrupt is enabled in GCSR, and will occur every 488 µs. It is cleared by
reading GCSR. It can operate at Priority 1, 2, or 3.
The secondary watchdog interrupt will occur whenever the secondary watchdog is
enabled and allowed to count down to zero. It is cleared by restarting the secondary watchdog by writing to WDTCR. The secondary watchdog interrupt always occurs at Priority 3.
48 Rabbit 5000 Microprocessor User’s Manual
4.3 Operation
4.3.1 Periodic Interrupt
The following steps explain how a periodic interrupt is used.
1. Write the vector to the interrupt service routine to the internal interrupt table.
2. Enable the periodic interrupt by writing to GCSR.
3. The interrupt request is cleared by reading from GCSR.
A sample interrupt handler is shown below.
periodic_isr::
push af
ioi ld a, (GCSR) ; clear the interrupt request and get status
; handle any periodic tasks here
pop af
ipres
ret
4.3.2 Real-Time Clock
The real-time clock consists of six 8-bit registers that together comprise a 48-bit value.
The real-time clock is not synchronized to the read operation, so the least-significant bit
should be read twice and checked for matching values; if the two reads do not match, then
the real-time clock may have been updating during the read and should be read again.
Writing to RTC0R latches the current real-time clock value into the RTCxR holding registers, so the following sequence should be used to read the real-time clock.
1. Write any value to RTC0R and then read back a value from RTC0R.
2. Write a value to RTC0R again, and again read back a value from RTC0R.
3. If the two values do not match, repeat Step 2 until the last two readings are identical.
4. At this point, registers RTC1R through RTC6R can also be read and used.
Note that the periodic interrupt and the real-time clock are clocked by the same edge of the
32 kHz clock; if read from the periodic interrupt, the count is guaranteed to be stable and
only needs to be read once (assuming it occurs within one clock of the 32 kHz clock).
The real-time clock can be reset by writing the sequence 0x40 – 0x80 to RTCCR. It can be
reset and left in the byte increment mode by writing 0x40 – 0xC0 to RTCCR and then
writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time
clock. The byte increment mode is disabled by writing 0x00 to RTCCR.
Chapter 4 System Management 49
4.3.3 Watchdog Timer
The watchdog timer is enabled on reset with a 2-second timeout. Unless specific data are
written to WDTCR before that time expires, the processor will be reset. The watchdog
timer can be disabled by writing a sequence of two bytes to WDTTR as described in the
register description.
Table 4-1. Watchdog Timer Settings
WDTCR Value Effect
0x5A Restart watchdog timer with 2-second timeout.
0x57 Restart watchdog timer with 1-second timeout.
0x59 Restart watchdog timer with 500-millisecond timeout.
0x53 Restart watchdog timer with 250-millisecond timeout.
0x5F Restart the secondary watchdog timer.
The watchdog timer also contains a special test mode that speeds up the timeout period by
clocking it with the peripheral clock instead of the 32 kHz clock. This mode can be
enabled by writing to WDTTR.
4.3.4 Secondary Watchdog Timer
The secondary watchdog timer is disabled on reset. The following steps explain how to
use the secondary watchdog timer.
1. Write the vector to the interrupt service routine to the internal interrupt table.
2. Write the desired timeout period to SWDTR. This also enables the secondary watchdog
timer.
3. Restart the secondary watchdog timer by either writing the timeout period to SWDTR
or writing 0x5F to WDTCR.
If the secondary watchdog timer counts down to zero, a Priority 3 secondary watchdog
interrupt will occur. This interrupt request is cleared by writing a new timeout value to
SWDTR. A sample interrupt handler is shown below.
secwd_isr::
push af
; determine why the interrupt occurred and take appropriate action
ld a, 0x40 ; timeout period of 0x40/32kHz = 1.95ms
ioi ld (SWDTR), a ; clear the interrupt request
pop af
ipres
ret
50 Rabbit 5000 Microprocessor User’s Manual
4.4 Register Descriptions
Global Control/Status Register (GCSR) (Address = 0x0000)
Bit(s) Value Description
7:6 00 No reset or watchdog timer timeout since the last read.
(Read-
only)
5 0 No effect on the periodic interrupt. This bit will always be read as zero.
4:2 000
01 The watchdog timer timed out. These bits are cleared by a read of this register.
10 This bit combination is not possible.
11 Reset occurred. These bits are cleared by a read of this register.
1 Force a periodic interrupt to be pending.
Processor clock from the main clock, divided by eight.
Peripheral clock from the main clock, divided by eight.
001
010
011
100
101
Processor clock from the main clock, divided by eight.
Peripheral clock from the main clock.
Processor clock from the main clock.
Peripheral clock from the main clock.
Processor clock from the main clock, divided by two.
Peripheral clock from the main clock, divided by two.
Processor clock from the 32 kHz clock, optionally divided via GPSCR.
Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
Processor clock from the 32 kHz clock, optionally divided via GPSCR.
Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.
The main clock is disabled.
110
111
1:0 00 Periodic interrupts are disabled.
01 Periodic interrupts use Interrupt Priority 1.
10 Periodic interrupts use Interrupt Priority 2.
11 Periodic interrupts use Interrupt Priority 3.
Chapter 4 System Management 51
Processor clock from the main clock, divided by four.
Peripheral clock from the main clock, divided by four.
Processor clock from the main clock, divided by six.
Peripheral clock from the main clock, divided by six.
Real-Time Clock Control Register (RTCCR) (Address = 0x0001)
Bit(s) Value Description
7:0 0x00
No effect on the real-time clock counter, or disable the byte increment function,
or cancel the real-time clock reset command.
Arm the real-time clock for reset or byte increment. This command must be
0x40
written prior to either the real-time clock reset command or the first byte
increment write.
0x80
0xC0
Reset all six bytes of the real-time clock counter to 0x00. The reset must be
preceded by writing 0x40 to arm the reset function.
Reset all six bytes of the real-time clock counter to 0x00, and remain in byteincrement mode in preparation for setting the time.
7:6 01 This bit combination must be used with every byte-increment write.
5:0 0 No effect on the real-time clock counter.
1 Increment the corresponding byte of the real-time clock counter.
Real-Time Clock x Register (RTC0R) (Address = 0x0002)
(RTC1R) (Address = 0x0003)
(RTC2R) (Address = 0x0004)
(RTC3R) (Address = 0x0005)
(RTC4R) (Address = 0x0006)
(RTC5R) (Address = 0x0007
Bit(s) Value Description
7:0 Read The current value of the 48-bit real-time clock counter is returned.
Write
Writing to RTC0R transfers the current count of the real-time clock to a holding
register while the real-time clock continues counting.
Watchdog Timer Control Register (WDTCR) (Address = 0x0008)
Bit(s) Value Description
7:0 0x5A Restart the watchdog timer with a 2-second timeout period.
0x57 Restart the watchdog timer with a 1-second timeout period.
0x59 Restart the watchdog timer with a 500 ms timeout period.
0x53 Restart the watchdog timer with a 250 ms timeout period.
0x5F Restart the secondary watchdog timer.
other No effect on watchdog timer or secondary watchdog timer.
52 Rabbit 5000 Microprocessor User’s Manual
Watchdog Timer Test Register (WDTTR) (Address = 0x0009)
Bit(s) Value Description
7:0 0x51 Clock the least significant byte of the watchdog timer from the peripheral clock.
0x52 Clock the most significant byte of the watchdog timer from the peripheral clock.
0x53 Clock both bytes of the watchdog timer, in parallel, from the peripheral clock.
Disable the watchdog timer. This value, by itself, does not disable the watchdog
0x54
timer. Only a sequence of two writes, where the first write is 0x51, 0x52, or
0x53, followed by a write of 0x54, actually disables the watchdog timer. The
watchdog timer will be re-enabled by any other write to this register.
other Normal clocking (32 kHz clock) for the watchdog timer.
Secondary Watchdog Timer Register (SWDTR) (Address = 0x000C)
Bit(s) Value Description
The time constant for the secondary watchdog timer is stored. This time constant
will take effect the next time that the secondary watchdog counter counts down
7:0
to zero. The timer counts modulo n + 1, where n is the programmed time constant.
The secondary watchdog timer can be disabled by writing the sequence 0x5A –
0x52 – 0x44 to this register.
Global ROM Configuration Register (GROM) (Address = 0x002C)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
(Read-
only)
1 Ignore the SMODE pins program fetch function.
6:5 Read These bits report the state of the SMODE pins.
4:0 00000 ROM identifier for this version of the chip.
Global RAM Configuration Register (GRAM) (Address = 0x002D)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
(Read-
only)
1 Ignore the SMODE pins program fetch function.
6:5 Read These bits report the state of the SMODE pins.
4:0 00001 RAM identifier for this version of the chip.
Chapter 4 System Management 53
Global Output Control Register (GOCR) (Address = 0x000E)
Bit(s) Value Description
7:6 00 CLK pin is driven with peripheral clock.
01 CLK pin is driven with peripheral clock divided by 2.
10 CLK pin is low.
11 CLK pin is high.
5:4 00 STATUS pin is active (low) during a first opcode byte fetch.
01 STATUS pin is active (low) during an interrupt acknowledge.
10 STATUS pin is low.
11 STATUS pin is high.
3:2 00 /WDTOUT pin functions normally.
01 Enable /WDTOUT for test mode. Reserved for internal use only.
10 /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz).
11 This bit combination is reserved and should not be used.
1:0 00 /BUFEN pin is active (low) during external I/O cycles.
01 /BUFEN pin is active (low) during data memory accesses.
10 /BUFEN pin is low.
11 /BUFEN pin is high.
Global CPU Register (GCPU) (Address = 0x002E)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
(Read-
only)
1 Ignore the SMODE pins program fetch function.
6:5 Read These bits report the state of the SMODE pins.
4:0 00011 CPU identifier for this version of the chip.
Global Revision Register (GREV) (Address = 0x002F)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
(Read-
only)
1 Ignore the SMODE pins program fetch function.
6:5 Read These bits report the state of the SMODE pins.
4:0 00011 CPU identifier for this version of the chip.
54 Rabbit 5000 Microprocessor User’s Manual
Battery-Backed Onchip-Encryption RAM (VRAM00) (Address = 0x0600)
through through
(VRAM31) (Address = 0x061F)
Bit(s) Value Description
7:0 General-purpose RAM locations. Cleared by Intrusion Detect conditions.
Chapter 4 System Management 55
56 Rabbit 5000 Microprocessor User’s Manual
5. MEMORY MANAGEMENT
5.1 Overview
The Rabbit 5000 supports both 8-bit and 16-bit external flash and SRAM devices; three
chip selects and two read/write-enable strobes allow up to six external devices to be
attached at once. The 8-bit mode allows 0, 1, 2, or 4 wait states to be specified for each
device, and the 16-bit mode allows 0 to 7 wait states depending on the settings. Both 8-bit
and 16-bit page-mode devices are also supported.
In addition, the Rabbit 5000 contains 128 KB of internal SRAM that resides on its own
chip select signal. It can be enabled in either 8- or 16-bit mode.
The Rabbit 5000’s physical memory space contains four consecutive banks, each of which
can be mapped to an individual chip-select/enable strobe pair. The banks can be set for
equal sizes ranging from 128 KB up to 4 MB, providing a total physical memory range
from 512 KB up to 16 MB. Figure 5-1 shows a sample configuration.
Chapter 5 Memory Management 57
Either one or both of the two most significant address bits (which are used to select the
1MB
0x00000
0x40000
0x3FFFF
0x80000
0x7FFFF
0xC0000
0xBFFFF
0xFFFFF
Memory Bank 3
MB3CR = 0x86
Memory Bank 2
MB2CR = 0xC5
Memory Bank 1
MB1CR = 0xC0
Memory Bank 0
MB0CR = 0xC0
1 wait state
/CS2
/OE1
/WE1
0 wait states
/CS1
/OE1
/WE1
0 wait states
/CS0
/OE0
/WE0
512KB
Flash
256KB
SRAM
256KB
SRAM
quadrant) can be inverted, providing the ability to bank-switch other pages from a larger
memory device into the same memory bank.
Code is executed in the 64 KB logical memory space, which is divided into four segments:
root, data, stack, and XMEM. The root segment is mapped directly to physical address
0x000000, while the data and stack segments can be mapped to 4 KB boundaries anywhere in the physical space. The boundaries between the root and data segments and the
data and stack segments can be adjusted in 4 KB blocks as well.
The XMEM segment is a fixed 8 KB, and points to a physical memory address block
specified in the XPC register. It is possible to run code in the XMEM window, providing
an easy means of storing and executing code beyond the 64 KB logical memory space.
Special call and return instructions to physical addresses are provided that automatically
update the XPC register as necessary.
58 Rabbit 5000 Microprocessor User’s Manual
Figure 5-1. Mapping Rabbit 5000 Physical Memory Space
Figure 5-2. Logical and Physical Memory Mapping
64 KB
16 MB
LOGICAL
ADDRESS MAP
PHYSICAL
ADDRESS MAP
ROOT
DATA
SEGMENT
STACK
SEGMENT
XPC
000000
FFFFFF
0000
FFFF
E000
x000
y000
SEGSIZE
REGISTER
(0x13) R/W
7 4 3 0
y
x
Chapter 5 Memory Management 59
The Rabbit 2000 and 3000 had numerous instructions for reading and writing data to logical
Memory Bank
Control
Interrupt
Request
MMIDR
MECR
RAMSR
STKSEG*
DATSEG*
SEGSIZE
WPCR
WPxR
WPSyR
WPSyLR
WPSyHR
STKCR
STKzLR
MBxCR
MTCR
MACR
ACSxCR
Logical or
Physical
Access
Interrupt
Handler
Memory
Protection
MMU
/CSx
/WEx
/OEx
D[15:0]
A[23:0]
Physical
Address
addresses, but only had limited support for reading and writing data to a physical memory
address. In the Rabbit 4000, a wide range of instructions was provided to read and write to
physical addresses. The same instructions can be used to write to logical addresses. All of
these instructions are available in the Rabbit 5000.
The 64 KB logical memory space limitation can also be expanded by using the separate
instruction and data space mode. When this mode is enabled, address bit A16 is inverted
for all data accesses in the root and/or data segments, and address bit A19 is inverted for
all data accesses in the root and/or data segments before bank selection (physical device)
occurs. These two features allow both code and data to access separate 64 KB logical
spaces instead of sharing a single space.
It is possible to protect memory in the Rabbit 5000 at three different levels—each of the
memory banks can be made read-only, physical memory can be write-protected in 64 KB
blocks, and two of those 64 KB blocks can be protected with a granularity of 4 KB. A
Priority 3 interrupt will occur if a write is attempted in one of the protected 64 KB or 4 KB
blocks. In addition, it is possible to place limits around the code execution stack and generate
an interrupt if a stack-related write occurs within 16 bytes of those limits.
5.1.1 Block Diagram
60 Rabbit 5000 Microprocessor User’s Manual
5.1.2 Registers
Register Name Mnemonic I/O Address R/W Reset
MMU Instruction/Data Register MMIDR 0x0010 R/W 00000000
Stack Segment Register STACKSEG 0x0011 R/W 00000000
Stack Segment LSB Register STACKSEGL 0x001A R/W 00000000
Stack Segment MSB Register STACKSEGH 0x001B R/W 00000000
Data Segment Register DATSEG 0x0012 R/W 00000000
Data Segment LSB Register DATSEGL 0x001E R/W 00000000
Data Segment MSB Register DATSEGH 0x001F R/W 00000000
Segment Size Register SEGSIZE 0x0013 R/W 11111111
Memory Bank 0 Control Register MB0CR 0x0014 R/W 00001000
Memory Bank 1 Control Register MB1CR 0x0015 R/W xxxxxxxx
Memory Bank 2 Control Register MB2CR 0x0016 R/W xxxxxxxx
Memory Bank 3 Control Register MB3CR 0x0017 R/W xxxxxxxx
MMU Expanded Code Register MECR 0x0018 R/W 00000000
Memory Timing Control Register MTCR 0x0019 R/W 00000000
Memory Alternate Control Register MACR 0x001D R/W 00000000
Advanced /CS0 Control Register ACS0CR 0x0410 R/W 00000000
Advanced /CS1 Control Register ACS1CR 0x0411 R/W 00000000
Advanced /CS2 Control Register ACS2CR 0x0412 R/W 00000000
RAM Segment Register RAMSR 0x0448 R/W 00000000
Write-Protect Control Register WPCR 0x0440 R/W 00000000
Write-Protect x Register WPxR 0x460+x W 00000000
Write-Protect Segment A Register WPSAR 0x0480 W 00000000
Write-Protect Segment A Low Register WPSALR 0x0481 W 00000000
Write-Protect Segment A High Register WPSAHR 0x0482 W 00000000
Write-Protect Segment B Register WPSBR 0x0484 W 00000000
Write-Protect Segment B Low Register WPSBLR 0x0485 W 00000000
Write-Protect Segment B High Register WPSBHR 0x0486 W 00000000
Stack Limit Control Register STKCR 0x0444 R/W 00000000
Stack Low Limit Register STKLLR 0x0445 W xxxxxxxx
Stack High Limit Register STKHLR 0x0446 W xxxxxxxx
Chapter 5 Memory Management 61
5.2 Dependencies
5.2.1 I/O Pins
There are three chip select pins, /CS0, /CS1, and /CS2; two read strobes, /OE0 and /OE1;
and two write strobes, /WE0 and /WE1. /CS3 is available to the internal SRAM only and
does not come out to a pin.
There are eight dedicated data bus pins, D0 through D7. If the 16-bit mode is enabled, then
PH0–PH7 automatically act as the upper byte of the data bus, D8 through D15.
There are 20 dedicated address pins, A0 through A19. Up to four more address pins can be
enabled on PE0–PE3, representing A20 through A23.
Pin PE4 can be enabled as /A0 to allow byte reads and writes in 16-bit SRAM devices.
5.2.2 Clocks
All memory operations are clocked by the processor clock.
5.2.3 Other Registers
Register Function
PEFR, PEALR, PEAHR Enable A20-A23 and /A0.
5.2.4 Interrupts
When a write is attempted to a write-protected 64 KB or 4 KB block, a write-protection
violation interrupt is generated. The interrupt request is cleared when it is handled. The
write-protection violation interrupt vector is in the IIR at offset 0x090. It is always set to
Priority 3.
When a stack-related write is attempted to a region outside that set by the stack limit registers, a stack limit violation occurs. The interrupt request is cleared when it is handled. The
stack limit violation interrupt vector is in the IIR at offset 0x1B0. It is always set to Priority 3.
62 Rabbit 5000 Microprocessor User’s Manual
5.3 Operation
5.3.1 Memory Management Unit (MMU)
Code execution takes place in the 64 KB logical memory space, which is divided into four
segments: root, data, stack, and extended (XMEM). The root segment is always mapped
starting at physical address 0x000000, but the other segments can be remapped to start at
any physical 4 KB block boundary.
The data and stack segment mappings are set by writing to the appropriate register, as shown
in Table 5-1. The DATASEG and STACKSEG registers provide backwards compatibility
to the Rabbit 2000 and 3000 processors; these registers map directly to DATASEGL and
STACKSEGL, but the contents of DATASEGH and STACKSEGH are set to zero.
Table 5-1. Memory Management Registers
Register Segment Size Comments
DATASEG Data 8 bits
DATASEGL Data 8 bits —
DATASEGH Data 4 bits —
STACKSEG Stack 8 bits
STACKSEGL Stack 8 bits —
STACKSEGH Stack 4 bits —
XPC XMEM 8 bits
LXPC XMEM 12 bits
Maps to DATASEGL;
DATASEGH set to 0x00
Maps to STACKSEGL;
STACKSEGH set to 0x00
Loaded via instructions
LD XPC,A and LD A,XPC
Loaded via instructions:
LD LXPC,HL and LD HL,LXPC
Each of these registers provides a 4 KB offset that is added to the logical address to provide
a physical address as shown in Figure 5-3.
Chapter 5 Memory Management 63
Figure 5-3. MMU Operation
0
DATASEG
16-bit logical address
20-bit physical address
0
+
16-bit logical address
+
DATASEGL
DATASEGH
16-bit logical address
+
0
16-bit logical address
20-bit physical address
0
+
STKSEG STKSEGL
24-bit physical address
24-bit physical address
STKSEGH
16-bit logical address
+
24-bit physical address
0
16-bit logical address
20-bit physical address
0
+
XPC
LXPC
5.3.2 Memory Bank Operation
On startup the Rabbit 5000 checks the status of the SYSCFG pins. To provide support for
external memory, both SYSCFG pins should be set low and Memory Bank 0 enabled to
use /CS0, /OE0, and /WE0 in 8-bit mode with four wait states and write protection
enabled. It is expected that an external flash device containing startup code is attached to
those strobes. The other memory banks come up undefined and their controls should be set
via the appropriate MBxCR register to a valid setting before use.
If SYSCFG0 is high and SYSCFG1 is low, Memory Bank 0 is enabled to use /CS3, /OE0,
and /WE0 in 16-bit mode. This allows the processor to start operation directly out of the
internal SRAM.
The size of the memory banks is defined in the MECR register. The default size is 256 KB
(the bank selection looks at the two most significant address bits), but this value can be
adjusted down to 128 KB or up to 4 MB per bank.
64 Rabbit 5000 Microprocessor User’s Manual
The two address bits used to select the bank can be inverted in MBxCR, which enables
0x00000
0x40000
0x3FFFF
0x80000
0x7FFFF
0xC0000
0xBFFFF
0xFFFFF
1MB
Memory
Device
A18, A19 normal
Memory
Bank 0
Memory
Bank 1
.
.
.
0x00000
0x40000
0x3FFFF
0x80000
0x7FFFF
0xC0000
0xBFFFF
0xFFFFF
1MB
Memory
Device
A18 normal,
A19 inverted
Memory
Bank 0
Memory
Bank 1
.
.
.
0x00000
0x40000
0x3FFFF
0x00000
0x40000
0x3FFFF
mapping different sections of a memory device larger than the current memory bank into
memory. Figure 5-4 shows an example of this feature.
Figure 5-4. Mapping Different Sections of a Memory Device
Larger Than the Current Memory Bank
It is possible to extend the timing of the /OE and/or /WE strobes by one half of a clock.
This provides slightly longer strobes for slower memories; see the timing diagrams in
Chapter 31. These options are available in MTCR.
It is possible to force /CS1 to be always active in MMIDR; enabling this will cause conflicts
only if a device shares a /OE or /WE strobe with another device. This option allows faster
access to particular memory devices.
Chapter 5 Memory Management 65
5.3.3 Memory Modes
The Rabbit 5000 supports both 8-bit and 16-bit memories on all chip selects, including the
internal SRAM. It also provides support for page-mode devices. The mode for each chip
select is set in MACR; 8-bit mode is the default for all chip selects.
When in basic 8-bit mode, the wait states are selected in the memory bank registers,
MBxCR; the options are 0, 1, 2, or 4 wait states. Note that this may put an upper bound on
the processor clock speed, depending on the access time of your 8-bit memory device.
When in 16-bit or page-mode (either 8- or 16-bit), the wait states are selected by both the
MBxCR and the advanced chip select registers, ACSxCR.
When the 16-bit mode is enabled, Parallel Port H is used for the high byte of the data, and
is configured automatically for this operation, overriding any other Parallel Port H function.
Table 5-2. Memory Modes
Mode
8-bit Yes No No MBxCR 0, 1, 2, 4
16-bit Selectable Yes Yes
8-bit Page Mode Yes No No
16-bit Page Mode Selectable Yes Yes
Byte
Writes?
Word
Reads?
Word
Writes?
Wait State
Register
MBxCR
ACSxCR
MBxCR
ACSxCR
MBxCR
ACSxCR
Wait State
Options
0–11
0–11 first access,
0–7 page accesses
0–11 first access,
0–7 page accesses
A 16-bit memory device may or may not support byte writes, so there is an option to select
between these two cases in ACSxCR. With the default option any byte writes or unaligned
word writes to a 16-bit memory will be suppressed (i.e., the /WE will not be asserted).
Any aligned word reads or writes are recognized internally and are combined into just one
write transaction on the external bus. The other option for the 16-bit bus does not inhibit
byte writes or unaligned word writes, and replicates the byte data on both halves of the
data bus in these cases. In this mode the A0 and /A0 signals must be used by the memory
to enable the individual bytes.
Table 5-3. A0 and /A0 Signals for Various Transaction Types
Transaction Type A0 /A0
Word Read (prefetch only) Low Low
Word Write Low Low
Byte Read or Write — Even Address Low High
Byte Read or Write — Odd Address High Low
66 Rabbit 5000 Microprocessor User’s Manual
All of the power-saving modes in Chapter 29 can be used with the 16-bit mode.
The second advanced bus mode is the Page Mode. This mode also can be enabled for any
external chip select, and can be used with either 8-bit or 16-bit memories connected to
these chip selects. Page-Mode memories provide for a faster access time if the requested
data are in the same page as the previous data. In the Rabbit 5000 (and most memory
devices) a page can be selected as either 8 or 16 bytes. Thus, if an address is identical to
the previous address except in the lower four bits, the access time is assumed to be faster.
These wait-state options are also controlled in the ACSxCR.
In Page Mode the chip select and /OE remain active from one page access to the next, and
only the three or four least-significant bits of the address change to request the new data.
This obviously interferes with a number of the power-saving modes and will take precedence over them for chip select accesses, as appropriate. The power-saving modes will
still apply to the other chip select and output-enable signals. The logic recognizes which
/OE is being used with each chip select in the Page Mode.
As mentioned previously, the ACSxCR registers each contain three fields to control the
generation of wait states in the advanced bus modes. These settings are in addition to the
wait-state setting in MBxCR when an advanced bus mode is enabled. When the 16-bit bus
is enabled, one to seven automatic wait states for memory read bus cycles can be enabled
in addition to the zero to four wait states in MBxCR. This setting is also used for the first
access when the Page Mode is enabled; a second setting selects the number of wait states
for all subsequent reads in the Page Mode, allowing from zero to three automatic wait
states for the same-page accesses in the Page Mode. The choices available for the
advanced bus wait states are sufficient to allow interfacing to a variety of standard memories for any Rabbit 5000 speed grade.
When a 16-bit memory is connected to /CS0, the first few instructions must program the
device to operate in 16-bit mode. This code is shown below. This code should be the first
thing executed by your device. Because the processor is fetching bytes from a 16-bit
memory device that is not connected to A0, only one-byte instructions can be used, and
they must occur in pairs.
ORG 0000h
XOR A ; a <= 00000000
XOR A
LD H, A ; h <= 00000000
LD H, A
SCF
SCF
RLA ; a <= 00000001
RLA ; a <= 00000010
LD B, A ; b <= 00000010
LD B, A
SCF
SCF
ADC A, B ; a <= 00000101
ADC A, B ; a <= 00000111
ADD A, A ; a <= 00001110
Chapter 5 Memory Management 67
ADD A, A ; a <= 00011100
SCF
SCF
ADC A, H ; a <= 00011101
ADC A, H
LD L, A ; l <= 00011101
LD L, A
IOI ; two IOIs same as one
IOI
LD (HL), B ; MACR <= 00000010
LD (HL), B ; dummy memory write (no /WE)
NOP ; required delay to start
NOP ; up the 16-bit bus
5.3.4 Separate Instruction and Data Space
To make better use of the 64 KB of logical space, an option is provided to map code and
data accesses in the same address space to separate devices. This is accomplished by
enabling the inversion of A16 and the most-significant bit of the bank select bits for accesses
in the root and data segments. Careful use of these features allows both code and data to
separately use up to 64 KB of logical memory.
The RAM segment register (RAMSR) provides a shortcut for updating code by accessing
it as data. It provides a “window” that uses the instruction address decoding when read or
written as data. This mapping will only occur when the RAMSR is within the root or data
segments; the RAMSR will be ignored if it is mapped to the stack segment or XPC
window.
The Rabbit 5000 Designer’s Handbook provides further details on the use of the separate
instruction and data space feature.
5.3.5 Memory Protection
Memory blocks may be protected at three separate granularities, as shown in Table 5-4.
Writes can be prevented to any memory bank by writing to MBxCR. Writes can be prevented and trapped at a resolution of 64 KB by enabling protection for that block in the
appropriate WPxR register. For further control, two of those 64 KB blocks can be further
subdivided into 4 KB blocks by selecting them as the write protect segments A or B.
When a write is attempted to a block protected in WPxR, WPSxLR, or WPSxHR, a
Priority 3 write-protect interrupt occurs. This feature is automatically enabled by writing to
the block protection registers; to disable it, set all the write-protect block registers to zero.
Table 5-4. Memory Protection Options
Method Block Size Registers Used
Memory Bank 128 KB – 4 MB MBxCR, MECR
Write-Protect Blocks 64 KB WPCR, WPxR
Write Protect Segment A/B 4 KB WPSxR, WPSxLR, WPSxHR
68 Rabbit 5000 Microprocessor User’s Manual
5.3.6 Stack Protection
The Rabbit 5000 provides stack overflow and underflow protection. Low and high logical
address limits can be set in STKLLR and STKHLR; a Priority 3 stack-violation interrupt
occurs when a stack-based write occurs within the 16 bytes below the upper limit or
within the 16 bytes above the lower limit. Note that the writes will still occur even if they
are within the 16 bytes surrounding the limits, but the interrupt can serve as a warning to
the application that the stack is in danger of being over or underrun.
The stack checking can be enabled or disabled by writing to STKCR.
Chapter 5 Memory Management 69
5.4 Register Descriptions
MMU Instruction/Data Register (MMIDR) (Address = 0x0010)
Bit(s) Value Description
Internal I/O addresses are decoded using only the lower eight bits of the internal
70
1
6 This bit is reserved an must be written with zero.
I/O address bus. This restricts internal I/O addresses to the range 0x0000–
0x00FF.
Internal I/O addresses are decoded using all 15 bits of the address internal I/O
address bus. This option must be selected to access internal I/O addresses of
0x0100 and higher.
50
1
4 0 Normal /CS1 operation.
1
3 0 Normal operation.
1
2 0 Normal operation.
1 For a data segment access, invert A16
1 0 Normal operation.
1
0 0 Normal operation.
Enable A16 and bank select address MSB inversion independent of
instruction/data.
Enable A16 and bank select address MSB inversion for data accesses only. This
enables the instruction/data split.
Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an output enable or write enable with
another memory.
For a data segment access, invert bank select address MSB before MBxCR
decision.
For a root segment access, invert bank select address MSB before MBxCR
decision.
1 For a root segment access, invert A16
Stack Segment Register (STACKSEG) (Address = 0x0011)
Bit(s) Value Description
7:0 Read The current contents of this register are reported.
Write
70 Rabbit 5000 Microprocessor User’s Manual
Eight LSBs (MSBs are set to zero by write) of physical address offset to use if
SEGSIZ[7:4] Addr[15:12] < 0xE
Stack Segment Low Register (STACKSEGL) (Address = 0x001A)
Bit(s) Value Description
7:0 Read The current contents of this register are reported.
Write
Eight LSBs of physical address offset to use if SEGSIZ[7:4] Addr[15:12] <
0xE
Stack Segment High Register (STACKSEGH) (Address = 0x001B)
Bit(s) Value Description
7:4
These bits are reserved and should always be written as zero. These bits always
return zeros when read.
3:0 Read The current contents of this register are reported.
Write
Four MSBs of physical address offset to use if SEGSIZ[7:4] Addr[15:12] <
0xE
Data Segment Register (DATSEG) (Address = 0x0012)
Bit(s) Value Description
7:0 Read The current contents of this register are reported.
Write
Eight LSBs (MSBs are set to zero by write) of physical address offset to use if:
SEGSIZ[3:0] Addr[15:12] < SEGSIZ[7:4]
Data Segment Low Register (DATSEGL) (Address = 0x001E)
Bit(s) Value Description
7:0
Eight LSBs of physical address offset to use if SEGSIZ[3:0] Addr[15:12] <
SEGSIZ[7:4]
Data Segment High Register (DATSEGH) (Address = 0x001F)
Bit(s) Value Description
7:4
3:0
Chapter 5 Memory Management 71
These bits are reserved and should always be written as zero. These bits always
return zeros when read.
Four MSBs of physical address offset to use if SEGSIZ[3:0] Addr[15:12] <
SEGSIZ[7:4]
Segment Size Register (SEGSIZ) (Address = 0x0013)
Bit(s) Value Description
7:0 Read The current contents of this register are reported.
7:4 Write Boundary value for switching from DATSEG to STACKSEG for translation.
3:0 Write Boundary value for switching from none to DATSEG for translation.
Memory Bank x Control Register (MB0CR) (Address = 0x0014)
(MB1CR) (Address = 0x0015)
(MB2CR) (Address = 0x0016)
(MB3CR) (Address = 0x0017)
Bit(s) Value Description
7:6 00 Four (five for writes) wait states for accesses in this bank.
01 Two (three for writes) wait states for accesses in this bank.
10 One (two for writes) wait states for accesses in this bank.
11 Zero (one for writes) wait states for accesses in this bank.
5 0 Pass bank select address MSB for accesses in this bank.
1 Invert bank select address MSB for accesses in this bank.
4 0 Pass bank select address LSB for accesses in this bank.
1 Invert bank select address LSB for accesses in this bank.
3:2 00 /OE0 and /WE0 are active for accesses in this bank.
01 /OE1 and /WE1 are active for accesses in this bank.
10
11
/OE0 only is active for accesses in this bank (i.e., read-only). Transactions are
normal in every other way.
/OE1 only is active for accesses in this bank (i.e., read-only). Transactions are
normal in every other way.
1:0 00 /CS0 is active for accesses in this bank.
01 /CS1 is active for accesses in this bank.
10 /CS2 is active for accesses in this bank.
/CS3 (internal memory) is active for accesses in this bank. When standalone
11
operation is selected (by strapping a pin), this bit combination is forced for
MB0CR only.
72 Rabbit 5000 Microprocessor User’s Manual
MMU Expanded Code Register (MECR) (Address = 0x0018)
Bit(s) Value Description
7:5 000 Bank select address is A[19:18].
001 Bank select address is A[20:19].
010 Bank select address is A[21:20].
011 Bank select address is A[22:21].
100 Bank select address is A[23:22].
101 This bit combination is reserved and should not be used.
110 This bit combination is reserved and should not be used.
111 Bank select address is A[18:17].
4:3 These bits are reserved and should be written with zeros. Read returns zeros.
2:0 000 Normal operation.
001 This bit combination is reserved and should not be used.
010 This bit combination is reserved and should not be used.
011 This bit combination is reserved and should not be used.
100 For an XPC access, use MB0CR independent of bank select address.
101 For an XPC access, use MB1CR independent of bank select address.
110 For an XPC access, use MB2CR independent of bank select address.
111 For an XPC access, use MB3CR independent of bank select address.
Memory Timing Control Register (MTCR) (Address = 0x0019)
Bit(s) Value Description
7:4 These bits are reserved and should be written with zeros.
3 0 Normal timing for /OE1 (rising edge to rising edge, one clock minimum).
1 Extended timing for /OE1 (one-half clock earlier than normal).
2 0 Normal timing for /OE0 (rising edge to rising edge, one clock minimum).
1 Extended timing for /OE0 (one-half clock earlier than normal).
10
Normal timing for /WE1 (rising edge to falling edge, one and one-half clocks
minimum).
1 Extended timing for /WE1 (falling edge to falling edge, two clocks minimum).
00
1 Extended timing for /WE0 (falling edge to falling edge, two clocks minimum).
Chapter 5 Memory Management 73
Normal timing for /WE0 (rising edge to falling edge, one and one-half clocks
minimum).
Memory Alternate Control Register (MACR) (Address = 0x001D)
Bit(s) Value Description
70
1
Normal 8-bit operation for /CS3. Use MBxCR for wait states. This bit is used
only when external memory is present.
Normal 16-bit operation for /CS3. Use MBxCR for wait states. When standalone operation is selected (by strapping a pin), this bit is forced high.
6 This bit is reserved and must not be used.
5:4 00 Normal 8-bit operation for /CS2.
01 Page-Mode 8-bit operation for /CS2.
10 Normal 16-bit operation for /CS2.
11 Page-Mode 16-bit operation for /CS2.
3:2 00 Normal 8-bit operation for /CS1.
01 Page-Mode 8-bit operation for /CS1.
10 Normal 16-bit operation for /CS1.
11 Page-Mode 16-bit operation for /CS1.
1:0 00 Normal 8-bit operation for /CS0.
01 Page-Mode 8-bit operation for /CS0.
10 Normal 16-bit operation for /CS0.
11 Page-Mode 16-bit operation for /CS0.
74 Rabbit 5000 Microprocessor User’s Manual
Advanced Chip Select x Control Register (ACS0CR) (Address = 0x0410)
(ACS1CR) (Address = 0x0411)
(ACS2CR) (Address = 0x0412)
Bit(s) Value Description
7:5 000 Zero extra wait states for reads, writes, or first Page-Mode access.
001 One extra wait state for reads, writes, or first Page-Mode read access.
010 Two extra wait states for reads, writes, or first Page-Mode access.
011 Three extra wait states for reads, writes, or first Page-Mode read access.
100 Four extra wait states for reads, writes, or first Page-Mode read access.
101 Five extra wait states for reads, writes, or first Page-Mode read access.
110 Six extra wait state for reads, writes, or first Page-Mode read access.
111 Seven extra wait state for reads, writes, or first Page-Mode read access.
4:3 00 Zero extra wait states for subsequent Page-Mode accesses.
01 One extra wait state for subsequent Page-Mode accesses.
10 Two extra wait states for subsequent Page-Mode accesses.
11 Three extra wait states for subsequent Page-Mode accesses.
2 This bit is reserved and should not be used.
1 0 Page size 16 bytes.
1 Page size 8 bytes.
0 0 Disable byte writes on 16-bit bus.
1 Enable byte writes on 16-bit bus.
RAM Segment Register (RAMSR) (Address = 0x0448)
Bit(s) Value Description
7:2 Compare value for RAM segment limit checking.
1:0 00 Disable RAM segment limit checking.
01 Select data-type MMU translation if PC[15:10] is equal to RAMSR[7:2].
10 Select data-type MMU translation if PC[15:11] is equal to RAMSR[7:3].
11 Select data-type MMU translation if PC[15:12] is equal to RAMSR[7:4].
Chapter 5 Memory Management 75
Write Protection Control Register (WPCR) (Address = 0x0440)
Bit(s) Value Description
7:1 These bits are reserved and should be written with zeros.
0 0 Write protection in User Mode only.
1 Write protection in System and User modes.
76 Rabbit 5000 Microprocessor User’s Manual
Write-Protect x Register (WP0R) (Address = 0x0460)
(WP1R) (Address = 0x0461)
(WP2R) (Address = 0x0462)
(WP3R) (Address = 0x0463)
(WP4R) (Address = 0x0464)
(WP5R) (Address = 0x0465)
(WP6R) (Address = 0x0466)
(WP7R) (Address = 0x0467)
(WP8R) (Address = 0x0468)
(WP9R) (Address = 0x0469)
(WP10R) (Address = 0x046A)
(WP11R) (Address = 0x046B)
(WP12R) (Address = 0x046C)
(WP13R) (Address = 0x046D)
(WP14R) (Address = 0x046E)
(WP15R) (Address = 0x046F)
(WP16R) (Address = 0x0470)
(WP17R) (Address = 0x0471)
(WP18R) (Address = 0x0472)
(WP19R) (Address = 0x0473)
(WP20R) (Address = 0x0474)
(WP21R) (Address = 0x0475)
(WP22R) (Address = 0x0476)
(WP23R) (Address = 0x0477)
(WP24R) (Address = 0x0478)
(WP25R) (Address = 0x0479)
(WP26R) (Address = 0x047A)
(WP27R) (Address = 0x047B)
(WP28R) (Address = 0x047C)
(WP29R) (Address = 0x047D)
(WP30R) (Address = 0x047E)
(WP31R) (Address = 0x047F)
Bit(s) Value Description
7:0 0 Disable write protection for the corresponding 64 KB segment.
Enable write protection for the corresponding 64 KB segment. The eight-bit
1
address of the segment to be write-protected is formed using bits [4:0] of the
WPxR register address concatenated with the bit address of the corresponding bit
in the register.
Chapter 5 Memory Management 77
Write-Protect Segment x Register (WPSAR) (Address = 0x0480)
(WPSBR) (Address = 0x0484)
Bit(s) Value Description
7:0
When these eight bits [23:16] match bits of the physical address, write-protect
that 64 KB range in 4 KB increments using WPSxLR and WPSxHR.
Write-Protect Segment x Low Register (WPSALR) (Address = 0x0481)
(WPSBLR) (Address = 0x0485)
Bit(s) Value Description
7 0 Disable 4 KB write protect for relative address 0x7000–0x7FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x7000–0x7FFF in WP Segment x.
6 0 Disable 4 KB write protect for relative address 0x6000–0x6FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x6000–0x6FFF in WP Segment x.
5 0 Disable 4 KB write protect for relative address 0x5000–0x5FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x5000–0x5FFF in WP Segment x.
4 0 Disable 4 KB write protect for relative address 0x4000–0x4FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x4000–0x4FFF in WP Segment x.
3 0 Disable 4 KB write protect for relative address 0x3000–0x3FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x3000–0x3FFF in WP Segment x.
2 0 Disable 4 KB write protect for relative address 0x2000–0x2FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x2000–0x2FFF in WP Segment x.
1 0 Disable 4 KB write protect for relative address 0x1000–0x1FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x1000–0x1FFF in WP Segment x.
0 0 Disable 4 KB write protect for relative address 0x0000–0x0FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x0000–0x0FFF in WP Segment x.
78 Rabbit 5000 Microprocessor User’s Manual
Write-Protect Segment x High Register (WPSAHR) (Address = 0x0482)
(WPSBHR) (Address = 0x0486)
Bit(s) Value Description
7 0 Disable 4 KB write protect for relative address 0xF000–0xFFFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0xF000–0xFFFF in WP Segment x.
6 0 Disable 4 KB write protect for relative address 0xE000–0xEFFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0xE000–0xEFFF in WP Segment x.
5 0 Disable 4 KB write protect for relative address 0xD000–0xDFFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0xD000–0xDFFF in WP Segment x.
4 0 Disable 4 KB write protect for relative address 0xC000–0xCFFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0xC000–0xCFFF in WP Segment x.
3 0 Disable 4 KB write protect for relative address 0xB000–0xBFFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0xB000–0xBFFF in WP Segment x.
2 0 Disable 4 KB write protect for relative address 0xA000–0xAFFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0xA000–0xAFFF in WP Segment x.
1 0 Disable 4 KB write protect for relative address 0x9000–0x9FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x9000–0x9FFF in WP Segment x.
0 0 Disable 4 KB write protect for relative address 0x8000–0x8FFF in WP Segment x.
1 Enable 4 KB write protect for relative address 0x8000–0x8FFF in WP Segment x.
Stack Limit Control Register (STKCR) (Address = 0x0444)
Bit(s) Value Description
7:1 These bits are reserved and should be written with zeros.
0 0 Disable stack-limit checking.
1 Enable stack-limit checking.
Stack Low Limit Register (STKLLR) (Address = 0x0445)
Bit(s) Value Description
Lower limit for stack-limit checking. If a stack operation or stack-relative
7:0
memory access is attempted at an address less than {STKLLR, 0x10}, a stacklimit violation interrupt is generated.
Chapter 5 Memory Management 79
Stack High Limit Register (STKHLR) (Address = 0x0446)
Bit(s) Value Description
Upper limit for stack-limit checking. If a stack operation or stack-relative
7:0
memory access is attempted at an address greater than {STKHLR, 0xEF}, a
stack-limit violation interrupt is generated.
80 Rabbit 5000 Microprocessor User’s Manual
6. INTERRUPTS
6.1 Overview
The Rabbit 5000 can operate at one of four priority levels, 0–3, with Priority 0 being the
expected standard operating level. The current priority and up to three previous priority
levels are kept in the processor’s 8-bit IP register, where bits 0–1 contain the current
priority. Every time an interrupt is handled or an IPSET instruction occurs, the value in the
register is shifted left by two bits, and the new priority placed in bits 0–1. When an IPRES
or IRET instruction occurs, the value in IP is shifted right by two bits (bits 0–1 are shifted
into bits 6–7). On reset, the processor starts at Priority 3.
Most interrupts can be set to be Priority 1–3. A pending interrupt will be handled only if
its interrupt priority is greater than the current processor priority. This means that even a
Priority 3 interrupt can be blocked if the processor is currently at Priority 3. The System
Mode Violation, Stack Limit Violation, Write Protection Violation, secondary watchdog,
and breakpoint interrupts are always enabled at Priority 3. In addition, when the System/
User Mode is enabled and the processor is in the User Mode, the processor will not actually enter Priority 3; any attempt to enter Priority 3 will actually be requested as Priority 2.
When an interrupt is handled, a call is executed to a fixed location in the interrupt vector
tables. This operation requires 11 clocks, the minimum interrupt latency for the Rabbit
5000. There are two vector tables, the internal and the external interrupt vector tables, that
can be located anywhere in logical memory by setting the processor’s IIR and EIR registers.
The IIR and EIR registers hold the upper byte of each table’s address. For example, if IIR
is loaded with 0xC4, then the internal interrupt vector table will start at the logical memory
address 0xC400.
The internal interrupt vector table occupies 512 bytes, and the external interrupt vector
table is 256 bytes in size. Since the RST and SYSCALL vectors use all eight bits of the
IIR for addressing, the lowermost bit of IIR should always be set to zero so to keep some
vectors from inadvertently overlapping.
Each interrupt’s vector begins on a 16-byte boundary inside the vector tables. It may be
possible to fit a small routine into that space, but it is typical to place a call to a separate
routine in that location.
Some Rabbit 5000 instructions are “chained atomic,” which means that an interrupt cannot
occur between that instruction and the following instruction. These instructions are useful
for doing things like exiting interrupt handlers properly or updating semaphores.
Chapter 6 Interrupts 81
6.2 Operation
To ensure proper operation, all interrupt handler routines should be written according to
the following guidelines.
• Push all registers to be used by the routine onto the stack before use, and pop them off
the stack before returning from the ISR.
• Keep the ISR as short and fast as possible. The use of assembly code is strongly recom-
mended.
• If the ISR will run for some time, lower the interrupt priority as soon as possible within
the ISR to allow other interrupts to occur.
• A number of special rules apply to interrupts when operating in the system/user mode;
please see the appropriate chapter for more details.
6.3 Interrupt Tables
Table 6-1 shows the structure of the internal interrupt vector table. The first column is the
vector address offset within the table. The second column shows the vectors in the first
256 bytes of the table, and the third column shows the vectors in the second 256 bytes.
Table 6-1. Internal Interrupt Vector Table Structure
Offset 0x0000 + Offset 0x0100 + Offset
0x00 Periodic Interrupt —
0x10 Secondary Watchdog —
0x20 RST 10 —
0x30 RST 18 —
0x40 RST20 —
0x50 RST 28 —
0x60 Syscall instruction —
0x70 RST 38 PWM
0x80 Slave Port Sys/User Mode Violation
0x90 Write Protect Violation Quadrature Decoder
0xA0 Timer A Input Capture
0xB0 Timer B Stack Limit Violation
0xC0 Serial Port A Serial Port E
0xD0 Serial Port B Serial Port F
0xE0 Serial Port C Network Port B/C
0xF0 Serial Port D Timer C
82 Rabbit 5000 Microprocessor User’s Manual
Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector
falls on a 16-byte boundary inside the table.
Table 6-2. External Interrupt Vector Table Structure
Offset 0x0000+
0x00 External Interrupt 0
0x10 External Interrupt 1
0x20 —
0x30 —
0x40 Breakpoints
0x50 —
0x60 —
0x70 —
0x80 DMA Channel 0
0x90 DMA Channel 1
0xA0 DMA Channel 2
0xB0 DMA Channel 3
0xC0 DMA Channel 4
0xD0 DMA Channel 5
0xE0 DMA Channel 6
0xF0 DMA Channel 7
There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3.
Interrupts marked as “cleared automatically” have their requests cleared when the interrupt is first handled.
Chapter 6 Interrupts 83
Table 6-3. Interrupt Priorities
Priority Interrupt Source Action Required to Clear the Interrupt
Highest Breakpoint Read the status from BDCR.
System Mode Violation Cleared automatically.
Stack Limit Violation Cleared automatically.
Write Protection Violation Cleared automatically.
Secondary Watchdog Restart secondary watchdog by writing to WDTCR.
External Interrupt 1 Cleared automatically.
External Interrupt 0 Cleared automatically.
Periodic Interrupt Read the status from GCSR.
Quadrature Decoder Read the status from QDCSR.
Timer B Read the status from TBCSR.
Timer A Read the status from TACSR.
Input Capture Read the status from ICCSR.
PWM Write any PWM register.
Timer C Read the status from TCCSR.
Slave Port
Rd: Read from SPD0R, SPD1R or SPD2R.
Wr: Write to SPD0R, SPD1R, SPD2R or dummy write to SPSR.
DMA 7 Cleared automatically.
DMA 6 Cleared automatically.
DMA 5 Cleared automatically.
DMA 4 Cleared automatically.
DMA 3 Cleared automatically.
DMA 2 Cleared automatically.
DMA 1 Cleared automatically.
DMA 0 Cleared automatically.
Network Port B/C Read interrupt status from NBCSR or NCCSR.
Serial Port E
Serial Port F
Serial Port A
Serial Port B
Rx: Read from SEDR or SEAR.
Tx: Write to SEDR, SEAR, SELR or dummy write to SESR.
Rx: Read from SFDR or SFAR.
Tx: Write to SFDR, SFAR, SFLR or dummy write to SFSR.
Rx: Read from SADR or SAAR.
Tx: Write to SADR, SAAR, SALR or dummy write to SASR.
Rx: Read from SBDR or SBAR.
Tx: Write to SBDR, SBAR, SBLR or dummy write to SBSR.
Serial Port C
Lowest Serial Port D
84 Rabbit 5000 Microprocessor User’s Manual
Rx: Read from SCDR or SCAR.
Tx: Write to SCDR, SCAR, SCLR or dummy write to SCSR.
Rx: Read from SDDR or SDAR.
Tx: Write to SDDR, SDAR, SDLR or dummy write to SDSR.
7. EXTERNAL INTERRUPTS
External Interrupts
Enable and
Edge Detection
PD0
External
Interrupt 0
Request
Enable and
Edge Detection
Enable and
Edge Detection
Interupt 0
Generation
PE0
PE4
Enable and
Edge Detection
Enable and
Edge Detection
Enable and
Edge Detection
PD1
PE1
PE5
Interrupt 1
Generation
External
Interrupt 1
Request
I0CR
I1CR
I0CR
I1CR
7.1 Overview
The Rabbit 5000 has six external interrupts available, and they share two interrupt vectors.
In the case of multiple interrupts sharing an interrupt vector, the data register corresponding to the parallel port(s) being used can be read. Each interrupt vector can be set to trigger
on a rising edge, a falling edge, or either edge.
The signal on the external interrupt pin must be present for at least three peripheral clock
cycles to be detected. In addition, the Rabbit 5000 has a minimum latency of 11 clocks to
respond to an interrupt, so the minimum external interrupt response time is three peripheral clock cycles plus 11 processor clock cycles.
7.2 Block Diagram
Chapter 7 External Interrupts 85
7.2.1 Registers
Register Name Mnemonic I/O Address R/W Reset
Interrupt 0 Control Register I0CR 0x0098 R/W xx000000
Interrupt 1 Control Register I1CR 0x0099 R/W xx000000
7.3 Dependencies
7.3.1 I/O Pins
The external interrupts can be enabled on pins PD0, PD1, PE0, PE1, PE4, and PE5. Each
pin is associated with a particular interrupt vector as shown in Table 7-1 below.
Table 7-1. Rabbit 5000 Interrupt Vectors
Vector Register Pins
Interrupt 0 I0CR PD0, PE0, PE4
Interrupt 1 I1CR PD1, PE1, PE5
7.3.2 Clocks
The external interrupts are controlled by the peripheral clock. A pulse must be present for
at least three peripheral clock cycles to trigger an interrupt.
7.3.3 Interrupts
An external interrupt is generated whenever the selected edge occurs on an enabled pin.
The interrupt request is automatically cleared when the interrupt is handled.
The external interrupt vectors are in the EIR at offsets 0x000 and 0x010. They can be set
as Priority 1, 2, or 3 in the appropriate IxCR.
7.4 Operation
The following steps must be taken to enable the external interrupts.
1. Write the vector(s) to the interrupt service routine to the external interrupt table.
2. Configure IxCR to select which pins are enabled for external interrupts, what edges are
detected on each pin, and the interrupt priority.
3. When an interrupt occurs, read PDDR and/or PEDR to determine which pin has a signal if more than one pin is enabled for a given external interrupt.
86 Rabbit 5000 Microprocessor User’s Manual
7.4.1 Example ISR
A sample interrupt handler is shown below.
extInt_isr::
; respond to external interrupt here
; interrupt is automatically cleared by interrupt acknowledge
ipres
ret
Chapter 7 External Interrupts 87
7.5 Register Descriptions
Interrupt x Control Register (I0CR) (Address = 0x0098)
(I1CR) (Address = 0x0099)
Bit(s) Value Description
7:6 00 Parallel Port D low nibble interrupt disabled.
01 Parallel Port D low nibble interrupt on falling edge.
10 Parallel Port D low nibble interrupt on rising edge.
11 Parallel Port D low nibble interrupt on both edges.
5:4 00 Parallel Port E high nibble interrupt disabled.
01 Parallel Port E high nibble interrupt on falling edge.
10 Parallel Port E high nibble interrupt on rising edge.
11 Parallel Port E high nibble interrupt on both edges.
3:2 00 Parallel Port E low nibble interrupt disabled.
01 Parallel Port E low nibble interrupt on falling edge.
10 Parallel Port E low nibble interrupt on rising edge.
11 Parallel Port E low nibble interrupt on both edges.
1:0 00 This external interrupt is disabled.
01 This external interrupt uses Interrupt Priority 1.
10 This external interrupt uses Interrupt Priority 2.
11 This external interrupt uses Interrupt Priority 3.
88 Rabbit 5000 Microprocessor User’s Manual
8. PARALLEL PORT A
Parallel Port A
SPCR
PADR
Data
Slave Data
External I/O Data
7:0
7:0
7:0
8.1 Overview
Parallel Port A is a byte-wide port that can be used as an input or an output port. Parallel
Port A is also used as the data bus for the slave port and external I/O bus. The Slave Port
Control Register (SPCR) is used to configure how Parallel Port A is used. Parallel Port A
is an input at startup or reset. If the SMODE pins have selected the slave port bootstrap
mode, Parallel Port A will be the slave port data bus until disabled by the processor. Parallel
Port A can also be used as an external I/O data bus to isolate external I/O from the main
data bus.
Table 8-1. Parallel Port A Pin Alternate Output Functions
Pin Name
PA[7:0] SD[7:0] ID[7:0]
Slave Port
Data Bus
External I/O
Bus
8.1.1 Block Diagram
8.1.2 Registers
Port A Data Register PADR 0x0030 R/W xxxxxxxx
Register Name Mnemonic I/O Address R/W Reset
Chapter 8 Parallel Port A 89
8.2 Dependencies
8.2.1 I/O Pins
Parallel Port A uses pins PA0 through PA7. These pins can be used as follows.
• General-purpose 8-bit data input (write 0x080 to SPCR)
• General-purpose 8-bit data output (write 0x084 to SPCR)
• Slave port data bus (write 0x088 to SPCR)
• External I/O data bus (write 0x08C to SPCR)
All Parallel Port A bits are inputs at startup or reset.
See the associated peripheral chapters for details on how they use Parallel Port A.
8.2.2 Clocks
Any outputs on Parallel Port A are clocked by the peripheral clock.
8.2.3 Other Registers
Register Function
SPCR Used to set up Parallel Port A.
8.2.4 Interrupts
There are no interrupts associated with Parallel Port A, except when the slave port is being
used.
8.3 Operation
The following steps explain how to set up Parallel Port A.
1. Select the desired mode using SPCR.
2. If the slave port or external I/O bus is selected, refer to the chapters for those peripherals for further setup.
Once Parallel Port A is set up, data can be read or written by accessing PADR. Note that
Parallel Port A is not available for general-purpose I/O while the slave port or the external
I/O bus is selected. Selecting these options for Parallel Port A affects Parallel Port B
because Parallel Port B is then used for address and control signals.
90 Rabbit 5000 Microprocessor User’s Manual
8.4 Register Descriptions
Parallel Port A Data Register (PADR) (Address = 0x0030)
Bit(s) Value Description
7:0 Read The current state of Parallel Port A pins PA7–PA0 is reported.
Write
Slave Port Control Register (SPCR) (Address = 0x0024)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
1 Ignore the SMODE pins program fetch function.
6:5 read These bits report the state of the SMODE pins.
write These bits are ignored and should be written with zero.
4:2 000 Disable the slave port. Parallel Port A is a byte-wide input port.
001 Disable the slave port. Parallel Port A is a byte-wide output port.
010 Enable the slave port, with /SCS from Parallel Port E bit 7.
011
100 This bit combination is reserved and should not be used.
The Parallel Port A buffer is written with this value for transfer to the Parallel
Port A output register on the next rising edge of the peripheral clock.
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel
Port B[7:2] is used for the address bus.
101 This bit combination is reserved and should not be used.
110 Enable the slave port, with /SCS from Parallel Port B bit 6.
111
1:0 00 Slave port interrupts are disabled.
01 Slave port interrupts use Interrupt Priority 1.
10 Slave port interrupts use Interrupt Priority 2.
11 Slave port interrupts use Interrupt Priority 3.
Chapter 8 Parallel Port A 91
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel
Port B[7:0] is used for the address bus.
92 Rabbit 5000 Microprocessor User’s Manual
9. PARALLEL PORT B
9.1 Overview
Parallel Port B is a byte-wide port with each bit programmable for direction. The Parallel
Port B pins are also used to access other peripherals on the chip—the slave port, the
auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A
and B. The Slave Port Control Register (SPCR) is used to configure how Parallel Port B is
used when selecting the slave port or the external I/O bus modes.
When the slave port is enabled, either under program control or during parallel bootstrap,
Parallel Port B pins carry the Slave Attention output signal, and the Slave Read strobe, Slave
Write strobe, and Slave Address inputs. The Slave Chip Select can also be programmed to
come from a Parallel Port B pin.
When the external I/O bus option is enabled, either six or eight pins carry the external I/O
address signals selected in SPCR.
Two pins are used for the clocks for Serial Ports A and B when they are configured for the
clocked serial mode. These two inputs can be used as clock outputs for these ports if
selected in the respective serial port control registers. Note that the clocked serial output
clock selection overrides all other programming for the two relevant Parallel Port B pins.
Table 9-1. Parallel Port B Pin Alternate Output Functions
Pin Name Slave Port
PB7 /SLVATTN — IA5
PB6 /SCS — IA4
PB5 SA1 — IA3
PB4 SA0 — IA2
PB3 /SRD — IA1
PB2 /SWR — IA0
PB1 — SCLKA IA7
PB0 — SCLKB IA6
Chapter 9 Parallel Port B 93
Serial Ports
A–D
External I/O
Bus
9.1.1 Block Diagram
Parallel Port B
SPCR
PBDDR
SACR
SBCR
PBDR
Data
7:0
7:2
1:0
External I/O
Address
Serial Ports A & B
Clocks
SA1, SA0, /SLAVATT N
/SCS, /SRD, /SWR
7:2, 7:0
9.1.2 Registers
Register Name Mnemonic I/O Address R/W Reset
Port B Data Register PBDR 0x0040 R/W 00xxxxxx
Port B Data Direction Register PBDDR 0x0047 R/W 11000000
9.2 Dependencies
9.2.1 I/O Pins
Parallel Port B uses pins PB0 through PB7. These pins can be used individually as data
inputs or outputs; as the address bits for the external I/O bus; as control signals for the
slave port; or as clocks for Serial Ports A and B.
On startup, bits 6 and 7 are outputs set low for backwards compatibility with the Rabbit
2000. All other pins are inputs.
Note that when the external I/O bus or slave port is enabled in SPCR, the Parallel Port B
pins associated with those peripherals perform those actions, no matter what the settings
are in PBDR or PBDDR. See the associated peripheral chapters for details on how they
use Parallel Port B.
9.2.2 Clocks
All outputs on Parallel Port B are clocked by the peripheral clock (perclk).
9.2.3 Other Registers
94 Rabbit 5000 Microprocessor User’s Manual
SPCR
Register Function
Sets the Parallel Port B function for some pins if the
slave port or external I/O bus is enabled.
9.2.4 Interrupts
There are no interrupts associated with Parallel Port B, except when the slave port is being
used.
9.3 Operation
The following steps must be taken before using Parallel Port B.
1. Select the desired input/output direction for each pin via PBDDR. Note that this setting
is superseded for some pins if the slave port or external I/O bus is enabled in SPCR or if
the clocked serial mode is enabled for Serial Ports A or B.
2. If the slave port or the external I/O bus is selected, refer to the chapters for those
peripherals for further setup information.
Once the port is set up, data can be read or written by accessing PBDR. The value in
PBDR of an output pin will reflect its current output value, but any value written to an
input pin will not appear on that pin until that pin becomes an output.
9.4 Register Descriptions
Parallel Port B Data Register (PBDR) (Address = 0x0040)
Bit(s) Value Description
7:0 Read The current state of Parallel Port B pins PB7–PB0 is reported.
Write
Parallel Port B Data Direction Register (PBDDR) (Address = 0x0047)
Bit(s) Value Description
7:0 0 The corresponding port bit is an input.
1 The corresponding port bit is an output.
The Parallel Port B buffer is written with this value for transfer to the Parallel
Port B output register on the next rising edge of the peripheral clock.
Chapter 9 Parallel Port B 95
Slave Port Control Register (SPCR) (Address = 0x0024)
Bit(s) Value Description
7 0 Program fetch as a function of the SMODE pins.
1 Ignore the SMODE pins program fetch function.
6:5 Read These bits report the state of the SMODE pins.
Write These bits are ignored and should be written with zero.
4:2 000 Disable the slave port. Parallel Port A is a byte-wide input port.
001 Disable the slave port. Parallel Port A is a byte-wide output port.
010 Enable the slave port, with /SCS from Parallel Port E bit 7.
011
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel
Port B[7:2] is used for the address bus.
100 This bit combination is reserved and should not be used.
101 This bit combination is reserved and should not be used.
110 Enable the slave port, with /SCS from Parallel Port B bit 6.
111
Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel
Port B[7:0] is used for the address bus.
1:0 00 Slave port interrupts are disabled.
01 Slave port interrupts use Interrupt Priority 1.
10 Slave port interrupts use Interrupt Priority 2.
11 Slave port interrupts use Interrupt Priority 3.
96 Rabbit 5000 Microprocessor User’s Manual
10. PARALLEL PORT C
10.1 Overview
Parallel Port C is a byte-wide port with each bit programmable for data direction and drive
level. These are simple inputs and outputs controlled and reported in the Port C Data Register (PCDR).
All the Parallel Port C pins have alternate output functions, and most of them can be used
as inputs to various on-chip peripherals.
Table 10-1. Parallel Port C Pin Alternate Output Functions
Pin Name Alt Out 0 Alt Out 1 Alt Out 2 Alt Out 3
PC7 TXA I7 PWM3 SCLKC
PC6 TXA I6 PWM2 TXE
PC5 TXB I5 PWM1 RCLKE
PC4 TXB I4 PWM0 TCLKE
PC3 TXC I3 TIMER C3 SCLKD
PC2 TXC I2 TIMER C2 TXF
PC1 TXD I1 TIMER C1 RCLKF
PC0 TXD I0 TIMER C0 TCLKF
Table 10-2. Parallel Port C Pin Alternate Input Functions
Pin Name Input Capture
PC7
PC6———
PC5
PC4 — — TCLKE
PC3
PC2———
PC1
PC0 — — TCLKF
×
×
×
×
Serial Ports
A–D
RXA RXE
RXB RCLKE
RXC RXF
RXD RCLKF
Serial Ports
E–F
Chapter 10 Parallel Port C 97
After reset, the default condition for Parallel Port C is four outputs (the even-numbered
Parallel Port C
PCFR
PCALR
PCAHR
PCDDR
PCDCR
PCDR
Data
7:0
7:4
External I/O
Strobes
Serial Ports AF
Tx, Rx, Clocks
PWM Output
Timer C Output
Input Capture
7:0
7:0
3:0
7, 5, 3, 1
bits) and four inputs (the odd-numbered bits). For compatibility with the Rabbit 2000 and
the Rabbit 3000 microprocessors, these outputs are driven with a logic zero (low) on PC6
and a logic one (high) on PC4, PC2, and PC0. When PCDR is read, the value of the voltage on the pin is returned. If the pin is an output, the value it is set to is returned.
10.1.1 Block Diagram
10.1.2 Registers
Register Name Mnemonic I/O Address R/W Reset
Port C Data Register PCDR 0x0050 R/W 00010101
Port C Data Direction Register PCDDR 0x0051 R/W 01010101
Port C Alternate Low Register PCALR 0x0052 R/W 00000000
Port C Alternate High Register PCAHR 0x0053 R/W 00000000
Port C Drive Control Register PCDCR 0x0054 R/W 00000000
Port C Function Register PCFR 0x0055 R/W 00000000
98 Rabbit 5000 Microprocessor User’s Manual
10.2 Dependencies
10.2.1 I/O Pins
Parallel Port C uses pins PC0 through PC7. These pins can be used individually as data
inputs or outputs; as serial port transmit and receive for Serial ports A–F; as clocks for
Serial Ports C–F; as external I/O strobes; or as outputs for the PWM and Timer C peripherals. The input capture peripheral can also watch pins PC7, PC5, PC3, and PC1.
On startup, PC4, PC2, and PC0 are outputs set high, PC6 is set low, and the other pins are
inputs for compatibility with the Rabbit 3000.
The individual pins can be set to be open-drain via PCDCR.
See the associated peripheral chapters for details on how they use Parallel Port C.
10.2.2 Clocks
All outputs on Parallel Port C are clocked by the peripheral clock.
10.2.3 Other Registers
Register Function
SACR, SBCR, SCCR,
SDCR, SECR, SFCR
ICS1R, ICS2R
Select a Parallel Port C pin as serial data (and
optional clock) input.
Select a Parallel Port C pin as a start/stop condition
for Input Capture input.
10.2.4 Interrupts
There are no interrupts associated with Parallel Port C.
10.3 Operation
The following steps must be taken before using Parallel Port C.
1. Select the desired input/output direction for each pin via PCDDR.
2. Select driven or open-drain functionality for outputs via PCDCR.
3. If an alternate peripheral output function is desired for a pin, select it via PCALR or
PCAHR and then enable it via PCFR. Refer to the appropriate peripheral chapter for
further use of that pin.
Once the port is set up, data can be read or written by accessing PCDR. The value in
PCDR of an output pin will reflect its current output value, but any value written to an
input pin will not appear on that pin until that pin becomes an output.
Chapter 10 Parallel Port C 99
10.4 Register Descriptions
Parallel Port C Data Register (PCDR) (Address = 0x0050)
Bit(s) Value Description
7:0 Read The current state of Parallel Port C pins PC7–PC0 is reported.
Write
Parallel Port C Data Direction Register (PCDDR) (Address = 0x0051)
Bit(s) Value Description
7:0 0 The corresponding port bit is an input.
1 The corresponding port bit is an output.
Parallel Port C Alternate Low Register (PCALR) (Address = 0x0052)
Bit(s) Value Description
7:6 00 Parallel Port C bit 3 alternate output 0 (TXC).
01 Parallel Port C bit 3 alternate output 1 (I3).
10 Parallel Port C bit 3 alternate output 2 (TIMER C3).
11 Parallel Port C bit 3 alternate output 3 (SCLKD).
The Parallel Port C buffer is written with this value for transfer to the Parallel
Port C output register on the next rising edge of the peripheral clock.
5:4 00 Parallel Port C bit 2 alternate output 0 (TXC).
01 Parallel Port C bit 2 alternate output 1 (I2).
10 Parallel Port C bit 2 alternate output 2 (TIMER C2).
11 Parallel Port C bit 2 alternate output 3 (TXF).
3:2 00 Parallel Port C bit 1 alternate output 0 (TXD).
01 Parallel Port C bit 1 alternate output 1 (I1).
10 Parallel Port C bit 1 alternate output 2 (TIMER C1).
11 Parallel Port C bit 1 alternate output 3 (RCLKF).
1:0 00 Parallel Port C bit 0 alternate output 0 (TXD).
01 Parallel Port C bit 0 alternate output 1 (I0).
10 Parallel Port C bit 0 alternate output 2 (TIMER C0).
11 Parallel Port C bit 0 alternate output 3 (TCLKF).
100 Rabbit 5000 Microprocessor User’s Manual
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