Digi NS9215 User Manual

NS9215

Hardware Reference

90000847_C Release date: 10 April 2008

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Contents

Chapter 1: Pinout (265) ..................................................... 27

The Legend .............................................................................. 27

Memory bus interface................... ....... ....... ........ ....... ............... ....... ... 28

Ethernet interface MAC....................................................................... 30

General purpose I/O (GPIO) ................................................................. 31

System clock ................................................................................... 43

System clock drawing.................................................................. 44

RTC clock and battery backup drawing ............................................. 45

System mode................................................................................... 45

System reset ................................................................................... 47

JTAG Test....................................................................................... 48

ADC ............................................... ............................................... 49

POR and battery-backed logic............................................................... 50

Power and ground ............................................................................. 51

Chapter 2: I/O Control Module ...........................................53

System memory bus I/O control...................................................... 53

Control and Status registers ................................................................. 53

GPIO Configuration registers ................................................................ 55

GPIO configuration options............................................................ 55

GPIO Configuration Register #0 ...................................................... 56

GPIO Configuration Register #1 ...................................................... 56

GPIO Configuration Register #2 ...................................................... 57

GPIO Configuration Register #3 ...................................................... 57

GPIO Configuration Register #4 ...................................................... 58

GPIO Configuration Register #5 ...................................................... 58

GPIO Configuration Register #6 ...................................................... 59

GPIO Configuration Register #7 ...................................................... 59

GPIO Configuration Register #8 ...................................................... 60

GPIO Configuration Register #9 ...................................................... 60

GPIO Configuration Register #10 ..................................................... 61

GPIO Configuration Register #11 ..................................................... 61

GPIO Configuration Register #12 ..................................................... 62

GPIO Configuration Register #13 ..................................................... 62

GPIO Configuration Register #14 ..................................................... 63

GPIO Configuration Register #15 .....................................................63

GPIO Configuration Register #16 .....................................................64

GPIO Configuration Register #17 .....................................................64

GPIO Configuration Register #18 .....................................................65

GPIO Configuration Register #19 .....................................................65

GPIO Configuration Register #20 .....................................................66

GPIO Configuration Register #21 .....................................................66

GPIO Configuration Register #22 .....................................................67

GPIO Configuration Register #23 .....................................................67

GPIO Configuration Register #24 .....................................................68

GPIO Configuration Register #25 .....................................................68

GPIO Configuration Register #26 .....................................................69

GPIO Control registers ........................................................................ 70

GPIO Control Register #0 .............................................................. 70

GPIO Control Register #1 .............................................................. 71

GPIO Control Register #2 .............................................................. 72

GPIO Control Register #3 .............................................................. 73

GPIO Status registers.......................................................................... 74

GPIO Status Register #1................................................................ 74

GPIO Status Register #2................................................................ 75

GPIO Status Register #3................................................................ 76

Memory Bus Configuration register ......................................................... 76

Chapter 3: Working with the CPU ....................................... 81

About the processor.................................................................... 81

Arm926EJ-S process block diagram ..................................................82

Instruction sets ................................................................................82

ARM instruction set.....................................................................82

Thumb instruction set.................................................................. 82

Java instruction set .................................................................... 83

System control processor (CP15) registers................................................. 83

ARM926EJ-S system addresses ........................................................ 83

Address manipulation example....................................................... 83

Accessing CP15 registers............................................................... 83

Terms and abbreviations .... .............. ........ ....... ....... ........ ....... ....... 84

R0: ID code and cache type status registers ..............................................86

R0: ID code .............................................................................. 86

R0: Cache type register................................................................ 86

Cache type register and field description ..........................................87

Dsize and Isize fields...................................................................87

R1: Control register ...........................................................................88

Control register ......................................................................... 89

Bit functionality.........................................................................89

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ICache and DCache behavior..........................................................90

R2: Translation Table Base register.........................................................91

R3:Domain Access Control register..........................................................91

Access permissions and instructions .................................................91

R4 register ......................................................................................92

R5: Fault Status registers............................................ ....... ........ ....... ...92

Access instructions......................................................................92

Status and domain fields...............................................................93

R6: Fault Address register....................................................................93

Access instructions......................................................................93

R7:Cache Operations register................................................................94

Write instruction........................................................................94

Cache functions .........................................................................94

Cache operation functions.............................................................95

Modified virtual address format (MVA) ..............................................96

Set/Way format .........................................................................96

Set/Way example .......................................................................96

Test and clean DCache instructions..................................................96

Test, clean, and invalidate DCache instruction....................................97

R8:TLB Operations register...................................................................97

TLB operations ..........................................................................97

TLB operation instructions ............................................................97

Modified virtual address format (MVA) ..............................................98

R9: Cache Lockdown register ................................................................98

Cache ways...............................................................................98

Instruction or data lockdown register ...............................................99

Access instructions......................................................................99

Modifying the Cache Lockdown register.............................................99

Cache Lockdown register L bits.......................................................99

Lockdown cache: Specific loading of addresses into a cache-way ............ 100

Cache unlock procedure ............................................................. 101

R10:TLB Lockdown register ................................................................ 101

P bit..................................................................................... 101

Invalidate operation.................................................................. 101

Programming instructions............................................................ 102

Sample code sequence............................................... ........ ....... . 102

R11 and R12 registers ................................................ ....... ........ ....... . 102

R13:Process ID register ..................................................................... 102

FCSE PID register........................................ ....... ....... ........ ....... . 103

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Access instructions ....................................................................103

Performing a fast context switch ...................................................103

Context ID register ....................................................................104

Access instructions ....................................................................104

R14 register....................................................................................104

R15: Test and debug register...............................................................104

Jazelle(Java) ..................................................................................104

DSP..............................................................................................105

MemoryManagement Unit (MMU)...........................................................105

MMU Features ..........................................................................105

Access permissions and domains ....................................................106

Translated entries.....................................................................106

MMU program accessible registers ..................................................107

Address translation....................................................................107

Translation table base ................................................................108

TTB register format ...................................................................108

Table walk process ....................................................................109

First-level fetch........................................................................109

First-level fetch concatenation and address ......................................110

First-level descriptor..................................................................110

Page table descriptors ................................................................110

First-level descriptor bit assignments: Priority encoding of fault status .....111

First-level descriptor bit assignments: Interpreting first level descriptor bits

[1:0]..................................................................................111

Section descriptor .....................................................................111

Section descriptor format ............................................................111

Section descriptor bit description...................................................112

Coarse page table descriptor ........................................................112

Coarse page table descriptor format...............................................112

Coarse page table descriptor bit description......................................112

Fine page table descriptor ...........................................................112

Fine page table descriptor format..................................................113

Fine page table descriptor bit description.........................................113

Translating section references ......................................................113

Second-level descriptor...............................................................114

Second-level descriptor format .....................................................114

Second-level descriptor pages.......................................................114

Second-level descriptor bit assignments...........................................115

Second-level descriptor least significant bits .....................................115

Translation sequence for large page references...... ....... ........ ....... ......116

Translating sequence for small page references .................................117

Translation sequence for tiny page references ...................................118

Subpages ................................................................................118

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MMU faults and CPU aborts................................................................. 119

Alignment fault checking ............................................................ 119

Fault Address and Fault Status registers .......................................... 119

Priority encoding table............................................................... 120

Fault Address register (FAR)......................................................... 120

FAR values for multi-word transfers ............................................... 120

Compatibility issues .................................................................. 121

Domain access control ...................................................................... 121

Specifying access permissions....................................................... 121

Interpreting access permission bits ................................................ 121

Fault checking sequence.................................................................... 122

Alignment faults....................................................................... 123

Translation faults ..................................................................... 124

Domain faults.......................................................................... 124

Permission faults...................................................................... 124

External aborts............................................................................... 125

Enabling and disabling the MMU........................................................... 125

Enabling the MMU..................................................................... 125

Disabling the MMU .................................................................... 1 26

TLB structure................................................................................. 126

Caches and write buffer .................................................................... 127

Cache features ........................................................................ 127

Write buffer............................................................................ 128

Enabling the caches .................................................................. 128

ICache I and M bit settings .......................................................... 129

ICache page table C bit settings.................................................... 129

R1 register C and M bits for DCache ............................................... 129

DCache page table C and B settings ............................................... 129

Cache MVA and Set/Way formats ......................................................... 130

Generic, virtually indexed, virtually addressed cache.......................... 131

ARM926EJ-S cache format ........................................................... 132

ARM926EJ-S cache associativity .................................................... 132

Set/way/word format for ARM926EJ-S caches ................................... 132

Noncachable instruction fetches .......................................................... 133

Self-modifying code .................................................................. 133

AHB behavior .......................................................................... 134

Instruction Memory Barrier.......................................................... 134

IMB operation.......................................................................... 134

Sample IMB sequences ............................................................... 135

. . . . .

Chapter 4: System Control Module ....................................137

Features ................................................................................ 137

Bus interconnection ......................................................................... 137

System bus arbiter........................................................................... 138

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High speed bus system................................................................138

High-speed bus arbiters...............................................................138

How the bus arbiter works ...........................................................138

Ownership...............................................................................139

Locked bus sequence..................................................................139

Relinquishing the bus .................................................................139

SPLIT transfers .........................................................................140

Arbiter configuration example.......................................................140

Address decoding.............................................................................141

Programmable timers........................................................................142

Software watchdog timer ............................................................142

General purpose timers/counters..........................................................143

Source clock frequency...............................................................143

GPTC characteristics............................... .............. ........ ....... ......143

Control field............................................................................143

16-bit mode options...................................................................144

Basic PWM function ..........................................................................144

Functional block diagram.............................................................144

Enhanced PWM function.....................................................................145

Sample enhanced PWM waveform ..................................................145

Quadrature decoder function...............................................................145

How the quadrature decoder/counter works ............................................146

Provides input signals.................................................................146

Monitors how far the encoder has moved..........................................147

Digital filter ............................................................................147

Testing signals..................................................... ........ ....... ......147

Timer support ..........................................................................147

Interrupt controller ..........................................................................148

FIQ interrupts ..........................................................................148

IRQ interrupts ..........................................................................148

32-vector interrupt controller.......................................................148

IRQ characteristics ....................................................................149

Interrupt sources ......................................................................149

Vectored interrupt controller (VIC) flow..................................................151

Configurable system attributes.............................................................151

PLL configuration.............................................................................151

PLL configuration and control system block diagram ............................152

Bootstrap initialization ......................................................................152

Configuring the powerup settings...................................................152

System configuration registers .............................................................154

General Arbiter Control register ...........................................................158

BRC0, BRC1, BRC2, and BRC3 registers ...................................................158

Channel allocation.....................................................................159

AHB Error Detect Status 1...................................................................159

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AHB Error Detect Status 2 .................................................................. 160

AHB Error Monitoring Configuration register ............................................ 161

Timer Master Control register ............................................................. 162

Timer 0–4 Control registers................................................................. 164

Timer 5 Control register .................................................................... 166

Timer 6–9 Control registers................................................................. 168

Timer 6–9 High registers .................................................................... 170

Timer 6–9 Low registers..................................................................... 171

Timer 6–9 High and Low Step registers................................................... 172

Timer 6–9 Reload Step registers........................................................... 172

Timer 0-9 Reload Count and Compare register ......................................... 173

Timer 0-9 Read and Capture register..................................................... 174

Interrupt Vector Address Register Level 31–0 ........................................... 175

Int (Interrupt) Config (Configuration) 31–0 registers................................... 175

Individual register mapping ......................................................... 175

ISADDR register............................................................................... 176

Interrupt Status Active...................................................................... 177

Interrupt Status Raw ........................................................................ 178

Software Watchdog Configuration ........................................................ 178

Software Watchdog Timer.................................................................. 179

Clock Configuration register ............................................................... 180

Module Reset register....................................................................... 182

Miscellaneous System Configuration and Status register .............................. 184

PLL Configuration register...... ........ ....... ....... ........ ....... ....... ........ ....... . 186

PLL frequency formula............................................................... 186

Active Interrupt Level ID Status register................................................. 187

Power Management.......................................................................... 187

AHB Bus Activity Status ..................................................................... 190

System Memory Chip Select 0 Dynamic Memory Base and Mask registers........... 190

System Memory Chip Select 1 Dynamic Memory Base and Mask registers........... 191

System Memory Chip Select 2 Dynamic Memory Base and Mask registers........... 192

System Memory Chip Select 3 Dynamic Memory Base and Mask registers........... 193

System Memory Chip Select 0 Static Memory Base and Mask registers.............. 194

System Memory Chip Select 1 Static Memory Base and Mask registers.............. 195

System Memory Chip Select 2 Static Memory Base and Mask registers.............. 196

System Memory Chip Select 3 Static Memory Base and Mask registers.............. 197

Gen ID register ............................................................................... 198

External Interrupt 0–3 Control register................................................... 199

RTC Module Control register ............................................................... 200

. . . . .

Chapter 5: Memory Controller .......................................... 203

Features ................................................................................ 203

Low-power operation................................................................ ....... . 204

Low-power SDRAM deep-sleep mode............................................... 204

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Low-power SDRAM partial array refresh ...........................................204

Memory map...................................................................................205

Power-on reset memory map ........................................................205

Chip select 1 memory configuration................................................205

Example: Boot from flash, SRAM mapped after boot ............................205

Example: Boot from flash, SDRAM remapped after boot ........................206

Static memory controller....................................................................207

Write protection.......................................................................208

Extended wait transfers ..............................................................208

Memory mapped peripherals.........................................................209

Static memory initialization ................................................................209

Access sequencing and memory width .............................................209

Wait state generation.................................................................209

Programmable enable.................................................................210

Static memory read control.................................................................210

Output enable programmable delay................................................210

ROM, SRAM, and Flash ................................................................210

Static memory read: Timing and parameters ............................................211

External memory read transfer with zero wait states ...........................211

External memory read transfer with two wait states............................211

External memory read transfer with two output enable delay states.........212

External memory read transfers with zero wait states..........................212

Burst of zero wait states with fixed length........................................213

Burst of two wait states with fixed length ........................................213

Asynchronous page mode read .............................................................214

Asynchronous page mode read: Timing and parameters ...............................214

External memory page mode read transfer .......................................214

External memory 32-bit burst read from 8-bit memory .........................215

Static memory write control................................................................216

Write enable programming delay ...................................................216

SRAM.....................................................................................216

Static memory Write: Timing and parameters...........................................216

External memory write transfer with zero wait states ..........................216

External memory write transfer with two wait states...........................217

External memory write transfer with two write enable delay states .........217

Two external memory write transfers with zero wait states ...................218

Flash memory ..........................................................................218

Bus turnaround................................................................................219

Bus turnaround: Timing and parameters..................................................219

Read followed by write with no turnaround.......................................219

Write followed by a read with no turnaround.....................................220

Read followed by a write with two turnaround cycles...........................220

Byte lane control .............................................................................221

Address connectivity.........................................................................222

Memory banks constructed from 8-bit or non-byte-partitioned memory devices

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222

Memory banks constructed from 16-or 32-bit memory devices................ 223

Dynamic memory controller................................................................ 225

Write protection ...................................................................... 225

Access sequencing and memory width............................. ........ ....... . 225

SDRAM Initialization ................................................................. ....... . 225

Left-shift value table: 32-bit wide data bus SDRAM (RBC) ..................... 226

Left-shift value table: 32-bit wide data bus SDRAM (BRC) ..................... 227

Left-shift value table: 16-bit wide data bus SDRAM (RBC) ..................... 227

Left-shift value table: 16-bit wide data bus SDRAM (BRC) ..................... 228

SDRAM address and data bus interconnect .............................................. 228

32-bit wide configuration............................................................ 228

32-bit wide configuration............................................................ 229

Registers ...................................................................................... 230

Reset values ........................................................................... 232

Control register .............................................................................. 232

Status register................................................................................ 234

Configuration register....................................................................... 234

Dynamic Memory Control register......................................................... 235

Dynamic Memory Refresh Timer register................................................. 236

Dynamic Memory Read Configuration register .......................................... 237

Dynamic Memory Precharge Command Period register................................ 238

Dynamic Memory Active to Precharge Command Period register .................... 239

Dynamic Memory Self-refresh Exit Time register ....................................... 240

Dynamic Memory Last Data Out to Active Time register .............................. 240

Dynamic Memory Data-in to Active Command Time register ......................... 241

Dynamic Memory Write Recovery Time register ........................................ 242

Dynamic Memory Active to Active Command Period register......... ........ ....... . 243

Dynamic Memory Auto Refresh Period register ......................................... 243

Dynamic Memory Exit Self-refresh register.............................................. 244

Dynamic Memory Active Bank A to Active Bank B Time register ..................... 245

Dynamic Memory Load Mode register to Active Command Time register........... 246

Static Memory Extended Wait register ................................................... 247

Example ................................................................................ 247

Dynamic Memory Configuration 0–3 registers ........................................... 247

Address mapping for the Dynamic Memory Configuration registers........... 249

Chip select and memory devices ................................................... 250

Dynamic Memory RAS and CAS Delay 0–3 registers ..................................... 250

StaticMemory Configuration 0–3 registers................................................ 251

StaticMemory Write Enable Delay 0–3 registers......................................... 254

Static Memory Output Enable Delay 0–3 registers ...................................... 255

Static Memory Read Delay 0–3 registers.................................................. 256

StaticMemory Page Mode Read Delay 0–3 registers..................................... 256

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Static Memory Write Delay 0–3 registers..................................................257

StaticMemory Turn Round Delay 0–3 registers ...........................................258

Chapter 6: Ethernet Communication Module ...................... 261

Features.................................................................................261

Common acronyms ....................................................................261

Ethernet communications module ..................................................262

Ethernet MAC..................................................................................262

MAC module block diagram ..........................................................263

MAC module features .................................................................263

PHY interface mappings ..............................................................264

Station address logic (SAL)..................................................................264

MAC receiver ...........................................................................265

Statistics module .............................................................................265

Ethernet front-end module .................................................................266

Ethernet front-end module (EFE) ...................................................266

Receive packet processor ............................................................266

Transmit packet processor ...........................................................267

Receive packet processor ...................................................................267

Power down mode.....................................................................267

Transferring a frame to system memory...........................................268

Receive buffer descriptor format ...................................................268

Receive buffer descriptor format description.....................................268

Receive buffer descriptor field definitions........................................269

Transmit packet processor..................................................................269

Transmit buffer descriptor format..................................................270

Transmit buffer descriptor field definitions.......................................270

Transmitting a frame..................................................................271

Frame transmitted successfully .....................................................272

Frame transmitted unsuccessfully ..................................................272

Transmitting a frame to the Ethernet MAC........................................272

Ethernet underrun.....................................................................272

Ethernet slave interface.....................................................................273

Interrupts ......................................................................................273

Interrupt sources ......................................................................273

Status bits...............................................................................274

Resets ..........................................................................................274

Multicast address filtering ..................................................................275

Filter entries ...........................................................................275

Multicast address filter registers....................................................275

Multicast address filtering example 1 ..............................................275

Multicast address filtering example 2 ..............................................276

Notes ....................................................................................276

Clock synchronization........................................................................276

14 Hardware Reference NS9215

Writing to other registers............................................................ 276

Ethernet Control and Status registers .................................................... 277

Ethernet General Control Register #1 .................................................... 279

Ethernet General Control Register #2 .................................................... 282

Ethernet General Status register.......................................................... 283

Ethernet Transmit Status register......................................................... 284

Ethernet Receive Status register.................................................. ....... . 286

MAC Configuration Register #1............................................................. 288

MAC Configuration Register #2............................................................. 289

PAD operation table for transmit frames.......................................... 291

Back-to-Back Inter-Packet-Gap register.................................................. 291

Non Back-to-Back Inter-Packet-Gap register ............................................ 292

Collision Window/Retry register........................................................... 293

Maximum Frame register ................................................................... 294

MII Management Configuration register .................................................. 295

Clocks field settings .................................................................. 296

MII Management Command register....................................................... 296

MII Management Address register ......................................................... 297

MII Management Write Data register...................................................... 298

MII Management Read Data register ...................................................... 298

MII Management Indicators register....................................................... 299

Station Address registers ................................................................... 300

Station Address Filter register............................................................. 301

RegisterHash Tables......................................................................... 302

HT1...................................................................................... 302

HT2...................................................................................... 303

Statistics registers ........................................................................... 303

Combined transmit and receive statistics counters address map ............. 303

Receive statistics counters address map.......................................... 304

Receive byte counter (A060 069C) ................................................. 304

Receive packet counter (A060 06A0) .............................................. 304

Receive FCS error counter (A060 06A4) ........................................... 305

Receive multicast packet counter (A060 06A8) .................................. 305

Receive broadcast packet counter (A060 06AC) ................................. 305

Receive control frame packet counter (A060 06B0)............................. 305

Receive PAUSE frame packet counter (A060 06B4).............................. 305

Receive unknown OPCODE packet counter (A060 06B8) ........................ 305

Receive alignment error counter (A060 06BC) ................................... 306

Receive code error counter (A060 06C4).......................................... 306

Receive carrier sense error counter (A060 06C8)................................ 306

Receive undersize packet counter (A060 06CC).................................. 306

Receive oversize packet counter (A060 06D0).................................... 306

Receive fragments counter (A060 06D4) .......................................... 306

Receive jabber counter (A060 06D8)............................................... 307

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Transmit statistics counters address map .........................................307

Transmit byte counter (A060 06E0).................................................307

Transmit packet counter (A060 06E4)..............................................308

Transmit multicast packet counter (A060 06E8)..................................308

Transmit broadcast packet counter (A060 06EC) .................................308

Transmit deferral packet counter (A060 06F4) ...................................308

Transmit excessive deferral packet counter (A060 06F8) .......................308

Transmit single collision packet counter (A060 06FC) ...........................308

Transmit multiple collision packet counter (A060 0700) ........................309

Transmit late collision packet counter (A060 0704)..............................309

Transmit excessive collision packet counter (A060 0708).......................309

Transmit total collision packet counter (A060 070C) ............................309

Transmit jabber frame counter (A060 0718) ......................................309

Transmit FCS error counter (A060 071C)...........................................309

Transmit oversize frame counter (A060 0724) ....................................310

Transmit undersize frame counter (A060 0728)...................................310

Transmit fragment counter (A060 072C)...........................................310

General Statistics registers address map ..........................................310

Carry Register 1........................................................................310

Carry Register 2........................................................................311

Carry Register 1 Mask register.......................................................312

Carry Register 2 Mask register.......................................................314

RX_A Buffer Descriptor Pointer register ..................................................315

RX_B Buffer Descriptor Pointer register ..................................................315

RX_C Buffer Descriptor Pointer register ..................................................316

RX_D Buffer Descriptor Pointer register ..................................................316

Ethernet Interrupt Status register .........................................................317

Ethernet Interrupt Enable register.........................................................319

TX Buffer Descriptor Pointer register .....................................................320

Transmit Recover Buffer Descriptor Pointer register ...................................321

TX Error Buffer Descriptor Pointer register ..............................................321

TX Stall Buffer Descriptor Pointer register ...............................................322

RX_A Buffer Descriptor Pointer Offset register..........................................323

RX_B Buffer Descriptor Pointer Offset register ..........................................324

RX_C Buffer Descriptor Pointer Offset register..........................................324

RX_D Buffer Descriptor Pointer Offset register..........................................325

Transmit Buffer Descriptor Pointer Offset register .....................................325

RX Free Buffer register ......................................................................326

Multicast Address Filter registers ..........................................................327

Multicast Low Address Filter Register #0...........................................327

Multicast Low Address Filter Register #1...........................................327

Multicast Low Address Filter Register #2...........................................327

Multicast Low Address Filter Register #3...........................................327

Multicast Low Address Filter Register #4...........................................327

Multicast Low Address Filter Register #5...........................................327

16 Hardware Reference NS9215

Multicast Low Address Filter Register #6.......................................... 328

Multicast Low Address Filter Register #7.......................................... 328

Multicast High Address Filter Register #0 ......................................... 328

Multicast High Address Filter Register #1 ......................................... 328

Multicast High Address Filter Register #2 ......................................... 328

Multicast High Address Filter Register #3 ......................................... 328

Multicast High Address Filter Register #4 ......................................... 328

Multicast High Address Filter Register #5 ......................................... 328

Multicast High Address Filter Register #6 ......................................... 329

Multicast High Address Filter Register #7 ......................................... 329

Multicast Address Mask registers .......................................................... 329

Multicast Low Address Mask Register #0........................................... 329

Multicast Low Address Mask Register #1........................................... 329

Multicast Low Address Mask Register #2........................................... 329

Multicast Low Address Mask Register #3........................................... 329

Multicast Low Address Mask Register #4........................................... 330

Multicast Low Address Mask Register #5........................................... 330

Multicast Low Address Mask Register #6........................................... 330

Multicast Low Address Mask Register #7........................................... 330

Multicast High Address Mask Register #0.......................................... 330

Multicast High Address Mask Register #1.......................................... 330

Multicast High Address Mask Register #2.......................................... 330

Multicast High Address Mask Register #3.......................................... 330

Multicast High Address Mask Register #4.......................................... 330

Multicast High Address Mask Register #5.......................................... 331

Multicast High Address Mask Register #6.......................................... 331

Multicast High Address Mask Register #7.......................................... 331

Multicast Address Filter Enable register.................................................. 331

TX Buffer Descriptor RAM................................................................... 332

Offset+0 ................................................................................ 332

Offset+4 ................................................................................ 333

Offset+8 ................................................................................ 333

Offset+C................................................................................ 333

RX FIFO RAM .................................................................................. 333

Sample hash table code............................... ........ ....... ....... ........ ....... . 334

. . . . .

Chapter 7: External DMA ................................................339

DMA transfers...... ........ ....... ........ ....... ....... ........ ....... ....... ............... . 339

Initiating DMA transfers.............................................................. 339

Processor-initiated.................................................................... 339

External peripheral-initiated........................................................ 339

DMA buffer descriptor.... ....... ........ ....... ....... ........ ....... ....... ............... . 340

DMA buffer descriptor diagram ..................................................... 340

Source address [pointer]............................................................ . 340

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Buffer length ................................ ........ ....... ....... ........ ....... ......340

Destination address [pointer]........................................... ....... ......340

Status....................................................................................341

Wrap (W) bit........... ........ ....... ....... ........ ....... ....... ........ ....... ......341

Interrupt (I) bit.........................................................................341

Last (L) bit..............................................................................341

Full (F) bit ..............................................................................341

Descriptor list processing.............................................................. ......341

Peripheral DMA read access.................................................................342

Determining the width of PDEN .....................................................342

Equation variables.....................................................................342

Peripheral DMA single read access..................................................343

Peripheral DMA burst read access...................................................343

Peripheral DMA write access................................................................343

Determining the width of PDEN .....................................................344

Peripheral DMA single write access.................................................344

Peripheral DMA burst write access..................................................344

Peripheral REQ and DONE signaling........................................................344

REQ signal...............................................................................344

DONE signal.............................................................................345

Special circumstances.................................................................345

Static RAM chip select configuration ......................................................345

Static ram chip select configuration................................................345

Control and Status registers ................................................................346

DMA Buffer Descriptor Pointer..............................................................346

DMA Control register.........................................................................347

DMA Status and Interrupt Enable register ................................................350

DMA Peripheral Chip Select register.......................................................352

Chapter 8: AES Data Encryption/Decryption Module ........... 355

18 Hardware Reference NS9215

Features.................................................................................355

Block diagram ..........................................................................356

Data blocks .............................................................................356

AES DMA buffer descriptor ..................................................................356

AES buffer descriptor diagram.......................................................357

Source address [pointer] .............................................................357

Source buffer length ..................................................................357

Destination buffer length........................................ ........ ....... ......357

Destination address [pointer]........................................... ....... ......357

AES control .............................................................................357

AES op code.............................................................................358

WRAP (W) bit...........................................................................358

Interrupt (I) bit.........................................................................358

Last (L) bit ............................................................................. 358

Full (F) bit.............................................................................. 358

Decryption .................................................................................... 359

ECB processing ............................................................................... 359

Processing flow diagram ............................................................. 359

CBC, CFB, OFB, and CTR processing ...................................................... 360

Processing flow diagram ............................................................. 360

CCM mode..................................................................................... 360

Nonce buffer........................................................................... 361

Processing flow........................................................................ 361

Chapter 9: I/O Hub Module .............................................. 363

Block diagram ......................................................................... 364

AHB slave interface.................................................................. . 364

DMA controller ............................................................................... 364

Servicing RX and FIFOs ............................................................... 364

Buffer descriptors..................................................................... 365

Source address [pointer]............................................................ . 365

Buffer length........................................................................... 365

Control[15] – W........................................................................ 365

Control[14] – I ......................................................................... 365

Control[13] – L......................................................................... 365

Control[12] – F......................................................................... 365

Control[11:0] .......................................................................... 366

Status[15:0]............................................................................ 366

Transmit DMA example...................................................................... 367

Process.................................................................................. 367

Visual example ........................................................................ 368

Control and status register address maps................................................ 368

UART A register address map ....................................................... 369

UART B register address map ....................................................... 369

UART C register address map ....................................................... 370

UART D register address map ....................................................... 370

SPI register address map............................................................. 371

AD register address map............................................................. 371

Reserved................................................................................ 371

I2C register address map............................................................. 371

Reserved................................................................................ 371

RTC register address map............................................................ 372

IO Hardware Assist register address map (0) ..................................... 372

IO Hardware Assist register address map (1) ..................................... 372

IO register address map (0) ......................................................... 372

IO register address map (1) ......................................................... 372

[Module] Interrupt and FIFO Status register............................................. 372

. . . . .

www.digiembedded.com 19

[Module] DMA RX Control....................................................................375

[Module] DMA RX Buffer Descriptor Pointer ..............................................376

[Module] RX Interrupt Configuration register ............................................377

[Module] Direct Mode RX Status FIFO......................................................378

[Module] Direct Mode RX Data FIFO .......................................................379

[Module] DMA TX Control....................................................................380

[Module] DMA TX Buffer Descriptor Pointer ..............................................381

[Module] TX Interrupt Configuration register ............................................381

[Module] Direct Mode TX Data FIFO .......................................................382

[Module] Direct Mode TX Data Last FIFO..................................................383

Chapter 10: Serial Control Module: UART ......................... 385

Features.................................................................................385

UART module structure...............................................................386

Normal mode operation .....................................................................386

Example configuration................................................................386

Baud rate generator..........................................................................387

Baud rates ..............................................................................387

Hardware-based flow control...............................................................388

Character-based flow control (XON/XOFF)...............................................388

Example configuration................................................................388

Forced character transmission .............................................................388

Force character transmission procedure...........................................389

Collecting feedback ...................................................................389

ARM wakeup on character recognition....................................................389

Example configuration................................................................389

Wrapper Control and Status registers .....................................................390

Wrapper Configuration register ............................................................391

Interrupt Enable register....................................................................393

Interrupt Status register.....................................................................395

Receive Character GAP Control register ..................................................398

Receive Buffer GAP Control register ......................................................399

Receive Character Match Control register................................................399

Receive Character-Based Flow Control register .........................................400

Force Transmit Character Control register...............................................402

ARM Wakeup Control register...............................................................403

Transmit Byte Count .........................................................................404

UART Receive Buffer.........................................................................405

UART Transmit Buffer........................................................................405

UART Baud Rate Divisor LSB ................................................................406

UART Baud Rate Divisor MSB................................................................406

UART Interrupt Enable register.............................................................407

UART Interrupt Identification register ....................................................408

20 Hardware Reference NS9215

UART FIFO Control register................................................................. 409

UART Line Control register................................................................. 409

UART Modem Control register ............................................................. 411

UART Line Status register .................................................................. 411

UART Modem Status register............................................................... 412

Chapter 11: Serial Control Module: HDLC ......................... 415

HDLC module structure .............................................................. 415

Receive and transmit operations.......................................................... 415

Receive operation..................................................................... 416

Transmit operation ................................................................... 416

Transmitter underflow ............................................................... 416

Clocking ............ ........................................................................... 416

Bits............................................................................................. 416

Last byte bit pattern table .......................................................... 417

Data encoding ................................................................................ 417

Encoding examples ................................................................... 417

Digital phase-locked-loop (DPLL) operation: Encoding ................................ 418

Transitions ............................................................................. 418

DPLL-tracked bit cell boundaries................................................... 419

NRZ and NRZI data encoding ........................................................ 419

Biphase data encoding ............................................................... 419

DPLL operation: Adjustment ranges and output clocks................................ 419

NRZ and NRZI encoding .............................................................. 420

Biphase-Level encoding.............................................................. 420

Biphase-Mark and Biphase-Space encoding ....................................... 421

IRDA-compliant encode .............................................................. 421

Normal mode operation..................................................................... 421

Example configuration ............................................................... 421

Wrapper and HDLC Control and Status registers........................................ 422

Wrapper Configuration register............................................................ 422

Interrupt Enable register ................................................................... 424

Interrupt Status register.................................................................... 425

HDLC Data Register 1........................................................................ 427

HDLC Data Register 2........................................................................ 427

HDLC Data register 3 ........................................................................ 428

HDLC Control Register 1 ...................................... ....... ............... ....... . 429

HDLC Control Register 2 ...................................... ....... ............... ....... . 429

HDLC Clock Divider Low .................................................................... 430

HDLC Clock Divider High.................................................................... 431

. . . . .

Chapter 12: Serial Control Module: SPI .............................433

Features ................................................................................ 433

www.digiembedded.com 21

SPI module structure..................................................................434

SPI controller..................................................................................434

Simple parallel/serial data conversion.............................................434

Full duplex operation .................................................................434

SPI clocking modes ...........................................................................435

Timing modes ..........................................................................435

Clocking mode diagrams..............................................................435

SPI clock generation..........................................................................436

Clock generation samples ............................................................436

In SPI master mode....................................................................436

In SPI slave mode ......................................................................436

System boot-over-SPI operation............................................................436

Available strapping options ..........................................................437

EEPROM/FLASH header ...............................................................437

Header format .........................................................................437

Time to completion ...................................................................438

SPI Control and Status registers............................................................439

SPI Configuration register...................................................................439

Clock Generation register...................................................................440

Interrupt Enable register....................................................................441

Interrupt Status register.....................................................................442

SPI timing characteristics ...................................................................443

SPI master timing diagram ...........................................................444

SPI slave timing parameters .........................................................444

SPI slave timing diagram..............................................................445

Chapter 13: I2C Master/Slave Interface ............................. 447

22 Hardware Reference NS9215

Overview................................................................................447

Physical I2C bus............................. ....... ........ ....... ....... ........ ....... ......447

Multi-master bus.......................................................................448

I2C external addresses.......................................................................448

I2C command interface......................................................................449

Locked interrupt driven mode.......................................................449

Master module and slave module commands......................................449

Bus arbitration .........................................................................449

I2C registers...................................................................................450

Command Transmit Data register..........................................................450

Status Receive Data register................................................................451

Master Address register..................................................................... 452

Slave Address register....................................................................... 453

Configuration register....................................................................... 454

Timing parameter for fast-mode ................................................... 454

Interrupt Codes .............................................................................. 455

Master/slave interrupt codes ....................................................... 455

Software driver............................................................................... 456

I2C master software driver.......................................................... 456

I2C slave high level driver ........................................................... 456

Flow charts ................................................................................... 457

Master module (normal mode, 16-bit)............................................. 457

Slave module (normal mode, 16-bit)............................................... 458

. . . . .

Chapter 14: Real Time Clock Module ................................. 459

RTC functionality ..................................................................... 459

RTC configuration and status registers................................................... 460

RTC General Control register .............................................................. 460

12/24 Hour register.......................................................................... 461

Time register ................................................................................. 462

Calendar register ............................................................................ 463

Time Alarm register ......................................................................... 464

Calendar Alarm register .................................................................... 465

Alarm Enable register ....................................................................... 465

Event Flags register ......................................................................... 466

Interrupt Enable register ................................................................... 468

Interrupt Disable register................................................................... 469

Interrupt Enable Status register........................................................... 470

General Status register ..................................................................... 4 71

Chapter 15: Analog-to-Digital Converter (ADC) Module ....... 473

Features ................................................................................ 473

ADC module structure................................................................ 473

ADC control block..................................................................... 474

ADC DMA procedure ......................................................................... 474

ADC control and status registers .......................................................... 475

www.digiembedded.com 23

ADC Configuration register............................................................ ......475

ADC Clock Configuration register ..........................................................477

ADC Output Registers 0-7 ...................................................................477

Chapter 16: Timing ........................................................ 479

Electrical characteristics....................................................................479

Absolute maximum ratings...........................................................479

Recommended operating conditions................................................480

Power dissipation......................................................................480

DC electrical characteristics................................................................481

Inputs....................................................................................481

Ouputs...................................................................................482

Reset and edge sensitive input timing requirements ...................................482

...........................................................................................483

Memory Timing................................................................................484

SDRAM burst read (16-bit)............................................................485

SDRAM burst read (16 bit), CAS latency = 3 .......................................486

SDRAM burst write (16 bit) ...........................................................487

SDRAM burst read (32 bit)............................................................488

SDRAM burst read (32 bit), CAS latency = 3 .......................................489

SDRAM burst write (32-bit)...........................................................490

SDRAM load mode......................................................................491

SDRAM refresh mode ..................................................................492

Clock enable timing ...................................................................493

Values in SRAM timing diagrams.....................................................494

Static RAM read cycles with 0 wait states .........................................495

Static RAM asynchronous page mode read, WTPG = 1 ...........................496

Static RAM read cycle with configurable wait states ............................497

Static RAM sequential write cycles .................................................498

Static RAM write cycle................................................................499

Static write cycle with configurable wait states .................................500

Slow peripheral acknowledge timing ...............................................501

Slow peripheral acknowledge read .................................................502

Slow peripheral acknowledge write ................................................502

Ethernet timing ........................................................................503

Ethernet MII timing....................................................................503

C timing ...............................................................................504

SPI Timing...............................................................................505

SPI master mode 0 and 1: 2-byte transfer.........................................507

SPI master mode2 and 3: 2-byte transfer..........................................507

SPI slave mode 0 and 1: 2-byte transfer ...........................................508

SPI slave mode 2 and 3: 2-byte transfer ...........................................508

Reset and hardware strapping timing .....................................................509

JTAG timing ...................................................................................510

24 Hardware Reference NS9215

Clock timing .................................................................................. 511

System PLL reference clock timing................................................. 511

Chapter 17: Packaging ..................................................... 513

Package........................................................................................ 513

Processor Dimensions ....................................................................... 514

Chapter 18: Change log ................................................... 517

Revision B ..................................................................................... 517

Revision C..................................................................................... 517

. . . . .

www.digiembedded.com 25

26 Hardware Reference NS9215

Pinout (265)

CHAPTER 1

The NS9215 offers a connection to a 10/100 Ethernet network, as well as a

glueless connection to SDRAM, PC100 DIMM, flash, EEPROM, and SRAM memories, and an external bus expansion module. It includes four multi-function serial ports, one I2C channel, 12-bit Analog to Digital converter, battery backed real time clock and an AES data encryption/decryption module. The NS215 provides up to 108 general purpose I/O (GPIO) pins and configurable power management with sleep mode.

The Legend

Heading Description

Pin Pin number assigned for a specific I/O signal

Signal Pin name for each I/O signal. Some signals have multiple function modes and are

identified accordingly. The mode is configured through firmware using one or more configuration registers.

_n is the signal name indicates that this signal is active is active low.

U/D U or D indicates whether the pin has an internal pullup resistor or a pulldown resistor:

U Pullup (input current source)

D Pulldown (input current sink)

If no value is listed, that pin has neither an internal pullup nor pulldown resistor.

I/O The type of signal: input (I), output (O), input/output (I/O), or power (P).

OD (mA) The output drive of an output buffer. The NS9215 uses one of two drivers:

 2 mA

 4 mA

PINOUT (265)

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Memory bus interface

Pin Signal U/D I/O OD Description

B9 clk_out[0] O 4 SDRAM bus clock

A15 clk_out[1] O 4 SDRAM bus clock

P12 addr[27] / gpio_a[3]

T14 addr[26] / gpio_a[2]

U15 addr[25] / gpio_a[1]

R12 addr[24] / gpio_a[0]

T13 addr[23] U I/O 4 Address bus, Boot width [0]

U14 addr[22] O 4 Address bus

U I/O 4 Address bus, Endian

U I/O 4 Address bus, SPI boot

U I/O 4 Address bus

U I/O 4 Address bus, Boot width [1]

T12 addr[21] O 4 Address bus

U13 addr[20] O 4 Address bus,

R11 addr[19] U I/O 4 Address bus, GENID 10

T11 addr[18] U I/O 4 Address bus, GENID 9

U12 addr[17] U I/O 4 Address bus, GENID 8

T10 addr[16] U I/O 4 Address bus, GENID 7

R9 addr[15] U I/O 4 Address bus, GENID 6

U11 addr[14] U I/O 4 Address bus, GENID 5

U10 addr[13] U I/O 4 Address bus, GENID 4

T9 addr[12] U I/O 4 Address bus, GENID 3

U9 addr[11] U I/O 4 Address bus, GENID 2

U8 addr[10] U I/O 4 Address bus, GENID 1

T8 addr[9] U I/O 4 Address bus, GENID 0

U7 addr[8] U I/O 4 Address bus

T7 addr[7] U I/O 4 Address bus, PLL bypass

U6 addr[6] U I/O 4 Address bus, PLL OD [1]

T6 addr[5] U I/O 4 Address bus, PLL OD [0]

U5 addr[4] U I/O 4 Address bus, PLL NR[4]

M2 addr[3] U I/O 4 Address bus, PLL NR[3]

N1 addr[2] U I/O 4 Address bus, PLL NR[2]

L2 addr[1] U I/O 4 Address bus, PLL NR[1]

28 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

M1 addr[0] U I/O 4 Address bus, PLL NR[0]

L1 data[31] U I/O 4 Data bus

K2 data[30] U I/O 4 Data bus

K1 data[29] U I/O 4 Data bus

J1 data[28] U I/O 4 Data bus

J2 data[27] U I/O 4 Data bus

H1 data[26] U I/O 4 Data bus

G1 data[25] U I/O 4 Data bus

J3 data[24] U I/O 4 Data bus

H2 data[23] U I/O 4 Data bus

F1 data[22] U I/O 4 Data bus

G2 data[21] U I/O 4 Data bus

PINOUT (265)

Memory bus interface

. . . . .

H3 data[20] U I/O 4 Data bus

E1 data[19] U I/O 4 Data bus

F2 data[18] U I/O 4 Data bus

D1 data[17] U I/O 4 Data bus

E2 data[16] U I/O 4 Data bus

H4 data[15] / gpio[31]

G3 data[14] / gpio[30] U I/O 4 Data bus

G4 data[13] / gpio[29] U I/O 4 Data bus

G5 data[12] / gpio[28] U I/O 4 Data bus

F3 data[11] / gpio[27] U I/O 4 Data bus

F4 data[10] / gpio[26] U I/O 4 Data bus

F5 data[9] / gpio[25] U I/O 4 Data bus

C1 data[8] / gpio[24] U I/O 4 Data bus

E4 data[7] / gpio[23] U I/O 4 Data bus

D2 data[6] / gpio[22] U I/O 4 Data bus

E3 data[5] / gpio[21] U I/O 4 Data bus

B1 data[4] / gpio[20] U I/O 4 Data bus

U I/O 4 Data bus

D4 data[3] / gpio[19] U I/O 4 Data bus

C2 data[2] / gpio[18] U I/O 4 Data bus

B2 data[1] / gpio[17] U I/O 4 Data bus

D3 data[0] / gpio[16] U I/O 4 Data bus

www.digiembedded.com 29

PINOUT (265)

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Ethernet interface MAC

Pin Signal U/D I/O OD Description

A10 data_mask[3] O 4 byte_enable data[31:24}

B11 data_mask[2] O 4 Byte enable data[23:16]

B10 data_mask[1] O 4 Byte enable data[15:08]

A11 data_mask[0] O 4 Byte enable data {07:00]

A9 ns_ta_strb I Slow peripheral transfer acknowledge

A6 rw_n O 4 Transfer direction

B7 clk_en[3] O 4 SDRAM clock enable

D7 clk_en[2] O 4 SDRAM clock enable

A7 clk_en[1] O 4 SDRAM clock enable

B8 clk_en[0] O 4 SDRAM clock enable

B4 cs[7] O 4 Chip select 7, dy_cs3

A3 cs[6] O 4 Chip select 6, st_cs3

A4 cs[5] O 4 Chip select 5, dy_cs2

C5 cs[4] O 4 Chip select 4, st_cs2

B5 cs[3] O 4 Chip select 3, dy_cs1

B6 cs[2] O 4 Chip select 2, st_cs1 (Flash boot)

D6 cs[1] O 4 Chip select 1, dy_cs0 (Boot sdram)

C6 cs[0] O 4 Chip select 0, st_cs0

C4 ras_n O 4 SDRAM RAS

A2 cas_n O 4 SDRAM CAS

C7 we_n O 4 SDRAM write enable

B3 ap10 O 4 SDRAM A10(AP)

A8 st_oe_n O 4 Static output enable

a. addr [27:24] reset to gpio mode. These address lines cannot be used for boot. b. gpio[31:16] reset to memory data bus data [15:0].

Ethernet interface MAC

Pin Signal U/D I/O OD Description

A12 mdc / gpio[32] U I/O 2 MII clock

D11 mdio / gpio[35] U I/O 2 MII data

B12 tx_clk / gpio[33] U I/O 2 TX clock

A16 txd[3] / gpio[47] U I/O 2 TX data 3

30 Hardware Reference NS9215

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Digi NS9215 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Pinout (265)

Memory bus interface

Ethernet interface MAC