Digi NS9215 User Manual

NS9215

Hardware Reference

90000847_C Release date: 10 April 2008

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Contents

Chapter 1: Pinout (265) ..................................................... 27

The Legend .............................................................................. 27

Memory bus interface................... ....... ....... ........ ....... ............... ....... ... 28

Ethernet interface MAC....................................................................... 30

General purpose I/O (GPIO) ................................................................. 31

System clock ................................................................................... 43

System clock drawing.................................................................. 44

RTC clock and battery backup drawing ............................................. 45

System mode................................................................................... 45

System reset ................................................................................... 47

JTAG Test....................................................................................... 48

ADC ............................................... ............................................... 49

POR and battery-backed logic............................................................... 50

Power and ground ............................................................................. 51

Chapter 2: I/O Control Module ...........................................53

System memory bus I/O control...................................................... 53

Control and Status registers ................................................................. 53

GPIO Configuration registers ................................................................ 55

GPIO configuration options............................................................ 55

GPIO Configuration Register #0 ...................................................... 56

GPIO Configuration Register #1 ...................................................... 56

GPIO Configuration Register #2 ...................................................... 57

GPIO Configuration Register #3 ...................................................... 57

GPIO Configuration Register #4 ...................................................... 58

GPIO Configuration Register #5 ...................................................... 58

GPIO Configuration Register #6 ...................................................... 59

GPIO Configuration Register #7 ...................................................... 59

GPIO Configuration Register #8 ...................................................... 60

GPIO Configuration Register #9 ...................................................... 60

GPIO Configuration Register #10 ..................................................... 61

GPIO Configuration Register #11 ..................................................... 61

GPIO Configuration Register #12 ..................................................... 62

GPIO Configuration Register #13 ..................................................... 62

GPIO Configuration Register #14 ..................................................... 63

GPIO Configuration Register #15 .....................................................63

GPIO Configuration Register #16 .....................................................64

GPIO Configuration Register #17 .....................................................64

GPIO Configuration Register #18 .....................................................65

GPIO Configuration Register #19 .....................................................65

GPIO Configuration Register #20 .....................................................66

GPIO Configuration Register #21 .....................................................66

GPIO Configuration Register #22 .....................................................67

GPIO Configuration Register #23 .....................................................67

GPIO Configuration Register #24 .....................................................68

GPIO Configuration Register #25 .....................................................68

GPIO Configuration Register #26 .....................................................69

GPIO Control registers ........................................................................ 70

GPIO Control Register #0 .............................................................. 70

GPIO Control Register #1 .............................................................. 71

GPIO Control Register #2 .............................................................. 72

GPIO Control Register #3 .............................................................. 73

GPIO Status registers.......................................................................... 74

GPIO Status Register #1................................................................ 74

GPIO Status Register #2................................................................ 75

GPIO Status Register #3................................................................ 76

Memory Bus Configuration register ......................................................... 76

Chapter 3: Working with the CPU ....................................... 81

About the processor.................................................................... 81

Arm926EJ-S process block diagram ..................................................82

Instruction sets ................................................................................82

ARM instruction set.....................................................................82

Thumb instruction set.................................................................. 82

Java instruction set .................................................................... 83

System control processor (CP15) registers................................................. 83

ARM926EJ-S system addresses ........................................................ 83

Address manipulation example....................................................... 83

Accessing CP15 registers............................................................... 83

Terms and abbreviations .... .............. ........ ....... ....... ........ ....... ....... 84

R0: ID code and cache type status registers ..............................................86

R0: ID code .............................................................................. 86

R0: Cache type register................................................................ 86

Cache type register and field description ..........................................87

Dsize and Isize fields...................................................................87

R1: Control register ...........................................................................88

Control register ......................................................................... 89

Bit functionality.........................................................................89

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ICache and DCache behavior..........................................................90

R2: Translation Table Base register.........................................................91

R3:Domain Access Control register..........................................................91

Access permissions and instructions .................................................91

R4 register ......................................................................................92

R5: Fault Status registers............................................ ....... ........ ....... ...92

Access instructions......................................................................92

Status and domain fields...............................................................93

R6: Fault Address register....................................................................93

Access instructions......................................................................93

R7:Cache Operations register................................................................94

Write instruction........................................................................94

Cache functions .........................................................................94

Cache operation functions.............................................................95

Modified virtual address format (MVA) ..............................................96

Set/Way format .........................................................................96

Set/Way example .......................................................................96

Test and clean DCache instructions..................................................96

Test, clean, and invalidate DCache instruction....................................97

R8:TLB Operations register...................................................................97

TLB operations ..........................................................................97

TLB operation instructions ............................................................97

Modified virtual address format (MVA) ..............................................98

R9: Cache Lockdown register ................................................................98

Cache ways...............................................................................98

Instruction or data lockdown register ...............................................99

Access instructions......................................................................99

Modifying the Cache Lockdown register.............................................99

Cache Lockdown register L bits.......................................................99

Lockdown cache: Specific loading of addresses into a cache-way ............ 100

Cache unlock procedure ............................................................. 101

R10:TLB Lockdown register ................................................................ 101

P bit..................................................................................... 101

Invalidate operation.................................................................. 101

Programming instructions............................................................ 102

Sample code sequence............................................... ........ ....... . 102

R11 and R12 registers ................................................ ....... ........ ....... . 102

R13:Process ID register ..................................................................... 102

FCSE PID register........................................ ....... ....... ........ ....... . 103

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Access instructions ....................................................................103

Performing a fast context switch ...................................................103

Context ID register ....................................................................104

Access instructions ....................................................................104

R14 register....................................................................................104

R15: Test and debug register...............................................................104

Jazelle(Java) ..................................................................................104

DSP..............................................................................................105

MemoryManagement Unit (MMU)...........................................................105

MMU Features ..........................................................................105

Access permissions and domains ....................................................106

Translated entries.....................................................................106

MMU program accessible registers ..................................................107

Address translation....................................................................107

Translation table base ................................................................108

TTB register format ...................................................................108

Table walk process ....................................................................109

First-level fetch........................................................................109

First-level fetch concatenation and address ......................................110

First-level descriptor..................................................................110

Page table descriptors ................................................................110

First-level descriptor bit assignments: Priority encoding of fault status .....111

First-level descriptor bit assignments: Interpreting first level descriptor bits

[1:0]..................................................................................111

Section descriptor .....................................................................111

Section descriptor format ............................................................111

Section descriptor bit description...................................................112

Coarse page table descriptor ........................................................112

Coarse page table descriptor format...............................................112

Coarse page table descriptor bit description......................................112

Fine page table descriptor ...........................................................112

Fine page table descriptor format..................................................113

Fine page table descriptor bit description.........................................113

Translating section references ......................................................113

Second-level descriptor...............................................................114

Second-level descriptor format .....................................................114

Second-level descriptor pages.......................................................114

Second-level descriptor bit assignments...........................................115

Second-level descriptor least significant bits .....................................115

Translation sequence for large page references...... ....... ........ ....... ......116

Translating sequence for small page references .................................117

Translation sequence for tiny page references ...................................118

Subpages ................................................................................118

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MMU faults and CPU aborts................................................................. 119

Alignment fault checking ............................................................ 119

Fault Address and Fault Status registers .......................................... 119

Priority encoding table............................................................... 120

Fault Address register (FAR)......................................................... 120

FAR values for multi-word transfers ............................................... 120

Compatibility issues .................................................................. 121

Domain access control ...................................................................... 121

Specifying access permissions....................................................... 121

Interpreting access permission bits ................................................ 121

Fault checking sequence.................................................................... 122

Alignment faults....................................................................... 123

Translation faults ..................................................................... 124

Domain faults.......................................................................... 124

Permission faults...................................................................... 124

External aborts............................................................................... 125

Enabling and disabling the MMU........................................................... 125

Enabling the MMU..................................................................... 125

Disabling the MMU .................................................................... 1 26

TLB structure................................................................................. 126

Caches and write buffer .................................................................... 127

Cache features ........................................................................ 127

Write buffer............................................................................ 128

Enabling the caches .................................................................. 128

ICache I and M bit settings .......................................................... 129

ICache page table C bit settings.................................................... 129

R1 register C and M bits for DCache ............................................... 129

DCache page table C and B settings ............................................... 129

Cache MVA and Set/Way formats ......................................................... 130

Generic, virtually indexed, virtually addressed cache.......................... 131

ARM926EJ-S cache format ........................................................... 132

ARM926EJ-S cache associativity .................................................... 132

Set/way/word format for ARM926EJ-S caches ................................... 132

Noncachable instruction fetches .......................................................... 133

Self-modifying code .................................................................. 133

AHB behavior .......................................................................... 134

Instruction Memory Barrier.......................................................... 134

IMB operation.......................................................................... 134

Sample IMB sequences ............................................................... 135

. . . . .

Chapter 4: System Control Module ....................................137

Features ................................................................................ 137

Bus interconnection ......................................................................... 137

System bus arbiter........................................................................... 138

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High speed bus system................................................................138

High-speed bus arbiters...............................................................138

How the bus arbiter works ...........................................................138

Ownership...............................................................................139

Locked bus sequence..................................................................139

Relinquishing the bus .................................................................139

SPLIT transfers .........................................................................140

Arbiter configuration example.......................................................140

Address decoding.............................................................................141

Programmable timers........................................................................142

Software watchdog timer ............................................................142

General purpose timers/counters..........................................................143

Source clock frequency...............................................................143

GPTC characteristics............................... .............. ........ ....... ......143

Control field............................................................................143

16-bit mode options...................................................................144

Basic PWM function ..........................................................................144

Functional block diagram.............................................................144

Enhanced PWM function.....................................................................145

Sample enhanced PWM waveform ..................................................145

Quadrature decoder function...............................................................145

How the quadrature decoder/counter works ............................................146

Provides input signals.................................................................146

Monitors how far the encoder has moved..........................................147

Digital filter ............................................................................147

Testing signals..................................................... ........ ....... ......147

Timer support ..........................................................................147

Interrupt controller ..........................................................................148

FIQ interrupts ..........................................................................148

IRQ interrupts ..........................................................................148

32-vector interrupt controller.......................................................148

IRQ characteristics ....................................................................149

Interrupt sources ......................................................................149

Vectored interrupt controller (VIC) flow..................................................151

Configurable system attributes.............................................................151

PLL configuration.............................................................................151

PLL configuration and control system block diagram ............................152

Bootstrap initialization ......................................................................152

Configuring the powerup settings...................................................152

System configuration registers .............................................................154

General Arbiter Control register ...........................................................158

BRC0, BRC1, BRC2, and BRC3 registers ...................................................158

Channel allocation.....................................................................159

AHB Error Detect Status 1...................................................................159

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AHB Error Detect Status 2 .................................................................. 160

AHB Error Monitoring Configuration register ............................................ 161

Timer Master Control register ............................................................. 162

Timer 0–4 Control registers................................................................. 164

Timer 5 Control register .................................................................... 166

Timer 6–9 Control registers................................................................. 168

Timer 6–9 High registers .................................................................... 170

Timer 6–9 Low registers..................................................................... 171

Timer 6–9 High and Low Step registers................................................... 172

Timer 6–9 Reload Step registers........................................................... 172

Timer 0-9 Reload Count and Compare register ......................................... 173

Timer 0-9 Read and Capture register..................................................... 174

Interrupt Vector Address Register Level 31–0 ........................................... 175

Int (Interrupt) Config (Configuration) 31–0 registers................................... 175

Individual register mapping ......................................................... 175

ISADDR register............................................................................... 176

Interrupt Status Active...................................................................... 177

Interrupt Status Raw ........................................................................ 178

Software Watchdog Configuration ........................................................ 178

Software Watchdog Timer.................................................................. 179

Clock Configuration register ............................................................... 180

Module Reset register....................................................................... 182

Miscellaneous System Configuration and Status register .............................. 184

PLL Configuration register...... ........ ....... ....... ........ ....... ....... ........ ....... . 186

PLL frequency formula............................................................... 186

Active Interrupt Level ID Status register................................................. 187

Power Management.......................................................................... 187

AHB Bus Activity Status ..................................................................... 190

System Memory Chip Select 0 Dynamic Memory Base and Mask registers........... 190

System Memory Chip Select 1 Dynamic Memory Base and Mask registers........... 191

System Memory Chip Select 2 Dynamic Memory Base and Mask registers........... 192

System Memory Chip Select 3 Dynamic Memory Base and Mask registers........... 193

System Memory Chip Select 0 Static Memory Base and Mask registers.............. 194

System Memory Chip Select 1 Static Memory Base and Mask registers.............. 195

System Memory Chip Select 2 Static Memory Base and Mask registers.............. 196

System Memory Chip Select 3 Static Memory Base and Mask registers.............. 197

Gen ID register ............................................................................... 198

External Interrupt 0–3 Control register................................................... 199

RTC Module Control register ............................................................... 200

. . . . .

Chapter 5: Memory Controller .......................................... 203

Features ................................................................................ 203

Low-power operation................................................................ ....... . 204

Low-power SDRAM deep-sleep mode............................................... 204

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Low-power SDRAM partial array refresh ...........................................204

Memory map...................................................................................205

Power-on reset memory map ........................................................205

Chip select 1 memory configuration................................................205

Example: Boot from flash, SRAM mapped after boot ............................205

Example: Boot from flash, SDRAM remapped after boot ........................206

Static memory controller....................................................................207

Write protection.......................................................................208

Extended wait transfers ..............................................................208

Memory mapped peripherals.........................................................209

Static memory initialization ................................................................209

Access sequencing and memory width .............................................209

Wait state generation.................................................................209

Programmable enable.................................................................210

Static memory read control.................................................................210

Output enable programmable delay................................................210

ROM, SRAM, and Flash ................................................................210

Static memory read: Timing and parameters ............................................211

External memory read transfer with zero wait states ...........................211

External memory read transfer with two wait states............................211

External memory read transfer with two output enable delay states.........212

External memory read transfers with zero wait states..........................212

Burst of zero wait states with fixed length........................................213

Burst of two wait states with fixed length ........................................213

Asynchronous page mode read .............................................................214

Asynchronous page mode read: Timing and parameters ...............................214

External memory page mode read transfer .......................................214

External memory 32-bit burst read from 8-bit memory .........................215

Static memory write control................................................................216

Write enable programming delay ...................................................216

SRAM.....................................................................................216

Static memory Write: Timing and parameters...........................................216

External memory write transfer with zero wait states ..........................216

External memory write transfer with two wait states...........................217

External memory write transfer with two write enable delay states .........217

Two external memory write transfers with zero wait states ...................218

Flash memory ..........................................................................218

Bus turnaround................................................................................219

Bus turnaround: Timing and parameters..................................................219

Read followed by write with no turnaround.......................................219

Write followed by a read with no turnaround.....................................220

Read followed by a write with two turnaround cycles...........................220

Byte lane control .............................................................................221

Address connectivity.........................................................................222

Memory banks constructed from 8-bit or non-byte-partitioned memory devices

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222

Memory banks constructed from 16-or 32-bit memory devices................ 223

Dynamic memory controller................................................................ 225

Write protection ...................................................................... 225

Access sequencing and memory width............................. ........ ....... . 225

SDRAM Initialization ................................................................. ....... . 225

Left-shift value table: 32-bit wide data bus SDRAM (RBC) ..................... 226

Left-shift value table: 32-bit wide data bus SDRAM (BRC) ..................... 227

Left-shift value table: 16-bit wide data bus SDRAM (RBC) ..................... 227

Left-shift value table: 16-bit wide data bus SDRAM (BRC) ..................... 228

SDRAM address and data bus interconnect .............................................. 228

32-bit wide configuration............................................................ 228

32-bit wide configuration............................................................ 229

Registers ...................................................................................... 230

Reset values ........................................................................... 232

Control register .............................................................................. 232

Status register................................................................................ 234

Configuration register....................................................................... 234

Dynamic Memory Control register......................................................... 235

Dynamic Memory Refresh Timer register................................................. 236

Dynamic Memory Read Configuration register .......................................... 237

Dynamic Memory Precharge Command Period register................................ 238

Dynamic Memory Active to Precharge Command Period register .................... 239

Dynamic Memory Self-refresh Exit Time register ....................................... 240

Dynamic Memory Last Data Out to Active Time register .............................. 240

Dynamic Memory Data-in to Active Command Time register ......................... 241

Dynamic Memory Write Recovery Time register ........................................ 242

Dynamic Memory Active to Active Command Period register......... ........ ....... . 243

Dynamic Memory Auto Refresh Period register ......................................... 243

Dynamic Memory Exit Self-refresh register.............................................. 244

Dynamic Memory Active Bank A to Active Bank B Time register ..................... 245

Dynamic Memory Load Mode register to Active Command Time register........... 246

Static Memory Extended Wait register ................................................... 247

Example ................................................................................ 247

Dynamic Memory Configuration 0–3 registers ........................................... 247

Address mapping for the Dynamic Memory Configuration registers........... 249

Chip select and memory devices ................................................... 250

Dynamic Memory RAS and CAS Delay 0–3 registers ..................................... 250

StaticMemory Configuration 0–3 registers................................................ 251

StaticMemory Write Enable Delay 0–3 registers......................................... 254

Static Memory Output Enable Delay 0–3 registers ...................................... 255

Static Memory Read Delay 0–3 registers.................................................. 256

StaticMemory Page Mode Read Delay 0–3 registers..................................... 256

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Static Memory Write Delay 0–3 registers..................................................257

StaticMemory Turn Round Delay 0–3 registers ...........................................258

Chapter 6: Ethernet Communication Module ...................... 261

Features.................................................................................261

Common acronyms ....................................................................261

Ethernet communications module ..................................................262

Ethernet MAC..................................................................................262

MAC module block diagram ..........................................................263

MAC module features .................................................................263

PHY interface mappings ..............................................................264

Station address logic (SAL)..................................................................264

MAC receiver ...........................................................................265

Statistics module .............................................................................265

Ethernet front-end module .................................................................266

Ethernet front-end module (EFE) ...................................................266

Receive packet processor ............................................................266

Transmit packet processor ...........................................................267

Receive packet processor ...................................................................267

Power down mode.....................................................................267

Transferring a frame to system memory...........................................268

Receive buffer descriptor format ...................................................268

Receive buffer descriptor format description.....................................268

Receive buffer descriptor field definitions........................................269

Transmit packet processor..................................................................269

Transmit buffer descriptor format..................................................270

Transmit buffer descriptor field definitions.......................................270

Transmitting a frame..................................................................271

Frame transmitted successfully .....................................................272

Frame transmitted unsuccessfully ..................................................272

Transmitting a frame to the Ethernet MAC........................................272

Ethernet underrun.....................................................................272

Ethernet slave interface.....................................................................273

Interrupts ......................................................................................273

Interrupt sources ......................................................................273

Status bits...............................................................................274

Resets ..........................................................................................274

Multicast address filtering ..................................................................275

Filter entries ...........................................................................275

Multicast address filter registers....................................................275

Multicast address filtering example 1 ..............................................275

Multicast address filtering example 2 ..............................................276

Notes ....................................................................................276

Clock synchronization........................................................................276

14 Hardware Reference NS9215

Writing to other registers............................................................ 276

Ethernet Control and Status registers .................................................... 277

Ethernet General Control Register #1 .................................................... 279

Ethernet General Control Register #2 .................................................... 282

Ethernet General Status register.......................................................... 283

Ethernet Transmit Status register......................................................... 284

Ethernet Receive Status register.................................................. ....... . 286

MAC Configuration Register #1............................................................. 288

MAC Configuration Register #2............................................................. 289

PAD operation table for transmit frames.......................................... 291

Back-to-Back Inter-Packet-Gap register.................................................. 291

Non Back-to-Back Inter-Packet-Gap register ............................................ 292

Collision Window/Retry register........................................................... 293

Maximum Frame register ................................................................... 294

MII Management Configuration register .................................................. 295

Clocks field settings .................................................................. 296

MII Management Command register....................................................... 296

MII Management Address register ......................................................... 297

MII Management Write Data register...................................................... 298

MII Management Read Data register ...................................................... 298

MII Management Indicators register....................................................... 299

Station Address registers ................................................................... 300

Station Address Filter register............................................................. 301

RegisterHash Tables......................................................................... 302

HT1...................................................................................... 302

HT2...................................................................................... 303

Statistics registers ........................................................................... 303

Combined transmit and receive statistics counters address map ............. 303

Receive statistics counters address map.......................................... 304

Receive byte counter (A060 069C) ................................................. 304

Receive packet counter (A060 06A0) .............................................. 304

Receive FCS error counter (A060 06A4) ........................................... 305

Receive multicast packet counter (A060 06A8) .................................. 305

Receive broadcast packet counter (A060 06AC) ................................. 305

Receive control frame packet counter (A060 06B0)............................. 305

Receive PAUSE frame packet counter (A060 06B4).............................. 305

Receive unknown OPCODE packet counter (A060 06B8) ........................ 305

Receive alignment error counter (A060 06BC) ................................... 306

Receive code error counter (A060 06C4).......................................... 306

Receive carrier sense error counter (A060 06C8)................................ 306

Receive undersize packet counter (A060 06CC).................................. 306

Receive oversize packet counter (A060 06D0).................................... 306

Receive fragments counter (A060 06D4) .......................................... 306

Receive jabber counter (A060 06D8)............................................... 307

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Transmit statistics counters address map .........................................307

Transmit byte counter (A060 06E0).................................................307

Transmit packet counter (A060 06E4)..............................................308

Transmit multicast packet counter (A060 06E8)..................................308

Transmit broadcast packet counter (A060 06EC) .................................308

Transmit deferral packet counter (A060 06F4) ...................................308

Transmit excessive deferral packet counter (A060 06F8) .......................308

Transmit single collision packet counter (A060 06FC) ...........................308

Transmit multiple collision packet counter (A060 0700) ........................309

Transmit late collision packet counter (A060 0704)..............................309

Transmit excessive collision packet counter (A060 0708).......................309

Transmit total collision packet counter (A060 070C) ............................309

Transmit jabber frame counter (A060 0718) ......................................309

Transmit FCS error counter (A060 071C)...........................................309

Transmit oversize frame counter (A060 0724) ....................................310

Transmit undersize frame counter (A060 0728)...................................310

Transmit fragment counter (A060 072C)...........................................310

General Statistics registers address map ..........................................310

Carry Register 1........................................................................310

Carry Register 2........................................................................311

Carry Register 1 Mask register.......................................................312

Carry Register 2 Mask register.......................................................314

RX_A Buffer Descriptor Pointer register ..................................................315

RX_B Buffer Descriptor Pointer register ..................................................315

RX_C Buffer Descriptor Pointer register ..................................................316

RX_D Buffer Descriptor Pointer register ..................................................316

Ethernet Interrupt Status register .........................................................317

Ethernet Interrupt Enable register.........................................................319

TX Buffer Descriptor Pointer register .....................................................320

Transmit Recover Buffer Descriptor Pointer register ...................................321

TX Error Buffer Descriptor Pointer register ..............................................321

TX Stall Buffer Descriptor Pointer register ...............................................322

RX_A Buffer Descriptor Pointer Offset register..........................................323

RX_B Buffer Descriptor Pointer Offset register ..........................................324

RX_C Buffer Descriptor Pointer Offset register..........................................324

RX_D Buffer Descriptor Pointer Offset register..........................................325

Transmit Buffer Descriptor Pointer Offset register .....................................325

RX Free Buffer register ......................................................................326

Multicast Address Filter registers ..........................................................327

Multicast Low Address Filter Register #0...........................................327

Multicast Low Address Filter Register #1...........................................327

Multicast Low Address Filter Register #2...........................................327

Multicast Low Address Filter Register #3...........................................327

Multicast Low Address Filter Register #4...........................................327

Multicast Low Address Filter Register #5...........................................327

16 Hardware Reference NS9215

Multicast Low Address Filter Register #6.......................................... 328

Multicast Low Address Filter Register #7.......................................... 328

Multicast High Address Filter Register #0 ......................................... 328

Multicast High Address Filter Register #1 ......................................... 328

Multicast High Address Filter Register #2 ......................................... 328

Multicast High Address Filter Register #3 ......................................... 328

Multicast High Address Filter Register #4 ......................................... 328

Multicast High Address Filter Register #5 ......................................... 328

Multicast High Address Filter Register #6 ......................................... 329

Multicast High Address Filter Register #7 ......................................... 329

Multicast Address Mask registers .......................................................... 329

Multicast Low Address Mask Register #0........................................... 329

Multicast Low Address Mask Register #1........................................... 329

Multicast Low Address Mask Register #2........................................... 329

Multicast Low Address Mask Register #3........................................... 329

Multicast Low Address Mask Register #4........................................... 330

Multicast Low Address Mask Register #5........................................... 330

Multicast Low Address Mask Register #6........................................... 330

Multicast Low Address Mask Register #7........................................... 330

Multicast High Address Mask Register #0.......................................... 330

Multicast High Address Mask Register #1.......................................... 330

Multicast High Address Mask Register #2.......................................... 330

Multicast High Address Mask Register #3.......................................... 330

Multicast High Address Mask Register #4.......................................... 330

Multicast High Address Mask Register #5.......................................... 331

Multicast High Address Mask Register #6.......................................... 331

Multicast High Address Mask Register #7.......................................... 331

Multicast Address Filter Enable register.................................................. 331

TX Buffer Descriptor RAM................................................................... 332

Offset+0 ................................................................................ 332

Offset+4 ................................................................................ 333

Offset+8 ................................................................................ 333

Offset+C................................................................................ 333

RX FIFO RAM .................................................................................. 333

Sample hash table code............................... ........ ....... ....... ........ ....... . 334

. . . . .

Chapter 7: External DMA ................................................339

DMA transfers...... ........ ....... ........ ....... ....... ........ ....... ....... ............... . 339

Initiating DMA transfers.............................................................. 339

Processor-initiated.................................................................... 339

External peripheral-initiated........................................................ 339

DMA buffer descriptor.... ....... ........ ....... ....... ........ ....... ....... ............... . 340

DMA buffer descriptor diagram ..................................................... 340

Source address [pointer]............................................................ . 340

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Buffer length ................................ ........ ....... ....... ........ ....... ......340

Destination address [pointer]........................................... ....... ......340

Status....................................................................................341

Wrap (W) bit........... ........ ....... ....... ........ ....... ....... ........ ....... ......341

Interrupt (I) bit.........................................................................341

Last (L) bit..............................................................................341

Full (F) bit ..............................................................................341

Descriptor list processing.............................................................. ......341

Peripheral DMA read access.................................................................342

Determining the width of PDEN .....................................................342

Equation variables.....................................................................342

Peripheral DMA single read access..................................................343

Peripheral DMA burst read access...................................................343

Peripheral DMA write access................................................................343

Determining the width of PDEN .....................................................344

Peripheral DMA single write access.................................................344

Peripheral DMA burst write access..................................................344

Peripheral REQ and DONE signaling........................................................344

REQ signal...............................................................................344

DONE signal.............................................................................345

Special circumstances.................................................................345

Static RAM chip select configuration ......................................................345

Static ram chip select configuration................................................345

Control and Status registers ................................................................346

DMA Buffer Descriptor Pointer..............................................................346

DMA Control register.........................................................................347

DMA Status and Interrupt Enable register ................................................350

DMA Peripheral Chip Select register.......................................................352

Chapter 8: AES Data Encryption/Decryption Module ........... 355

18 Hardware Reference NS9215

Features.................................................................................355

Block diagram ..........................................................................356

Data blocks .............................................................................356

AES DMA buffer descriptor ..................................................................356

AES buffer descriptor diagram.......................................................357

Source address [pointer] .............................................................357

Source buffer length ..................................................................357

Destination buffer length........................................ ........ ....... ......357

Destination address [pointer]........................................... ....... ......357

AES control .............................................................................357

AES op code.............................................................................358

WRAP (W) bit...........................................................................358

Interrupt (I) bit.........................................................................358

Last (L) bit ............................................................................. 358

Full (F) bit.............................................................................. 358

Decryption .................................................................................... 359

ECB processing ............................................................................... 359

Processing flow diagram ............................................................. 359

CBC, CFB, OFB, and CTR processing ...................................................... 360

Processing flow diagram ............................................................. 360

CCM mode..................................................................................... 360

Nonce buffer........................................................................... 361

Processing flow........................................................................ 361

Chapter 9: I/O Hub Module .............................................. 363

Block diagram ......................................................................... 364

AHB slave interface.................................................................. . 364

DMA controller ............................................................................... 364

Servicing RX and FIFOs ............................................................... 364

Buffer descriptors..................................................................... 365

Source address [pointer]............................................................ . 365

Buffer length........................................................................... 365

Control[15] – W........................................................................ 365

Control[14] – I ......................................................................... 365

Control[13] – L......................................................................... 365

Control[12] – F......................................................................... 365

Control[11:0] .......................................................................... 366

Status[15:0]............................................................................ 366

Transmit DMA example...................................................................... 367

Process.................................................................................. 367

Visual example ........................................................................ 368

Control and status register address maps................................................ 368

UART A register address map ....................................................... 369

UART B register address map ....................................................... 369

UART C register address map ....................................................... 370

UART D register address map ....................................................... 370

SPI register address map............................................................. 371

AD register address map............................................................. 371

Reserved................................................................................ 371

I2C register address map............................................................. 371

Reserved................................................................................ 371

RTC register address map............................................................ 372

IO Hardware Assist register address map (0) ..................................... 372

IO Hardware Assist register address map (1) ..................................... 372

IO register address map (0) ......................................................... 372

IO register address map (1) ......................................................... 372

[Module] Interrupt and FIFO Status register............................................. 372

. . . . .

www.digiembedded.com 19

[Module] DMA RX Control....................................................................375

[Module] DMA RX Buffer Descriptor Pointer ..............................................376

[Module] RX Interrupt Configuration register ............................................377

[Module] Direct Mode RX Status FIFO......................................................378

[Module] Direct Mode RX Data FIFO .......................................................379

[Module] DMA TX Control....................................................................380

[Module] DMA TX Buffer Descriptor Pointer ..............................................381

[Module] TX Interrupt Configuration register ............................................381

[Module] Direct Mode TX Data FIFO .......................................................382

[Module] Direct Mode TX Data Last FIFO..................................................383

Chapter 10: Serial Control Module: UART ......................... 385

Features.................................................................................385

UART module structure...............................................................386

Normal mode operation .....................................................................386

Example configuration................................................................386

Baud rate generator..........................................................................387

Baud rates ..............................................................................387

Hardware-based flow control...............................................................388

Character-based flow control (XON/XOFF)...............................................388

Example configuration................................................................388

Forced character transmission .............................................................388

Force character transmission procedure...........................................389

Collecting feedback ...................................................................389

ARM wakeup on character recognition....................................................389

Example configuration................................................................389

Wrapper Control and Status registers .....................................................390

Wrapper Configuration register ............................................................391

Interrupt Enable register....................................................................393

Interrupt Status register.....................................................................395

Receive Character GAP Control register ..................................................398

Receive Buffer GAP Control register ......................................................399

Receive Character Match Control register................................................399

Receive Character-Based Flow Control register .........................................400

Force Transmit Character Control register...............................................402

ARM Wakeup Control register...............................................................403

Transmit Byte Count .........................................................................404

UART Receive Buffer.........................................................................405

UART Transmit Buffer........................................................................405

UART Baud Rate Divisor LSB ................................................................406

UART Baud Rate Divisor MSB................................................................406

UART Interrupt Enable register.............................................................407

UART Interrupt Identification register ....................................................408

20 Hardware Reference NS9215

UART FIFO Control register................................................................. 409

UART Line Control register................................................................. 409

UART Modem Control register ............................................................. 411

UART Line Status register .................................................................. 411

UART Modem Status register............................................................... 412

Chapter 11: Serial Control Module: HDLC ......................... 415

HDLC module structure .............................................................. 415

Receive and transmit operations.......................................................... 415

Receive operation..................................................................... 416

Transmit operation ................................................................... 416

Transmitter underflow ............................................................... 416

Clocking ............ ........................................................................... 416

Bits............................................................................................. 416

Last byte bit pattern table .......................................................... 417

Data encoding ................................................................................ 417

Encoding examples ................................................................... 417

Digital phase-locked-loop (DPLL) operation: Encoding ................................ 418

Transitions ............................................................................. 418

DPLL-tracked bit cell boundaries................................................... 419

NRZ and NRZI data encoding ........................................................ 419

Biphase data encoding ............................................................... 419

DPLL operation: Adjustment ranges and output clocks................................ 419

NRZ and NRZI encoding .............................................................. 420

Biphase-Level encoding.............................................................. 420

Biphase-Mark and Biphase-Space encoding ....................................... 421

IRDA-compliant encode .............................................................. 421

Normal mode operation..................................................................... 421

Example configuration ............................................................... 421

Wrapper and HDLC Control and Status registers........................................ 422

Wrapper Configuration register............................................................ 422

Interrupt Enable register ................................................................... 424

Interrupt Status register.................................................................... 425

HDLC Data Register 1........................................................................ 427

HDLC Data Register 2........................................................................ 427

HDLC Data register 3 ........................................................................ 428

HDLC Control Register 1 ...................................... ....... ............... ....... . 429

HDLC Control Register 2 ...................................... ....... ............... ....... . 429

HDLC Clock Divider Low .................................................................... 430

HDLC Clock Divider High.................................................................... 431

. . . . .

Chapter 12: Serial Control Module: SPI .............................433

Features ................................................................................ 433

www.digiembedded.com 21

SPI module structure..................................................................434

SPI controller..................................................................................434

Simple parallel/serial data conversion.............................................434

Full duplex operation .................................................................434

SPI clocking modes ...........................................................................435

Timing modes ..........................................................................435

Clocking mode diagrams..............................................................435

SPI clock generation..........................................................................436

Clock generation samples ............................................................436

In SPI master mode....................................................................436

In SPI slave mode ......................................................................436

System boot-over-SPI operation............................................................436

Available strapping options ..........................................................437

EEPROM/FLASH header ...............................................................437

Header format .........................................................................437

Time to completion ...................................................................438

SPI Control and Status registers............................................................439

SPI Configuration register...................................................................439

Clock Generation register...................................................................440

Interrupt Enable register....................................................................441

Interrupt Status register.....................................................................442

SPI timing characteristics ...................................................................443

SPI master timing diagram ...........................................................444

SPI slave timing parameters .........................................................444

SPI slave timing diagram..............................................................445

Chapter 13: I2C Master/Slave Interface ............................. 447

22 Hardware Reference NS9215

Overview................................................................................447

Physical I2C bus............................. ....... ........ ....... ....... ........ ....... ......447

Multi-master bus.......................................................................448

I2C external addresses.......................................................................448

I2C command interface......................................................................449

Locked interrupt driven mode.......................................................449

Master module and slave module commands......................................449

Bus arbitration .........................................................................449

I2C registers...................................................................................450

Command Transmit Data register..........................................................450

Status Receive Data register................................................................451

Master Address register..................................................................... 452

Slave Address register....................................................................... 453

Configuration register....................................................................... 454

Timing parameter for fast-mode ................................................... 454

Interrupt Codes .............................................................................. 455

Master/slave interrupt codes ....................................................... 455

Software driver............................................................................... 456

I2C master software driver.......................................................... 456

I2C slave high level driver ........................................................... 456

Flow charts ................................................................................... 457

Master module (normal mode, 16-bit)............................................. 457

Slave module (normal mode, 16-bit)............................................... 458

. . . . .

Chapter 14: Real Time Clock Module ................................. 459

RTC functionality ..................................................................... 459

RTC configuration and status registers................................................... 460

RTC General Control register .............................................................. 460

12/24 Hour register.......................................................................... 461

Time register ................................................................................. 462

Calendar register ............................................................................ 463

Time Alarm register ......................................................................... 464

Calendar Alarm register .................................................................... 465

Alarm Enable register ....................................................................... 465

Event Flags register ......................................................................... 466

Interrupt Enable register ................................................................... 468

Interrupt Disable register................................................................... 469

Interrupt Enable Status register........................................................... 470

General Status register ..................................................................... 4 71

Chapter 15: Analog-to-Digital Converter (ADC) Module ....... 473

Features ................................................................................ 473

ADC module structure................................................................ 473

ADC control block..................................................................... 474

ADC DMA procedure ......................................................................... 474

ADC control and status registers .......................................................... 475

www.digiembedded.com 23

ADC Configuration register............................................................ ......475

ADC Clock Configuration register ..........................................................477

ADC Output Registers 0-7 ...................................................................477

Chapter 16: Timing ........................................................ 479

Electrical characteristics....................................................................479

Absolute maximum ratings...........................................................479

Recommended operating conditions................................................480

Power dissipation......................................................................480

DC electrical characteristics................................................................481

Inputs....................................................................................481

Ouputs...................................................................................482

Reset and edge sensitive input timing requirements ...................................482

...........................................................................................483

Memory Timing................................................................................484

SDRAM burst read (16-bit)............................................................485

SDRAM burst read (16 bit), CAS latency = 3 .......................................486

SDRAM burst write (16 bit) ...........................................................487

SDRAM burst read (32 bit)............................................................488

SDRAM burst read (32 bit), CAS latency = 3 .......................................489

SDRAM burst write (32-bit)...........................................................490

SDRAM load mode......................................................................491

SDRAM refresh mode ..................................................................492

Clock enable timing ...................................................................493

Values in SRAM timing diagrams.....................................................494

Static RAM read cycles with 0 wait states .........................................495

Static RAM asynchronous page mode read, WTPG = 1 ...........................496

Static RAM read cycle with configurable wait states ............................497

Static RAM sequential write cycles .................................................498

Static RAM write cycle................................................................499

Static write cycle with configurable wait states .................................500

Slow peripheral acknowledge timing ...............................................501

Slow peripheral acknowledge read .................................................502

Slow peripheral acknowledge write ................................................502

Ethernet timing ........................................................................503

Ethernet MII timing....................................................................503

C timing ...............................................................................504

SPI Timing...............................................................................505

SPI master mode 0 and 1: 2-byte transfer.........................................507

SPI master mode2 and 3: 2-byte transfer..........................................507

SPI slave mode 0 and 1: 2-byte transfer ...........................................508

SPI slave mode 2 and 3: 2-byte transfer ...........................................508

Reset and hardware strapping timing .....................................................509

JTAG timing ...................................................................................510

24 Hardware Reference NS9215

Clock timing .................................................................................. 511

System PLL reference clock timing................................................. 511

Chapter 17: Packaging ..................................................... 513

Package........................................................................................ 513

Processor Dimensions ....................................................................... 514

Chapter 18: Change log ................................................... 517

Revision B ..................................................................................... 517

Revision C..................................................................................... 517

. . . . .

www.digiembedded.com 25

26 Hardware Reference NS9215

Pinout (265)

CHAPTER 1

The NS9215 offers a connection to a 10/100 Ethernet network, as well as a

glueless connection to SDRAM, PC100 DIMM, flash, EEPROM, and SRAM memories, and an external bus expansion module. It includes four multi-function serial ports, one I2C channel, 12-bit Analog to Digital converter, battery backed real time clock and an AES data encryption/decryption module. The NS215 provides up to 108 general purpose I/O (GPIO) pins and configurable power management with sleep mode.

The Legend

Heading Description

Pin Pin number assigned for a specific I/O signal

Signal Pin name for each I/O signal. Some signals have multiple function modes and are

identified accordingly. The mode is configured through firmware using one or more configuration registers.

_n is the signal name indicates that this signal is active is active low.

U/D U or D indicates whether the pin has an internal pullup resistor or a pulldown resistor:

U Pullup (input current source)

D Pulldown (input current sink)

If no value is listed, that pin has neither an internal pullup nor pulldown resistor.

I/O The type of signal: input (I), output (O), input/output (I/O), or power (P).

OD (mA) The output drive of an output buffer. The NS9215 uses one of two drivers:

 2 mA

 4 mA

PINOUT (265)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Memory bus interface

Pin Signal U/D I/O OD Description

B9 clk_out[0] O 4 SDRAM bus clock

A15 clk_out[1] O 4 SDRAM bus clock

P12 addr[27] / gpio_a[3]

T14 addr[26] / gpio_a[2]

U15 addr[25] / gpio_a[1]

R12 addr[24] / gpio_a[0]

T13 addr[23] U I/O 4 Address bus, Boot width [0]

U14 addr[22] O 4 Address bus

U I/O 4 Address bus, Endian

U I/O 4 Address bus, SPI boot

U I/O 4 Address bus

U I/O 4 Address bus, Boot width [1]

T12 addr[21] O 4 Address bus

U13 addr[20] O 4 Address bus,

R11 addr[19] U I/O 4 Address bus, GENID 10

T11 addr[18] U I/O 4 Address bus, GENID 9

U12 addr[17] U I/O 4 Address bus, GENID 8

T10 addr[16] U I/O 4 Address bus, GENID 7

R9 addr[15] U I/O 4 Address bus, GENID 6

U11 addr[14] U I/O 4 Address bus, GENID 5

U10 addr[13] U I/O 4 Address bus, GENID 4

T9 addr[12] U I/O 4 Address bus, GENID 3

U9 addr[11] U I/O 4 Address bus, GENID 2

U8 addr[10] U I/O 4 Address bus, GENID 1

T8 addr[9] U I/O 4 Address bus, GENID 0

U7 addr[8] U I/O 4 Address bus

T7 addr[7] U I/O 4 Address bus, PLL bypass

U6 addr[6] U I/O 4 Address bus, PLL OD [1]

T6 addr[5] U I/O 4 Address bus, PLL OD [0]

U5 addr[4] U I/O 4 Address bus, PLL NR[4]

M2 addr[3] U I/O 4 Address bus, PLL NR[3]

N1 addr[2] U I/O 4 Address bus, PLL NR[2]

L2 addr[1] U I/O 4 Address bus, PLL NR[1]

28 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

M1 addr[0] U I/O 4 Address bus, PLL NR[0]

L1 data[31] U I/O 4 Data bus

K2 data[30] U I/O 4 Data bus

K1 data[29] U I/O 4 Data bus

J1 data[28] U I/O 4 Data bus

J2 data[27] U I/O 4 Data bus

H1 data[26] U I/O 4 Data bus

G1 data[25] U I/O 4 Data bus

J3 data[24] U I/O 4 Data bus

H2 data[23] U I/O 4 Data bus

F1 data[22] U I/O 4 Data bus

G2 data[21] U I/O 4 Data bus

PINOUT (265)

Memory bus interface

. . . . .

H3 data[20] U I/O 4 Data bus

E1 data[19] U I/O 4 Data bus

F2 data[18] U I/O 4 Data bus

D1 data[17] U I/O 4 Data bus

E2 data[16] U I/O 4 Data bus

H4 data[15] / gpio[31]

G3 data[14] / gpio[30] U I/O 4 Data bus

G4 data[13] / gpio[29] U I/O 4 Data bus

G5 data[12] / gpio[28] U I/O 4 Data bus

F3 data[11] / gpio[27] U I/O 4 Data bus

F4 data[10] / gpio[26] U I/O 4 Data bus

F5 data[9] / gpio[25] U I/O 4 Data bus

C1 data[8] / gpio[24] U I/O 4 Data bus

E4 data[7] / gpio[23] U I/O 4 Data bus

D2 data[6] / gpio[22] U I/O 4 Data bus

E3 data[5] / gpio[21] U I/O 4 Data bus

B1 data[4] / gpio[20] U I/O 4 Data bus

U I/O 4 Data bus

D4 data[3] / gpio[19] U I/O 4 Data bus

C2 data[2] / gpio[18] U I/O 4 Data bus

B2 data[1] / gpio[17] U I/O 4 Data bus

D3 data[0] / gpio[16] U I/O 4 Data bus

www.digiembedded.com 29

PINOUT (265)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ethernet interface MAC

Pin Signal U/D I/O OD Description

A10 data_mask[3] O 4 byte_enable data[31:24}

B11 data_mask[2] O 4 Byte enable data[23:16]

B10 data_mask[1] O 4 Byte enable data[15:08]

A11 data_mask[0] O 4 Byte enable data {07:00]

A9 ns_ta_strb I Slow peripheral transfer acknowledge

A6 rw_n O 4 Transfer direction

B7 clk_en[3] O 4 SDRAM clock enable

D7 clk_en[2] O 4 SDRAM clock enable

A7 clk_en[1] O 4 SDRAM clock enable

B8 clk_en[0] O 4 SDRAM clock enable

B4 cs[7] O 4 Chip select 7, dy_cs3

A3 cs[6] O 4 Chip select 6, st_cs3

A4 cs[5] O 4 Chip select 5, dy_cs2

C5 cs[4] O 4 Chip select 4, st_cs2

B5 cs[3] O 4 Chip select 3, dy_cs1

B6 cs[2] O 4 Chip select 2, st_cs1 (Flash boot)

D6 cs[1] O 4 Chip select 1, dy_cs0 (Boot sdram)

C6 cs[0] O 4 Chip select 0, st_cs0

C4 ras_n O 4 SDRAM RAS

A2 cas_n O 4 SDRAM CAS

C7 we_n O 4 SDRAM write enable

B3 ap10 O 4 SDRAM A10(AP)

A8 st_oe_n O 4 Static output enable

a. addr [27:24] reset to gpio mode. These address lines cannot be used for boot. b. gpio[31:16] reset to memory data bus data [15:0].

Ethernet interface MAC

Pin Signal U/D I/O OD Description

A12 mdc / gpio[32] U I/O 2 MII clock

D11 mdio / gpio[35] U I/O 2 MII data

B12 tx_clk / gpio[33] U I/O 2 TX clock

A16 txd[3] / gpio[47] U I/O 2 TX data 3

30 Hardware Reference NS9215

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Signal U/D I/O OD Description

D12 txd[2] / gpio[46] U I/O 2 TX data 2

C12 txd[1] / gpio[45] U I/O 2 TX data 1

B13 txd[0] / gpio[44] U I/O 2 TX data 0

B15 tx_er / gpio[43] U I/O 2 TX code err

B14 tx_en / gpio[42] U I/O 2 TX enable

C14 col / gpio[48] U I/O 2 Collision

C13 crs / gpio[49] U I/O 2 Carrier sense

A14 rx_clk / gpio[34] U I/O 2 RX clock

E17 rxd[3] / gpio[41] U I/O 2 RX data 3

D16 rxd[2] / gpio[40] U I/O 2 RX data 2

B17 rxd[1] / gpio[39] U I/O 2 RX data 1

D13 rxd[0] / gpio[38] U I/O 2 RX data 0

PINOUT (265)

General purpose I/O (GPIO)

. . . . .

C17 rx_er / gpio[37] U I/O 2 RX error

D17 rx_dv / gpio[36] U I/O 2 RX data valid

General purpose I/O (GPIO)

 Some signals are multiplexed to two or more GPIOs, to maximize the number of

possible applications. These duplicate signals are marked as (dup) in the Descriptions column in the table. Selecting the primary GPIO pin and the duplicate GPIO pin for the same function is not recommended. If both the primary GPIO pin and duplicate GPIO pin are programmed for the same function, however, the primary GPIO pin has precedence and will be used.

 The I

C module must be held in reset until the GPIO assigned to I2C has been

configured.

www.digiembedded.com 31

PINOUT (265)

General purpose I/O (GPIO)

Note:

All GPIOs except 12 and 16 to 31 are reset to mode 3, input. GPIO 12 is reset to mode 2, reset_done. GPIO 16 to 31 are reset to mode 0, external memory data 15:0.

Pin Signal U/D I/O OD Description

K15 gpio[0] U I/O 2 0 DCD UART A

1 Ext DMA Done Ch 0

2 PIC_0_GEN_IO[0](I/O)

3 gpio[0]

4 SPI EN (dup)

K17 gpio[1] U I/O 2 0 CTS UART A

1Ext Int 0

2 PIC_0_GEN_IO[1](I/O)

3 gpio[1]

4 Reserved

J17 gpio[2] U I/O 2 0 DSR UART A

1 Ext Int 1

2 PIC_0_GEN_IO[2](I/O)

3 gpio[2]

4 Reserved

J16 gpio[3] U I/O 2 0 RXD UART A

1 Ext DMA Pden Ch 0

2 PIC_0_GEN_IO[3](I/O)

3 gpio[3]

4 SPI RXD (dup)

H17 gpio[4] U I/O 2 0 RI UART A

1Ext Int Ch 2

2 Ext Timer Event In Ch 6

3 gpio[4]

4 SPI CLK (dup)

H13 gpio[5] U I/O 2 0 RTS / RS485 Control UART A

1Ext Int Ch 3

2 Ext Timer Event Out Ch 6

3 gpio[5]

4 SPI CLK (dup)

H14 gpio[6] U I/O 2 0 TXC / DTR UART A

1 Ext DMA Req Ch 0

2 Ext Timer Event In Ch 7

3 gpio[6]

4 PIC_DBG_DATA_OUT(O)

G14 gpio[7] U I/O 2 0 TXD UART A

1 Ext Timer Event In Ch 8

2 Ext Timer Event Out Ch 7

3 gpio[7]

4 SPI TXD (dup)

32 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

G17 gpio[8] U I/O 2 0 DCD / TXC UART C

1 Ext DMA Done Ch 1

2 Ext Timer Event Out Ch 8

3 gpio[8]

4 SPI EN (dup)

PINOUT (265)

General purpose I/O (GPIO)

. . . . .

G15 gpio[9] U I/O 4 0 CTS UART C

G16 gpio[10] U I/O 2 0 DSR UART C

F13 gpio[11] U I/O 2 0 RXD UART C

F17 gpio[12] U I/O 4 0 RXC / RI UART C

F15 gpio[13] U I/O 2 0 RXC / RTS / RS485 Control UART C

C SCL

2 Ext Int Ch 0 (dup)

3 gpio[9]

4 PIC_DBG_DATA_IN(I)

1 QDC 1

2 Ext Int Ch 1 (dup)

3 gpio[10]

4 PIC_DBG_CLK(O)

1 Ext DMA Pden Ch 1

2 Ext Int Ch 2 (dup)

3 gpio[11]

4 SPI RXD (boot)

C SDA

2 reset_done

3 gpio[12]

4 SPI CLK (dup)

1 QDC Q

2 Ext Timer Event Out Ch 9

3 gpio[13]

4 SPI CLK (boot)

E14 gpio[14] U I/O 2 0 TXC / DTR UART C

1 DMA Req Ch 1

2 PIC_0_CAN_RXD(I)

3 gpio[14]

4 SPI TXD (boot)

D14 gpio[15] U I/O 2 0 TXD UART C

1 Ext Timer Event In Ch 9

2 PIC_0_CAN_TXD(O)

3 gpio[15]

4 SPI EN (boot)

www.digiembedded.com 33

PINOUT (265)

General purpose I/O (GPIO)

Pin Signal U/D I/O OD Description

D3 gpio[16] U I/O 4 0 data[0]

1 DCD UART B

2 Ext Int Ch 0 (dup)

3 gpio[16]

B2 gpio[17] U I/O 4 0 data[1]

1CTS UART B

2 Ext Int Ch 1 (dup)

3 gpio[17]

C2 gpio[18] U I/O 4 0 data[2]

1DSR UART B

2 Ext Int Ch 2 (dup)

3 gpio[18]

D4 gpio[19] U I/O 4 0 data[3]

1RXD UART B

2 EXT INT CH 3 (dup)

3 gpio[19]

B1 gpio[20] U I/O 4 0 data[4]

1RI UART B

2 Ext DMA Done Ch 0 (dup)

3 gpio[20]

E3 gpio[21] U I/O 4 0 data[5]

1 RTS / RS485 Control UART B

2 Ext DMA Pden Ch 0 (dup)

3 gpio[21]

D2 gpio[22] U I/O 4 0 data[6]

1 TXC / DTR UART B

2 Ext DMA Done Ch 1 (dup)

3 gpio[22]

E4 gpio[23] U I/O 4 0 data[7]

1TXD UART B

2 PIC_1_CAN_RXD(I)

3 gpio[23]

C1 gpio[24] U I/O 4 0 data[8]

1 DCD UART D

2 PIC_1_CAN_TXD(O)

3 gpio[24]

F5 gpio[25] U I/O 4 0 data[9]

1CTS UART D

2 reset_done (dup)

3 gpio[25]

34 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

F4 gpio[26] U I/O 4 0 data[10]

1DSR UART D

2 PIC_1_GEN_IO[0](I/O)

3 gpio[26]

F3 gpio[27] U I/O 4 0 data[11]

1RXD UART D

2 PIC_1_GEN_IO[1](I/O)

3 gpio[27]

G5 gpio[28] U I/O 4 0 data[12]

1 RI UART D

2 PIC_1_GEN_IO[2](I/O)

3 gpio[28]

G4 gpio[29] U I/O 4 0 data[13]

1 RTS / RS485 Control UART D

2 PIC_1_GEN_IO[3](I/O)

3 gpio[29]

PINOUT (265)

General purpose I/O (GPIO)

. . . . .

G3 gpio[30] U I/O 4 0 data[14]

1 TXC / DTR UART D

2 Reserved

3 gpio[30]

H4 gpio[31] U I/O 4 0 data[15]

1TXD UART D

2 Reserved

3 gpio[31]

A12 gpio[32] U I/O 2 0 Ethernet MII MDC

1 PIC_0_GEN_IO[0](I/O)(dup)

2 Reserved

3 gpio[32]

B12 gpio[33] U I/O 2 0 Ethernet MII TXC

1 PIC_0_GEN_IO[1](I/O)(dup)

2 Reserved

3 gpio[33]

A14 gpio[34] U I/O 2 0 Ethernet MII RXC

1 PIC_0_GEN_IO[2](I/O)(dup)

2 Reserved

3 gpio[34]

D11 gpio[35] U I/O 2 0 Ethernet MII MDIO

1 PIC_0_GEN_IO[3](I/O)(dup)

2 Reserved

3 gpio[35]

www.digiembedded.com 35

PINOUT (265)

General purpose I/O (GPIO)

Pin Signal U/D I/O OD Description

D17 gpio[36] U I/O 2 0 Ethernet MII RX DV

1 PIC_0_GEN_IO[4](I/O)(dup)

2 Reserved

3 gpio[36]

C17 gpio[37] U I/O 2 0 Ethernet MII RX ER

1 PIC_0_GEN_IO[5](I/O)(dup)

2 Reserved

3 gpio[37]

D13 gpio[38] U I/O 2 0 Ethernet MII RXD[0]

1 PIC_0_GEN_IO[6](I/O)(dup)

2 Reserved

3 gpio[38]

B17 gpio[39] U I/O 2 0 Ethernet MII RXD[1]

1 PIC_0_GEN_IO[7](I/O)(dup)

2 Reserved

3 gpio[39]

D16 gpio[40] U I/O 2 0 Ethernet MII RXD [2]

1 PIC_1_GEN_IO[0](I/O)(dup)

2 Reserved

3 gpio[40]

E17 gpio[41] U I/O 2 0 Ethernet MII RXD[3]

1 PIC_1_GEN_IO[1](I/O)(dup)

2 Reserved

3 gpio[41]

B14 gpio[42] U I/O 2 0 Ethernet MII TX EN

1 PIC_1_GEN_IO[2](I/O)(dup)

2 Reserved

3 gpio[42]

B15 gpio[43] U I/O 2 0 Ethernet MII TX ER

1 PIC_1_GEN_IO[3](I/O)(dup)

2 Reserved

3 gpio[43]

B13 gpio[44] U I/O 2 ) Ethernet MII TXD[0]

1 PIC_1_GEN_IO[4](I/O)(dup)

2 Reserved

3 gpio[44]

C12 gpio[45] U I/O 2 0 Ethernet MII TXD[1]

1 PIC_1_GEN_IO[5](I/O)(dup)

2 Reserved

3 gpio[45]

36 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

D12 gpio[46] U I/O 2 0 Ethernet MII TXD[2]

1 PIC_1_GEN_IO[6](I/O)(dup)

2 Reserved

3 gpio[46]

A16 gpio[47] U I/O 2 0 Ethernet MII TXD[3]

1 PIC_1_GEN_IO[7](I/O)(dup)

2 Reserved

3 gpio[47]

C14 gpio[48] U I/O 2 0 Ethernet MII COL

1 Reserved

2 Reserved

3 gpio[48]

C13 gpio[49] U I/O 2 0 Ethernet MII CRS

1 Reserved

2 Reserved

3 gpio[49]

PINOUT (265)

General purpose I/O (GPIO)

. . . . .

C11 gpio[50] U I/O 2 0 Ethernet MII PHY Int

1 PIC_1_CLK(I)

2 PIC_1_CLK(O)

3 gpio[50]

E10 gpio[51] U I/O 2 0 DCD UART B (dup)

1 PIC_0_BUS_1[8](I/O)

2 PIC_1_BUS_1[8](I/O)

3 gpio[51]

D10 gpio[52] U I/O 2 0 CTS UART B (dup)

1 PIC_0_BUS_1[9](I/O)

2 PIC_1_BUS_1[9](I/O)

3 gpio[52]

C10 gpio[53] U I/O 2 0 DSR UART B (dup)

1 PIC_0_BUS_1[10](I/O)

2 PIC_1_BUS_1[10](I/O)

3 gpio[53]

C9 gpio[54] U I/O 2 0 RXD UART B (dup)

1 PIC_0_BUS_1[11](I/O)

2 PIC_1_BUS_1[11](I/O)

3 gpio[54]

H5 gpio[55] U I/O 2 0 RI UART B (dup)

1 PIC_0_BUS_1[12](I/O)

2 PIC_1_BUS_1[12](I/O)

3 gpio[55]

www.digiembedded.com 37

PINOUT (265)

General purpose I/O (GPIO)

Pin Signal U/D I/O OD Description

J4 gpio[56] U I/O 2 0 RTS/RS485 Control UART B (dup)

1 PIC_0_BUS_1[13](I/O)

2 PIC_1_BUS_1[13](I/O)

3 gpio[56]

K3 gpio[57] U I/O 2 0 TXC/DTR UART B (dup)

1 PIC_0_BUS_1[14](I/O)

2 PIC_1_BUS_1[14](I/O)

3 gpio[57]

K4 gpio[58] U I/O 2 0 TXD UART B (dup)

1 PIC_0_BUS_1[15](I/O)

2 PIC_1_BUS_1[15](I/O)

3 gpio[58]

K5 gpio[59] U I/O 2 0 DCD UART D (dup)

1 PIC_0_BUS_1[16](I/O)

2 PIC_1_BUS_1[16](I/O)

3 gpio[59]

R6 gpio[60] U I/O 2 0 CTS UART D (dup)

1 PIC_0_BUS_1[17](I/O)

2 PIC_1_BUS_1[17](I/O)

3 gpio[60]

P6 gpio[61] U I/O 2 0 DSR UART D (dup)

1 PIC_0_BUS_1[18](I/O)

2 PIC_1_BUS_1[18](I/O)

3 gpio[61]

R7 gpio[62] U I/O 2 0 RXD UART D (dup)

1 PIC_0_BUS_1[19](I/O)

2 PIC_1_BUS_1[19](I/O)

3 gpio[62]

P7 gpio[63] U I/O 2 0 RI UART D (dup)

1 PIC_0_BUS_1[20](I/O)

2 PIC_1_BUS_1[20](I/O)

3 gpio[63]

R8 gpio[64] U I/O 2 0 RTS/R5485 Control UART D (dup)

1 PIC_0_BUS_1[21](I/O)

2 PIC_1_BUS_1[21](I/O)

3 gpio[64]

P8 gpio[65] U I/O 2 0 TXC/DTR UART D (dup)

1 PIC_0_BUS_1[22](I/O)

2 PIC_1_BUS_1[22](I/O)

3 gpio[65]

38 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

N8 gpio[66] U I/O 2 0 TXD UART D (dup)

1 PIC_0_BUS_1[23](I/O)

2 PIC_1_BUS_1[23](I/O)

3 gpio[66]

P9 gpio[67] U I/O 2 0 PIC_0_CLK(I)

1 PIC_0_CLK(O)

2 Ext Int Ch 3 (dup)

3 gpio[67]

R10 gpio[68] U I/O 2 0 PIC_0_GEN_IO[0](I/O)(dup)

1 PIC_1_GEN_IO[0](I/O)

2 PIC_1_CAN_RXD(I)(dup)

3 gpio[68]

P10 gpio[69] U I/O 2 0 PIC_0_GEN_IO[1](I/O)(dup)

1 PIC_1_GEN_IO[1](I/O)

2 PIC_1_CAN_TXD(O)(dup)

3 gpio[69]

PINOUT (265)

General purpose I/O (GPIO)

. . . . .

N10 gpio[70] U I/O 2 0 PIC_0_GEN_IO[2](I/O)(dup)

1 PIC_1_GEN_IO[2](I/O)

2PWM Ch 0

3 gpio[70]

P11 gpio[71] U I/O 2 0 PIC_0_GEN_IO[3](I/O)(dup)

1 PIC_1_GEN_IO[3](I/O)

2PWM Ch 1

3 gpio[71]

N12 gpio[72] U I/O 2 0 PIC_0_GEN_IO[4](I/O)

1 PIC_1_GEN_IO[4](I/O)

2PWM Ch 2

3 gpio[72]

R13 gpio[73] U I/O 2 0 PIC_0_GEN_IO[5](I/O)

1 PIC_1_GEN_IO[5](I/O)

2PWM Ch 3

3 gpio[73]

P13 gpio[74] U I/O 2 0 PIC_0_GEN_IO[6](I/O)

1 PIC_0_GEN_IO[6](I/O)

2 Ext Timer Event In Ch 0

3 gpio[74]

U16 gpio[75] U I/O 2 0 PIC_0_GEN_IO[7](I/O)

1 PIC_1_GEN_IO[7](I/O)

2 Ext Timer Event in Ch 1

3 gpio[75]

www.digiembedded.com 39

PINOUT (265)

General purpose I/O (GPIO)

Pin Signal U/D I/O OD Description

T15 gpio[76] U I/O 2 0 PIC_0_CTL_IO[0](I/O)

1 PIC_1_CTL_IO[0](I/O)

2 Ext Timer Event in Ch 2

3 gpio[76]

T16 gpio[77] U I/O 2 0 PIC_0_CTL_IO[1](I/O)

1 PIC_1_CTL_IO[1](I/O)

2 Ext Timer Event in Ch 3

3 gpio[77]

R14 gpio[78] U I.O 2 0 PIC_0_CTL_IO[2](I/O)

1 PIC_1_CTL_IO[2](I/O)

2 Ext Timer Event in Ch 4

3 gpio[78]

P14 gpio[79] U I/O 2 0 PIC_0_CTL_IO[3](I/O)

1 PIC_1_CTL_IO[3](I/O)

2 Ext Timer Event in Ch 5

3 gpio[79]

R17 gpio[80] U I/O 2 0 PIC_0_BUS_0[0](I/O)

1 PIC_1_BUS_0[0](I/O)

2 Ext Timer Event in Ch 6 (dup)

3 gpio[80]

P17 gpio[81] U I/O 2 0 PIC_0_BUS_0[1](I/O)

1 PIC_1_BUS_0[1](I/O)

2 Ext Timer Event in Ch 7(dup)

3 gpio[81]

N16 gpio[82] U I/O 2 0 PIC_0_BUS_0[2](I/O)

1 PIC_1_BUS_0[2](I/O)

2 Ext Timer Event in Ch 8 (dup)

3 gpio[82]

N17 gpio[83] U I/O 2 0 PIC_0_BUS_0[3](I/O)

1 PIC_1_BUS_0[3](I/O)

2 Ext Timer Event in Ch 9 (dup)

3 gpio[83]

M17 gpio[84] U I/O 2 0 PIC_0_BUS_0[4](I/O)

1 PIC_1_BUS_0[4](I/O)

2 Ext Timer Event Out Ch 0

3 gpio[84]

L15 gpio[85] U I/O 2 0 PIC_0_BUS_0[5](I/O)

1 PIC_1_BUS_0[5](I/O)

2 Ext Timer Event Out Ch 1

3 gpio[85]

40 Hardware Reference NS9215

Pin Signal U/D I/O OD Description

K13 gpio[86] U I/O 2 0 PIC_0_BUS_0[6](I/O)

1 PIC_1_BUS_0[6](I/O)

2 Ext Timer Event Out Ch 2

3 gpio[86]

K16 gpio[87] U I/O 2 0 PIC_0_BUS_0[7](I/O)

1 PIC_1_BUS_0[7](I/O)

2 Ext Timer Event Out Ch 3

3 gpio[87]

K14 gpio[88] U I/O 2 0 PIC_0_BUS_0[8](I/O)

1 PIC_1_BUS_0[8](I/O)

2 Ext Timer Event Out Ch 4

3 gpio[88]

J14 gpio[89] U I/O 2 0 PIC_0_BUS_0[9](I/O)

1 PIC_1_BUS_0[9](I/O)

2 Ext Timer Event Out Ch 5

3 gpio[89]

PINOUT (265)

General purpose I/O (GPIO)

. . . . .

H16 gpio[90] U I/O 2 0 PIC_0_BUS_0[10](I/O)

1 PIC_1_BUS_0[10](I/O)

2 Ext Timer Event Out Ch 6

3 gpio[90]

H15 gpio[91] U I/O 2 0 PIC_0_BUS_0[11](I/O)

1 PIC_1_BUS_0[11](I/O)

2 Ext Timer Event Out Ch 7

3 gpio[91]

F14 gpio[92] U I/O 2 0 PIC_0_BUS_0[12](I/O)

1 PIC_1_BUS_0[12](I/O)

2 Ext Timer Event Out Ch 8

3 gpio[92]

F16 gpio[93] U I/O 2 0 PIC_0_BUS_0[13](I/O)

1 PIC_1_BUS_0[13](I/O)

2 Ext Timer Event Out Ch 9

3 gpio[92]

E15 gpio[94] U I/O 2 0 PIC_0_BUS_0[14](I/O)

1 PIC_1_BUS_0[14](I/O)

2 QDC I (dup)

3 gpio[94]

E16 gpio[95] U I/O 2 0 PIC_0_BUS_0[15](I/O)

1 PIC_1_BUS_0[15](I/O)

2 QDC Q (dup)

3 gpio[95]

www.digiembedded.com 41

PINOUT (265)

General purpose I/O (GPIO)

Pin Signal U/D I/O OD Description

C16 gpio[96] U I/O 2 0 PIC_0_BUS_1[0](I/O)

1 PIC_1_BUS_1[0](I/O)

2 PIC_0_CAN_RXD(I)(dup)

3 gpio[96]

B16 gpio[97] U I/O 2 0 PIC_0_BUS_1[1](I/O)

1 PIC_1_BUS_1[1](I/O)

2 PIC_0_CAN_TXD(O)(dup)

3 gpio97

D15 gpio[98] U I/O 2 0 PIC_0_BUS_1[2](I/O)

1 PIC_1_BUS_1[2](I/O)

2 PIC_1_CAN_RXD(I)(dup)

3 gpio[98]

E8 gpio[99] U I/O 2 0 PIC_0_BUS_1[3](I/O)

1 PIC_1_BUS_1[3](I/O)

2 PIC_1_CAN_TXD(O)(dup)

3 gpio[99]

D8 gpio[100] U I/O 2 0 PIC_0_BUS_1[4](I/O)

1 PIC_1_BUS_1[4](I/O)

2PWM Ch 4

3 gpio[100]

C8 gpio[101] U I/O 2 0 PIC_0_BUS_1[5](I/O)

1 PIC_1_BUS_1[5](I/O)

2 Ext Int Ch 3 (dup)

3 gpio[101]

E6 gpio[102] U I/O 4 0 PIC_0_BUS_1[6](I/O)

1 PIC_1_BUS_1[6](I/O)

C SCL (dup)

3 gpio[102]

D5 gpio[103] U I/O 4 0 PIC_0_BUS_1[7](I/O)

1 PIC_1_BUS_1[7](I/O)

C SDA (dup)

3 gpio[103]

R12 gpio_a[0] U I/O 4 0 addr[24]

C SCL (dup)

2 Ext Int Ch 0 (dup)

3 gpio_a[0], Boot width[1]

U15 gpio_a[1] U I/O 4 0 addr[25]

C SDA (dup)

2 Ext Int Ch 1(dup)

3 Ext Int Ch 0]

42 Hardware Reference NS9215

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Signal U/D I/O OD Description

T14 gpio_a[2] U I/O 4 0 addr[26]

1 Reserved 1 cs0_we_n

2 Ext Int Ch 2 (dup)

3 gpio_a[2], SPI boot

P12 gpio_a[3] U I/O 4 0 addr[27]

1 Reserved 1 cs0_oe_n

2 UART ref clock

3 gpio_a[3], Endian

a. There is a possible conflict when gpio12 is used as the I2C_SDA signal. in this case the I2C_SDA signal is driven low

while in reset, then driven active high after end of reset, until software configures this pin for the I2C function.

System clock

Pin Signal U/D I/O OD Description

PINOUT (265)

System clock

. . . . .

L16 x1_sys_osc I System oscillator circuit in

L17 x2_sys_osc O System oscillator circuit out

M15 sys_pll_dvdd P PLL clean power

M16 sys_pll_dvss P PLL clean ground

P2 x1_rtc_osc I RTC oscillator circuit in (32.768 KHz)

R2 x2_rtc_osc O RTC oscillator circuit out

www.digiembedded.com 43

System clock drawing

PINOUT (265)

System clock

44 Hardware Reference NS9215

RTC clock and

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

battery backup drawing

PINOUT (265)

System mode

. . . . .

System mode

Note: If RTC battery backup is not used, the following connection changes can be made.

N3, M4 bat_vdd_reg tie to 1.8V

32.788kHz crystal load capacitors tie to N3, M4 (1.8V)

N4 bat_vdd tie to 3.3V

R1 aux_comp tie to ground

Pin Signal U/D I/O OD Description

M13 sys_mode_2 I test mode pins

M14 sys_mode_1 I test mode pins

L14 sys_mode_0 I test mode pins

www.digiembedded.com 45

PINOUT (265)

System mode

sys_mode_2 sys_mode_1 sys_mode_0 Description

0 0 0 manufacturing test

0 0 1 manufacturing test

0 1 0 manufacturing test

0 1 1 normal operation, boundary scan enabled, POR disabled

1 0 0 normal operation, boundary scan enabled, POR enabled

1 0 1 board test mode, all outputs tristated

1 1 0 normal operation, ARM debug enabled, POR disabled

1 1 1 normal operation, ARM debug enabled, POR enabled

46 Hardware Reference NS9215

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System reset

POR

trips when

voltage on L3

drops below

2.74V/2.97V

POR disable

(as encoded on mode pins)

NS9215 C ore

NS9215

reset_out_n

reset_done

reset_ n

sreset_n

De finition s

reset_n – hardware reset input buffer with pull-up resistor sreset_n – soft reset input buffer with pull-up resistor, does not reset the PLL reset_out_n – hardware reset to NS9215 core and output buffer, resets all logic in NS9215 core including PLL reset_done – reflects the state of the ARM926 reset, for any type of reset event

PINOUT (265)

System reset

. . . . .

Pin Signal U/D I/O OD Description

E12 reset_n U I System reset

A5 reset_out_n O 2 System reset output

A13 reset_done O 2 Reset done

D9 sreset_n U I Soft system reset

RESET_n pin

SPI YES YES YES YES

BootStrapping PL YES NO NO NO

Other Strappings (Endianess

GPIO Configuration YES NO NO NO

Other (ASIC) Registers YES YES YES YEs

YESNONONO

SRESET_n pin

PLL Config Reg. Update

Watchdog Time-Out Reset

www.digiembedded.com 47

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Test

PINOUT (265)

JTAG Test

Pin Signal U/D I/O OD Description

N14 tdi U I Test data in

N15 tdo O 2 Test data out

T17 tms U I Test mode select

R16 trst_n U I Test mode reset. For normal operation, this pin

is tied to ground or pulled down.

P15 tck I Test mode clock

P16 rtck O 2 Test mode return clock

48 Hardware Reference NS9215

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADC

PINOUT (265)

ADC

. . . . .

Pin Signal U/D I/O OD Description

P4 agnd_ref_adc Analog reference ground

P5 VREF_adc Analog reference voltage (3.3max

T2 vss_adc ADC_VSS

N6 vdd_adc ADC VDD (3.3V)

R4 vin0_adc I ADC input 0

T3 vin1_adc I ADC input 1

R5 vin2_adc I ADC input 2

U2 vin3_adc I ADC input 3

T4 vin4_adc I ADC input 4

U3 vin5_adc I ADC input 5

T5 vin6_adc I ADC input 6

U4 vin7_adc I ADC input 7

If the ADC feature is not used, the inputs must be terminated as shown below:

P4 agnd_ref_adc tie to ground

P5 VREF_adc tie to ground

T2 vss_adc tie to ground

N6 vdd_adc tie to 3.3V

R4 vin0_adc tie to ground

T3 vin1_adc tie to ground

R5 vin2_adc tie to ground

U2 vin3_adc tie to ground

T4 vin4_adc tie to ground

U3 vin5_adc tie to ground

T5 vin6_adc tie to ground

U4 vin7_adc tie to ground

www.digiembedded.com 49

PINOUT (265)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POR and battery-backed logic

Pin Signal U/D I/O OD Description

M3 por_gnd_reg POR reference ground

N2 por_vss POR VSS

P1 por_vdd POR VDD (3.3V)

L3 por_reference POR reference trip voltage (2.74V min /

T1 por_early_reference POR early power loss voltage (1.19V min /

N4 bat_vdd Battery VDD (3.0V)

R1 aux_comp Auxiliary analog comparator input (trip point

N3, M4 bat_vdd_reg Battery regulated core VDD (1.8V)

P3 por_bypass U I POR bypass, pull low to disable POR

2.97V max)

1.28V max)

2.4V min / 2.5V max)

L4 por_test POR analog test pin, leave unconnected

The POR will generate keep reset_out_n low between 75ms and 300ms after 3.3V reaches the POR reference trip voltage threshold. The POR reference trip voltage is between 2.74V and 2.97V, with hysteresis between 50mV and 80mV.

If the POR feature is not used, and the RTC is used, the inputs must be terminated as shown below.

M3 por_gnd_reg tie to ground

N2 por_vss tie to ground

P1 por_vdd tie to 3.3V

L3 por_reference tie to 3.3V

T1 por_early_reference tie to ground

P3 por_bypass tie to 1.8V

E12 reset_n tie to system reset (remains active low 40 ms Min. after 3.3V & 1.8V are valid)

A5 reset_out_n leave open

M13, M14, L14

sys_mode [2.0] POR disabled (See System mode table & JTAG drawing following JTAG Test

table)

50 Hardware Reference NS9215

If the RTC feature is not used, the inputs must be terminated as shown below.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N4 Bat_vdd tie to 3.3V

R1 aux_comp tie to ground

N3, M4 bat_vdd_reg tie to ground

P2 x1_rtc_osc tie to ground

R2 x2_rtc_osc leave open

If the RTC feature is used, see RTC clock and battery backup drawing on page 45.

Power and ground

Pin Signal

E7, E11, G7, G11, G13, L5, L7, L11, L13, N7, N11 Core VCC (1.8V)

PINOUT (265)

Power and ground

. . . . .

A1. A17. C3, C15, E5, E9, E13, J5, J13, J15, N5, N9, N13, R3, R15, U1, U17 I/O VCC (3.3V)

G8, G9, G10, H7, H8, H9, H10, H11, J7, J8, J9, J10, J11, K7, K8, K9, K10, K11, L8, L9, L10, M5

GND

www.digiembedded.com 51

PINOUT (265)

Power and ground

52 Hardware Reference NS9215

I/O Control Module

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 2

The NS9215 ASIC contains 108 pins that are designated as general purpose I/O

(GPIO).

 The first 16 GPIO can be configured to serve one of five functions.  The remaining GPIO can be configured to serve one of four functions.

All signals set to a disabled peripheral are held in the inactive state. The I/O control module contains the control register and multiplexing logic required to accomplish this task.

System memory bus I/O control

The registers in this section control these system memory I/O configuration options:

 System chip select options, used to select which chip select is output  Upper address option

Control and Status registers

The I/O control module configuration registers are located at base address 0xA090_2000.

Address Description Access Reset value

A090_2000 GPIO Configuration Register #0 R/W 0x18181818

A090_2004 GPIO Configuration Register #1 R/W 0x18181818

A090_2008 GPIO Configuration Register #2 R/W 0x18181818

I/O CONTROL MODULE

Control and Status registers

Address Description Access Reset value

A090_200C GPIO Configuration Register #3 R/W 0x18181810

A090_2010 GPIO Configuration Register #4 R/W 0x00000000

A090_2014 GPIO Configuration Register #5 R/W 0x00000000

A090_2018 GPIO Configuration Register #6 R/W 0x00000000

A090_201C GPIO Configuration Register #7 R/W 0x00000000

A090_2020 GPIO Configuration Register #8 R/W 0x18181818

A090_2024 GPIO Configuration Register #9 R/W 0x18181818

A090_2028 GPIO Configuration Register #10 R/W 0x18181818

A090_202C GPIO Configuration Register #11 R/W 0x18181818

A090_2030 GPIO Configuration Register #12 R/W 0x18181818

A090_2034 GPIO Configuration Register #13 R/W 0x18181818

A090_2038 GPIO Configuration Register #14 R/W 0x18181818

A090_203C GPIO Configuration Register #15 R/W 0x18181818

A090_2040 GPIO Configuration Register #16 R/W 0x18181818

A090_2044 GPIO Configuration Register #17 R/W 0x18181818

A090_2048 GPIO Configuration Register #18 R/W 0x18181818

A090_204C GPIO Configuration Register #19 R/W 0x18181818

A090_2050 GPIO Configuration Register #20 R/W 0x18181818

A090_2054 GPIO Configuration Register #21 R/W 0x18181818

A090_2058 GPIO Configuration Register #22 R/W 0x18181818

A090_205C GPIO Configuration Register #23 R/W 0x18181818

A090_2060 GPIO Configuration Register #24 R/W 0x18181818

A090_2064 GPIO Configuration Register #25 R/W 0x18181818

A090_2068 GPIO Configuration Register #26 R/W 0x18181818

A090_206C GPIO Control Register #0 R/W 0x00000000

A090_2070 GPIO Control Register #1 R/W 0x00000000

A090_2074 GPIO Control Register #2 R/W 0x00000000

A090_2078 GPIO Control Register #3 R/W 0x00000000

A090_207C GPIO Status Register #0 R Undefined

A090_2080 GPIO Status Register #1 R Undefined

A090_2084 GPIO Status Register #2 R Undefined

A090_2088 GPIO Status Register #3 R Undefined

54 Hardware Reference NS9215

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address Description Access Reset value

A090_208C Memory Bus Configuration register R/W 007D6344

1 The reset values for all the status bits are undefined because they depend on the state of the GPIO

pins to NS9215.

GPIO Configuration registers

GPIO Configuration registers #0 through #26 contain the configuration information for each of the 108 GPIO pins. Each GPIO pin can have up to four functions. Configure each pin for the function and direction needed, using the configuration options shown below.

I/O CONTROL MODULE

GPIO Configuration registers

. . . . .

GPIO configuration options

Each GPIO configuration section is set up the same way. This table shows the settings using bits D07:00; the same settings apply to the corresponding bits in D15:08, D23:D16, and D31:24.

Bit(s) Mnemonic Description

D07:06 Reserved N/A

D05:03 FUNC Use these bits to select the function you want to use. For a definition of each

function, see “General purpose I/O (GPIO)” on page 31.

000 Function #0

001 Function #1

010 Function #2

011 Function #3

100 Function #4 (applicable only for GPIO 0–15)

D02 DIR Controls the pin direction when the FUNC field is configured for GPIO

mode, function #3.

0 Input

1 Output

All GPIO pins reset to the input state.

Note: The pin direction is controlled by the selected function in modes

#0 through #2.

D01 INV Controls the inversion function of the GPIO pin.

0 Disables the inversion function

1 Enables the inversion function

This bit applies to all functional modes.

D00 PUDIS Controls the GPIO pin pullup resistor operation.

0 Enables the pullup

1 Disables the pullup

Note: The pullup cannot be disabled on GPIO[9], GPIO[12], and on

GPIO_A[0] and GPIO_A[1].

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I/O CONTROL MODULE

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GPIO3 GPIO2

GPIO1

GPIO0

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO7 GPIO6

GPIO5

GPIO4

GPIO Configuration registers

GPIO Configuration Register #0

GPIO Configuration Register #1

Address: A090_2000

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO3 0x18 GPIO[3] configuration

D23:16 R/W GPIO2 0x18 GPIO[2] configuration

D15:08 R/W GPIO1 0x18 GPIO[1] configuration

D07:00 R/W GPIO0 0x18 GPIO[0] configuration

Address: A090_2004

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO7 0x18 GPIO[7] configuration

D23:16 R/W GPIO6 0x18 GPIO[6] configuration

D15:08 R/W GPIO5 0x18 GPIO[5] configuration

D07:00 R/W GPIO4 0x18 GPIO[4] configuration

56 Hardware Reference NS9215

I/O CONTROL MODULE

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GPIO11 GPIO10

GPIO9

GPIO8

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GP IO15 GPIO 1 4

GPIO13

GPIO12

GPIO Configuration registers

. . . . .

GPIO Configuration Register #2

GPIO Configuration Register #3

Address: A090_2008

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO11 0x18 GPIO[11] configuration

D23:16 R/W GPIO10 0x18 GPIO[10] configuration

D15:08 R/W GPIO9 0x18 GPIO[9] configuration

D07:00 R/W GPIO8 0x18 GPIO[8] configuration

Address: A090_200C

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO15 0x18 GPIO[15] configuration

D23:16 R/W GPIO14 0x18 GPIO[14 configuration

D15:08 R/W GPIO13 0x18 GPIO[13] configuration

D07:00 R/W GPIO12 0x10 GPIO[12] configuration

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GPIO19 GPIO18

GPIO17

GPIO16

13121110987654321015 14

31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO23 GPIO22

GPIO21

GPIO20

GPIO Configuration registers

GPIO Configuration Register #4

GPIO Configuration Register #5

Address: A090_2010

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO19 0x00 GPIO[19] configuration

D23:16 R/W GPIO18 0x00 GPIO[18] configuration

D15:08 R/W GPIO17 0x00 GPIO[17] configuration

D07:00 R/W GPIO16 0x00 GPIO[16] configuration

Address: A090_2014

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO23 0x00 GPIO[23] configuration

D23:16 R/W GPIO22 0x00 GPIO[22] configuration

D15:08 R/W GPIO21 0x00 GPIO[21] configuration

D07:00 R/W GPIO20 0x00 GPIO[20] configuration

58 Hardware Reference NS9215

I/O CONTROL MODULE

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO27 GPIO26

GPIO25

GPIO24

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO39 G PIO38

GPIO37

GPIO36

GPIO Configuration registers

. . . . .

GPIO Configuration Register #6

GPIO Configuration Register #7

Address: A090_2018

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO27 0x00 GPIO[27] configuration

D23:16 R/W GPIO26 0x00 GPIO[26] configuration

D15:08 R/W GPIO25 0x00 GPIO[25] configuration

D07:00 R/W GPIO24 0x00 GPIO[24] configuration

Address: A090_201C

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO31 0x00 GPIO[31] configuration

D23:16 R/W GPIO30 0x00 GPIO[30] configuration

D15:08 R/W GPIO29 0x00 GPIO[29] configuration

D07:00 R/W GPIO28 0x00 GPIO[28] configuration

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GP IO35 GP IO 3 4

GPIO33

GPIO32

13121110987654321015 14

31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

G P IO39 GP IO38

GPIO37

GPIO36

GPIO Configuration registers

GPIO Configuration Register #8

GPIO Configuration Register #9

Address: A090_2020

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO35 0x18 GPIO[35] configuration

D23:16 R/W GPIO34 0x18 GPIO[34] configuration

D15:08 R/W GPIO33 0x18 GPIO[33] configuration

D07:00 R/W GPIO32 0x18 GPIO[32] configuration

Address: A090_2024

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO39 0x18 GPIO[39] configuration

D23:16 R/W GPIO38 0x18 GPIO[38] configuration

D15:08 R/W GPIO37 0x18 GPIO[37] configuration

D07:00 R/W GPIO36 0x18 GPIO[36] configuration

60 Hardware Reference NS9215

I/O CONTROL MODULE

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G P IO 43 GPIO42

GPIO41

GPIO40

13121110987654321015 14

31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO47 GPIO46

GPIO45

GPIO44

GPIO Configuration registers

. . . . .

GPIO Configuration Register #10

GPIO Configuration Register #11

Address: A090_2028

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO43 0x18 GPIO[43] configuration

D23:16 R/W GPIO42 0x18 GPIO[42] configuration

D15:08 R/W GPIO41 0x18 GPIO[41] configuration

D07:00 R/W GPIO40 0x18 GPIO[40] configuration

Address: A090_202C

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO47 0x18 GPIO[47] configuration

D23:16 R/W GPIO46 0x18 GPIO[46] configuration

D15:08 R/W GPIO45 0x18 GPIO[45] configuration

D07:00 R/W GPIO44 0x18 GPIO[44] configuration

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GPIO51 GPIO50

GPIO49

GPIO48

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO55 GPIO54

GPIO53

GPIO52

GPIO Configuration registers

GPIO Configuration Register #12

GPIO Configuration Register #13

Address: A090_2030

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO51 0x18 GPIO[51] configuration

D23:16 R/W GPIO50 0x18 GPIO[50] configuration

D15:08 R/W GPIO49 0x18 GPIO[49] configuration

D07:00 R/W GPIO48 0x18 GPIO[48] configuration

Address: A090_2034

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO55 0x18 GPIO[55] configuration

D23:16 R/W GPIO54 0x18 GPIO[54] configuration

D15:08 R/W GPIO53 0x18 GPIO[53] configuration

D07:00 R/W GPIO52 0x18 GPIO[52] configuration

62 Hardware Reference NS9215

I/O CONTROL MODULE

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GPIO59 GPIO 5 8

GPIO57

GPIO56

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO63 GPIO62

GPIO61

GPIO60

GPIO Configuration registers

. . . . .

GPIO Configuration Register #14

GPIO Configuration Register #15

Address: A090_2038

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO59 0x18 GPIO[59] configuration

D23:16 R/W GPIO58 0x18 GPIO[58] configuration

D15:08 R/W GPIO57 0x18 GPIO[57] configuration

D07:00 R/W GPIO56 0x18 GPIO[56] configuration

Address: A090_203C

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO63 0x18 GPIO[63] configuration

D23:16 R/W GPIO62 0x18 GPIO[62] configuration

D15:08 R/W GPIO61 0x18 GPIO[61] configuration

D07:00 R/W GPIO60 0x18 GPIO[60] configuration

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GPIO67 GPIO66

GPIO65

GPIO64

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO71 GPIO70

GPIO69

GPIO68

GPIO Configuration registers

GPIO Configuration Register #16

GPIO Configuration Register #17

Address: A090_2040

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO67 0x18 GPIO[67] configuration

D23:16 R/W GPIO66 0x18 GPIO[66] configuration

D15:08 R/W GPIO65 0x18 GPIO[65] configuration

D07:00 R/W GPIO64 0x18 GPIO[64] configuration

Address: A090_2044

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO71 0x18 GPIO[71] configuration

D23:16 R/W GPIO70 0x18 GPIO[70] configuration

D15:08 R/W GPIO69 0x18 GPIO[69] configuration

D07:00 R/W GPIO68 0x18 GPIO[68] configuration

64 Hardware Reference NS9215

I/O CONTROL MODULE

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

G P IO75 GPIO7 4

GPIO73

GPIO72

13121110987654321015 14

31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO79 GPIO78

GPIO77

GPIO76

GPIO Configuration registers

. . . . .

GPIO Configuration Register #18

GPIO Configuration Register #19

Address: A090_2048

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO75 0x18 GPIO[75] configuration

D23:16 R/W GPIO74 0x18 GPIO[74] configuration

D15:08 R/W GPIO73 0x18 GPIO[73] configuration

D07:00 R/W GPIO72 0x18 GPIO[72] configuration

Address: A090_204C

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO79 0x18 GPIO[79] configuration

D23:16 R/W GPIO78 0x18 GPIO[78] configuration

D15:08 R/W GPIO77 0x18 GPIO[77] configuration

D07:00 R/W GPIO76 0x18 GPIO[76] configuration

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I/O CONTROL MODULE

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GPIO83 GPIO82

GPIO81

GPIO80

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO87 GPIO86

GPIO85

GPIO84

GPIO Configuration registers

GPIO Configuration Register #20

GPIO Configuration Register #21

Address: A090_2050

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO83 0x18 GPIO[83] configuration

D23:16 R/W GPIO82 0x18 GPIO[82] configuration

D15:08 R/W GPIO81 0x18 GPIO[81] configuration

D07:00 R/W GPIO80 0x18 GPIO[80] configuration

Address: A090_2054

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO87 0x18 GPIO[87] configuration

D23:16 R/W GPIO86 0x18 GPIO[86] configuration

D15:08 R/W GPIO85 0x18 GPIO[85] configuration

D07:00 R/W GPIO84 0x18 GPIO[84] configuration

66 Hardware Reference NS9215

I/O CONTROL MODULE

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

G P IO91 G P IO90

GPIO89

GPIO88

13121110987654321015 14

31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO95 GPIO94

GPIO93

GPIO92

GPIO Configuration registers

. . . . .

GPIO Configuration Register #22

GPIO Configuration Register #23

Address: A090_2058

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO91 0x18 GPIO[91] configuration

D23:16 R/W GPIO90 0x18 GPIO[90] configuration

D15:08 R/W GPIO89 0x18 GPIO[89] configuration

D07:00 R/W GPIO88 0x18 GPIO[88] configuration

Address: A090_205C

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO95 0x18 GPIO[95] configuration

D23:16 R/W GPIO94 0x18 GPIO[94] configuration

D15:08 R/W GPIO93 0x18 GPIO[93] configuration

D07:00 R/W GPIO92 0x18 GPIO[92] configuration

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G P IO99 GPIO98

GPIO97

GPIO96

13121110987654321015 14

31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO103 GPIO102

GPIO101

GPIO100

GPIO Configuration registers

GPIO Configuration Register #24

GPIO Configuration Register #25

Address: A090_2060

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO99 0x18 GPIO[99] configuration

D23:16 R/W GPIO98 0x18 GPIO[98] configuration

D15:08 R/W GPIO97 0x18 GPIO[97] configuration

D07:00 R/W GPIO96 0x18 GPIO[96] configuration

Address: A090_2064

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO103 0x18 GPIO[103] configuration

D23:16 R/W GPIO102 0x18 GPIO[102] configuration

D15:08 R/W GPIO101 0x18 GPIO[101] configuration

D07:00 R/W GPIO100 0x18 GPIO[100] configuration

68 Hardware Reference NS9215

I/O CONTROL MODULE

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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630

GPIO_A3 GPIO_A2

GPIO_A1

GPIO_A0

GPIO Configuration registers

. . . . .

GPIO Configuration Register #26

Address: A090_2068

Bit(s) Access Mnemonic Reset Description

D31:24 R/W GPIO_A3 0x18 GPIO_A[3] configuration

D23:16 R/W GPIO_A2 0x18 GPIO_A[2] configuration

D15:08 R/W GPIO_A1 0x18 GPIO_A[1] configuration

D07:00 R/W GPIO_A0 0x18 GPIO_A[0] configuration

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GPIO Control re gisters

GPIO Control registers

GPIO Control Registers #0 through #3 contain the control information for each of the 108 GPIO pins. When a GPIO pin is configured as a GPIO output, the corresponding bit in GPIO Control Registers #0 through #3 is driven out the GPIO pin. In all configurations, the CPU has read/write access to these registers.

GPIO Control Register #0

Address: A090_206C

Bit(s) Access Mnemonic Reset Description

D00 R/W GPIO0 0 GPIO[0] control bit

D01 R/W GPIO1 0 GPIO[1] control bit

D02 R/W GPIO2 0 GPIO[2] control bit

D03 R/W GPIO3 0 GPIO[3] control bit

D04 R/W GPIO4 0 GPIO[4] control bit

D05 R/W GPIO5 0 GPIO[5] control bit

D06 R/W GPIO6 0 GPIO[6] control bit

D07 R/W GPIO7 0 GPIO[7] control bit

D08 R/W GPIO8 0 GPIO[8] control bit

D09 R/W GPIO9 0 GPIO[9] control bit

D10 R/W GPIO10 0 GPIO[10] control bit

D11 R/W GPIO11 0 GPIO[11] control bit

D12 R/W GPIO12 0 GPIO[12] control bit

D13 R/W GPIO13 0 GPIO[13] control bit

D14 R/W GPIO14 0 GPIO[14] control bit

D15 R/W GPIO15 0 GPIO[15] control bit

D16 R/W GPIO16 0 GPIO[16] control bit

D17 R/W GPIO17 0 GPIO[17] control bit

D18 R/W GPIO18 0 GPIO[18] control bit

D19 R/W GPIO19 0 GPIO[19] control bit

D20 R/W GPIO20 0 GPIO[20] control bit

D21 R/W GPIO21 0 GPIO[21] control bit

D22 R/W GPIO22 0 GPIO[22] control bit

D23 R/W GPIO23 0 GPIO[23] control bit

D24 R/W GPIO24 0 GPIO[24] control bit

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I/O CONTROL MODULE

Bit(s) Access Mnemonic Reset Description

D25 R/W GPIO25 0 GPIO[25] control bit

D26 R/W GPIO26 0 GPIO[26] control bit

D27 R/W GPIO27 0 GPIO[27] control bit

D28 R/W GPIO28 0 GPIO[28] control bit

D29 R/W GPIO29 0 GPIO[29] control bit

D30 R/W GPIO30 0 GPIO[30] control bit

D31 R/W GPIO31 0 GPIO[31] control bit

GPIO Control registers

. . . . .

GPIO Control Register #1

Address: A090_2070

Bit(s) Access Mnemonic Reset Description

D00 R/W GPIO32 0 GPIO[32] control bit

D01 R/W GPIO33 0 GPIO[33] control bit

D02 R/W GPIO34 0 GPIO[34] control bit

D03 R/W GPIO35 0 GPIO[35] control bit

D04 R/W GPIO36 0 GPIO[36] control bit

D05 R/W GPIO37 0 GPIO[37] control bit

D06 R/W GPIO38 0 GPIO[38] control bit

D07 R/W GPIO39 0 GPIO[39] control bit

D08 R/W GPIO40 0 GPIO[40] control bit

D09 R/W GPIO41 0 GPIO[41] control bit

D10 R/W GPIO42 0 GPIO[42] control bit

D11 R/W GPIO43 0 GPIO[43] control bit

D12 R/W GPIO44 0 GPIO[44] control bit

D13 R/W GPIO45 0 GPIO[45] control bit

D14 R/W GPIO46 0 GPIO[46] control bit

D15 R/W GPIO47 0 GPIO[47] control bit

D16 R/W GPIO48 0 GPIO[48] control bit

D17 R/W GPIO49 0 GPIO[49] control bit

D18 R/W GPIO50 0 GPIO[50] control bit

D19 R/W GPIO51 0 GPIO[51] control bit

D20 R/W GPIO52 0 GPIO[52] control bit

D21 R/W GPIO53 0 GPIO[53] control bit

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I/O CONTROL MODULE

GPIO Control re gisters

Bit(s) Access Mnemonic Reset Description

D22 R/W GPIO54 0 GPIO[54] control bit

D23 R/W GPIO55 0 GPIO[55] control bit

D24 R/W GPIO56 0 GPIO[56] control bit

D25 R/W GPIO57 0 GPIO[57] control bit

D26 R/W GPIO58 0 GPIO[58] control bit

D27 R/W GPIO59 0 GPIO[59] control bit

D28 R/W GPIO60 0 GPIO[60] control bit

D29 R/W GPIO61 0 GPIO[61] control bit

D30 R/W GPIO62 0 GPIO[62] control bit

D31 R/W GPIO63 0 GPIO[63] control bit

GPIO Control Register #2

Address: A090_2074

Bit(s) Access Mnemonic Reset Description

D00 R/W GPIO64 0 GPIO[64] control bit

D01 R/W GPIO65 0 GPIO[65] control bit

D02 R/W GPIO66 0 GPIO[66] control bit

D03 R/W GPIO67 0 GPIO[67] control bit

D04 R/W GPIO68 0 GPIO[68] control bit

D05 R/W GPIO69 0 GPIO[69] control bit

D06 R/W GPIO70 0 GPIO[70] control bit

D07 R/W GPIO71 0 GPIO[71] control bit

D08 R/W GPIO72 0 GPIO[72] control bit

D09 R/W GPIO73 0 GPIO[73] control bit

D10 R/W GPIO74 0 GPIO[74] control bit

D11 R/W GPIO75 0 GPIO[75] control bit

D12 R/W GPIO76 0 GPIO[76] control bit

D13 R/W GPIO77 0 GPIO[77] control bit

D14 R/W GPIO78 0 GPIO[78] control bit

D15 R/W GPIO79 0 GPIO[79] control bit

D16 R/W GPIO80 0 GPIO[80] control bit

D17 R/W GPIO81 0 GPIO[81] control bit

D18 R/W GPIO82 0 GPIO[82] control bit

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I/O CONTROL MODULE

Bit(s) Access Mnemonic Reset Description

D19 R/W GPIO83 0 GPIO[83] control bit

D20 R/W GPIO84 0 GPIO[84] control bit

D21 R/W GPIO85 0 GPIO[85] control bit

D22 R/W GPIO86 0 GPIO[86] control bit

D23 R/W GPIO87 0 GPIO[87] control bit

D24 R/W GPIO88 0 GPIO[88] control bit

D25 R/W GPIO89 0 GPIO[89] control bit

D26 R/W GPIO90 0 GPIO[90] control bit

D27 R/W GPIO91 0 GPIO[91] control bit

D28 R/W GPIO92 0 GPIO[92] control bit

D29 R/W GPIO93 0 GPIO[93] control bit

D30 R/W GPIO94 0 GPIO[94] control bit

GPIO Control registers

. . . . .

GPIO Control Register #3

D31 R/W GPIO95 0 GPIO[95] control bit

Address: A090_2078

Bit(s) Access Mnemonic Reset Description

D00 R/W GPIO96 0 GPIO[96] control bit

D01 R/W GPIO97 0 GPIO[97] control bit

D02 R/W GPIO98 0 GPIO[98] control bit

D03 R/W GPIO99 0 GPIO[99] control bit

D04 R/W GPIO100 0 GPIO[100] control bit

D05 R/W GPIO101 0 GPIO[101] control bit

D06 R/W GPIO102 0 GPIO[102] control bit

D07 R/W GPIO103 0 GPIO[103] control bit

D08 R/W GPIO_A0 0 GPIO_A[0] control bit

D09 R/W GPIO_A1 0 GPIO_A[1] control bit

D10 R/W GPIO_A2 0 GPIO_A[2] control bit

D11 R/W GPIO_A3 0 GPIO_A[3] control bit

D31:12 N/A Reserved N/A N/A

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GPIO Status registers

GPIO Status Registers #0 through #3 contain the status information for each of the 108 GPIO pins. In all configurations, the value on the GPIO input pin is brought to the status register and the CPU has read-only access to the register.

GPIO Status Register #1

Address: A090_2080

Bit(s) Access Mnemonic Reset Description

D00 R GPIO32 Undefined GPIO[32] status bit

D01 R GPIO33 Undefined GPIO[33] status bit

D02 R GPIO34 Undefined GPIO[34] status bit

D03 R GPIO35 Undefined GPIO[35] status bit

D04 R GPIO36 Undefined GPIO[36] status bit

D05 R GPIO37 Undefined GPIO[37] status bit

D06 R GPIO38 Undefined GPIO[38] status bit

D07 R GPIO39 Undefined GPIO[39] status bit

D08 R GPIO40 Undefined GPIO[40] status bit

D09 R GPIO41 Undefined GPIO[41] status bit

D10 R GPIO42 Undefined GPIO[42] status bit

D11 R GPIO43 Undefined GPIO[43] status bit

D12 R GPIO44 Undefined GPIO[44] status bit

D13 R GPIO45 Undefined GPIO[45] status bit

D14 R GPIO46 Undefined GPIO[46] status bit

D15 R GPIO47 Undefined GPIO[47] status bit

D16 R GPIO48 Undefined GPIO[48] status bit

D17 R GPIO49 Undefined GPIO[49] status bit

D18 R GPIO50 Undefined GPIO[50] status bit

D19 R GPIO51 Undefined GPIO[51] status bit

D20 R GPIO52 Undefined GPIO[52] status bit

D21 R GPIO53 Undefined GPIO[3] status bit

D22 R GPIO54 Undefined GPIO[54] status bit

D23 R GPIO55 Undefined GPIO[55] status bit

D24 R GPIO56 Undefined GPIO[56] status bit

D25 R GPIO57 Undefined GPIO[57] status bit

74 Hardware Reference NS9215

I/O CONTROL MODULE

GPIO Status registers

Bit(s) Access Mnemonic Reset Description

D26 R GPIO58 Undefined GPIO[58] status bit

D27 R GPIO59 Undefined GPIO[59] status bit

D28 R GPIO60 Undefined GPIO[60] status bit

D29 R GPIO61 Undefined GPIO[61] status bit

D30 R GPIO62 Undefined GPIO[62] status bit

D31 R GPIO63 Undefined GPIO[63] status bit

. . . . .

GPIO Status Register #2

Address: A090_2084

Bit(s) Access Mnemonic Reset Description

D00 R GPIO64 Undefined GPIO[64] status bit

D01 R GPIO65 Undefined GPIO[65] status bit

D02 R GPIO66 Undefined GPIO[66] status bit

D03 R GPIO67 Undefined GPIO[67] status bit

D04 R GPIO68 Undefined GPIO[68] status bit

D05 R GPIO69 Undefined GPIO[69] status bit

D06 R GPIO70 Undefined GPIO[70] status bit

D07 R GPIO71 Undefined GPIO[71] status bit

D08 R GPIO72 Undefined GPIO[72] status bit

D09 R GPIO73 Undefined GPIO[73] status bit

D10 R GPIO74 Undefined GPIO[74] status bit

D11 R GPIO75 Undefined GPIO[75] status bit

D12 R GPIO76 Undefined GPIO[76] status bit

D13 R GPIO77 Undefined GPIO[77] status bit

D14 R GPIO78 Undefined GPIO[78] status bit

D15 R GPIO79 Undefined GPIO[79] status bit

D16 R GPIO80 Undefined GPIO[80] status bit

D17 R GPIO81 Undefined GPIO[81] status bit

D18 R GPIO82 Undefined GPIO[82] status bit

D19 R GPIO83 Undefined GPIO[83] status bit

D20 R GPIO84 Undefined GPIO[84] status bit

D21 R GPIO85 Undefined GPIO[85] status bit

D22 R GPIO86 Undefined GPIO[86] status bit

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I/O CONTROL MODULE

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Memory Bus Configuration register

Bit(s) Access Mnemonic Reset Description

D23 R GPIO87 Undefined GPIO[87] status bit

D24 R GPIO88 Undefined GPIO[88] status bit

D25 R GPIO89 Undefined GPIO[89] status bit

D26 R GPIO90 Undefined GPIO[90] status bit

D27 R GPIO91 Undefined GPIO[91] status bit

D28 R GPIO92 Undefined GPIO[92] status bit

D29 R GPIO93 Undefined GPIO[93] status bit

D30 R GPIO94 Undefined GPIO[94] status bit

D31 R GPIO95 Undefined GPIO[95] status bit

GPIO Status Register #3

Address: A090_2088

Bit(s) Access Mnemonic Reset Description

D00 R GPIO96 Undefined GPIO[96] status bit

D01 R GPIO97 Undefined GPIO[97] status bit

D02 R GPIO98 Undefined GPIO[98] status bit

D03 R GPIO99 Undefined GPIO[99] status bit

D04 R GPIO100 Undefined GPIO[100] status bit

D05 R GPIO101 Undefined GPIO[101] status bit

D06 R GPIO102 Undefined GPIO[102] status bit

D07 R GPIO103 Undefined GPIO[103] status bit

D08 R GPIO_A0 Undefined GPIO_A[0] status bit

D09 R GPIO_A1 Undefined GPIO_A[1] status bit

D10 R GPIO_A2 Undefined GPIO_A[2] status bit

D11 R GPIO_A3 Undefined GPIO_A[3] status bit

D31:12 N/A Reserved N/A N/A

Memory Bus Configuration register

The Memory Bus Configuration register controls chip select and upper address options.

Address: A090_208C

76 Hardware Reference NS9215

I/O CONTROL MODULE

Memory Bus Configuration register

Bit(s) Access Mnemonic Reset Description

D02:00 R/W CS0 0x4 Controls which system memory chip select is

routed to CS0

000 dy_cs_0

001 dy_cs_1

010 dy_cs_2

011 dy_cs_3

100 st_cs_0 (default)

101 st_cs_1

110 st_cs_2

111 st_cs_3

D05:03 R/W CS1 0x0 Controls which system memory chip select is

routed to CS1

000 dy_cs_0 (default)

001 dy_cs_1

010 dy_cs_2

011 dy_cs_3

100 st_cs_0

101 st_cs_1

110 st_cs_2

111 st_cs_3

. . . . .

D08:06 R/W CS2 0x5 Controls which system memory chip select is

routed to CS2

000 dy_cs_0

001 dy_cs_1

010 dy_cs_2

011 dy_cs_3

100 st_cs_0

101 st_cs_1 (default)

110 st_cs_2

111 st_cs_3

D11:09 R/W CS3 0x1 Controls which system memory chip select is

routed to CS3

000 dy_cs_0

001 dy_cs_1 (default)

010 dy_cs_2

011 dy_cs_3

100 st_cs_0

101 st_cs_1

110 st_cs_2

111 st_cs_3

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I/O CONTROL MODULE

Memory Bus Configuration register

Bit(s) Access Mnemonic Reset Description

D14:12 R/W CS4 0x6 Controls which system memory chip select is

routed to CS4

000 dy_cs_0

001 dy_cs_1

010 dy_cs_2

011 dy_cs_3

100 st_cs_0

101 st_cs_1

110 st_cs_2 (default)

111 st_cs_3

D17:15 R/W CS5 0x2 Controls which system memory chip select is

routed to CS5

000 dy_cs_0

001 dy_cs_1

010 dy_cs_2 (default)

011 dy_cs_3

100 st_cs_0

101 st_cs_1

110 st_cs_2

111 st_cs_3

D20:18 R/W CS6 0x7 Controls which system memory chip select is

routed to CS6

000 dy_cs_0

001 dy_cs_1

010 dy_cs_2

011 dy_cs_3

100 st_cs_0

101 st_cs_1

110 st_cs_2

111 st_cs_3 (default)

D23:21 R/W CS7 0x3 Controls which system memory chip select is

routed to CS7

000 dy_cs_0

001 dy_cs_1

010 dy_cs_2

011 dy_cs_3 (default)

100 st_cs_0

101 st_cs_1

110 st_cs_2

111 st_cs_3

D24 R/W DHPUDIS 0x0 High data bus pullup control

0 Enable pullup resistors on data[31:16]

1 Disable pullup resistors on data[31:16]

Note: Bits 15:00 are output and controlled

through GPIO

78 Hardware Reference NS9215

I/O CONTROL MODULE

Memory Bus Configuration register

Bit(s) Access Mnemonic Reset Description

D25 R/W APUDIS 0x0 Address bus pullup control

(Applicable only to address associated with hardware strapping)

0 Enable pullup resistors

1 Disable pullup resistors

Note: Bits 27:24 are output and controlled

through GPIO

D31:26 N/A Reserved N/A N/A

. . . . .

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I/O CONTROL MODULE

Memory Bus Configuration register

80 Hardware Reference NS9215

Working with the CPU

CHAPTER 3

This processor core is based on the ARM926EJ-S processor. The ARM926EJ-S

processor belongs to the ARM9 family of general-purpose microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications in which full memory management, high performance, low die size, and low power are important.

About the processor

The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instructions sets, allowing you to trade off between high performance and high code density. The processor includes features for efficient execution of Java byte codes, providing Java performance similar to JIT but without the associated overhead.

The ARM926EJ-S supports the ARM debug architecture, and includes logic to assist in both hardware and software debug. The processor has a Harvard-cached architecture and provides a complete high-performance processor subsystem, including:

 ARM926EJ-S integer core  Memory Management Unit (MMU) (see "MemoryManagement Unit (MMU),"

beginning on page 105, for information)

 Separate instruction and data AMBA AHB bus interfaces

WORKING WITH THE CPU

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DEXT

Write buffer

DCACHE

Cache

TAGRAM

writeback

write buffer

MMU

TLB

ARM926EJ-S

IROUTE

DROUTE

FCSE

WDATA RDATA

INSTR

ICACHE

IEXT

Bus

interface

unit

Data AHB

interface

Instruction

AHB

interface

AHB

DMVA

IMVA

Instruction sets

Arm926EJ-S process block diagram

This drawing shows the main blocks in the ARM926EJ-S processor.

Instruction sets

The processor executes three instruction sets:

 32-bit ARM instruction set  16-bit Thumb instruction set  8-bit Java instruction set

ARM instruction set

Thumb instruction set

82 Hardware Reference NS9215

The ARM instruction set allows a program to achieve maximum performance with the minimum number of instructions. The majority of instructions are executed in a single cycle.

The Thumb instruction set is simpler than the ARM instruction set, and offers increased code density for code that does not require maximum performance. Code can switch between ARM and Thumb instruction sets on any procedure call.

WORKING WITH THE CPU

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System control processor (CP15) registers

. . . . .

Java instruction set

In Java state, the processor core executes a majority of Java bytecodes naturally. Bytecodes are decoded in two states, compared to a single decode stage when in ARM/Thumb mode. See “Jazelle(Java)” on page 104 for more information about Java.

System control processor (CP15) registers

The system control processor (CP15) registers configure and control most of the options in the ARM926EJ-S processor. Access the CP15 registers using only the MRC and MCR instructions in a privileged mode; the instructions are provided in the explanation of each applicable register. Using other instructions, or MRC and MCR in unprivileged mode, results in an UNDEFINED instruction exception.

ARM926EJ-S system addresses

The ARM926EJ-S has three distinct types of addresses:

 In the ARM926EJ-S domain: Virtual address (VA)  In the Cache and MMU domain: Modified virtual address (MVA)  In the AMBA domain: Physical address (PA)

Address manipulation example

Accessing CP15 registers

This is an example of the address manipulation that occurs when the ARM926EJ-S core requests an instruction:

1 The ARM926EJ-S core issues the virtual address of the instruction. 2 The virtual address is translated using the FCSE PID (fast context switch

extension process ID) value to the modified virtual address. The instruction cache (ICache) and memory management unit (MMU) find the modified virtual address (see “R13:Process ID register” on page 102).

3 If the protection check carried out by the MMU on the modified virtual address

does not abort and the modified virtual address tag is in the ICache, the instruction data is returned to the ARM926EJ-S core.

If the protection check carried out by the MMU on the modified virtual address does not abort but the cache misses (the MVA tag is not in the cache), the MMU translates the modified virtual address to produce the physical address. This address is given to the AMBA bus interface to perform an external access.

Use only registers. Figure 1 shows the MRC and MCR instruction bit pattern.

MRC and MCR instructions, only i n privileged mode, to access CP15

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WORKING WITH THE CPU

Cond

1110 1111 1L

Opcode

CRn CRmRd

31 28 27 26 25 24 23 21 20 19 16 15 12 11 10 9 8 7 5 4 3 0

System control processor (CP15) registers

Figure 1: CP15 MRC and MCR bit pattern

The mnemonics for these instructions are:

MCR{cond} p15,opcode_1,Rd,CRn,CRm,opcode_2

MRC{cond} p15,opcode_1,Rd,CRn,CRm,opcode_2

If you try to read from a write-only register or write to a read-only register, you will

UNPREDICTABLE results. In all instructions that access CP15:

have

 The opcode_1 field SHOULD BE ZERO, except when the values specified are used

to select the operations you want. Using other values results in unpredictable behavior.

 The opcode_2 and CRm fields SHOULD BE ZERO, except when the values specified

are used to select the behavior you want. Using other values results in unpredictable behavior.

Te rm s an d abbreviations

This table lists the terms and abbreviations used in the CP15 registers and explanations.

Term Abbreviation Description

UNPREDICTABLE UNP For reads:

The data returned when reading from this location is unpredictable, and can have any value.

For writes:

Writing to this location causes unpredictable behavior, or an unpredictable change in device configuration.

UNDEFINED UND An instruction that accesses CP15 in the manner

indicated takes the exception.

SHOULD BE ZERO SBZ When writing to this field, all bits of the field

SHOULD BE ZERO.

SHOULD BE ONE SBO When writing to this location, all bits in this field

SHOULD BE ONE.

SHOULD BE ZERO or PRESERVED

SBZP When writing to this location, all bits of this field

SHOULD BE ZERO or PRESERVED by writing the

same value that has been read previously from the same field.

UNDEFINED instruction

84 Hardware Reference NS9215

WORKING WITH THE CPU

System control processor (CP15) registers

. . . . .

Note:

In all cases, reading from or writing any data values to any CP15 registers, including those fields specified as

BE ZERO,

does not cause any physical damage to the chip.

 Register locatio ns 0, 5, and 13 each provide access to more than one register.

The register accessed depends on the value of the

MRC/MCR instructions (see “Accessing CP15 registers” on page 83).

 Register location 9 provides access to more than one register. The register

accessed depends on the value of the on page 83).

0 ID code (based on

0 Cache type (based on opcode_2 value) Unpredictable

1 Control Control

2 Translation table base Translation table base

3 Domain access control Domain access control

UNPREDICTABLE, SHOULD BE ONE, or SHOULD

opcode_2 field in the CP15

CRm field (see “Accessing CP15 registers”

opcode_2 value) Unpredictable

4 Reserved Reserved

5 Data fault status (based on opcode_2 value) Data fault status (based on opcode_2 value)

6 Instruction fault status (based on opcode_2

value)

7 Cache operations Cache operations

8 Unpredictable TLB

9 Cache lockdown (based on

10 TLB lockdown TLB lockdown

11 and 12 Reserved Reserved

13 FCSE PID (based on

FCSE = Fast context switch extension

PID = Process identifier

13 Context ID (based on

14 Reserved Reserved

15 Test configuration Test configuration

CRm value) Cache lockdown

opcode_2 value)

opcode_2 value) Context ID (based on opcode_2 value)

Instruction fault status (based on opcode_2 value)

FCSE PID (based on opcode_2 value)

FCSE = Fast context switch extension

PID = Process identifier

All CP15 register bits that are defined and contain state are set to 0 by reset, with these exceptions:

 The V bit is set to 0 at reset if the VINITHI signal is low, and set to 1 if the

VINITHI signal is high.

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WORKING WITH THE CPU

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R0: ID code and cache type status registers

 The B bit is set to 0 at reset if the BIGENDINIT signal is low, and set to 1 if the

BIGENDINIT signal is high.

R0: ID code and cache type status registers

Register R0 access the ID register, and cache type register. Reading from R0 returns the device ID, and the cache type, depending on the

opcode_2=0 ID value

opcode_2=1 instruction and data cache type

The

CRm field SHOULD BE ZERO when reading from these registers. This table shows

the instructions you can use to read register R0.

Function Instruction

opcode_2 value:

Read ID code

Read cache type

Writing to register R0 is

MRC p15,0,Rd,c0,c0,{0, 3-7}

MRC p15,0,Rd,c0,c0,1

UNPREDICTABLE.

R0: ID code R0: ID code is a read-only register that returns the 32-bit device ID code. You can

access the ID code register by reading CP15 register R0 with the opcode_2 field set to any value other than 1 or 2. Note this example:

MRC p15, 0, Rd, c0, c0, {0, 3-7}; returns ID

This is the contents of the ID code register.

Bits Function Value

[31:24] ASCII code of implementer trademark 0x41

[23:20] Specification revision 0x0

[19:16] Architecture (ARMv5TEJ) 0x6

[15:4] Part number 0x926

[3:0] Layout revision 0x0

R0: Cache type regist e r

R0: Cache type is a read-only register that contains information about the size and architecture of the instruction cache (ICache) and data cache (DCache) enabling operating systems to establish how to perform operations such as cache cleaning and lockdown. See “Cache features” on page 127 for more information about cache.

86 Hardware Reference NS9215

Cache type

Ctype

Dsize

31 28 25 24 23 12

Isize

11 10 9 6 5 3 2 1 0

00 Size MAssoc Len

WORKING WITH THE CPU

R0: ID code and cache type status registers

. . . . .

You can access the cache type register by reading CP15 register R0 with the opcode_2 field set to 1. Note this example:

MRC p15, 0, Rd, c0, c0, 1; returns cache details

Field Description

Ctype Determines the cache type, and specifies whether the cache supports lockdown and how it is

cleaned. Ctype encoding is shown below; all unused values are reserved.

Value: 0b1110

Method: Writeback

Cache cleaning: Register 7 operations (see “R7:Cache Operations register” on page 94)

Cache lockdown: Format C (see “R9: Cache Lockdown register” on page 98)

Dsize and Isize fields

S bit Specifies whether the cache is a unified cache (S=0) or separate ICache and DCache (S=1).

Will always report separate ICache and DCache for this processor.

Dsize Specifies the size, line length, and associativity of the DCache.

Isize Species the size, length and associativity of the ICache.

The Dsize and Isize fields in the cache type register have the same format, as shown:

The field contains these bits:

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R1: Control register

Field Description

Size Determines the cache size in conjunction with the M bit.

 The M bit is 0 for DCache and ICache.

 The size field is bits [21:18] for the DCache and bits [9:6] for the ICache.

 The minimum size of each cache is 4 KB; the maximum size is 128 KB.

 Cache size encoding with M=0:

Size field Cache size

0b0011 4 KB 0b0100 8 KB

Note: The processor always reports 4KB for DCache and 8KB for ICache.

Assoc Determines the cache associativity in conjunction with the M bit.

 The M bit is 0 for both DCache and ICache.

 The assoc field is bits [17:15 for the DCache and bits [5:3] for the ICache.

 Cache associativity with encoding:

Assoc field Associativity

0b010 4-way

Other values Reserved

M bit Multiplier bit. Determines the cache size and cache associativity values in conjunction with

Len Determines the line length of the cache.

R1: Control register

Register R1 is the control register for the ARM926EJ-S processor. This register specifies the configuration used to enable and disable the caches and MMU (memory management unit). It is recommended that you access this register using a readmodify-write sequence.

For both reading and writing, the CRm and opcode_2 fields SHOULD BE ZERO. Use these instructions to read and write this register:

MRC p15, 0, Rd, c1, c0, 0; read control register

MCR p15, Rd, c1, c0, 0; write control register

All defined control bits are set to zero on reset except the V bit and B bit.

the size and assoc fields.

Note: This field must be set to 0 for the ARM926EJ-S processor.

 The len field is bits [13:12] for the DCache and bits [1:0] for the ICache.

 Line length encoding:

Len field Cache line length

10 8 words (32 bytes) Other values Reserved

 The V bit is set to zero at reset if the VINITHI signal is low.  The B bit is set to zero at reset if the BIGENDINIT signal is low, and set to one if

BIGENDINIT signal is high.

the

88 Hardware Reference NS9215

Control register

131 19 16 15 12 11 10 9 8 7 3 0218 17 14 13 6

S B Z

SBZ

S B O

L4R

SBZ

RSB

SBO

CAM

Bit functionality

WORKING WITH THE CPU

R1: Control register

. . . . .

Bits Name Function

[31:19] N/A Reserved:

 When read, returns an UNPREDICTABLE value.

 When written, SHOULD BE ZERO, or a value read from bits

[31:19] on the same processor.

 Use a read-modify-write sequence when modifying this

[18] N/A Reserved, SBO. Read = 1, write =1.

[17] N/A Reserved, SBZ. read = 0, write = 0.

[16] N/A Reserved, SBO. Read = 1, write = 1.

[15] L4 Determines whether the T is set when load instructions change

the PC.

0 Loads to PC set the T bit

1 Loads to PC do not set the T bit

[14] RR bit Replacement strategy for ICache and DCache

0 Random replacement

1 Round-robin replacement

[13] V bit Location of exception vectors

0 Normal exception vectors selected; address range=

to 0x0000 001C

0000

0x0000

1 High exception vectors selected; address range=0xFFFF

to 0xFFFF 001C

0000

Set to the value of VINITHI on reset.

[12] I bit ICache enable/disable

0 ICache disabled

1 ICache enabled

[11:10] N/A

SHOULD BE ZERO

[9] R bit ROM protection

Modifies the ROM protection system.

[8] S bit System protection

Modifies the MMU protection system. See "MemoryManagement Unit (MMU)," beginning on page 105.

[7] B bit Endianness

0 Little endian operation

1 Big endian operation

Set to the value of

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BIGENDINIT on reset.

WORKING WITH THE CPU

R1: Control register

Bits Name Function

[6:3] N/A Reserved. SHOULD BE ONE.

[2] C bit DCache enable/disable

0 Cache disabled

1 Cache enabled

[1] A bit Alignment fault enable/disable

0 Data address alignment fault checking disabled

1 Data address alignment fault checking enabled

[0] M bit MMU enable/disable

0Disabled

1 Enabled

ICache and DCache behavior

The M, C, I, and RR bits directly affect ICache and DCache behavior, as shown:

Cache MMU Behavior

ICache disabled Enabled or disabled All instruction fetches are from external memory (AHB).

ICache enabled Disabled All instruction fetches are cachable, with no protection

checking. All addresses are flat-mapped; that is: VA=MVA=PA.

ICache enabled Enabled Instruction fetches are cachable or noncachable, and

protection checks are performed. All addresses are remapped from VA to PA, depending on the MMU page table entry; that is, VA translated to MVA, MVA remapped to PA.

DCache disabled Enabled or disabled All data accesses are to external memory (AHB).

DCache enabled Disabled All data accesses are noncachable nonbufferable. All

addresses are flat-mapped; that is, VA=MVA=PA.

DCache enabled Enabled All data accesses are cachable or noncachable, and

protection checks are performed. All addresses are remapped from VA to PA, depending on the MMU page table entry; that is, VA translated to MVA, MVA remapped to PA.

If either the DCache or ICache is disabled, the contents of that cache are not accessed. If the cache subsequently is re-enabled, the contents will not have changed. To guarantee that memory coherency is maintained, the DCache must be cleaned of dirty data before it is disabled.

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R2: Translation Table Base register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31 014 13

Translation table base

UNP/SBZ

31 014 13 12 11 10 9 8 7 6 5 4 3 2 115161718192021222324252627282930

D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15

 Reading from R2 returns the pointer to the currently active first-level

translation table in bits [31:14] and an

 Writing to R2 updates the pointer to the first-level translation table from the

value in bits[31:14] of the written value. Bits [13:0]

Use these instructions to access the Translation Table Base register:

MRC p15, 0, Rd, c2, c0, 0; read TTBR

MCR p15, 0, Rd, c2, c0, 0; write TTBR

The CRm and opcode_2 fields SHOULD BE ZERO when writing to R2.

WORKING WITH THE CPU

R2: Translation Table Base register

. . . . .

UNPREDICTABLE value in bits [13:0].

SHOULD BE ZERO.

R3:Domain Access Control register

 Reading from R3 returns the value of the Domain Access Control register.  Writing to R3 writes the value of the Domain Access Control register.

Access permissions and instructions

Each two-bit field defines the access permissions for one of the 16 domains (D15–D0):

00 No access: Any access generates a domain fault

01 Client: Accesses are checked against the access permission bits in the section or page descriptor

10 Reserved: Currently behaves like no access mode (00)

11 Manager: Accesses are not checked against the access permission bits, so a permission fault

cannot be generated.

Use these instructions to access the Domain Access Control register:

MRC p15, 0, Rd, c3, c0, 0; read domain access permissions

MCR p15, 0, Rd, c3, c0, 0; write domain access permissions

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WORKING WITH THE CPU

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31 0987 43

UNP/SBZ Domain Status

R4 register

Accessing (reading or writing) this register causes UNPREDICTABLE behavior.

R5: Fault Status registers

Register R5 accesses the Fault Status registers (FSRs). The Fault Status registers contain the source of the last instruction or data fault. The instruction-side FSR is intended for debug purposes only.

The FSR is updated for alignment faults and for external aborts that occur while the MMU is disabled. The FSR accessed is determined by the opcode_2 value:

opcode_2=0 Data Fault Status register (DFSR)

opcode_2=1 Instruction Fault Status register (IFSR)

Access instructions

See "MemoryManagement Unit (MMU)," beginning on page 105, for the fault type encoding.

Access the FSRs using these instructions:

MRC p15, 0, Rd, c5, c0, 0; read DFSR

MCR p15, 0, Rd, c5, c0, 0; write DFSR

MRC p15, 0, Rd, c5, c0, 1; read IFSR

MCR p15, 0, Rd, c5, c0, 1; write IFSR

Bits Description

[31:9]

[8] Always reads as zero. Writes are ignored.

[7:4] Specifies which of the 16 domains (D15–D0) was being accessed when a data fault

UNPREDICTABLE/SHOULD BE ZERO

occurred.

[3:0] Type of fault generated. (See "MemoryManagement Unit (MMU)," beginning on page

105.)

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R6: Fault Address register

. . . . .

Status and domain fields

This table shows the encodings u sed for the status field in the Fault Status register, and indicates whether the domain field contains valid information. Se e “MMU faults and CPU aborts” on page 119 for information about MMU aborts in Fault Address and Fault Status registers.

Priority Source Size Status Domain

Highest Alignment N/A

External abort on translation First level

Second level

Translation Section page

Domain Section page

Permission Section page

Lowest External abort Section page

0b00x1

0b1100

0b1110

0b0101

0b0111

0b1001

0b1011

0b1101

0b1111

0b1000

0b1010

Invalid

Valid

Invalid

Valid

R6: Fault Address register

Register R6 accesses the Fault Address register (FAR). The Fault Address register contains the modified virtual address of the access attempted when a data abort occurred. This register is updated only for data aborts, not for prefetch aborts; it is updated also for alignment faults and external aborts that occur while the MMU is disabled.

Writing R6 sets the Fault Address register to the value of the data written. This is useful for debugging, to restore the value of a Fault Address register to a previous state.

CRm and opcode_2 fields SHOULD BE ZERO when reading or writing R6.

The

Access instructions

Use these instructions to access the Fault Address register:

MRC p15, 0, Rd, c6, c0, 0; read FAR

MCR p15, 0, Rd, c6, c0, 0; write FAR

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R7:Cache Operations register

Register R7 controls the caches and write buffer. The function of each cache operation is selected by the writes to CP15 R7. Writing other

Reading from R7 is UNPREDICTABLE, with the exception of the two test and clean operations (see “Cache operation functions” on page 95 and “Test and clean DCache instructions” on page 96).

Write instruction Use this instruction to write to the Cache Operations register:

MCR p15, opcode_1, Rd, CRn, CRm, opcode_2

Cache functions This table describes the cache functions provided by register R7.

Function Description

Invalidate cache Invalidates all cache data, including any dirty data.

opcode_2 and CRm fields in the MCR instruction that

opcode_2 or CRm values is UNPREDICTABLE.

Invalidate single entry using either index or modified virtual address

Clean single data entry using either index or modified virtual address

Clean and invalidate single data entry using wither index or modified virtual address.

Test and clean DCache Tests a number of cache lines, and cleans one of them if

Test, clean, and invalidate DCache Tests a number of cache lines, and cleans one of them if

Prefetch ICache line Performs an ICache lookup of the specified modified

Invalidates a single cache line, discarding any dirty data.

Writes the specified DCache line to main memory if the line is marked valid and dirty. The line is marked as not dirty, and the valid bit is unchanged.

Writes the specified DCache line to main memory if the line is marked valid and dirty. The line is marked not valid.

any are dirty. Returns the overall dirty state of the cache in bit 30. (See “Test and clean DCache instructions” on page 96).

any are dirty. When the entire cache has been tested and cleaned, it is invalidated. (See “Test and clean DCache instructions” on page 96).

virtual address. If the cache misses and the region is cachable, a linefill is performed.

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R7:Cache Operations register

Function Description

Drain write buffer Acts as an explicit memory barrier. This instruction drains

the contents of the write buffers of all memory stores occurring in program order before the instruction is completed. No instructions occurring in program order after this instruction are executed until the instruction completes.

Use this instruction when timing of specific stores to the level two memory system has to be controlled (for example, when a store to an interrupt acknowledge location has to complete before interrupts are enabled).

Wait for interrupt Drains the contents of the write buffers, puts the processor

into low-power state, and stops the processor from executing further instructions until an interrupt (or debug request) occurs. When an interrupt does occur, the

MCR

instruction completes, and the IRQ or FIRQ handler is entered as normal.

The return link in of the

MCR instruction plus eight, so the typical instruction

used for interrupt return instruction following the

R14_irq or R14_fiq contains the address

(SUBS PC,R14,#4) returns to the

MCR.

. . . . .

Cache operation functions

This table lists the cache operation functions and associated data and instruction formats for R7.

Function/operation Data format Instruction

Invalidate ICache and DCache SBZ

Invalidate ICache SBZ

Invalidate ICache single entry (MVA) MVA

Invalidate ICache single entry (set/way) Set/Way

Prefetch ICache line (MVA) MVA

Invalidate DCache SBZ

Invalidate DCache single entry (MVA) MVA

Invalidate DCache single entry (set/way) Set/Way

Clean DCache single entry (MVA) MVA

Clean DCache single entry (set/way) Set/Way

Test and clean DCache N/A

Clean and invalidate DCache entry (MVA) MVA

Clean and invalidate DCache entry (set/way) Set/Way

MCR p15, 0, Rd, c7, c7, 0

MCR p15, 0, Rd, c7, c5, 0

MCR p15, 0, Rd, c7, c5, 1

MCR p15, 0, Rd, c7, c5, 2

MCR p15, 0, Rd, c7, c13, 1

MCR p15, 0, Rd, c7, c6, 0

MCR p15, 0, Rd, c7, c6, 1

MCR p15, 0, Rd, c7, c6, 2

MCR p15, 0, Rd, c7, c10, 1

MCR p15, 0, Rd, c7, C10, 2

MRC p15, 0, Rd, c7, c10, 3

MCR p15, 0, Rd, c7, c14, 1

MCR p15, 0, Rd, c7, c14, 2

Test, clean, and invalidate DCache N/A

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MRC p15, 0, Rd, c7, c14, 3

WORKING WITH THE CPU

31 0S+4 4

SBZSet(=index) Word

Tag

215S+5

31 0S+4 4

SBZSet(=index) Word

SBZ

215S+5

Way

32-A 31-A

R7:Cache Operations register

Function/operation Data format Instruction

Drain write buffer SBZ

Wait for interrupt SBZ

Modified virtual

This is the modified virtual address format for

address format (MVA)

 The tag, set, and word fields define the MVA.  For all cache operations, the word field SHOULD BE ZERO.

Set/Way format This is the Set/Way format for

 A and S are the base-two logarithms of the associativity and the number of

sets.

MCR p15, 0, Rd, c7, c10, 4

MCR p15, 0, Rd, c7, c0, 4

Rd for the CP15 R7 MCR operations.

 The set, way, and word files define the format.  For all of the cache operations, word SHOULD BE ZERO.

Set/Way example For example, a 16 KB cache, 4-way set associative, 8-word line results in the

following:

 A = log  S = log

associativity = log24 = 2

NSETS where

NSETS = cache size in bytes/associativity/line length in bytes: NSETS = 16384/4/32 = 128

Te st and cl ean DCache instructions

Result: S = log

The test and clean DCache instruction provides an efficient way to clean the entire DCache, using a simple loop. The test and clean DCache instruction tests a number of lines in the DCache to determine whether any of them are dirty. If any dirty lines

128 = 7

are found, one of those lines is cleaned. The test and clean DCache instructi on also returns the status of the entire DCache in bit 30.

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R8:TLB Operations register

. . . . .

Note:

The test and clean DCache instruction MRC p15, 0, r15, c7, c10, 3 is a special encoding that uses using this instruction, however. This code flags.

If the cache contains any dirty lines, bit 30 is set to 0. If the cache contains no dirty lines, bit 30 is set to 1. Use the following loop to clean the entire cache:

tc_loop: MRC p15, 0, r15, c7, c10, 3; test and clean

Test, clean, and invalidate DCache instruction

The test, clean, and invalidate DCache instruction is the same as the test and clean DCache instruction except that when the entire cache has been cleaned, it is invalidated. Use the following loop to test, clean, and invalidate the entire DCache:

tci_loop: MRC p15, 0, r15, c7, c14, 3; test clean and invalidate

R8:TLB Operations register

Register R8 is a write-only register that controls the translation lookaside buffer (TLB). There is a single TLB used to hold entries for both data and instructions. The TLB is divided into two parts:

r15 as a destination operand. The PC is not changed by

MRC instruction also sets the condition

BNE tc_loop

BNE tci_loop

 Set-associative  Fully-associative

The fully-associative part (also referred to as the lockdown part of the TLB) stores entries to be locked down. Entries held in the lockdown part of the register are preserved during an invalidate-TLB operation. Entries can be removed from the lockdown TLB using an invalidate TLB single entry operation.

TLB operations There are six TLB operations; the function to be performed is selected by the

opcode_2 and CRm fields in the MCR instruction used to write register R8. Writing

opcode_2 or CRm values is UNPREDICTABLE. Reading from this register is

other

UNPREDICTABLE.

TLB operation

Use these instruction to perform TLB operations.

instructions

Operation Data Instruction

Invalidate set-associative TLB SBZ

Invalidate single entry SBZ

Invalidate set-associative TLB SBZ

MCR p15, 0, Rd, c8, c7, 0

MCR p15, 0, Rd, c8, c7. 1

MCR p15, 0, Rd, c8, c5, 0

Invalidate single entry MVA

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MCR p15, 0, Rd, c8, c5, 1

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31 09

SBZ

Modified virtual address

R9: Cache Lockdown register

Operation Data Instruction

Modified virtual address format (MVA)

Invalidate set-associative TLB SBZ

Invalidate single entry MVA

 The invalidate TLB operations invalidate all the unpreserved entries in the

MCR p15, 0, Rd, c8, c6, 0

MCR p15, 0, Rd, c8, c6, 1

TLB.

 The invalidate TLB single entry operations invalidate any TLB entry

corresponding to the modified virtual address given in

Rd, regardless of its

preserved state. See "R10:TLB Lockdown register," beginning on page 101, for an explanation of how to preserve TLB entries.

This is the modified virtual address format used for invalid TLB single entry operations.

Note:

If either small or large pages are used, and these pages contain subpage access permissions that are different, you must use four invalidate TLB single entry operations, with the MVA set to each subpage, to invalidate all information related to that page held in a TLB.

R9: Cache Lockdown register

Cache ways The Cache Lockdown register uses a cache-way-based locking scheme (format C)

that allows you to control each cache way independently. These registers allow you to control which cache-ways of the four-way cache are

used for the allocation on a linefill. When the registers are defined, subsequent linefills are placed only in the specified target cache way. This gives you some control over the cache pollution cause by particular applications, and provides a traditional lockdown operation for locking critical code into the cache.

A locking bit for each cache way determines whether the normal cache allocation is allowed to access that cache way (see “Cache Lockdown register L bits” on page 99). A maximum of three cache ways of the four-way associative cache can be locked, ensuring that normal cache line replacement is performed.

Note:

98 Hardware Reference NS9215

If no cache ways have the L bit set to 0, cache way 3 is used for all linefills.

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31 03

SBZ/UNP

15 416

SB0

L bits

(cache ways

0 to 3)

R9: Cache Lockdown register

. . . . .

Instruction or data lockdown regi s t e r

Access instructions

Modifying the Cache Lockdown regi s t e r

The first four bits of this register determine the L bit for the associated cache way. The opcode_2 field of the MRC or MCR instruction determines whether the instruction or data lockdown register is accessed:

opcode_2=0 Selects the DCache Lockdown register, or the Unified

Cache Lockdown register if a unified cache is implemented. The ARM926EJ-S processor has separate DCache and ICache.

opcode_2=1 Selects the ICache Lockdown register.

Use these instructions to access the CacheLockdown register.

Function Data Instruction

Read DCache Lockdown register L bits

Write DCache Lockdown register L bits

Read ICache Lockdown register L bits

Write ICache Lockdown register L bits

MRC p15, 0, Rd, c9, c0, 0

MCR p15, 0, Rd, c9, c0, 0

MRC p15, 0, Rd, c9, c0, 1

MCR p15, 0, Rd, c9, c0, 1

You must modify the Cache Lockdown register using a modify-read-write sequence; for example:

MRC p15, 0, Rn, c9, c0, 1;

ORR Rn, Rn, 0x01;

MCR p15, 0, Rn, c9, c0, 1;

This sequence sets the L bit to 1 for way 0 of the ICache.

Cache Lockdown register L bits

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This table shows the format of the Cache Lockdown register L bits. All cache ways are available for allocation from reset.

Bits 4-way associative Notes

[31:16] UNP/SBZ Reserved

[15:4] 0xFFF SBO

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R9: Cache Lockdown register

Bits 4-way associative Notes

[3] L bit for way 3 Bits [3:0] are the L bits for each cache way:

[2] L bit for way 2

[1] L bit for way 1

[0] L bit for way 0

0 Allocation to the cache way is determined by the standard

replacement algorithm (reset state)

1 No allocation is performed to this way

Lockdown cache: Specific loading of addresses into a cache-way

Use this procedure to lockdown cache. The procedure to lock down code and data into way i of cache, with N ways, using format C, makes it impossible to allocate to any cache way other than the target cache way:

1 Ensure that no processor exceptions can occur during the execution of this

procedure; for example, disable interrupts. If this is not possible, all code and data used by any exception handlers must be treated as code and data as in Steps 2 and 3.

2 If an ICache way is being locked down, be sure that all the code executed by

the lockdown procedure is in an uncachable area of memory or in an already locked cache way.

3 If a DCache way is being locked down, be sure that all data used by the

lockdown procedure is in an uncachable area of memory or is in an already locked cache way.

4 Ensure that the data/instructions that are to be locked down are in a cachable

area of memory.

5 Be sure that the data/instructions that are to be locked down are not already in

the cache. Use the Cache Operations register (R7) clean and/or invalidate functions to ensure this.

6 Write these settings to the Cache Lockdown register (R9), to enable allocation

to the target cache way:

CRm = 0

Set L == 0 for bit i

Set L == 1 for all other bits

7 For each of the cache lines to be locked down in cache way i:

–

– If an ICache is being locked down, use the Cache Operations register (R7) MCR

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If a DCache is being locked down, use an LDR instruction to load a word from the memory cache line to ensure that the memory cache line is loaded into the cache.

prefetch ICache line

(<CRm>==c13, <opcode2>==1) to fetch the memory cache line

into the cache.

Digi NS9215 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Pinout (265)

Memory bus interface

Ethernet interface MAC

General purpose I/O (GPIO)

System clock

System mode

System reset

JTAG Test

POR and battery-backed logic

Power and ground

I/O Control Module

Control and Status registers

GPIO Configuration registers

GPIO Control re gisters

GPIO Status registers

Memory Bus Configuration register

Working with the CPU

Instruction sets

System control processor (CP15) registers

R0: ID code and cache type status registers

R1: Control register

R2: Translation Table Base register

R3:Domain Access Control register

R4 register

R5: Fault Status registers

R6: Fault Address register

R7:Cache Operations register

R8:TLB Operations register

R9: Cache Lockdown register