Digi NS7520 User Manual

NS7520 Hardware Reference

90000353_D

NS7520 Hardware Reference

Part number/version: 90000353_D
Release date: March 2006
www.digi.com

©2001-2006 Digi International Inc.
Printed in the United States of America. All rights reserved.

Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi
International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi
International, Inc. in the United States and other countries worldwide. All other trademarks are the
property of their respective owners.

Information in this document is subject to change without notice and does not represent a committment
on the part of Digi International.

Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including,
but not limited to, the implied warranties of, fitness or merchantability for a particular purpose. Digi may
make improvements and/or changes in this manual or in the product(s) and/or the program(s) described
in this manual at any time.

This product could include technical inaccuracies or typographical errors. Changes are made periodically
to the information herein; these changes may be incorporated in new editions of the publication.

Digi International
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Minnetonka, MN 55343 U.S.A.
United States: [phone]
Other locations: [phone]

www.digi.com/support/
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Contents

Chapter 1: About the NS7520..................................................1

NS7520 Features ......................................................................... 2

Key features and operating modes of the major NS7520 modules........ 2

NS7520 module block diagram......................................................... 5

Operating frequency .................................................................... 6

Chapter 2:

Packaging ................................................................................. 8

Pinout detail tables and signal descriptions........................................11

Chapter 3:

ARM Thumb concept ...................................................................30

CPU performance.......................................................................30

Working with ARM exceptions ........................................................31

Pinout and Packaging ............................................7

System bus interface............................................................12

Chip select controller........................................................... 16

Ethernet interface MAC................................ ........ ....... ....... ... 18

“No connect” pins ...............................................................21

General-purpose I/O ............................................................21

System clock and reset .........................................................24

System mode (test support)....................................................25

JTAG test (ARM debugger) .....................................................26

Power supply .....................................................................28

Working with the CPU......................................... 29

Summary of ARM exceptions ...................................................32

Exception priorities.............................................................. 32

       iii

Exception vector table.......................................................... 33

Detail of ARM exceptions....................................................... 34

Entering and exiting an exception (software action) ......................37

Hardware Interrupts....................................................................39

FIRQ and IRQ lines............................................................... 39

Interrupt controller.............................................................. 39

Interrupt sources................................................................. 40

Chapter 4:

BBus Module ...........................................................43

BBus masters and slaves...............................................................44

Cycles and BBus arbitration...........................................................44

Address decoding .......................................................................45

Chapter 5:

SYS Module.............................................................47

Signal description....................................................................... 48

JTAG support............................................................................48

ARM debug...............................................................................49

System clock generation (NS7520 clock module) .................................. 49

External oscillator vs. internal PLL circuit...................................49

NS7520 clock module block diagram.......................................... 50

Using the external oscillator.......................................................... 50

External oscillator mode hardware configuration ..........................51

Using the PLL circuit ...................................................................52

PLL mode hardware configuration ............................................ 52

Setting the PLL frequency.............................................................54

PLL Settings register: Setting the PLL frequency on bootup..............54

PLL Control register: Setting the PLL frequency with the PLL Control

register............................................................................ 57

Reset circuit sources...................................................................59

NS7520 bootstrap initialization....................................................... 60

iv       

Chapter 6: GEN Module

.............................................................61

Module configuration................................................................... 62

GEN module hardware initialization.................................................62

GEN module registers ..................................................................63

System Control register.........................................................63

System Status register ..........................................................68

Software Service register.......................................................70

Timer Control registers .........................................................70

Timer Status registers...........................................................73

PORTA Configuration register.................................................. 74

PORTC Configuration register.................................................. 77

Interrupts ................................................................................ 80

Interrupt controller registers ..................................................81

Chapter 7:

Memory Controller Module................................. 85

About the MEM module ................................................................86

MEM module hardware initialization................................................. 86

Pin configuration.................................................................86

MEM module configuration ............................................................88

Setting the chip select address range ........................................88

Memory Module Configuration register.......................................90

Chip Select Base Address register.............................................93

Chip Select Option Register A ................................................. 97

Chip Select Option Register B.................................................101

Static memory (SRAM) controller ...................................................102

Single cycle read/write........................................................103

Burst cycles......................................................................104

NS7520 DRAM address multiplexing.................................................105

Using the internal multiplexer................................................105

Using the external multiplexer...............................................108

DRAM refresh...........................................................................109

FP/EDO DRAM controller .............................................................109

Single cycle read/write........................................................110

FP/EDO DRAM burst cycles ....................................................111

SDRAM ...................................................................................111

NS7520 SDRAM interconnect .................................. ....... ....... .. 1 12

SDRAM A10/AP support ........................................................116

Command definitions...........................................................117

Memory timing fields — SDRAM ...............................................118

BSIZE configuration.............................. ....... ........ ....... ....... .. 1 18

SDRAM Mode register..................... ....... ....... ........ ....... ....... .. 1 19

       v

SDRAM read cycles.............................................................. 1 20

SDRAM write cycles............................................... ....... .......122

Peripheral page burst size ...........................................................124

Chapter 8:

DMA Module.......................................................... 127

DMA module ............................................................................128

Fly-by operation transfers.....................................................128

Memory-to-memory operation................................................129

DMA buffer descriptor ................................................................130

DMA channel assignments ............................................................133

DMA channel registers ................................................................134

Address map.....................................................................134

Buffer Descriptor Pointer register ...........................................136

DMA Control register ........ ........ ....... ....... ........ ....... ....... ....... 1 36

DMA Status/Interrupt Enable register .......................................142

Ethernet transmitter considerations................................................144

Ethernet receiver considerations ...................................................145

External peripheral DMA support....................................................145

Signal description...............................................................146

External DMA configuration ...................................................146

Memory-to-memory mode.....................................................146

DMA controller reset ..................................................................147

Chapter 9:

Ethernet Module .................................................. 149

Ethernet front-end (EFE) .............................................................150

Transmit and receive FIFOs ...................................................151

EFE transmit processing .......................................................151

EFE receive processing.........................................................151

Receive buffer descriptor selection .........................................152

External CAM filtering ................................................................153

MAC module ............................................................................154

MAC module block diagram ...................................................154

DMA channel assignments ............................................................156

EFE configuration......................................................................156

Ethernet General Control register (EGCR) bit definitions ................158

Ethernet General Status register (EGSR) bit definitions..................164

vi       

Ethernet FIFO Data register...................................................167

Ethernet Transmit Status register............................................169

Ethernet Receive Status register.............................................174

MAC Configuration Register 1.................................................178

MAC Configuration Register 2.................................................180

Back-to-Back Inter-Packet-Gap register.....................................184

Non-Back-to-Back Inter-Packet-Gap register...............................185

Collision Window/Collision Retry register ..................................186

Maximum Frame register ......................................................187

PHY Support register...........................................................188

Test register.....................................................................189

MII Management Configuration register .....................................191

MII Management Command register..........................................193

MII Management Address register ............................................194

MII Management Write Data register ........................................195

MII Management Read Data register .........................................196

MII Management Indicators register..........................................197

SMII Status register .............................................................198

Station Address registers ......................................................198

Station Address Filter register................................................201

Register hash table.............................................................202

Chapter 10:

Serial Controller Module .................................209

Supported features....................................................................210

Bit-rate generator .....................................................................211

Serial protocols ........................................................................212

UART mode .............................................................................212

SPI mode ................................................................................213

FIFO management ................ ........ ....... ....... ........ ....... ....... .. 2 14

General-purpose I/O configurations ................................................222

Serial port performance..............................................................223

Configuration...........................................................................223

Serial Channel registers ..............................................................225

Serial Channel 1, 2 Control Register A ......................................225

Serial Channel 1, 2 Control Register B ......................................231

Serial Channel 1, 2 Status Register A........................................235

Serial Channel 1, 2 Bit-Rate registers .......................................244

       vii

Serial Channel 1, 2 FIFO registers............................................254

Serial Channel 1, 2 Receive Buffer Gap Timer .............................255

Serial Channel 1, 2 Receive Character Gap Timer.........................256

Serial Channel 1,2 Receive Match register..................................258

Serial Channel 1, 2 Receive Match MASK register..........................258

Chapter 11:

Electrical Characteristics............................... 261

DC characteristics .....................................................................262

Recommended operating conditions.........................................262

Input/Output characteristics .................................................263

Pad pullup and pulldown characteristics....................................263

Absolute maximum ratings ....................................................265

AC characteristics .....................................................................265

AC electrical specifications ...................................................265

Oscillator Characteristics...................................................... .......267

Timing Diagrams ................................... ....... ........ ....... ....... .......269

Timing_Specifications............... ...........................................269

Reset_timing ....................................................................270

SRAM timing .....................................................................271

SDRAM timing....................................................................281

FP DRAM timing .................................................................289

Ethernet timing .................................................................296

JTAG timing......................................................................298

External DMA timing............................................................300

Serial internal/external timing...............................................303

GPIO timing......................................................................305

viii       

Index

Using This Guide

Using This Guide

Review this section for basic information about the guide you are using, as

well as general support and contact information.

About this guide

This guide provides information about the NS7520 32-bit networked
microprocessor. The NS7520 is part of the NET+ARM line of SoC (System-on­Chip) products, and supports high-bandwidth applications for intelligent
networked devices.

The NET+ARM family is part of the NET+Works integrated product family, which
includes the NET+OS network software suite.

Who should read this guide

This guide is for hardware developers, system software developers, and
applications programmers who want to use the NS7520 for development.

To complete the tasks described in this guide, you must:

 Understand the basics of hardware and software design, operating

systems, and microprocessor design.

 Understand the NS7520 architecture.

       ix

What’s in this guide

This table shows where you can find specific information in this guide:

To read about See

NS7520 key features Chapter 1, "About the NS7520"
NS7520 ball grid array assignments & packaging Chapter 2, "Pinout and Packaging"
NS7520 CPU and ARM Thumb concept Chapter 3, "Working with the CPU"
BBus functionality Chapter 4, "BBus Module"
System functionality Chapter 5, "SYS Module"
General (GEN) module functionality Chapter 6, "GEN Module"
How the NS7520 can be configured to interface

with different types of memory devices
DMA controller, supported DMA channels, and

internal and external DMA transfers
Ethernet controller module Chapter 9, "Ethernet Module"
Serial channels A and B Chapter 10, "Serial Controller Module"
NS7520 timing information and diagrams Chapter 11, "Electrical Characteristics"

Conventions used in this guide

This table describes the typographic conventions used in this guide:

This convention Is used for

italic type Emphasis, new terms, variables, and document titles.

monospaced type

_ (underscore) Defines a signal as being active low.
‘b Indicates that the number following this indicator is in binary radix

Filenames, pathnames, and code examples.

Chapter 7, "Memory Controller Module"

Chapter 8, "DMA Module"

‘d Indicates that the number following this indicator is in decimal radix
‘h Indicates that the number following this indicator is in hexadecimal radix

x       

NS7520 Hardware Reference, Rev. D 03/2006

Related documentation

NS7520 Jumpers and Components provides a hardware description of the NET+Works
Development Board, and includes information about jumpers, connectors, switches,
and interface configurations, as well as development board diagrams.

Review the documentation CD-ROM that came with your development kit for
information on third-party products and other components.

See the NET+OS software documentation for information appropriate to the chi p you
are using.

Documentation updates

Digi occasionally provides documentation updates on the Web site
(www.digi.com/support).

Be aware that if you see differences between the documentation you received in your
package and the documentation on the Web site, the Web site content is the latest
version.

Customer support

To get help with a question or technical problem with this product, or to make
comments and recommendations about our products or documentation, use the
contact information listed in this table:

For Contact information

Technical support United States: [phone]

Other locations: [phone]
www.digi.com/support
www.digi.com

www.digi.com

       xi

About the NS7520

CHAPTER 1

This chapter provides an overview of the NS7520. The NS7520 is a high-

performance, highly integrated, 32-bit system-on-a-chip ASIC designed for use in
intelligent networked devices and Internet appliances. The NS7520 is based on the
standard architecture in the NET+ARM family of devices.

NET+ARM is the hardware foundation of the NET+Works family of integrated hardware
and software solutions for device networking. These comprehensive platforms
include drivers, popular operating systems, networking software, development tools,
APIs, and complete development boards.

       1

NS7520 Features

NS7520 Features

The NS7520 can support most any networking scenario, and includes a 10/100 BaseT
Ethernet MAC and two independent serial ports (each of which can run in UART or SPI
mode).

The CPU is an ARM7TDMI (ARM7) 32-bit RISC processor core with a rich complement of
support peripherals and memory controllers, including:

 Glueless connection to different types of memory; for example, flash,

SDRAM, EEPROM, and others.

 Programmable timers
 13-channel DMA controller
 External bus expansion module
 16 general-purpose I/O (GPIO) pins

Key features and operating modes of the major NS7520 modules

 CPU core

 13-channel DMA controller

2       

– ARM7 32-bit RISC processor
– 32-bit internal bus
– 32-bit ARM mode and 16-bit Thumb mode
– 15 general-purpose 32-bit registers
– 32-bit program counter (PC) and status register
– Five supervisor modes, one user mode

– Two channels dedicated to Ethernet transmit and receive
– Four channels dedicated to two serial modules’ transmit and receive
– Four channels for external peripherals (only two channels — either 3 and 5

or 4 and 6 — can be configured at one time)

– Three channels available for memory-to-memory transfers
– Flexible buffer management

NS7520 Hardware Reference, Rev. D 03/2006

About the NS7520

 General-purpose I/O pins

– 16 programmable GPIO interface pins
– Four pins programmable with level-sensitive interrupt

 Serial ports

– Two fully independent serial ports (UART, SPI)
– Digital phase lock loop (DPLL) for receive clock extractions
– 32-byte transmit/receive FIFOs
– Internal programmable bit-rate generators
– Bit rates 75–230400 in 16X mode
– Bit rates 1200 bps–4 Mbps in 1X mode
– Flexible baud rate generator, external clock for synchronous operation
– Receive-side character and buffer gap timers
– Four receive-side data match detectors

 Power and operating voltages

– 500 mW maximum at 55 MHz (all outputs switching)
– 418 mW maximum at 46 MHz (all outputs switching)
– 291 mW maximum at 36 MHz (all outputs switching)
– 3.3 V — I/O
– 1.5 V — Core

 Integrated 10/100 Ethernet MAC

– 10/100 Mbps MII-based PHY interface
– 10 Mbps ENDEC interface
– Support for TP-PMD and fiber-PMD devices
– Full-duplex and half-duplex modes
– Optional 4B/5B coding
– Station, broadcast, and multicast address detection filtering
– 512-byte transmit FIFO, 2 Kbyte receive FIFO
– Intelligent receive-side buffer size selection

www.digi.com

       3

NS7520 Features

 Programmable timers

– Two independent timers (2μs–20.7 hours)
– Watchdog timer (interrupt or reset on expiration)
– Programmable bus monitor or timer

 Operating frequency

– 36, 46, or 55 MHz internal clock operation from 18.432 MHz quartz crystal

or crystal oscillator

– f

= 36, 46, or 55 MHz (grade-dependent)

MAX

– System clock source by external quartz crystal or crystal oscillator, or clock

signal

– Programmable PLL, which allows a range of operating frequencies from 10

to f

MAX

– Maximum operating frequency from external clock or using PLL

multiplication f

 Bus interface

MAX

– Five independent programmable chip selects with 256 Mb addressing per

chip select

– All chip selects support SRAM, FP/EDO DRAM, SDRAM, flash, and EEPROM

without external glue

– Supports 8-, 16-, and 32-bit peripherals
– External address decoding and cycle termination
– Dynamic bus sizing
– Internal DRAM/SDRAM controller with address multiplexer and

programmable refresh frequency

– Internal refresh controller (CAS before RAS)

4       

– Burst-mode support
– 0–63 wait states per chip select
– Address pins that configure chip operating modes; see "NS7520 bootstrap

initialization" on page 60.

NS7520 Hardware Reference, Rev. D 03/2006

NS7520 module block diagram

Figure 1 is an overview of the NS7520, including all the modules.

About the NS7520

Debugger

Power

3.3V

1.5V

PLL

System
Clock

BBUS

D
M
A

Serial-A

UART
SPI

JTAG Debug

ARM7TDMI

D
M
A

Serial-B

UART
SPI

16 GPIO

Interface

4
level
interrupt
inputs

FIRQ

IRQ

NS7520

2 timers

D
M
A

Ethernet
controller

802.3
compliant

Reset

Watchdog
timer

D
M
A

External
memory
controller

Address bus

Serial transceivers and other
devices

Figure 1: NS7520 overview

MII

Boot
config

www.digi.com

Memory
devices

Flash
SRAM
FP DRAM
SDRAM

       5

Operating frequency

Operating frequency

The NS7520 is available in grades operating at three maximum operating frequencies:
36 MHz, 46 MHz, and 55 MHz. The operating frequency is set during bootstrap
initialization, using pins A[8:0]. These address pins load the PLL settings register on
powerup reset. A[8:7] determines IS (charge pump current); A[6:5] determines FS
(output divider), and A[4:0] defines ND (PLL multiplier). Each bit in A[8:0] can be set
individually.

See "Setting the PLL frequency," beginning on page 54, for more detailed
information.

6       

NS7520 Hardware Reference, Rev. D 03/2006

Pinout and Packaging

CHAPTER 2

The NS7520 can be used in any embedded environment requiring networking

services in an Ethernet LAN. The NS7520 contains an integrated ARM RISC processor,
10/100 Ethernet MAC, serial ports, memory controllers, and parallel I/O. The NS7520
can interface with another processor using a register or shared RAM interface. The
NS7520 provides all the tools required for any embedded networking application.

       7

Packaging

Packaging

Table 1 provides the NS7520 packaging dimensions. Figure 2 shows the pinout and
NS7520 dimensions. Figure 3 shows the NS7520 BGA layout.

Symbol Min Nom Max

A——1.4
A1 0.35 0.40 0.45
A2——0.95
b 0.45 0.50 0.55
D 13.0 BSC
D1 11.2 BSC
E 13.0 BSC
E1 11.2 BSC
e 0.8 BSC
aaa 0.1

Table 1: NS7520 packaging dimensions

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NS7520 Hardware Reference, Rev. D 03/2006

177 PFBGA

Pinout and Packaging

Figure 2: NS7520 pinout and dimensions

www.digi.com

       9

Packaging

R

P1

R1

A0

A3

R2

P2

A6

GNDPY1

R3

P3 B3

VCCPY2

A7

R4

P4

GNDPY2

A8

P5

R5

VCCPY3

VDDC01

GNDPY11

RESV2+

XTALB2

A10

R6

A13

A15

R7

A17

GNDPY3

R8

A19

R9

VSSC01

A22

R10

P10

A26/0WE_ A27/0OE_

A24

P11

R11

NC2

R12

NC4

RESV1-

P13

R13

NC6

R14

P14

NC5

VSSOSC1

P15

R15

TCK

P6

P7

P8

P9

P

N

N1

D31

N2
A1

N3

VCCPY1

N4
A4

N5

A9

N6

A12

N7

A16

N8

A20

N9

A23

N10

N11
NC3

N12

XTALB1

N13

OSCVCC1

N14

TDI

N15 L15

PLLTST_

M

M1

D30

M2

VCCPY4

M3
A2

M4
A5

M5

A11

M6

A14

M7

A18

M8

GNDPY4

M9

A21

M10
A25

M11
NC1

M12
TMS

M13

TDO

M14

TRST_

M15

BISTEN_

L

L1

L2

D28

L3

D29

L4

D27

L12

PLLVSS

L13

SCANEN_

L14

VDDC02

PLLVDD

E

K

K1

D23

D20

K2 D2

D24

D22

K3

D21

D25

K4

VCCPY5

GNDPY5

H

J

H1

J1

D14

D17

H2 C2

J2

D16

D12

H3

J3

D19

D13

H4

J4

D15

D18

F

G

G1

GNDPY13

G2

D10

G3

G4

D9

D11

F1

F2

F3

F4

E1
D8

E2
D7

E3
D6

E4

VCCPY8

E5

GUIDE PIN

NS7520, 177 PFBGA

Top View, Balls Facing Down

V1.0

K12

XTAL2

K13

VSSC02

K14

XTAL1

K15

GNDPY12

J12

PORTA4

J13

PORTA6

PORTA7

J15

PORTA5

H12

H13

PORTA1

H14

VCCPY6

H15

PORTA3

G12

PORTA0

G13

PORTC7

G14

PORTC6

G15

GNDPY6

PORTC4

PORTC3

VCCPY7

PORTC5

F12

F13

F14

F15

E12

PORTC1

E13

GNDPY7

E14

PORTC0

E15

PORTC2

C

D

D1

D5

GNDPY8

D3 A3

OSCVCC2

D1

D4
D2

CAS2_

D5

CS2_

CS0_

D6

RW_

WE_

D7

BR_

BG_

D8

TEA_

TA_

D9

BE1_

BE3_

D10

C10

MDC

TXCLK

D11

C11

GNDPY14

TXD1

C12

D12

RXCRS

RXCLKPORTA2

D13

C13

VDDC04

VSSC04

C14

D14

VDDC03

RXD3

C15

D15

RXDV

RXER

B

B1

C1

D3D26

D4

B2

D0

VSSOSC2

C3

CAS1_

C4

B4

CS4_

C5

B5

CS1_

C6

B6

OE_

C7

B7

BUSY_

B8

C8

VCCPY10

B9

C9

BE0_

B10

MDIO

B11

TXD2

B12

TXEN

B13

RXD0

B14

VSSC03

B15

RXD2

A

A1

CAS3_

A2

CAS0_

VCCPY9

A4

CS3_

A5

GNDPY9

A6

BCLK

A7

GNDPY10

A8

TS_

A9

BE2_

A10

RESET_

A11

TXD0

A12P12

TXD3

A13

TXER

A14J14

TXCOL

A15

RXD1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Figure 3: NS7520 BGA layout

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NS7520 Hardware Reference, Rev. D 03/2006

Pinout detail tables and signal descriptions

Each pinout table applies to a specific interface and contains the following
information:

Column Description

Signal The pin name for each I/O signal. Some signals have multiple function modes and

are identified accordingly. The mode is configured through firmware using one or
more configuration registers.

Pin The pin number assignment for a specific I/O signal.

 U next to the pin number indicates that the pin is a pullup resistor (input

current source).

 D next to the pin number indicates that the pin is a pulldown resistor (input

current sink).

 No value next to the pin indicates that the pin has neither a pullup nor

pulldown resistor.

See Figure 28, "Internal pullup characteristics," on page 264 and Figure 29,
"Internal pulldown characteristics," on page 264 for an illustration of the
characteristics of these pins. Use the figures to select the appropriate value of the
complimentary resistor to drive the signal to the opposite logic state. For those
pins with no pullup or pulldown resistor, you must select the appropriate value per
your design requirements.

Pinout and Packaging

_ An underscore (bar) indicates that the pin is active low.
I/O The type of signal — input, output, or input/output.
OD The output drive strength of an output buffer. The NS7520 uses one of three

drivers:

 2 mA
 4 mA
 8 mA

Notes:

 NO CONNECT as a description for a pin means do not connect to this pin.
 The 177th pin (package ball) is for alignment of the package on the PCB.

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       11

Pinout detail tables and signal descriptions

System bus interface

Symbol Pin I/O OD Description

BCLK A6 O 8 Synchronous bus clock
External bus Other External bus Other
ADDR27 CS0OE_ N10 U I/O 4 Addr bit 27 Logical AND of CS0_

ADDR26 CS0WE_ P10 U I/O 4 Addr bit 26 Logical AND of CS0_

External bus External bus

ADDR25 M10 U I/O 4 Remainder of address bus (through

ADDR24 R10 U I/O 4
ADDR23 N9 U I/O 4
ADDR22 R9 U I/O 4
ADDR21 M9 U I/O 4

and OE_

and WE_

ADDR0)

ADDR20 N8 U I/O 4
ADDR19 P8 U I/O 4
ADDR18 M7 U I/O 4
ADDR17 R7U I/O 4
ADDR16 N7 U I/O 4
ADDR15 R6 U I/O 4
ADDR14 M6 U I/O 4
ADDR13 P6 U I/O 4
ADDR12 N6 U I/O 4
ADDR11 M5 U I/O 4
ADDR10 P5 U I/O 4
ADDR9 N5 U I/O 4
ADDR8 R4 U I/O 4

Table 2: System bus interface pinout

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NS7520 Hardware Reference, Rev. D 03/2006

Symbol Pin I/O OD Description

ADDR7 R3 U I/O 4
ADDR6 R2 U I/O 4
ADDR5 M4 U I/O 4
ADDR4 N4 U I/O 4
ADDR3 R1 U I/O 4
ADDR2 M3 U I/O 4
ADDR1 N2 U I/O 4
ADDR0 P1 U I/O 4
DATA31 N1 I/O 4 Data bus
DATA30 M1 I/O 4
DATA29 L3 I/O 4
DATA28 L2 I/O 4
DATA27 L4 I/O 4
DATA26 L1 I/O 4

Pinout and Packaging

DATA25 K3 I/O 4
DATA24 K2 I/O 4
DATA23 K1 I/O 4
DATA22 J2 I/O 4
DATA21 J3 I/O 4
DATA20 J1 I/O 4
DATA19 H3 I/O 4
DATA18 H4 I/O 4
DATA17 H1 I/O 4
DATA16 H2 I/O 4
DATA15 G4 I/O 4
DATA14 G1 I/O 4
DATA13 G3 I/O 4

Table 2: System bus interface pinout

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Pinout detail tables and signal descriptions

Symbol Pin I/O OD Description

DATA12 G2 I/O 4
DATA11 F4 I/O 4
DATA10 F2 I/O 4
DATA9 F3 I/O 4
DATA8 E1 I/O 4
DATA7 E2 I/O 4
DATA6 E3 I/O 4
DATA5 D1 I/O 4
DATA4 C1 I/O 4
DATA3 B1 I/O 4
DATA2 D4 I/O 4
DATA1 D3 I/O 4
DATA0 C2 I/O 4
BE3_ D9 I/O 2 Byte enable D31:D24
BE2_ A9 I/O 2 Byte enable D23:D16
BE1_ C9 I/O 2 Byte enable D15:D08
BE0_ B9 I/O 2 Byte enable D07:D00
TS_ A8 U I/O 4 DO NOT USE

TA_ D8 U I/O 4 Data transfer acknowledge

Table 2: System bus interface pinout

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Add an external 820 ohm pullup to 3.3 V.

Add an external 820 ohm pullup to 3.3 V.
TA_ is bidirectional. It is used in input

mode to terminate a memory cycle
externally. It is used in output mode for
reference purposes only.

NS7520 Hardware Reference, Rev. D 03/2006

Pinout and Packaging

Symbol Pin I/O OD Description

TEA_ C8 U I/O 4 Data transfer error acknowledge

Add an external 820 ohm pullup to 3.3 V.
TEA_ is bidirectional. It is used in input

mode to terminate a memory cycle
externally. It is used in output mode for

reference purposes only.
RW_ D6 I/O 2 Transfer direction
BR_ D7 NO CONNECT
BG_ C7 NO CONNECT
BUSY_ B7 NO CONNECT

Table 2: System bus interface pinout

Signal descriptions

Mnemonic Signal Description

BCLK Bus clock Provides the bus clock. All system bus interface

signals are referenced to the BCLK signal.

ADDR[27:0] Address bus Identifies the address of the peripheral being

addressed by the current bus master. The address
bus is bi-directional.

DATA[31:0] Data bus Provides the data transfer path between the

NS7520 and external peripheral devices. The data
bus is bi-directional.

Recommendation: Less than x32 (S)DRAM/SRAM
memory configurations. Unconnected data bus
pins will float during memory read cycles. Floating
inputs can be a source of wasted power.

For other than x32 DRAM/SRAM configurations,

the unused data bus signals should be pulled up.
TS_ Transfer start NO CONNECT
BE_ Byte enable Identifies which 8-bit bytes of the 32-bit data bus

are active during any given system bus memory

cycle. The BE_ signals are active low and

bi-directional.

Table 3: System bus interface signal description

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Pinout detail tables and signal descriptions

Mnemonic Signal Description

TA_ Transfer acknowledge Indicates the end of the current system bus

memory cycle. This signal is driven to 1 prior to
tri-stating its driver.

TA_ is bi-directional.

TEA_ Transfer error

RW_ Read/write indicator Indicates the direction of the system bus memory

BR_ Bus request NO CONNECT
BG_ Bus grant NO CONNECT
BUSY_ Bus busy NO CONNECT

Table 3: System bus interface signal description

Chip select controller

acknowledge

Indicates an error termination or burst cycle
termination:

 In conjunction with TA_ to signal the end of a

burst cycle.

 Independently of TA_ to signal that an error

occurred during the current bus cycle. TEA_
terminates the current burst cycle.

This signal is driven to 1 prior to tri-stating its
driver.

TEA_ is bi-directional. The NS7520 or the external
peripheral can drive this signal.

cycle. RW_ high indicates a read operation; RW_
low indicates a write operation. The RW_ signal is
bi-directional.

The NS7520 supports five unique chip select configurations:

Symbol Pin I/O OD Description

CS4_ B4 O 4 Chip select/DRAM RAS_
CS3_ A4 O 4 Chip select/DRAM RAS_
CS2_ C5 O 4 Chip select/DRAM RAS_
CS1_ B5 O 4 Chip select/DRAM RAS_

Table 4: Chip select controller pinout

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NS7520 Hardware Reference, Rev. D 03/2006