Digi 50M1663 Hardware Reference Manual
ConnectCore™ 9M 2443
and Wi-9M 2443
Hardware Reference
90000952_B
Release date: August 2009
©2009 Digi International Inc.
All rights reserved.
Digi, Digi International, the Digi logo, a Digi International Company, Digi JumpStart Kit and ConnectCore are
trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide.
All other trademarks are the property of their respective owners.
All other trademarks mentioned in this document are the property of their respective owners.
Information in this document is subject to change without notice and does not represent a commitment on the part
of Digi International.
Digi provides this document “as is,” without warranty of any kind, either expressed or implied, including, but not
limited to, the implied warranties of fitness or merchantability for a particular purpose. Digi may make
improvements and/or changes in this manual or in the product(s) and/or the program(s) described in this manual at
any time.
This product could include technical inaccuracies or typographical errors. Changes are periodically made to the
information herein; these changes may be incorporated in new editions of the publication.
www.digiembedded.com
ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
This guide provides information about the Digi ConnectCore 9M 2443 embedded
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core module family. Visit the Digi support website:
www.digiembedded.com/support.
To access current technical documentation available for the S3C2443 processor,
please visit the Samsung website.
. . . . .
Conventions used
in this guide
This table describes the typographic conventions used in this guide:
This convention Is used for
italic type Emphasis, new terms, variables, and document titles.
monospaced type Filenames, pathnames, and code examples.
Digi information
Documentation
updates
Please always check the product specific section on the Digi support website for the
most current revision of this document: www.digiembedded.com/support.
Change Log
Revision B Added WLan information for the ConnectCore Wi-9M 2443.
Added WLan information under environmental specifications in Appendix A.
Added a new drawing on page 136.
Made minor document updates.
www.digiembedded.com
Chapter 1
Contact
information
For more information about your Digi products, or for customer service and
technical support, contact Digi International.
To contact Digi International by Use
Mail Digi International
11001 Bren Road East
Minnetonka, MN 55343
U.S.A
World Wide Web http://www.digiembedded.com/support/
email http://www.digiembedded.com/support/
Telephone (U.S.) (952) 912-3444 or (877) 912-3444
Telephone (other locations) +1 (952) 912-3444 or (877) 912-3444
6 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Contents
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. . . . . . .
Change Log....................................................................................... 5
Revision B ................................................................................. 5
Chapter 1:
Features and functionality ...................................................................12
Block diagrams .................................................................................16
Detailed module description .................................................................18
Memory ..........................................................................................23
Configuration pins - CPU module ............................................................24
Chip selects .....................................................................................25
Multiplexed GPIO pins .........................................................................26
Interfaces ....................................................................................... 32
About the Module ............................................................... 12
CPU........................................................................................16
Module .................................................................................... 17
Configuration ............................................................................18
Power Supply ............................................................................ 18
Power management.....................................................................19
NORMAL mode ...........................................................................20
IDLE mode ................................................................................20
STOP mode ...............................................................................20
SLEEP mode ..............................................................................20
Wake-up event ..........................................................................21
Reset ......................................................................................22
DDR SDRAM memory ....................................................................23
NAND Flash memory ....................................................................23
Chip select memory map ..............................................................25
S3C2443X Port Configuration..........................................................26
RTC ........................................................................................32
UART interface ..........................................................................32
SPI interface .............................................................................34
I2C interface .............................................................................35
USB interface ............................................................................35
Ethernet interface ......................................................................36
WLAN interface..........................................................................37
A/D converter and touch screen interface..........................................37
Touch screen interface modes ........................................................37
Reset controller .........................................................................38
Chapter 2
JTAG ......................................................................................38
Common features .......................................................................38
Watchdog timer .........................................................................39
IIS-Bus interface .........................................................................39
IIS block diagram: .......................................................................40
IIS-Bus format............................................................................40
Camera interface........................................................................41
.............................................................................................41
AC97 Controller..........................................................................42
SD host interface ........................................................................44
PWM timer................................................................................44
Clock output .............................................................................45
CF/ATA....................................................................................45
PC card controller.......................................................................46
ATA controller ...........................................................................46
High-speed MMC .........................................................................46
High speed SPI ...........................................................................47
External address/data bus.............................................................47
WLAN connectors........................................................................47
LCD controller display features ..............................................................49
STN LCD displays ........................................................................49
TFT LCD displays ........................................................................49
Common features .......................................................................49
Module pinout ..................................................................................50
System connector X1 ...................................................................50
System connector X2 ...................................................................56
Configuration pins - CPU ......................................................................61
Chapter 2:
About the Development Board .........................................62
What’s on the development board? ..................................................62
The development board................................................................63
User interface ..................................................................................64
Power management.....................................................................64
General information ...........................................................................64
Power supply.............................................................................64
3.3VDC power controller - VLIO.......................................................65
Power LEDs ...............................................................................65
Coin cell for RTC ........................................................................65
Current measuring option..............................................................65
Reset ......................................................................................65
JTAG interface ..........................................................................65
I²C interface .............................................................................65
PoE connectors ..........................................................................65
Peripheral application connector.....................................................66
LCD Application Kit Connector ........................................................66
8 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
VGA interface ........................................................................... 66
UARTs .................................................................................... 66
UART A - console ....................................................................... 66
UART B - UART / MEI................................................................... 66
UART C - TTL interface ................................................................ 66
UART D - TTL interface ................................................................ 66
SPI interface(s) ......................................................................... 67
Camera interface.............................................................................. 68
Switches and push-buttons .................................................................. 69
Reset control, S1 ....................................................................... 69
Power switch, S2 ....................................................................... 69
Legend for multi-pin switches........................................................ 70
Module configuration switches, S4................................................... 70
Serial port B MEI configuration switches............................................ 70
Test points ..................................................................................... 71
Numbers and description.............................................................. 71
Factory default interface configuration for development board ...................... 72
LEDs ............................................................................................. 73
WLAN, LE10.............................................................................. 73
Power LEDs, LE1, LE4, and LE7....................................................... 73
User LEDs, LE5 and LE6 ................................................................ 74
Serial status LEDs....................................................................... 74
Status LEDs Serial port A .............................................................. 75
Status LEDs Serial port B .............................................................. 75
Debug, LE3 .............................................................................. 75
Battery and battery holder .................................................................. 76
Serial UART ports.............................................................................. 77
Serial port A, RS232, X27.............................................................. 77
Serial port B, MEI interface, X16..................................................... 79
Serial port C, TTL interface, X19 .................................................... 79
Serial port D, TTL interface, X22 .................................................... 80
I2C interface ................................................................................... 81
I2C connector, X22 ..................................................................... 81
SPI interface ................................................................................... 82
X8-SPI connector........................................................................ 83
Current Measurement Option................................................................ 84
Measurement options .................................................................. 84
How the CMO works .................................................................... 85
PoE module connectors - IEEE802.3af...................................................... 86
The PoE module ........................................................................ 87
PoE connector (power in), X17 ....................................................... 87
PoE connector (power out), X26 ..................................................... 87
POE_GND................................................................................. 87
VGA connector ................................................................................. 88
VGA connector, X18.................................................................... 88
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www.digiembedded.com 9
Chapter 2
USB connectors .................................................................................90
USB device connector, X15 ............................................................90
USB host connector, X14 ...............................................................90
Digital I/O .......................................................................................91
I2C digital I/O expansion, X44 ........................................................91
JTAG interface .................................................................................92
Standard JTAG ARM connector, X13..................................................93
Peripheral (extension) headers ..............................................................94
LCD application header, X5............................................................95
Peripheral application header, X3....................................................96
Module connectors and signal rails ..........................................................97
Signal rails................................................................................97
X10 pinout ................................................................................98
X11 pinout ................................................................................99
X20 pinout .............................................................................. 100
X21 pinout .............................................................................. 101
Power connector ............................................................................. 102
Jumpers ....................................................................................... 103
Jumpers................................................................................. 104
Ethernet interface ........................................................................... 105
RJ-45 pin allocation, X7 .............................................................. 106
WLAN Interface............................................................................... 108
Interfaces without special connectors.................................................... 109
ADC signals ............................................................................. 109
CF signals ............................................................................... 109
I2S/AC97 signals ....................................................................... 110
SPI1 signal .............................................................................. 110
Module and test connectors ................................................................ 111
X1 pinout ............................................................................... 111
X2 pinout ............................................................................... 121
Network interface ........................................................................... 128
WLAN interface............................................................................... 128
Environmental specifications............................................................... 130
ConnectCore
9M 2443 ................................................................................. 130
ConnectCore
Wi-9M 2443 ............................................................................. 130
Thermal specifications ...................................................................... 131
Standard Operating Temperature Ranges ......................................... 131
recommendations ..................................................................... 132
Power requirements ......................................................................... 133
Typical Power Requirements ............................................................... 133
ConnectCore 9M 2443 ................................................................ 133
ConnectCore “Wi-9M 2443”.......................................................... 134
Mechanical specifications................................................................... 136
10 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
ConnectCore 9M 2443................................................................. 136
ConnectCore
Wi-9M 2443 ............................................................................. 138
Connector Reference Parts ................................................................. 139
Base Board Connector X1, X2 ........................................................139
Base Board Connector X3, X4 ........................................................139
Cable specification : U.FL/W.FL to RP-SMA FEMALE.................................... 140
Attributes............................................................................... 140
Dimensions ............................................................................. 140
Antenna specification: 802.11a/b/g antenna............................................ 141
Attributes............................................................................... 141
Dimensions ............................................................................. 141
Antenna Specification: 802.11b/g antenna .............................................. 142
Attributes............................................................................... 142
Dimensions ............................................................................. 142
Polar Plots ..................................................................................... 143
Safety statements ............................................................................ 144
........................................................................................... 144
FCC Part 15 Class B .......................................................................... 145
. . . . .
www.digiembedded.com 11
About the Module
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CHAPTER 1
The network-enabled ConnectCore 9M 2443 core module family delivers leading
performance, low power operation, and rich peripheral interface support for a wide
variety of applications, including medical devices, transportation, security/access
control, networked displays, and more.
The modules utilize an innovative and power-efficient Samsung S3C2443 processor
with up to 533 MHz and a multilayered memory bus architecture that allows
simultaneous data transfer between processor, memory and peripherals. This
optimized design eliminates the traditional bus bandwith bottlenecks that are
common on other platforms. For example, updating graphical information through
the LCD controller and retrieving relevant data from memory at the same time can
now be realized without compromising overall performance and user experience.
Designed from the ground up with power budget conscious applications in mind, the
ConnectCore 9M 2443 module family is an ideal system platform for mobile and
battery-operated product designs with full off-the-shelf hard- and software support
for all power management modes. The modules also offer a wide variety of onboard peripherals such as network connectivity options, a TFT/CSTN LCD controller,
camera interface, audio codec interfaces, hi-speed USB device, full-speed USB host,
high-speed memory card support, external mass storage, and other interfaces.
Features and functionality
32-bit Samsung S3C2443 processor
ARM920T core at 400/533 MHz
16 KB of instruction/data cache
Up to 133 MHz memory bus speed
Up to 1 GB of NAND Flash
Up to 256 MB DDR SDRAM
www.digiembedded.com 12
Chapter 1
LCD controller (CSTN/TFT)
Up 1024x1024 pixels resolution
Up to 16 grey levels/4096 colors (STN)
Up to 24 bpp, two overlay windows (TFT)
Camera interface
ITU-R BT 601/656 8-bit mode support
4096x4096 pixels / 2048x2048 scaling
Mirror, 180° rotation, digital zoom in
RGB 16/24-bit, YCbCr 4:2:0/4:2:2 output
I2S and AC’97 audio codec controllers
USB support with integrated PHYs
USB 2.0 device, 1-port, high-/full-speed
USB 1.1 host, 2-port, low-/full-speed
Ethernet interface
– 10/100 Mbit Ethernet MAC and PHY
WLAN interface
– 802.11a/b/g WLAN interface with dual-diversity antenna setup
4-channel UART
Up to 921 kbps, IrDA 1.0 SIR mode
2-port SPI/Single-port HS-SPI
Master and slave mode
Up to 33 MHz
I2C-Bus Interface
1-ch Multi-Master IIC-Bus
Serial, 8-bit oriented and bi-directional data transfers up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in fast mode
13 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
SD/SDIO/MMC
1-/4-bit and block/stream, up to 25 MHzHigh-Speed (HS) MMC
SD HC 1.0, SD MC 2.1, SDIO 1.0, MMC 4.2
1-/4-/8-bit modes, up to 50 MHz
CE-ATA mode support
CF/ATA
Compact Flash 3.0 PC card mode
ATA/ ATAP I-6 mo de w it h PI O/ UDM A
10-bit ADC & Touch Screen Interface
10-channel multiplexed, 500k samples/s
Timer s /P W M
4-ch 16-bit timer/PWM, 1-ch 16-bit internal
8-/16-bit external memory bus interface
Power management modes
Normal, idle, stop, and sleep
Ext IRQ, RTC alarm, tick interrupt wake-up
GPIO options
Up to 15 external IRQs
Up to 134 GPIOs
Watchdog Timer (16-bit)
Real-time clock with calendar function
Two 120-pin board-to-board connectors
www.digiembedded.com 14
Chapter 1
JTAG signals available on module connectors
Standard module variants
The ConnectCore 9M 2443 module is currently available in the standard variants
below.
Speed Flash SDRAM Operating
temperature
533 MHz 128 MB 64 MB -40 to 85C CC-9M-NA37-Z1
533 MHz 64MB 32 MB -40 to 85C CC-9M-NA26-Z1
400 MHz 64 MB 32 MB -20 to 70C CC-9M-QA25-Z1
533 MHz 128 MB 64 MB -40 to 65C* CC-W9M-NA37-XE
533 MHz 64MB 32 MB -40 to 65C* CC-W9M-NA26-XE
400 MHz 64 MB 32 MB -20 to 65C* CC-W9M-QA25-XE
P/N
* See section "Thermal specifications" in this document for details.
Please visit the Digi website, www.digiembedded.com/support, or contact Digi for
additional population options.
15 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Block diagrams
CPU
www.digiembedded.com 16
Chapter 1
S3C2443
Et he rn et -I/ F,
PHY
120pi n
Co nn 1
2 b anks
DDR
SDRAM
NAND
Flash
Reset
Generator
Flash Control
Address Bus
COM 0/COM 1
JTAG
+3.3V
RSTOUT#
RSTIN#
120pin
Conn 2
PWRGOOD
GND
VRTC
LEDLNK
LEDH0
Configurati on
LCD/TFT-I/F
Bus Control
U SB host1/device0
USB De te ct/PWR En abl e
Clock
Serial
EEP ROM
Ext. IN T
AGND
AVCC
I2C
SPI
Timer Out
Address Bus
Data Bus
AC97/ I2S-I/F
SD-I/F
DMA
Analog In
Touch Sc reen
Timer In
PWR Enable Core
USB host0
US B PWR Enable
Buffer
CLKOUT
RTC
VLIO
VRTC
Core
Voltage
VLIO
Batte ry Fault
Camera-I/F
PLL
Volta ge
SDRAM l/F
Wireless
PR IM . Antenna
SEC . Antenna
LED
Module
17 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Detailed module description
Configuration The ConnectCore 9M 2443 Module supports 8 configuration pins:
4 pins provided for software configuration, which are routed to standard pin
locations on the development board (CONF[7:4]).
4 pins provided for hardware configuration, routed to the base board at
standard pin locations, including debug enable (DEBUG_EN#) and NAND flash
write protect (NAND_FWP#).
Power Supply The common power supply for the module is 3.3VDC. VLIO has to be connected to
3.3V on the base board.
The CPU specific core voltage of 1.2V@300MHz (1.3V@400MHz) and the voltage for
VDD alive will be generated on the module from the VLIO input, while the voltage for
memory power supply and I/OS is fed directly from the 3.3V.
The following requirements have to be met by the power supply:
Power Supply @400MHz @533MHz
Module Power Supply 3.3V 3.3V ±5% 3.3V ± 5%
Module Power Supply VLIO 3.3V ±5% 3.3V ±5%
Core Voltage 1.3V (1.25V - 1.35V) 1.375 (1.325V - 1.425V)
VDD alive 1.15V - 1.35V 1.15V - 1.2V
Voltage for internal RTC 3V (1.8V - 3.6V) 3V (1.8V - 3.6V)
Power Supply for ext. RTC
VRTC
Analog Voltage 3.3V (3V - 3.6V) 3.3V (3V - 3.6V)
VIN at common CPU pins -0.3V - 3.3V ± 0.3V -0.3V - 3.3V ± 0.3V
3V (e.g. Li-Battery) 3V (e.g. Li-Battery)
The voltage at pin RTCVDD has been connected to 3.3V, even though the RTC is not
used. If VDD_RTC is not used, it has to be high (VDD_RTC=3.3V).
The S3C2443 supports DVS (dynamic voltage scaling). This means that the core
voltage may be reduced to 1V in idle mode while clock frequency is also reduced.
VRTC is used to connect a battery on the base board for the external RTC on the
module. If the external RTC is not used, pin VRTC doesn't need to be connected. VRTC
is only used to power the external RTC on the module.
If a battery supplies the power for the module, the pin BATT_FLT# can be connected
to a comparator output on the base board. The comparator may supervise the battery
voltage on the base board. The CPU does not wake up at power-off mode in case of
www.digiembedded.com 18
Chapter 1
low battery state. If this feature is not used, the pin has to be left open, because a
10k pull up resistor is provided at the module.
Analog voltage AVCC and AGND, e.g. for a touch screen, are also provided on the
module system connector.
For the power control logic, the S3C2443 has various power management schemes
to keep optimal power consumption for a given task. These schemes are related to
PLL, clock control logics (ARMCLK, HCLK, and PCLK) and wakeup signals.
ARMCLK is used for ARM920T core.
HCLK is the reference clock for internal AHB bus and peripherals such as the
memory controller, the interrupt controller, LCD controller, the DMA, USB host
block, System Controller, Power down controller and etc.
PCLK is used for internal APB bus and peripherals such as WDT, IIS, I2C, PWM
timer, ADC, UART, GPIO, RTC and SPI etc.
The following figure shows the clock distribution:
Power
management
19 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
The power management block in the S3C2443 can activate four modes: NORMAL,
STOP, IDLE, and SLEEP. These are described below.
NORMAL mode In General Clock Gating mode, the On/Off clock gating of the individual clock
source of each IP block is performed by controlling each corresponding clock source
enable bit. The Clock Gating is applied instantly whenever the corresponding bit is
changed.
IDLE mode In IDLE mode, the clock to the CPU core is stopped. The IDLE mode is activated just
after the execution of the STORE instruction that enables the IDLE Mode bit. The
IDLE Mode bit should be cleared after wake-up from IDLE state.
STOP mode All clocks are stopped for minimum power consumption. Therefore, the PLL and
oscillator circuits are also stopped (oscillator circuit is controlled by PWRCFG
register). The STOP mode is activated after the execution of the STORE instruction
that enables the STOP mode bit. The STOP Mode bit should be cleared after wakeup from STOP state.
To exit from STOP mode, external interrupt, RTC alarm, RTC Tick, or BATT_FLT has
to be activated. During the wake-up sequence, the crystal oscillator and PLL may
begin to operate. The crystal oscillator settle-down time and the PLL lock-time is
required for a stable ARMCLK and automatically inserted by the hardware of
S3C2443X. During these lock and settle-down times, no clock is supplied to the
internal logic circuitry.
The following describes the sequence initiating STOP mode:
1 Set the STOP Mode bit (by the main CPU).
2 System controller requests bus controller to finish pending transaction.
3 Bus controller sends acknowledgement to system controller after bus
transactions are completed.
4 System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
5 System controller waits for self-refresh acknowledgement from memory
controller.
6 After receiving the self-refresh acknowledge, system controller disables system
clocks, and switches SYSCLK source to MPLL reference clock.
7 Disables PLLs and Crystal (XTI) oscillation. If OSC_EN_STOP bit in PWRCFG
register is 'high,' then system controller does not disable crystal oscillation.
Note: DRAM has to be in self-refresh mode during STOP and SLEEP mode to retain valid
memory data. LCD must be stopped before STOP and SLEEP mode, because DRAM can
not be accessed when it is in self-refresh mode.
SLEEP mode The block disconnects power to CPU, and the internal logic, with the exception of
the wake-up logic. Activating the SLEEP mode requires two independent power
sources. One of the two power sources supplies the power for the wake-up logic.
www.digiembedded.com 20
Chapter 1
The other power source supplies the CPU and internal logic, and should be
controlled for power on/off. In SLEEP mode, the second power supply source for the
CPU and internal logic will be turned off. The wake-up from SLEEP mode can be
issued by EINT[15:0].
In SLEEP mode, VDDi, VDDiarm, VDDMPLL and VDDEPLL will be turned off, and are
controlled by PWREN. If the PWREN signal is activated (H), VDDi and VDDiarm are
supplied by an external voltage regulator. If PWREN pin is inactive (L), VDDi and
VDDiarm are turned off.
In Power_OFF mode 1.2V have to be supplied to the VDD alive pin, and it is also
necessary to provide the I/O-voltages of 1.8V/3.3V. Therefore the LDO, which
supplies VDD alive will not be switched off.
The following describes the sequence of entering SLEEP mode:
1 One of the SLEEP Mode entering events is triggered by the system software or by
the hardware.
2 System controller requests bus controller to finish pending transaction.
3 Bus controller sends acknowledgement to system controller after bus
transactions are completed.
4 System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
5 System controller waits for self-refresh acknowledgement from memory
controller.
6 After receiving the self-refresh acknowledge, disables the XTAL and PLL
oscillation and also disables the external power source for the internal logic by
asserting the PWR_EN pin to low state. The PWR_EN pin is the regulator disable
control signal for the internal logic power source.
The SLEEP mode exit sequence is as follows.
1 System controller enables external power source by deasserting PWR_EN to high
state and initiates power settle down programmable through a register in the
PWRSETCNT field of RSTCON register.
2 System controller releases the System Reset (synchronously, relatively to the
system clock) after the power supply is stabilized.
Wake-up event When S3C2443X wakes up from the STOP Mode by an External Interrupt, an RTC
alarm interrupt and other interrupts, the PLL is turned on automatically. The initialstate of S3C2443X after wake-up from the SLEEP Mode is almost the same as the
Power-On-Reset state except for the contents of the external DRAM is preserved. In
contrast, S3C2443X automatically recovers the previous working state after wakeup from the STOP Mode. The following table shows the states of PLLs and internal
clocks after wake-ups from the power-saving modes.
21 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Mode before wake-up PLL on/off after wake-up SYSCLK after wake-up
Wake-up source
Wake-up source
Reset or restricted
wake-up events
and before the lock time
IDLE Unchanged PLL output PLL output
SYSCLK after the lock
time by internal logic
STOP PLL state ahead of entering STOP
mode (PLL ON or not)
SLEEP Off PLL reference clock PLL reference (input) clock
To enter sleep mode by BATT_FLT, BATF_CFG bits of PWRCFG register must be
PLL reference clock SYSCLK ahead of entering
STOP mode (PLL output or
not)
configured.
Do not exit from sleep mode when BATT_FLT is LOW; SLEEP_CFG bit of PWRCFG
register must be configured.
A Battery Fault Signal (BATT_FLT#) is provided at the CPU to recognize the battery
state of the battery at the base board, which powers the module. Therefore this pin
is routed to the system connector. At the base board a comparator has to supervise
the battery state and the output of the comparator delivers the BATT_FLT# signal.
The figure below shows the power management state diagram:
Reset There are 3 reset signals defined, which are routed to the system connector:
www.digiembedded.com 22
a reset input to the module (RSTIN#)
an output of the reset controller from the module (PWRGOOD)
a reset output from the CPU (RSTOUT#)
Chapter 1
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Memory
RSTIN# signal from the base board is connected to the reset generator device
on the module. At the base board there could be a reset switch connected to
the RSTIN# signal. A 10k pull up resistor is connected to the RSTIN# signal on
the module.
PWRGOOD must be held to low level at least 4 FCLKs to recognize the reset
signal.
The low active reset of the reset controller is connected to the system via a 470R
series resistor.
RSTOUT# can be used for external device reset control. RSTOUT# is a function of
Watchdog Reset and Software Reset (RSTOUT# = PWRGOOD & WDTRST# &
SW_RESET).
DDR SDRAM
memory
NAND Flash
memory
On the module there are two banks provided for DDR SDRAM memory. Both banks can
support a 16-bit mobile DDR memory chip. Bank 1 provides one part of a 16bit DDR
SDRAM in a FBGA60 package, with 1.8V power supply.
Total size of memory is possible from 16MB (only one bank) up to 256MB (128MB each
bank).
Both banks have to be populated with equal devices since they share all control
signals with the exception of their chip selects.These are defined in the bank control
registers BANKCFG and BANKCON1-3 and Refresh Control Register.
NAND Flash memory is provided, as a single Flash device. In order to support NAND
flash boot loader, the S3C2443 is equipped with an internal SRAM buffer called
Steppingstone. When booting, the first 4 KBytes of the NAND flash memory will be
loaded into Steppingstone and the boot code loaded into Steppingstone will be
executed.
Generally, the boot code will copy NAND flash content to DDR-SDRAM. Using hardware
ECC, the NAND flash data validity will be checked. Upon the completion of the copy,
the main program will be executed on the DDR-SDRAM.
Features:
NAND Flash memory I/F: Supports 512Bytes and 2KBytes Page.
Interface: 8-bit NAND flash memory interface bus.
Hardware ECC generation, detection and indication (Software correction).
23 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
SFR I/F: Supports Little Endian Mode, Byte/half word/word access to Data and
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECC Data register, and Word access to other registers.
Steppingstone I/F: Supports Little/Big Endian, Byte/half word/word access.
The Steppingstone 4-KB internal SRAM buffer can be used for another purpose
after NAND flash booting.
The write protect pin of the Flash device is routed to the hardware configuration
pin of the system connector FWP#. The device can be write protected at the base
board by connecting this pin to GND. At the module, a pull-up resistor is equipped.
Configuration pins - CPU module
There are eight configuration pins provided on the system connector. Four of them
are provided as hardware configuration pins, and the other four can be used as
software configuration pins. A 10k pull up resistor is provided on each signal line of
the configuration pins.
The following pins on the connector are defined as hardware configuration pins:
Signal Description
DEBUGEN# Debug enable
FWP# Write protect of internal flash
CONF2 Hardware configuration 2 (not yet used)
CONF3 Hardware configuration 3 (not yet used)
The following port pins are defined as software configuration pins:
Signal Port Pin Description
CONF4 GPF2 Software configuration 0
CONF5 GPF3 Software configuration 1
CONF6 GPF4 Software configuration 2
CONF7 GPF5 Software configuration 3
The signal DEBUGEN# (CONF0) from the base board to the module is necessary to
allow switching a connection on and off between the system reset and the JTAG
reset.
Signal State Description
DEBUGEN# High Switch is on, TRST# and PWRGOOD are connecte d (defa ult)
DEBUGEN# Low Switch is off, TRST# and PWRGOOD are disconnected
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Chip selects
Chip select
memory map
At the module a pull up resistor is provided on the DEBUGEN# signal. Therefore only
a jumper to GND is necessary on the base board.
Name CPU Signal
name
Pin Address
Range
Size [Mb] Usage Comments
SCS0# SCS0# H15 0x3000_0000-
0x37FF_FFFF
SCS1# SCS1# D17 0x3800_0000-
0x3FFF_FFFF
RCS0# RCS0# A2 0x0000_0000-
0x03FF_FFFF
RCS1# RCS1# A1 0x0800_0000-
0x083F_FFFF
RCS2# RCS2# B3 0x1000_0000-
0x103F_FFFF
RCS3# RCS3# C1 0x1800_0000-
0x183F_FFFF
RCS4# RCS4# C4 0x2000_0000-
0x203F_FFFF
RCS5# RCS5# E4 0x2800_0000-
0x283F_FFFF
128 SDRAM bank 0 First bank on
module
128 SDRAM bank 1
64 not available
64 external, RCS1#
64 external, RCS2#
64 external, RCS3#
64 external, RCS4#
64 internal, RCS5# Used for Ethernet
Controller
25 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
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Multiplexed GPIO pins
S3C2443X Port
Configuration
Port A Selectable Pin Functions On module,
GPA15 Output only nWE_CF - Output
GPA14 Output only RSMAVD - Output
GPA13 Output only RSMCLK - Output
GPA12 Output only nRCS5 - nRCS5
GPA11 Output only nOE_CF - Output
GPA10 RDATA_OEN RADDR25 - RADDR25
GPA9 Output only RADDR24 - RADDR24
GPA8 Output only RADDR23 - RADDR23
GPA7 Output only RADDR22 - RADDR22
GPA6 Output only RADDR21 - RADDR21
GPA5 Output only RADDR20 - RADDR20
GPA4 Output only RADDR19 - RADDR19
default used as
GPA3 Output only RADDR18 - RADDR18
GPA2 Output only RADDR17 - RADDR17
GPA1 Output only RADDR16 - RADDR16
GPA0 Output only RADDR0 - RADDR0
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Chapter 1
Port B Selectable Pin Functions On module,
default used as
GPB10 Input/Output nXDREQ0 XDREQ0 Input
GPB9 Input/Output nXDACK0 XDACK0 Input
GPB8 Input/Output nXDR EQ1 XDREQ1 Input
GPB7 Input/Output nXDACK1 XDACK1 Input
GPB6 Input/Output nXBREQ XBREQ Input
GPB5 Input/Output nXBACK XBACK Input
GPB4 Input/Output TCLK - Input
GPB3 Input/Output TOUT3 - not used, reserved
GPB2 Input/Output TOUT2 - Input
GPB1 Input/Output TOUT1 - Input
GPB0 Output only TOUT0 - Input
Port C Selectable Pin Functions On module,
default used as
GPC15 Input/Output VD7 - VD7
GPC14 Input/Output VD6 - VD6
GPC13 Input/Output VD5 - VD5
GPC12 Input/Output VD4 - VD4
GPC11 Input/Output VD3 - VD3
GPC10 Input/Output VD2 - VD2
GPC9 Input/Output VD1 - Input
GPC8 Input/Output VD0 - Input
GPC7 Input/Output LCD_VF[2] - LCD_VF[2]
GPC6 Input/Output LCD_VF[1] - LCD_VF[1]
GPC5 Input/Output LCD_VF[0] - LCD_VF[0]
GPC4 Input/Output VM - VM
GPC3 Input/Output VFRAME - VFRAME
GPC2 Input/Output VLINE - VLINE
GPC1 Input/Output VCLK - Output
GPC0 Input/Output LEND - Input
27 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Port D Selectable Pin Functions On module,
default used as
GPD15 Input/Output VD23 - VD23
GPD14 Input/Output VD22 - VD22
GPD13 Input/Output VD21 - VD21
GPD12 Input/Output VD20 - VD20
GPD11 Input/Output VD193 - VD193
GPD10 Input/Output VD18 - VD18
GDA9 Input/Output VD17 - Input
GPD8 I np ut/Outp ut VD16 - Input
GPD7 Input/Output VD15 - VD15
GPD6 Input/Output VD14 - VD14
GPD5 Input/Output VD13 - VD13
GPD4 Input/Output VD12 - VD12
GPD3 Input/Output VD11 - VD11
GPD2 Input/Output VD10 - VD10
GPD1 I np ut/Outp ut VD9 - Input
GPA0 I np ut/Outp ut VD8 - Input
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Chapter 1
Port E Selectable Pin Functions On module,
default used as
GPE15 Input/Output IICSDA - IICSDA
GPE14 Input/Output IICSCL - IICSC L
GPE13 Input/Output SPICLK0 - SPICLK0
GPE12 Input/Output SPIMOSI0 - SPIMOSI0
GPE11 Input/Output SPIMISO0 - SPIMISO0
GPE10 Input/Output SD0_DAT3 - SD0_DAT3
GPE9 Input/Output SD0_DAT2 AC_nRESET SD0_DAT2
GPE8 Input/Output SD0_DAT1 AC_SYNC SD0_DAT1
GPE7 Input/Output SD0_DAT0 AC_SDO SD0_DAT0
GPE6 Input/Output SD0_CMD AC_SDI SD0_CMD
GPE5 Input/Output SD0_CLK AC_BIT_CLK SD0_CLK
GPE4 Input/Output I2SSDO AC_SDO Input
GPE3 Input/Output I2SSDI AC_SDI Input
GPE2 Input/Output CDCLK AC _BI T_CLK Input
GPE1 Input/Output I2SSCLK AC_SYNC Input
GPE0 Input/Output I2SLRCK AC_nRESET Input
Port F Selectable Pin Functions On module,
default used as
GPF7 Input/Output EINT7 - Input
GPF6 Input/Output EINT6 - Input
GPF5 Input/Output EINT5 - Input
GPA4 Input/Output EINT4 - Internal Input
GPF3 Input/Output EINT3 - Internal Input
GPF2 Input/Output EINT2 - Internal Input
GPF1 Input/Output EINT1 - Input
GPF0 Input/Output EINT0 - Input
Port G Selectable Pin Functions On module,
default used as
GPA15 Input/Output EINT23 CARD_PWREN Input
GPA14 Input/Output EINT22 RESET_CF Input
GPG13 Input/Output EINT21 nREG_CF Input
GPG12 Input/Output EINT20 nlNPACK Input
29 ConnectCore 9M 2443 & Wi-9M 2443 Hardware Reference
Port G Selectable Pin Functions On module,
default used as
GPG11 Input/Output EINT19 nlREQ_CF Input
GPG10 Input/Output EINT18 - Input
GPG9 Input/Output EINT17 - Input
GPG8 Input/Output EINT16 - Input
GPG7 Input/Output EINT15 - Internal Input
GPG6 Input/Output EINT14 - Input
GPG5 Input/Output EINT13 - Input
GPG4 Input/Output EINT12 LCD_PWREN Internal Input
GPG3 Input/Output EINT11 - Input
GPG2 Input/Output EINT10 - Internal output
GPG1 Input/Output EINT9 - Internal Input
GPG0 Input/Output EINT8 - Input
Port H Selectable Pin Functions On module,
default used as
GPH14 Input/Output CLKOUT1 - CLKOUT1
GPH13 Input/Output CLKOUT0 - CLKOUT0
GPH12 Input/Output EXTUARTCLK - Internal Input
GPH11 Input/Output nRTS1 - nRTS1
GPH10 Input/Output nCTS1 - nCTS1
GPH9 Input/Output mRTS0 - mRTS0
GPH8 Input/Output nCTS0 - nCTS0
GPH7 Input/Output RXD3 nCTS2 RXD3
GPH6 Input/Output TXD2 nRTS2 TXD2
GPH5 Input/Output TXD2 - TXD2
GPH4 Input/Output RXD1 - RXD1
GPH3 Input/Output RXD1 - RXD1
GPH2 Input/Output TXD1 - TXD1
GPH1 Input/Output RXD0 - RXD0
GPH0 Input/Output TXD0 - TXD0
Port J Selectable Pin Functions On module,
default used as
GPJ15 Input/Output nSD1_WP - Input
GPJ14 Input/Output nSD1_CD - Input
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