Dialog Semiconductor SLG46824, SLG46826 Programming Manual

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In-System Programming Guide

SLG46824/6

ISPG-SLG46824/6

SLG46824/6

1 Hardware Requirements ......................................................................................................................................................3

1.1 Pinout and Signals .................................................................................................................................................3

2 Programming Algorithm for NVM Configuration Register Space ....................................................................................5

3 I2C Signal Specifications .....................................................................................................................................................7

3.1 Commands .............................................................................................................................................................7

3.2 Addressing .............................................................................................................................................................8

4 Memory Spaces ....................................................................................................................................................................9

4.1 Memory Map ..........................................................................................................................................................9

4.2 Special Pages ......................................................................................................................................................10

5 Programming Algorithm for the Emulated EEPROM Space ..........................................................................................11

6 Protection for Emulated EEPROM ....................................................................................................................................13

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DD2

IO9

IO10

IO2

IO1

IO0

IO4

IO3

IO7

IO8

GND

SDA

SCL

IO6

IO13

IO12

IO14

IO11

IO5

SLG46824/6

Introduction

This document describes the in-system programming procedures for SLG46824 and SLG46826.

1 Hardware Requirements

1.1 PINOUT AND SIGNALS

Four pins are required to program the SLG46824/6: VDD, GND, SCL and SDA.

The VDD pin requires a voltage ranging from 2.5 V to 5.5 V for Programming (Write) operations, and 2.3 V to 5.5 V for Verification (Read) operations.

The SCL and SDA pins are defined to be standard I Mode speed (400 kHz) NVM write communication is supported for these devices. For the timing characteristics for signals on these pins refer to Table 1.

C signaling. I2C Fast Mode Plus speed (1 MHz) NVM read and I2C Fast

Figure 1: STQFN-20 Pin Configuration

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IO5

IO4

IO3

SDA

SCL

IO6

IO0 IO1

IO2

IO11

IO12

IO13

IO14

IO9

IO10

IO7

IO8

GND

DD2

SLG46824/6

Figure 2: TSSOP-20 Pin Configuration

Table 1: I2C Specifications

Symbol Parameter Condition

SCL

LOW

HIGH

BUF

HD_STA

SU_STA

HD_DAT

SU_DAT

SU_STD

Clock Frequency, SCL VDD = 2.3 V to 5.5 V -- -- 400 -- -- 1000 kHz

Clock Pulse Width Low VDD = 2.3 V to 5.5 V 1300 -- -- 500 -- -- ns

Clock Pulse Width High VDD = 2.3 V to 5.5 V 600 -- -- 260 -- -- ns

Input Filter Spike Suppression

(SCL, SDA)

VDD = 2.3 V to 5.5 V -- -- 50 -- -- 50 ns

Clock Low to Data Out Valid VDD = 2.3 V to 5.5 V -- -- 900 -- -- 450 ns

Bus Free Time between Stop and Start

Start Hold Time VDD = 2.3 V to 5.5 V 600 -- -- 260 -- -- ns

Start Set-up Time VDD = 2.3 V to 5.5 V 600 -- -- 260 -- -- ns

Data Hold Time VDD = 2.3 V to 5.5 V 0 -- -- 0 -- -- ns

Data Set-up Time VDD = 2.3 V to 5.5 V 100 -- -- 50 -- -- ns

Inputs Rise Time VDD = 2.3 V to 5.5 V -- -- 300 -- -- 120 ns

Inputs Fall Time VDD = 2.3 V to 5.5 V -- -- 300 -- -- 120 ns

Stop Set-up Time VDD = 2.3 V to 5.5 V 600 -- -- 260 -- -- ns

Data Out Hold Time VDD = 2.3 V to 5.5 V 50 -- -- 50 -- -- ns

Fast-Mode Fast-Mode Plus

Min Typ Max Min Typ Max

Unit

= 2.3 V to 5.5 V 1300 -- -- 500 -- -- ns

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VDD

POR Delay

Control Code = XXXXb

Block Address = 000b

Word Address = E3H

Data = 8EH?

Data = Data + 01H

Control Code = XXXXb

Block Address = 010b

Word Address = 00H

Page Write

Command

Wait 20ms

Sequential

Read for

Verify

Data

Correct

Fail

Word

Address

= E0H?

Done

Word Address =

Word Address +

10H

Yes

SLG46824/6

2 Programming Algorithm for NVM Configuration Register Space

The SLG46824 and SLG46826 programming algorithm for the NVM Configuration space consists of a series of I2C Sequential Write commands, each of which will program one 16 byte page of NVM memory (Note 1).

Data “1” cannot be re-programmed as data “0” without erasure. Each byte can only be programmed one time without erasure.

Note 1: The functionality of the device is based upon the registers. The registers will not be reloaded from the NVM until power is cycled or a reset command is

issued.

The SLG46824 and SLG46826 can be programmed either with or without an acknowledge polling routine. The acknowledge polling routine is implemented to optimize time sensitive applications that would prefer not to wait the fixed maximum write cycle time (t

operation can be started.

). This method allows the application to know instantly when the NVM write cycle has completed so a subsequent

Figure 3: Flowchart for Programming NVM without Acknowledge Polling

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VDD

POR Delay

Control Code = XXXXb

Block Address = 000b

Word Address = E3H

Data = 8EH?

Data = Data + 01H

Control Code = XXXXb

Block Address = 010b

Word Address = 00H

Page Write

Command

Data

Correct

Fail

Word

Address

= E0H?

Done

Word Address =

Word Address +

10H

Yes

Seq.

Read for

Verify

Not Acknowledged

Acknowledged

SLG46824/6

Figure 4: Flowchart for Programming NVM with Acknowledge Polling

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X X X X

A 9

A 8

Control Byte Word Address (n)

Control

Code

Block

Address

R/W bit

ACK

Acknowledge

bit

Start

bit

Data (n)

Stop

bit

SDA LINE

Bus Activity

ACK

Data (n+1)

ACK

Data (n + 15)

Acknowledge

bit

ACK

A 7

A 6

A 5

A 3

A 2

A 1

A 0

X X X X

A 9

A 8

Control Byte Word Address (n)

Control

Code

Block

Address

Read bit

ACK

Acknowledge

bit

Start

bit

Control Byte

Stop

bit

SDA

LINE

Bus Activity

ACK

Data (n)

ACK

Data (n + x)

No Ack

bit

XXX A

A 9

Read bit

Control

Code

Block

Address

edge

SLG46824/6

3I2C Signal Specifications

3.1 COMMANDS

3.1.1 Write Command

Write access to the NVM is possible by setting A3 A2 A1 A0 to "0000", which allows serial write data for a single page only. Upon receipt of the proper Control Byte and Word Address bytes, the SLG46824/6 will send an ACK. The device will then be ready to receive page data, which is 16 sequential writes of 8-bit data words. The SLG46824/6 will respond with an ACK after each data word is received. The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition after all page data is written. At that time the GPAK will enter an internally self-timed write cycle, which will be completed within

= 20 ms (max). While the data is being written into the NVM Memory Array, all inputs, outputs, internal logic and I2C access

to the Register data will be operational/valid.

Figure 5: Page Write Command Example

3.1.2 Verify Command

The Random Sequential Read command can be used for verification. The command starts with a Control Byte (with R/W bit set to "0", indicating a write command) and Word Address to set the internal byte address, followed by a Start bit, and then the Control Byte for the read (exactly the same as the Byte Write command). The Start bit in the middle of the command will halt the decoding of a Write command, but will set the internal address counter in preparation for the second half of the command. After the Start bit, the Bus Master issues a second Control Byte with the R/W bit set to "1", after which the SLG46824/6 issues an Acknowledge bit, followed by the requested eight data bits. Once the SLG46824/6 transmits the first data byte, the Bus Master issues an Acknowledge bit. The Bus Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition.

Figure 6: Random Sequential Read Command

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SLG46824/6

3.1.3 Erase Command

The erase scheme allows a 16 byte page in the emulated EEPROM (Note 2) space or the 2K bits NVM chip configuration space to be erased by modifying the contents of the Erase Register (ERSR). When the ERSE bit is set in the ERSR register, the device will start a self-timed erase cycle which will complete in a maximum of t accomplished with a Byte Write sequence with the requirements outlined in this section. The ERSR register is located on the E3H address.

Note 2: Emulated EEPROM is available for SLG46826 only.

Table 2: Erase Register Bit format

b7 b6 b5 b4 b3 b2 b1 b0

Page Erase

ERSE -- -- ERSEB4 ERSEB3 ERSEB2 ERSEB1 ERSEB0

Table 3: Erase Register Bit Function Description

Bit Name Typ e Description

7ERSE

Erase

Enable

Setting b7 bit to “1” will start in internal erase cycle on the page defined by ERSEB4-0

6-- -- ----

5-- -- ----

4 ERSEB4

3 ERSEB3 W

2 ERSEB2 W

1 ERSEB1 W

Page Selection for Erase

Define the page address, which will be erased. ERSB4 = 0 corresponds to the Upper 2K NVM used for chip configuration; ERSB4 = 1 corresponds to the 2-k emulated EEPROM (Note 2).

0 ERSEB0 W

= 20 ms (max). Changing the state of the ERSR is

Upon receipt of the proper Device Address and Erase Register Address, the SLG46824/6 will send an ACK. The device will then be ready to receive Erase Register data. The SLG46824/6 will respond with a non-compliant I

C ACK after the Erase Register data word is received. Please reference the SLG46824/6 errata document (revision XC) posted on Dialog’s website for more information. The addressing device, such as a bus Master, must then terminate the write operation with a Stop condition. At that time, the GPAK will enter an internally self-timed erase cycle, which will be completed within t

(max 20 ms). While the data is

being written into the Memory Array, all inputs, outputs, internal logic and I2C access to the Register data will be operational/valid.

After the erase has taken place, the contents of ERSE bits will be set to "0" automatically. Erase will be triggered by Stop Bit in

C command.

3.2 ADDRESSING

Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are shown in Figure 7. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently from the register or by value defined externally by IO5, IO4, IO3 and IO2. The LSB of the control code is defined by the value of IO2, while the MSB is defined by the value of IO5. The address source (either register bit or PIN) for each bit in the control code is defined by reg <1623:1620>. This gives the user flexibility on the chip level addressing of this device and other devices on the same I

C bus. The default control code is 0001. The Block Address is the next three bits (A10,A9, A8), which will define the most significant bits in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit, which selects whether a read command or write command is requested, with a "1" selecting for a Read command, and a "0" selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data

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X X X X

A 9

A 8

R/W

Control Byte

Control

Code

Block

Address

Read/Write bit

ACK

Acknowledge

bit

Start

bit

Word Address

A 0

A 7

2 Kbits Register Data Configuration

Not Used

2 Kbits NVM Data Configuration

2 Kbits EEPROM (Note 2)

Not Used

I2C Block Address

Memory Space

A10 = 0

A10 = 1

A9 = 0

A9 = 1

A9 = X

A8 = 0

A8 = 1

A8 = 0

A8 = 1

A8 = X

Lowest I2C

Address = 000h

Highest I

Address = 7FFh

A10 = 0

16 pages to

configure GPAK

16 pages for

emulated

EEPROM

(Note 2)

SLG46824/6

4 Memory Spaces

4.1 MEMORY MAP

Figure 7: Page Write Command

In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of information, resulting in a total address space of 16K bytes. Valid addresses are shown in the memory map in Figure 8.

Figure 8: I

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C Block Addressing

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2 Kbits Register Data

Configuration

Not Used

2 Kbits NVM Registers

2 Kbits EEPROM

Not Used

000H

7FFH

200H

300H

Function Page # EEPROM Emulation Page 0 0 EEPROM Emulation Page 1 1 EEPROM Emulation Page 2 2 EEPROM Emulation Page 3 3 EEPROM Emulation Page 4 4 EEPROM Emulation Page 5 5 EEPROM Emulation Page 6 6 EEPROM Emulation Page 7 7 EEPROM Emulation Page 8 8 EEPROM Emulation Page 9 9 EEPROM Emulation Page 10 10 EEPROM Emulation Page 11 11 EEPROM Emulation Page 12 12 EEPROM Emulation Page 13 13 EEPROM Emulation Page 14 14 EEPROM Emulation Page 15 15

Function Page # Matrix Output 0 Matrix Output 1 Matrix Output 2 Matrix Output 3 Reserved 4 Reserved 5 I/Os 6 I/Os + Matrix Input 7 OSC/ACMP/VREF 8 Digital Macrocells 9 Multi-Function Macrocells 10 Pattern ID 11 Reserved 12 Reserved 13 Protection Page 14 Service Page 15

SLG46824/6

Figure 9: I2C Address Mapping

4.2 SPECIAL PAGES

GreenPAK's internal NVM memory is divided into 32 pages which hold 16 bytes each. 16 pages are used to configure the GreenPAK, and the other 16 are used for the emulated EEPROM (Note 2) function.

4.2.1 Protection Page

Page #14 inside the 2Kbits NVM Registers memory space is a dedicated protection page. All 16 bytes of Page #14 are dedicated to protection settings, even though only 3 of those bytes are used. The whole page is used because a page is the smallest NVM section that can be programmed/erased or blocked for erase/program.

Once the user determines the security setting, they can do an NVM page 14 programming (program the security setting and set security page lock bit = 1). The changes to the Protection Page will not be active until the device is reset. The user can do an immediate reset using one of the following methods:

Power down the device, then power it back on Perform a soft reset using an I

This will allow the memory interface circuit to know that page 14 (security page) is write/erase protected.

4.2.2 Service Page

Page #15 inside the 2Kbits NVM Registers memory space contains reserved information that is preprogrammed during device final test. The information on this page can be Read but not Written by the user. As this page cannot be altered by the user, the programming algorithm does not need to address this page.

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VDD

POR Delay

Control Code = XXXXb

Block Address = 000b

Word Address = E3H

Data = 9FH?

Data = Data + 01H

Control Code = XXXXb

Block Address = 011b

Word Address = 00H

Page Write

Command

Wait 20ms

Sequential

Read for

Verify

Data

Correct

Fail

Word

Address

= E0H?

Done

Word Address =

Word Address +

10H

Yes

SLG46824/6

5 Programming Algorithm for the Emulated EEPROM Space

The SLG46824 and SLG46826 programming algorithm for the emulated EEPROM (Note 2) space consists of a series of I2C Sequential Write commands, each of which will program one 16 byte page of NVM memory.

Data “1” cannot be re-programmed as data “0” without erasure. Each byte can only be programmed one time without erasure.

Programming of the emulated EEPROM (Note 2) follows a similar flow to programming of the NVM with two differences:

 Block Address for emulated EEPROM (Note 2) is 011b (in contrast to the NVM Configuration Registers Block Address, which

is 010b)

 With emulated EEPROM (Note 2), all 16 pages are user accessible.

Figure 10: Flowchart for Programming EEPROM without Acknowledge Polling

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VDD

POR Delay

Control Code = XXXXb

Block Address = 000b

Word Address = E3H

Data = 9FH?

Data = Data + 01H

Control Code = XXXXb

Block Address = 011b

Word Address = 00H

Page Write

Command

Data

Correct

Fail

Word

Address

= E0H?

Done

Word Address =

Word Address +

10H

Yes

Seq.

Read for

Verify

Not Acknowledged

Acknowledged

SLG46824/6

Figure 11: Flowchart for Programming Emulated EEPROM with Acknowledge Polling

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SLG46824/6

6 Protection for Emulated EEPROM

The SLG46824/6 utilizes a software scheme that allows a portion or the entire emulated EEPROM (Note 2) to be inhibited from being written/ erased to by modifying the contents of the Write Protection Register (WPR). If desired, the WPR can be set so that it may no longer be modified/erased, thereby making the current protection scheme permanent. The status of the WPR can be determined by following a Random Read sequence. Changing the state of the WPR is accomplished with a Byte Write sequence with the requirements outlined in this section.

The WPR register is located on I the WPR bit functions are included in Table 5.

Table 4: Write/Erase Protect Register Format

b7 b6 b5 b4 b3 b2 b1 b0

WPR WPRE WPB1 WPB0

Table 5: Write/Erase Protect Register Bit Function Description

Bit Name Type Description

2WPRE

WPB1

1:0

WPB0 R/W

C Block Address = 000b, I2C Word Address = E2H.The WPR format is shown in Table 4, and

Write Protect

Block Bits

R/W

R/W 00: Upper quarter of emulated EEPROM (Note 2) is write protected

0: No Software Write Protection enabled (default) 1: Write Protection is set by the state of WPB[1:0] bits

(default) 01: Upper half of emulated EEPROM (Note 2) is write protected 10: Upper 3/4 of emulated EEPROM (Note 2) is write protected. 11: Entire emulated EEPROM (Note 2) is write protected.

Write Protect Enable (WPRE): The Write Protect Enable Bit is used to enable or disable the device Software Write/Erase Protect. A Logic 0 in this position will disable Software Write/Erase Protection, and a Logic 1 will enable this function.

Write Protect Block Bits (WPB1:WPB0): The Write Protect Block bits allow four levels of protection of the Memory Array, provided that the WPRE bit is a Logic 1. If the WPRE bit is a Logic 0, the state of the WPB1:0 bits have no impact on device protection.

Protect Lock Bit (PRL): The Protect Lock Bit is used to permanently lock the current state of the WPR, as well as RPR and NPR. A Logic 0 indicates that the WPR, RPR, and NPR can be modified, whereas a Logic 1 indicates the WPR, RPR, and NPR has been locked and can no longer be modified. The PRL register bit is located at reg <1824>.

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Glossary

ACK Acknowledge bit

ERSE Erase Enable

ERSR Erase Register

IO Input/Output

LSB Least Significant Bit

MSB Most Significant Bit

NPR Non-Volatile Memory Read/Write/Erase Protection

NVM Non-Volatile Memory

PRL Protect Lock Bit

R/W Read/Write

reg Register

RPR Register Read/Write Protection

SCL I

SDA I

WPB Write Protect Block Bits

WPR Write Protection Register

WPRE Write Protect Register Enable

C Clock Input

C Data Input/Output

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Revision History

Revision Date Description

1.1 4-Mar-2019

1.0 13-Feb-2018 Initial release

Status Definitions

Status Definition

DRAFT The content of this document is under review and subject to formal approval, which may

APPROVED OR unmarked The content of this document has been approved for publication

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Updated Flowcharts Added a reference to the NVM and EEPROM Erase Register erratum in section 3.1.3”

result in modifications or additions

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Dialog Semiconductor SLG46824, SLG46826 Programming Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Introduction

1 Hardware Requirements

1.1 PINOUT AND SIGNALS

2 Programming Algorithm for NVM Configuration Register Space

3I2C Signal Specifications

3.1 COMMANDS

3.1.1 Write Command

3.1.2 Verify Command

3.1.3 Erase Command

3.2 ADDRESSING

4 Memory Spaces

4.1 MEMORY MAP

4.2 SPECIAL PAGES

4.2.1 Protection Page

4.2.2 Service Page

5 Programming Algorithm for the Emulated EEPROM Space

6 Protection for Emulated EEPROM

Glossary

Revision History