User Manual
DA1469x PRO Development Kit
UM-B-093
Abstract
DA1469x Development Kit Pro hardware provides a tested reference platform, access to all signals
for connecting peripherals, and advanced debugging features.
UM-B-093
DA1469x PRO Development Kit
User Manual
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Contents
Abstract ................................................................................................................................................ 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 2
Tables ................................................................................................................................................... 3
1 Terms and Definitions ................................................................................................................... 4
2 References ..................................................................................................................................... 4
3 DA1469x DK PRO Hardware Architecture and Implementation ............................................... 5
3.1 Introduction ........................................................................................................................... 5
3.2 Features ................................................................................................................................ 5
3.3 DA1469x PRO DK Hardware Block Diagram ....................................................................... 5
3.4 Main Features of Mainboard in DA1469x PRO DK .............................................................. 6
3.5 User Accessible Elements in DA1469x PRO DK .................................................................. 8
3.6 DA1469x PRO DK Daughterboard (db-VFBGA-100 and db-LFBGA-86) ............................. 9
3.7 Current Measurement Section in DA1469x DK PRO ......................................................... 12
3.8 DA1469x PRO DK Power Block Diagram ........................................................................... 12
........................................... 14
................................................................... 15
3.11 GPIO Assignments .............................................................................................................. 16
3.12 Jumper/DIP Switch Settings ............................................................................................... 18
3.13 QSPI-RAM Operation .......................................................................................................... 18
3.14 Test Section ........................................................................................................................ 18
Revision History ................................................................................................................................ 21
Figures
Figure 1: System Block Diagram ........................................................................................................... 5
Figure 2: DA1469x DK PRO Mainboard Breakout Headers ................................................................. 6
Figure 3: VBAT Adjustable LDO ............................................................................................................ 6
Figure 4: DIP Switch .............................................................................................................................. 7
Figure 5: Arduino Sockets ..................................................................................................................... 7
Figure 6: MikroBUS sockets .................................................................................................................. 7
Figure 7: Main Accessible Features in Main Board/Daughter Board in DA1469x PRO DK ................. 8
Figure 8: DA1469x PRO DK Daughterboard ......................................................................................... 9
Figure 9: USB Overvoltage Protection .................................................................................................. 9
Figure 10: Power Options .................................................................................................................... 10
Figure 11: Connection to Mainboard ................................................................................................... 10
Figure 12: CIB Debugging Header ...................................................................................................... 11
Figure 13: LED Powering Circuit ......................................................................................................... 11
Figure 14: DA1469x PRO DK Power Distribution Diagram ................................................................. 12
Figure 15: 3.3V LDO for USB Hub ...................................................................................................... 13
Figure 16: 3.3 V LDO for Mainboard Peripherals ................................................................................ 13
Figure 17: Op-Amps/ADC 5.0 V Power Supply ................................................................................... 13
Figure 18: Negative Supply for Op-Amps ............................................................................................ 14
Figure 19: Voltage Level Translation Circuit ....................................................................................... 15
Figure 20: Mainboard/Daughterboard Alignment ................................................................................ 16
Figure 21: QSPI-RAM .......................................................................................................................... 18
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Tables
Table 1: Signals with Level Translation ............................................................................................... 14
Table 2: Mainboard/Daughterboard Mating Connectors ..................................................................... 15
Table 3: Mainboard/Daughterboard Pin Assignment .......................................................................... 16
Table 4: Default Jumper Settings ........................................................................................................ 18
Table 5: Mainboard Test Points (Placed on the Bottom Of DA1469x PRO DK) ................................. 18
Table 6: Daughterboard Test Points ................................................................................................... 20
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1 Terms and Definitions
BLE Bluetooth Low Energy
CIB Communication Interface Board
DB Daughterboard
LRA Linear Resonant Actuator
ERM Eccentric Rotating Mass
GPIO General Purpose Input Output
HDK HW Development Kit
I2C Inter-Integrated Circuit
JTAG Join Test Action Group
LDO Low Dropout
LRA Linear Resonant Actuator
MB Motherboard
MISO Master In Slave Out
MOSI Master Out Slave In
NTC Negative temperature coefficient (resistor)
OVP Over Voltage Protection
PCB Printed Circuit Board
PRS Product Requirement Specification
QSPI Quad Serial Peripheral Interface
RF Radio Frequency
RFIO Radio Frequency Input Output
SDK SW Development Kit
SIMO Single-Inductor Multiple-Output
SOC System on Chip
SPI Serial Peripheral Interface
SW Software
SWD Serial Wire Debug
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus
2 References
[1] DA1469x, Datasheet, Dialog Semiconductor.
[2] AN-B-052, DA1458x/68x Development Kit J-Link Interface, Application Note, Dialog
Semiconductor.
[3] AN-B-037, DA1468x Power Measurements, Application Note, Dialog Semiconductor.
[4] DA1469x Pro Development Kit Mainboard Schematics, Reference Design, Dialog
Semiconductor.
[5] DA1469x Pro Development Kit VFBGA-100 Schematics, Reference Design, Dialog
Semiconductor.
[6] DA1469x Pro Development Kit VFBGA-86 Daughterboard Schematics, Reference Design,
Dialog Semiconductor.
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3 DA1469x DK PRO Hardware Architecture and Implementation
3.1 Introduction
The DA1469x development kit PRO is available as a mainboard providing a socket for one of two
variants of daughterboard (VFBGA-100/LFBGA-86).
Our engineers have paid special attention in designing this DK to provide trouble-free user
experiences and to keep compatibility with existing tools from DA1458x/DA1468x/ product lines.
When combined with the DA1469x SDK and SmartSnippets tools, the DA1469x DK PRO provides an
easy-to-use and complete platform for software/hardware development.
3.2 Features
■ Flexible battery options
■ QSPI-Flash memory for booting
■ Headers for I/O monitoring and expandability
■ Option to support Arduino shields
■ Option to support MikroBUS click boards
■ Provisions for automated test
■ On-board basic peripherals for demo and development
■ JTAG debugger and connectivity to PC
■ Look and feel similar to DA14680 PRO DK
■ DA1469x silicon easily replaceable on a daughterboard core module
3.3 DA1469x PRO DK Hardware Block Diagram
Figure 1: System Block Diagram
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3.4 Main Features of Mainboard in DA1469x PRO DK
■ Main USB connector
NOTE
USB host must support USB 2.0 high-speed for reliable power measurements.
■ USB hub with two downstream ports:
□ Port1: SEGGER JLink-OB SWD-JTAG debugger for ARM Cortex M33
□ Port2: FT2232H multiprotocol serial interface providing a booting/debugging/HCI UART (2-pin
or 4-pin) and SPI connected to the current measurement circuit Analog/Digital converter
■ Low profile Connectors mating to the 69x daughterboard
■ Breakout Headers (Figure 2, two pieces, 2 × 20 pins in each piece) for monitoring GPIO and
power signals, with markings of signal names on the PCB top silkscreen
Figure 2: DA1469x DK PRO Mainboard Breakout Headers
■ Headers for the dedicated LRA/ERM haptic motor driver pins
■ One user button K1, connected to a GPIO through a jumper
■ LDO adjustable from 1.8 V up to 4.2 V to supply the VBAT pin (default 3.0 V)
Figure 3: VBAT Adjustable LDO
P1_1
P1_0
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2 P1_12
P1_11
P1_10
P1_9
P1_8
P1_13
P1_18
P1_17
P1_16
P1_15
P0_17
P1_22
P1_21
P1_20
P1_19
P1_14
P0_29
P0_30
P0_26
P0_18
P0_8
P0_28
P0_19
P0_24
P0_6
P0_16
P0_27
P0_20
P0_25
P0_9
P0_7
P0_21
P0_0
P0_3
P0_2
P0_1
P0_31
P0_12
P0_11
P0_10
P0_5
P0_4
P0_23x
P0_22x
P0_15x
P0_14x
P0_13
LED2
LED1
RSTn
VBAT_IN
V12
V14
V18
V18P
V30
J3
3020-40-0300-00
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J4
3020-40-0300-00
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
R127
100.0k
C115
10nF
TP11
VFB
1.8V OPEN
R93
8.06k
ADJ PLACE 1-2
3.0V PLACE 2-3
R24
0
VBUS_HUB
U5
AP2127K-ADJTRG1
Vin
1
GND
2
3
SHDN
4
ADJ
OUT
5
R25
9.53k
C20
1.0uF
C21
1.0uF
PWR_ENABLE
VLDO
R23
12.0k
R121
3.9k
J5
87898-0455
LP5
500mA_470 OHM
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■ Circuit to measure/monitor the current from LDO to VBAT
□ Software trigger support for SmartSnippets Toolbox (driven from a DA1469x GPIO, P0_16,
through a jumper)
■ DIP switch to isolate UART and JTAG signals (in case we need to secure the most accurate
sleep current measurements, Figure 4)
□ The board is shipped with all switches at the “ON” position (all signals connected to the
related DA1469x pins)
□ Signal names are marked on PCB top silkscreen
Figure 4: DIP Switch
■ Test points (TP) for automated production test (placed on the bottom of the board)
■ Ground points (TP28 and TP29) for connecting crocodile clips
■ QSPI-RAM option (not populated)
■ Optional Arduino sockets (supporting 3.3 V compatible Arduino shields)
Figure 5: Arduino Sockets
■ Optional 2× MikroBUS sockets (supporting 3.3 V compatible click boards from MikroElektronika
or other sources)
Figure 6: MikroBUS sockets
TP49
TP54
TP52
TP48
TP50
TP51
P0_11
P0_10
M33_SWCLK
M33_SWDIO
S1
97C06SRT
1
2
3
4
12
11
10
9
5 8
6 7
P0_9
P1_0
P0_8URX
URTS
P0_7
UTX
UCTS
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3.5 User Accessible Elements in DA1469x PRO DK
Figure 7: Main Accessible Features in Main Board/Daughter Board in DA1469x PRO DK
1. USB connector on mainboard for power and communication interface
2. Connector for CIB cable (option for JTAG/UART in standalone daughterboard)
3. Reset button
4. USB connector on daughterboard, which is an alternative power option and connects to
DA1469x USB data pins
5. Power selector switch [LDO or battery]
6. Header for current measurement circuit input (J9.1-2)
7. Header for current measurement circuit output (J9.3-4)
8. Header (J8.1-2) for enabling user button (K1 on mainboard)
9. Software trigger header (J8.3-4)
10. DIP switch (S1) connecting the debugging interface signals (JTAG/UART)
11. LDO voltage selection header, J5, (3.0 V as default, can be adjustable from 1.8 V to 4.2 V)
12. Trimmer to define the adjustable LDO voltage (R127)
13. User button (K1)
14. RF coaxial switch (J7 on daughterboard)
15. Signal/Power breakout headers (J3 and J4)
16. LRA/ERM interface header (J10)
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3.6 DA1469x PRO DK Daughterboard (db-VFBGA-100 and db-LFBGA-86)
Figure 8: DA1469x PRO DK Daughterboard
● DA1469x in micro-BGA package (U1)
● Crystals with frequencies of 32 MHz and 32.768 kHz, (Y1 and Y2, respectively)
● QSPI Flash (SOIC-8 or USON-8 package), the default of which is W25Q80EWSNIG (8 Mbit),
(U2)
● Printed RF antenna (ANT1)
● Coaxial switch for conducted RF measurements (J7)
● Reset button, K1(RESET)
● USB connector for charging and data communications (supporting USB 2.0 full speed), (J3)
● OVP circuit on the VBUS power input (Figure 9)
Figure 9: USB Overvoltage Protection
● Battery/Power connectors (Figure 10):
Q2
DMP3099L-7
3
1
2
DIODES Inc.
R22
2.2k
R23 4.7k
D4
BZX84C5V6-7-F
1
3
Q5
BC807-25_215
3
1
2
R9 NP
VBUS
VBUS_IN
R18
10.0k
C13
100nF
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○ 2-pin connector for Li-Ion/LiPo (J6, default)
○ Optional coin cell holder (unpopulated, CR2032 type)
○ Power selector switch (can be used as on-off switch), (SW1)
Figure 10: Power Options
● Low profile connectors (2×, placed on the bottom of the PCB, Figure 11) matching a set of mating
connectors on the main board (J1, J2)
Figure 11: Connection to Mainboard
● CIB debugging connector (Figure 12):
○ SWD pins connected to Cortex M33 core
○ Reset from JLink-OB or button on the CIB board
○ 2-pin UART signals connected to bootable UART pins
LDO/DBG
VBAT_IN
SW1
SW_MA12R_TR
3 2 1
6 7
89
J6
53261-0271
1
2
3
4
LiPO
VBAT
D6
ACPDQC24VE-HF
2
1
+
BT1
NP
COIN
P1_15
P1_7
P1_2
P1_1
P1_22
P1_21
P1_20
P1_19
P1_18
P1_13
P1_12
P1_10
P1_9
P1_6
P1_11
P1_14
P1_17
P1_16
VBAT_IN
P0_30
P0_19
P0_20
P0_7
J2
10132798-052100LF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VBAT_IN
P0_29
P0_26
P0_31
P0_27
P0_25
P0_28
P0_24
VBAT
VBATn
VBUS
LED2
P0_15x
P0_14x
LED1
V18P
V18
V30
VLED
P1_8
V14
V12
P1_4
P1_0
P1_5
P1_3
P1_1
RSTn
J1
10132798-052100LF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P0_21
P0_6
P0_16
P0_18
P0_8
P0_17
P0_0
P0_3
P0_2
P0_1
P0_9
P0_12
P0_11
P0_10
P0_5
P0_4
HDRVP
HDRVM
VBUSn
P0_23x
P0_22x
P0_13
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○ Can provide power to the daughterboard in stand-alone operation
Figure 12: CIB Debugging Header
● RGB LED, (D3)
NOTE
The RGB LED is only available on the DA14699 daughterboard.
○ Green and Blue segments connected to dedicated LED driver pins
○ Red segment connected to a MOSFET driven by a GPIO
○ Circuit for powering the LED from either VBUS or VBAT
○ Option to power the LEDs from the 6.0 V available on the mainboard. If this option is chosen,
the SmartSnippets Toolbox measurement will exclude the LED current
Figure 13: LED Powering Circuit
● ESD protection diodes at the most susceptible points (USB connector J3, CIB interface J4, and
power selector switch SW1)
● Possibility to operate stand-alone (without the mainboard), powered from one of these options:
VBAT_IN
D3
D5V0P4B5LP08-7
1
2
3
4
5
URX
SWDIO
UTX
SWCLK
J4
Jtag_Conn_2x5_1mm27
VDD
7
DIO
4
CLK
3
URX
2
UTX
1
RST
6
VPP
5
GND1
8
NC19GND2
10
R13 NP
R11 0 R12 NP
R10 0
J4_RESET
P0_9
P0_8
P0_13
P0_12P0_11
P0_10
R3 0
R4 0
D5
BAT54CLT1G
132
D9
NP
2 1
TP66
VLED
VLED
6.0V
P1_1
Option on the
mainboard
VBATn
VLED
TP18
VLED
C11
4.7uF
D1
LTST-C19HE1WT
123
4
BLUE
GREEN
LED1
LED2
RED
VBUSn
Q1B
DMN63D8LDWQ-7
4
5
3
R16
NP
R17
150
R14
NP
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○ Li-Ion/LiPo/coin Battery
○ USB connector
○ CIB interface (providing also JTAG/UART debugging functions)
3.7 Current Measurement Section in DA1469x DK PRO
● Following the DA1469x DK current measurement topology and circuitry
● Full scale range 250 mA
● Measurement accuracy down to 1 µA
● Current sense resistors of 2.37 Ω in series to VBAT
● FTDI chip for transferring data to the PC
● Analog processing blocks
● Software trigger circuit
● Fast 24-bit ADC with SPI interface
● Known limitation: measurement accuracy between 500 µA and 1 mA is worse than the typical 1%
we have in all other cases (from 1 µA to 250 mA)
3.8 DA1469x PRO DK Power Block Diagram
Figure 14: DA1469x PRO DK Power Distribution Diagram
● USB on the daughterboard (feeding VBUS pin)
● Li-ion/Li-Po/coin battery on the daughterboard (VBAT)
● Debugging (CIB) port on the daughterboard (VBAT)
● Adjustable LDO (default) supplied by the USB connector on the main board (VBAT). This is the
only option where current can be measured by SmartSnippets Toolbox. By default, the LDO
provides 3.0 V.
The debugging section consists of JTAG, UART, and current sense circuitry. This section is supplied
from the mainboard USB connector.
The USB Hub has its own dedicated 3.3 V LDO (U13, always on, Figure 15).
CC/CV CHARGER
V18 V18P V14 V12
V18F
VBAT1
VBAT2
VBAT
VBUS
BATTERY
VBAT
LDO
USB HUB
V33
HUB
LDO
V33
DIG
LDO
JLINK
FTDI
ADC
ANALOG
LDOs
ADC 5V
OpAmp 5V
OpAmp -Vgg
VBUS_HUB
DA1469x daughterboard
V30
SIMO DCDC
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Figure 15: 3.3V LDO for USB Hub
The remaining support circuits on the mainboard are powered by a second 3.3 V supply (U14). This
powers SEGGER (U4), FTDI (U12), and ADC (U8).
U14 is enabled by a signal coming from the USB hub. This signal (PWR_ENABLE) goes high after
the hub has successfully enumerated with a USB host. If we need to operate the system without a
host, for example, with an AC wall adapter, we need to solder a header on J6 and place a jumper.
Figure 16: 3.3 V LDO for Mainboard Peripherals
The analog/digital converter and several op-amps on the current measurement section need a clean
5.0 V power supply (Figure 17). This is generated by a step-up regulator (U18) which generates 6.0
V, and U18 is followed by a 5 V LDO (U17). U18 is also controlled by PWR_ENABLED.
Figure 17: Op-Amps/ADC 5.0 V Power Supply
VBUS_HUB
TP23
+3V3
C77
1.0uFC76
22nF
C75
1.0uF
U13
RT9193-33GB
VIN
1
GND
2
EN3BP
4
VOUT
5
VDD_3V3_HUB
LP8
500mA_470 OHM
R70
330
D5
LED green
2
1
LP9
500mA_470 OHM
U14
RT9193-33GB
VIN
1
GND
2
EN3BP
4
VOUT
5
C78
22nF
C80
1.0uF
C79
1.0uF
PWR_ENABLE
3.3VA
LP10
500mA_470 OHM
C104
NP
3.3V
R71
10.0k
J6
NP
VDD_3V3_PERF
VBUS_HUB
TP38
3.3V
TP40
3.3VA
TP41
PWRLED
TP39
5.0V
U17
MIC5205-5.0YM5
IN
1
GND
2
EN3BP
4
OUT
5
5.0V
C86
4.7uF
LP13
500mA_470 OHM
TP37
6.0V
6.0V
C88
1.0nF
D8
RB521S30T1G
2 1
L2
FLF3215T-100M
C105
100nF
PWR_ENABLE
LP1
500mA_470 OHM
R85
0
R84
10.0k
R83 38.3k
C85
1.0uF
C89
1.0uF
C87
1.0uF
3.3V
U18
AP3012KTR-G1
VIN
5
FB
3
SHDN
4
SW
1
GND
2
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The Op-Amps also require a small negative supply (-0.232 V) generated by U20 (Figure 18).
Figure 18: Negative Supply for Op-Amps
Voltage translation is required because the DA1469x I/O voltage varies depending on the battery
level and setting for the I/OLDO (V30).For example, if the other side (on board interfaces,
JTAG/UART) is fixed at 3.3 V, there is a leakage through the pins if the DA1469x voltage I/Os are at
3.0 V or less.
Table 1: Signals with Level Translation
Pin Name
Signal Name
P0_10
SWDIO
P0_11
SWCLK
P0_9
UTX
P0_8
URX
P1_0
URTS
P0_7
UCTS
TP70
-Vgg
C112
100nF
VDD_3V3_PERF
U20
LM7705
CF+
1
VSS
2
SD
3
VDD
4
CF-
8
VSS
5
VOUT
6
CRES
7
C109
4.7uF
C110 4.7uF
C111
10uF
-Vgg
C113
10uF
LP3
500mA_470 OHM
C114
100nF
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Figure 19: Voltage Level Translation Circuit
VDDIO is a buffered version of the voltage used in the I/O from DA1469x side. This powers a triple
buffer gate (U22) with the direction from mainboard to DA1469x pins and also the single bidirectional
transceiver used for SWDIO (U21) on the DA1469x side.
The direction of signals from DA1469x to the mainboard is handled by U23 powered from the
mainboard 3.3 V.
The DA1469x debugging pins can be disconnected by the associated main board peripherals
through the multiple DIP-switch S1.
The daughterboard can be placed on top of the mainboard via two low-profile SMD connectors,
which are specified for a limited number of mating cycles (50).
Table 2: Mainboard/Daughterboard Mating Connectors
Main Board
Daughter Board
Amphenol FCI
10132797-055100LF
Amphenol FCI
10132798-052100LF
NOTE: The connectors have no polarity feature, so please be careful not to connect the
daughterboard rotated by 180°. Small arrows on the top silk screens of both boards are added to
indicate a properly aligned placement (Figure 20). The arrows on the mainboard must point to the
arrows on the daughterboard.
VOLTAGE LEVEL TRANSLATION
R72
33
VDDIO
VDDIO
BRSTn
VDDIO
M33_SWDIO
R149
100.0k
T_SWDIO
3.3V
U21
NTB0101GW_125
1
VCCA
A
3
2
GND
OE
5
B
4
6
VCCB
C3
1.0nF
C4
100nF
R4
0
R148
Mohm: 10M
LP11
500mA_470 OHM
C116
1.0nF
R1
NP
3.3V
R147
NP
UCTS
URX
T_SWCLK
U_CTS
U_RX
TP49
TP54
TP52
TP48
TP50
TP51
R3
100.0k
U22
NC7NZ34K8X
1A
1
GND
4
2A32Y
5
VCC
8
1Y
7
3A63Y
2
P0_11
P0_10
M33_SWCLK
M33_SWDIO
S1
97C06SRT
1
2
3
4
12
11
10
9
5 8
6 7
P0_9
P1_0
P0_8URX
URTS
P0_7
UTX
UCTS
M33_SWCLK
V30 VREF
-
+
U1
LMV321AS5X
1
3
4
5
2
C1
100nF
5.0V
BRSTn
3.3V
RSTn
C117
100nF
U_TX
U_RTS
UTX
URTS
U23
NC7NZ34K8X
1A
1
GND
4
2A32Y
5
VCC
8
1Y
7
3A63Y
2
TP44
VDDIO
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Figure 20: Mainboard/Daughterboard Alignment
3.11 GPIO Assignments
Table 3: Mainboard/Daughterboard Pin Assignment
Pin Name
DK Function
Comments
P0_0
QSPIR_D0
QSPI RAM for parallel LCD framebuffer.
1.8 V only.
P0_1
QSPIR_D1
P0_2
QSPIR_D2
P0_3
QSPIR_D3
P0_4
QSPIR_CSn
P0_5
QSPIR_CLK
P0_6
GP_BUTT
P0_7
UCTS
P0_8
URXD
P0_9
UTXD
P0_10
M33 SWDIO
P0_11
M33 SWCLK
P0_12
P0_13
P0_14
USB_DP
Daughterboard USB
P0_15
USB_DM
P0_16
C_TRIG
software trigger
P0_17
P0_18
P0_19
P0_20
P0_21
P0_22
XTAL32km
Daughterboard xtal 32.768kHz
P0_23
XTAL32kp
P0_24
P0_25
P0_26
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Pin Name
DK Function
Comments
P0_27
P0_28
P0_29
P0_30
P0_31
P1_0
URTS
P1_1
RGB LED (RED)
Daughterboard LED
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
P1_16
P1_17
P1_18
P1_19
P1_20
P1_21
P1_22
LED1
RGB LED (BLUE)
Daughterboard LED
LED2
RGB LED (GREEN)
HDRVP
J10 HEADER
LRA/ERM motor driving pins
HDRVM
RSTn
RESET (active low)
Daughterboard button
Note 1 USB and XTAL32k signals are typically not connected to the mainboard breakout headers. Series
resistors must be placed on the daughterboard to connect these signals.
Note 2 LCD (various types), micro-motor drive, ADC inputs, NTC (charger), and sleep mode PWM outputs
are available on specific pins only. Check the DA1469x datasheet [1] for more details.
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3.12 Jumper/DIP Switch Settings
Table 4: Default Jumper Settings
Jumper Block
Default Position
Comment
J5
2-3
Selects 3.0 V as default VBAT
J6
not placed
J8
1-2 & 3-4
button (K1) and C_TRIG
J9
1-2 & 3-4
Current measurement input and output
J10
1-2 no jumpers
Haptic driver outputs
3-4
Enable reset from SEGGER
The DIP switch (S1) has all individual segments set to the “ON” position by default.
3.13 QSPI-RAM Operation
QSPI-RAM may be used in applications where we need bulk data transfers with DMA. The most
common case is as an LCD framebuffer. The selected QSPI-RAM chip (APS6404L-SQ-SN) is not
populated on the PCBs and it has to be added by users.
Figure 21: QSPI-RAM
3.14 Test Section
Table 5: Mainboard Test Points (Placed on the Bottom Of DA1469x PRO DK)
TP Name on Reference
Design
Signal Name
Comments
TP1
VDD_CR
3.3V (SEGGER)
TP2
T_RESET
JTAG Reset
TP3
sERASE
SEGGER chip programming
TP4
sVCC
TP5
sRST
TP6
sDIO
TP7
sCLK
TP8
sTDI
TP9
DBLED
SEGGER LED
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TP Name on Reference
Design
Signal Name
Comments
TP10
sTDO
SEGGER chip programming
TP11
VFB
VBAT LDO feedback
TP12
VBAT
3.0 V
TP13
VINN
2.5 V
TP14
VINP
2.5 V
TP15
5.0VA
5 V (ADC analog)
TP16
VREF
2.5 V
TP17
27MHz
ADC reference clock
TP18
VREG
1.8 V (FTDI)
TP19
VBUS2
5 V (USB)
TP20
PWR_EN
Enable for most LDOs
TP23
+3V3
3.3 V (USB hub)
TP24
GND
TP25
GND
TP26
GND
TP27
GND
TP30
RSTn
RESETn (from db)
TP31
V12
1.2 V (from db)
TP32
V14
1.4 V (from db)
TP36
USBLED
USB hub LED
TP37
6.0V
6 V
TP38
3.3V
3.3 V
TP39
5.0V
5 V
TP40
3.3VA
3.3 V
TP41
PWRLED
3.3 V Peripheral Power LED
TP42
VOUT
Current measurement output (high scale)
TP44
VDDIO
VDDIO (buffered V30)
TP48
UTX
UART Tx (FTDI side)
TP49
SWDIO
SEGGER data I/O
TP50
URX
UART Rx (FTDI side)
TP51
URTS
UART RTS (FTDI side)
TP52
UCTS
UART CTS (FTDI side)
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TP Name on Reference
Design
Signal Name
Comments
TP54
SWCLK
SEGGER Clock
TP56
C_TRIG
Software trigger for SmartSnippets Toolbox
TP57
V30
3.0 V
TP58
OSC_EN
Enable for ADC clock
TP59
BCBUS7
Aux I/O from FTDI
TP60
VOUT2
Current measurement output (low scale)
TP61
SEL
ADC control from FTDI
TP62
VS+
Current measurement sense+
TP63
VS-
Current measurement sense-
TP64
BCBUS5
Aux I/O from FTDI
Table 6: Daughterboard Test Points
TP Name on
Reference Design
Signal Name
Comments
Position on Daughter
Board
TP1
V18
1.8 V ± 5%
top
TP2
FCS
Flash chip select
top
TP3
VBUS
5.0 V ± 5% (output of OVP circuit)
top
TP4
V30
3.0 V ± 2%
top
TP5
V18
1.8 V ± 5%
bottom
TP6
V18P
1.8 V ± 5%
bottom
TP7
V14
1.4 V ± 5%
bottom
TP8
V12
1.2 V ± 5%
bottom
TP9
VBAT
Battery (default LDO 3.0 V ± 2%)
top
TP12
GND
bottom
TP13
GND
top
TP14
GND
bottom
TP15
VBUS_IN
5.0 V ± 5% (from USB, before OVP)
top
TP16
VBATn
VBAT pin (default LDO 3.0 V ± 2 %)
bottom
TP17
VBUSn
5.0 V ± 5% (to DA1469x pin)
bottom
TP18
VLED
LED power (VBUS or VBAT - 0.2 V)
bottom
TP20
GND
top
TP21
V18
VFLASH 1.8 V ± 5%
bottom
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Revision History
Revision
Date
Description
1.1
19-Feb-2019
To be released with DA1469x Pro DKs.
Change details:
● Update document title to “DA1469x PRO Development Kit”
● Removed reference to Basic Kit
● Minor text editing
● Improved template compliance
1.0
15-Feb-2018
Initial version (specification)
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Status
Definition
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The content of this document has been approved for publication.
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