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DA14682-00
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Dialog Semiconductor DA1468 Series, DA14681-01, DA14680-01, DA14683-00, DA14680 Application Note

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Company confidential
Application note
DA1468x Application hardware
design guidelines
AN-B-061

Abstract

Minimal reference schematic, circuit explanation and design guidelines for BLE applications based on the DA14680-01, DA14681-01, DA14682-00 and the DA14683-00 SoCs.
AN-B-061
DA1468x Application hardware design guidelines
Company confidential
Application note
Revision 1.9
CFR0014 Rev 3
2 of 45

Contents

Abstract ................................................................................................................................................ 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 3
Tables ................................................................................................................................................... 3
1 Terms and definitions ................................................................................................................... 4
2 References ..................................................................................................................................... 4
3 Introduction.................................................................................................................................... 5
4 Device revision numbering and Marking .................................................................................... 6
5 Minimal design for the DA1468x SoC .......................................................................................... 7
5.1 Power section of DA1468x .................................................................................................. 12
5.1.1 Supplying external loads...................................................................................... 14
5.1.2 Supply rails discharging ....................................................................................... 16
5.1.3 SIMO Buck DC/DC Characteristics ..................................................................... 17
5.2 I/O pins ................................................................................................................................ 19
5.3 Crystals and clocks ............................................................................................................. 20
5.3.1 16 MHz and 32 MHz clock ................................................................................... 20
5.3.2 32.768 KHz clock ................................................................................................. 22
5.3.3 Generating a clock output from the DA1468x ..................................................... 24
5.4 UART................................................................................................................................... 25
5.5 SWD (JTAG) ....................................................................................................................... 25
5.6 QSPI Flash memory ............................................................................................................ 26
5.7 USB and VBUS ................................................................................................................... 27
5.7.1 USB ESD measures ............................................................................................ 27
5.7.2 VBUS circuitry. ..................................................................................................... 28
5.8 Hibernation Mode and wakeup ........................................................................................... 30
5.9 RFIO port ............................................................................................................................ 32
5.10 PCB layout .......................................................................................................................... 32
5.10.1 PCB layout for WLCSP53 package ..................................................................... 33
5.10.2 PCB layout for AQFN60 package ........................................................................ 37
5.11 AQFN60 - Package Outline (POD) Information .................................................................. 39
5.12 WLCSP53 - Package Outline (POD) Information ............................................................... 39
Appendix: AQFN60 assembly and soldering guidelines ............................................................... 40
A.1 PCB ..................................................................................................................................... 40
A.2 Stencil Design ..................................................................................................................... 41
A.3 Component Placement........................................................................................................ 42
A.4 Reflow Profile ...................................................................................................................... 43
Revision history ................................................................................................................................. 44
AN-B-061
DA1468x Application hardware design guidelines
Company confidential
Application note
Revision 1.9
CFR0014 Rev 3
3 of 45

Figures

Figure 1: Block diagram of the DA1468x minimal design ..................................................................... 7
Figure 2: Minimal design for DA14681-01 WLCSP53 package ............................................................ 8
Figure 3: Minimal design for DA14681-01 AQFN60 package ............................................................... 9
Figure 4: Minimal design for DA14683-00 WLCSP53 package .......................................................... 10
Figure 5: Minimal design for DA14683-00 AQFN60 package ............................................................. 11
Figure 6: The power section of the DA1468x ...................................................................................... 12
Figure 7: 4.7µF- 6.3V capacitance change for 0402 (purple) and 0603 (blue) ................................... 14
Figure 8: DA1468x power management unit block diagram ............................................................... 15
Figure 9: V14, V18, V18P rails discharging by HW Reset .................................................................. 16
Figure 10: Discharging rails FSM timing ............................................................................................. 16
Figure 11: SIMO BUCK DC/DC Block Diagram .................................................................................. 17
Figure 12: PAD I/O configuration ........................................................................................................ 19
Figure 13: 16 MHz or 32 MHz crystal oscillator, recommended operating conditions ........................ 21
Figure 14: Connection of the crystal (left) and external 16 MHz clock (right) for AQFN package ...... 21
Figure 15: 32.768 KHz crystal oscillator, recommended operating conditions ................................... 23
Figure 16: Clock output, P10_MODE_REG - PUPD and PID selection ............................................. 25
Figure 17: Clock output, GPIO_CLK_SEL - FUNC_CLK_SEL, clock selection .................................. 25
Figure 18: Recommended topology for USB functionality .................................................................. 27
Figure 19: Relation between damping and step-response of a series LC resonator .......................... 28
Figure 20: used USB circuit for testing ................................................................................................ 28
Figure 21: Step response with 60 cm (left) and 150 cm (right) cable (non USB-cable). A damping
network of 0.39 Ω and 10 μF capacitor on VBUS is used. .................................................................. 29
Figure 22: Step response with 300 cm cable (non USB-cable) and the same damping network as
above (0.39 Ω and 10 μF capacitor on VBUS). ................................................................................... 29
Figure 23: Step response of VBUS with 0.39 Ω and 10 μF for a 1.5 m USB cable. ........................... 30
Figure 24: Wakeup from Hibernation by VBUS voltage using GPIO trigger ....................................... 31
Figure 25: GPIO set as Input (no pull) ................................................................................................. 31
Figure 26: RF matching circuit must be placed as close as possible to the antenna ........................ 32
Figure 27: WLCSP53 PCB stackup ..................................................................................................... 33
Figure 28: WLCSP53 PCB layout, top side ......................................................................................... 34
Figure 29: WLCSP53 PCB layout, layer 2 ........................................................................................... 35
Figure 30: WLCSP53 PCB layout, layer 3, reference GND ................................................................ 35
Figure 31: Ground connectivity Top (left) and layer 2 (right) ............................................................... 36
Figure 32: AQFN60 PCB stackup ....................................................................................................... 37
Figure 33: AQFN60 PCB layout, top layer .......................................................................................... 38
Figure 34: AQFN60 PCB layout, layer2, reference ground ................................................................. 39
Figure 35: PCB footprint data .............................................................................................................. 40
Figure 36: Recommend of stencil opening of thermal ......................................................................... 42
Figure 37: Reflow profile for solder paste SAC305 ............................................................................. 43

Tables

Table 1: DA14680/14682 and DA14681/14683 chip options ................................................................ 5
Table 2 CHIP_REVISION_REG (0x50003204)..................................................................................... 6
Table 3 CHIP_TEST1_REG (Minor revision) ........................................................................................ 6
Table 4 Chip revision numbering ........................................................................................................... 6
Table 5: Suggested decoupling capacitors for the power section ....................................................... 13
Table 6: SIMO DC/DC inductor examples and characteristics ........................................................... 13
Table 7: DA1468x supply rail capabilities overview ............................................................................ 15
Table 8: 16 MHz crystal examples and characteristics ....................................................................... 22
Table 9: 32 MHz crystal examples and characteristics ....................................................................... 22
Table 10: 32.768 KHz crystal examples and characteristics ............................................................... 23
Table 11: Default UART pins ............................................................................................................... 25
Table 12: JTAG pins ............................................................................................................................ 25
AN-B-061
DA1468x Application hardware design guidelines
Company confidential
Application note
Revision 1.9
CFR0014 Rev 3
4 of 45

1 Terms and definitions

AQFN Advanced Quad-Flat No-leads (package) BLE Bluetooth Low Energy BUCK Type of DC/DC converter CCCV Constant Current Constant Voltage (battery charger type in the DA1468x) CS Chip Select DC/DC DC-to-DC Converter DK Development Kit FTDI Brand name of USB – UART interface GPIO General Purpose Input Output OTP One Time Programmable PCB printed circuit board PTH Plated Thru Hole SDK Software Development Kit SPI Serial Peripheral Interface SRAM Static Random Access Memory SWD Serial Wire Debug USB Universal Serial Bus UART Universal Asynchronous Receiver/Transceiver WLCSP Wafer Level Chip Scale Package

2 References

[1] DA14680-01, DA14681-01, DA14682-00, DA14683-00 Datasheet, Dialog Semiconductor. [2] DA1468x Pro-Development Kit, Dialog Semiconductor. [3] AN-B-056 - DA14680_681 Recovery from System Level ESD Events, Dialog Semiconductor. [4] AN-B-45 - DA1468x Booting from serial interfaces, Dialog Semiconductor.
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CFR0014 Rev 3
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3 Introduction

The DA1468x family are flexible System-on-Chips combining an application processor, memories, cryptography engine, power management unit, digital and analog peripherals and a Bluetooth® Smart MAC engine and radio transceiver. The chips are based on an ARM® Cortex®-M0 CPU delivering up to 84 DMIPS and provides a flexible memory architecture, enabling code execution from embedded memory (RAM, ROM) or non-volatile memory (FLASH, OTP).
For the DA14680/682, a QSPI flash of 8Mbit capacity is embedded in the package, whereas for the DA14681/683 the QSPI flash is resided externally and it is connected to the chip with the QSPI bus.
There are two available packages for the DA14681 and DA14683: WLCSP53 and AQFN60. And one package is available for the DA14680 and DA14682 having the embedded QSPI Flash: AQFN60.
Table 1: DA14680/14682 and DA14681/14683 chip options
Chip
package
No of pins
QSPI Flash
DA14680/682
AQFN60
60
8Mbit embedded
DA14681/683
WLCSP53
53
External
QSPI flash
AQFN60
60
The purpose of this document is to present the absolute necessary circuit required for proper operation of DA1468x. Based on this, system designers can build a BLE application on the top of it. Recommended schematic, chip interfaces and surrounding components as well as PCB layout guidelines of the DA1468x SoC family are provided.
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Application note
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4 Device revision numbering and Marking

The revision number of the chip can be read from the device by reading below ARM registers (Table 2 and Table 3). The combination of this will explain the commercial chip revision (Table 4)
Table 2 CHIP_REVISION_REG (0x50003204)
Bit
Mode
Symbol
Description
Reset
7:0
R
REVISION_ID
Chip version, corresponds with type number in ASCII. 0x41 = ‘A’, 0x42 = ‘B’.
-
Table 3 CHIP_TEST1_REG (Minor revision)
Bit
Mode
Symbol
Description
Reset
7:0
R
MINOR
0x00 = ‘A’, . . . . . ., 0x03 = ’D’, 0x07 = ‘E’.
-
The chip’s commercial version number can be read from Table 4, below:
Table 4 Chip revision numbering
Commercial number
CHIP_REVISION_REG
(0x50003204)
CHIP_TEST1_REG
(0x5000320A)
DA14680-01/681-01 DA14682-00/683-00
0x41 (A) 0x42 (B)
0x07 (E) 0x01 (B)
Version format: xx = commercial chip revision: ‘00’ or ‘01’. Date code format: yy = Year, ww = Week, nnnn = Dialog internal number
x x 0 0 0
y y w w n n n n
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Revision 1.9
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5 Minimal design for the DA1468x SoC

The DA1468x SoC requires a minimum number of external components for proper operation. These are a 16MHz crystal, a DCDC inductor and a number of supply rail decoupling caps. The absolute necessary sections required for a minimal system operation are the Power section, Crystals, UART, JTAG, Flash memory and Radio section. The external QSPI flash memory chip is only required for the DA14681 and DA14683, which do not have an embedded flash memory. A 32MHz crystal is only supported by the DA14682 and the DA14683. 16 MHz crystal operation is supported by all types. The 32.768 KHz crystal is optional, alternatively the internal accurate RCX oscillator can be used as sleep clock.
Below are the block diagram and minimal schematics for the two packages AQFN60 and WLCSP53. Only the schematics for the DA14681 and DA14683 are given, the DA14680 and DA14682 schematics are identical except for not having the external QSPI flash chip. Please be aware that the DA14680 and DA14682 QSPI signals are not available externally since these pins are not bonded out. Hence the 10K pull-up resistor on the DA14680’s and DA14682’s /CS (P0_5) pin can be omitted as well. This 10K pull-up resistor is R3 in the schematics. Please note that the VDDIO pin, for the interface supply voltage of the embedded QSPI flash, still needs to be connected to V18, the 1.8V supply rail for the internal QSPI flash.
DA1468x
matching
QSPI
Flash*
USB
UART
JTAG
GPIOs
16/32 MHz
32.768 KHz (optional)
Vusb
Power
Battery
Antenna
* Not needed for DA14680/682
Figure 1: Block diagram of the DA1468x minimal design
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Figure 2: Minimal design for DA14681-01 WLCSP53 package
VBAT+
VBAT-
RST
Z1
TBD
Z2 10pF
C1
1.0uF
C3
4.7uF
C2
4.7uF
VDDIO
V33
R1
0.1
U1
DA14681_WLCSP53
ADC3/P0_7
A6
QSPI_D3/P0_4
C8
LY
F7
USBN/P1_1
F3
RST
G1
SWDIO/ADC4/P0_6
F4
RFIOp
A4
QSPI_D2/P0_3
A8
SOCN
E3
QSPI_CS/P0_5
C7
VBAT2
F6
QSPI_VDDIO
D7
V12
E7
XTAL_32Kp/P2_0
E1
XTAL_32Km/P2_1
F1
XTAL16Mm
A1
XTAL16Mp
B1
SOCP
F2
V14_RF
A2
VDD1V8P
F8
LX
G8
VDD1V8
E8
V14
D8
QSPI_D1/P0_2B7QSPI_D0/P0_1
A7
QSPI_CLK/P0_0
B8
VBUS
G5
LED1
G2
USBP/P2_2
G3
V33
G4
VBAT1
G6
ADC0/P1_2C1ADC5/P1_0C2ADC2/P1_3
B6
ADC1/P1_4D1ADC6/P1_5
B2
NTC/P1_6E2P1_7
D2
P2_3
B5
SWCLK/ADC7/P2_4
F5
RFIOm
A3
ESDN
A5
PSUB_RF
B4
GND_RF1
D3
GND_RF2
C3
GND_AVS1
D4
GND_VSS1
C6
GND_VSS2
D5
VSSIOQ
D6
GND_BUCK
G7
VSSIO1
E6
VSSIO2
E5
GND_AVS2
E4
Y1
16MHz
ANT1
IFA_type
C6
4.7uF
C7
4.7uF
V12
SWDIO_P0_6
C8
4.7uF
C5
10uF
C4
10uF
FL_CS
V18PV18
FL_D0
FL_D3
FL_D2
FL_D1
FL_CLK
U3
W25Q80EW
VCC
A1
/CS
A2
/HOLD
B1
DO
B2
CLK
C1
/WP
C2
DI
D1
GND
D2
FL_D3
QUAD SPI FLASH
FL_D0
FL_CLK
R3
10.0k
VDDIO
C9
100nF
FL_D2
FL_D1
FL_CS
VDDIO
Y2
32.768KHZ R2
10MOhm
URX
UTX
J17
Battery
connector
C10
1uF
C11
1uF
V14
VBUS
R5
0.56
VDDIO
V18
R6 0
L1
470nH
SWCLK_P2_4
SOCn
SOCp
LED1
X16p
X16m
Z3
TBD
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Application note
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Figure 3: Minimal design for DA14681-01 AQFN60 package
Note: for the DA14680-01 (embedded flash), U2, R3, C12 are not present. And P0_0~P0_5 are N.C.
URX
SWDIO_P0_6
SOCp
X16m
X16p
SOCn
RST
SWCLK_P2_4
UTX
C1
1.0uF
L1
470nH
C2
10uF
C11
1.0uF
Z3
TBD
C4
10uF
C7
4.7uF
ANT1
IFA_type
Y1
16MHz
C8
4.7uF
J17
U1
DA14681_aQFN60
ADC3/P0_7
A34
QSPI_D3/P0_4
A4
LY
B5
USBN/P1_1
A17
RST
A21
SWDIO/ADC4/P0_6
B8
RFIOp
B20
QSPI_D2/P0_3
A1
SOCN
B9
QSPI_CS/P0_5
A5
VBAT2
B6
QSPI_VDDIO
B2
V12
B3
XTAL_32Kp/P2_0
A23
XTAL_32Km/P2_1
B13
XTAL16Mm
A29
XTAL16Mp
A30
SOCP
A18
V14_RF
B18
VDD1V8P
B4
LX
A11
VDD1V8
A8
V14
A6
QSPI_D1/P0_2A3QSPI_D0/P0_1
A2
QSPI_CLK/P0_0
B1
VBUS
B7
LED1
B10
USBP/P2_2
A16
V33
A15
VBAT1
A13
ADC0/P1_2
A27
ADC5/P1_0
B15
ADC2/P1_3
B23
ADC1/P1_4
A26
ADC6/P1_5
A28
NTC/P1_6
B12
P1_7
A25
P2_3
A35
P3_0
A37
P3_1
A12
P3_4A9P3_5
A20
P3_6
A22
P3_7
B14
P4_0
A24
P4_1
B16
P4_2
B17
P4_3
A31
P4_4
A32
P4_5
A33
P4_6
B22
P4_7
A36
P3_2
A10
P3_3
A7
LED2
A19
LED3
B11
SWCLK/ADC7/P2_4
A14
RFIOm
B19
GND
PAD
ESDN
B21
Y2
32.768KHZ
C6
4.7uF
C5
10uF
Z2 10pF
R4 0
C3
4.7uF
Z1
TBD
R5
0.56
R2
10MOhm
R1
0.1
C10
1.0uF
V33
VDDIO
VBUS
V12V18PV18
VBAT+
VBAT-
V18
V14
Battery
connector
VDDIO
FL_CLK
FL_CS
FL_D0
FL_D3
FL_D2
FL_D1
U2
W25Q80EW
VCC
A1
/CS
A2
/HOLD
B1
DO
B2
CLK
C1
/WP
C2
DI
D1
GND
D2
FL_D0
FL_CLK
FL_D3
R3
10.0k
QUAD SPI FLASH
C12
100nF
VDDIO
FL_CS
VDDIO
FL_D2
FL_D1
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Application note
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DA14683_WLCS
P53
Figure 4: Minimal design for DA14683-00 WLCSP53 package
VBAT+
VBAT-
RST
Z1
TBD
Z2 10pF
C1
1.0uF
C3
4.7uF
C2
4.7uF
VDDIO
V33
R1
0.1
U1
DA14681_WLCSP53
ADC3/P0_7
A6
QSPI_D3/P0_4
C8
LY
F7
USBN/P1_1
F3
RST
G1
SWDIO/ADC4/P0_6
F4
RFIOp
A4
QSPI_D2/P0_3
A8
SOCN
E3
QSPI_CS/P0_5
C7
VBAT2
F6
QSPI_VDDIO
D7
V12
E7
XTAL_32Kp/P2_0
E1
XTAL_32Km/P2_1
F1
XTAL16Mm
A1
XTAL16Mp
B1
SOCP
F2
V14_RF
A2
VDD1V8P
F8
LX
G8
VDD1V8
E8
V14
D8
QSPI_D1/P0_2B7QSPI_D0/P0_1
A7
QSPI_CLK/P0_0
B8
VBUS
G5
LED1
G2
USBP/P2_2
G3
V33
G4
VBAT1
G6
ADC0/P1_2C1ADC5/P1_0C2ADC2/P1_3
B6
ADC1/P1_4D1ADC6/P1_5
B2
NTC/P1_6E2P1_7
D2
P2_3
B5
SWCLK/ADC7/P2_4
F5
RFIOm
A3
ESDN
A5
PSUB_RF
B4
GND_RF1
D3
GND_RF2
C3
GND_AVS1
D4
GND_VSS1
C6
GND_VSS2
D5
VSSIOQ
D6
GND_BUCK
G7
VSSIO1
E6
VSSIO2
E5
GND_AVS2
E4
Y1
16MHz
ANT1
IFA_type
C6
4.7uF
C7
4.7uF
V12
SWDIO_P0_6
C8
4.7uF
C5
10uF
C4
10uF
FL_CS
V18PV18
FL_D0
FL_D3
FL_D2
FL_D1
FL_CLK
U3
W25Q80EW
VCC
A1
/CS
A2
/HOLD
B1
DO
B2
CLK
C1
/WP
C2
DI
D1
GND
D2
FL_D3
QUAD SPI FLASH
FL_D0
FL_CLK
R3
10.0k
VDDIO
C9
100nF
FL_D2
FL_D1
FL_CS
VDDIO
Y2
32.768KHZ R2
10MOhm
URX
UTX
J17
Battery
connector
C10
1uF
C11
1uF
V14
VBUS
R5
0.56
VDDIO
V18
R6 0
L1
470nH
SWCLK_P2_4
SOCn
SOCp
LED1
X16p
X16m
Z3
TBD
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DA14683_aQFN60
Figure 5: Minimal design for DA14683-00 AQFN60 package
Note: for the DA14682-01 (embedded flash), U2, R3, C12 are not present. And P0_0~P0_5 are N.C.
URX
SWDIO_P0_6
SOCp
X16m
X16p
SOCn
RST
SWCLK_P2_4
UTX
C1
1.0uF
L1
470nH
C2
10uF
C11
1.0uF
Z3
TBD
C4
10uF
C7
4.7uF
ANT1
IFA_type
Y1
16MHz
C8
4.7uF
J17
U1
DA14681_aQFN60
ADC3/P0_7
A34
QSPI_D3/P0_4
A4
LY
B5
USBN/P1_1
A17
RST
A21
SWDIO/ADC4/P0_6
B8
RFIOp
B20
QSPI_D2/P0_3
A1
SOCN
B9
QSPI_CS/P0_5
A5
VBAT2
B6
QSPI_VDDIO
B2
V12
B3
XTAL_32Kp/P2_0
A23
XTAL_32Km/P2_1
B13
XTAL16Mm
A29
XTAL16Mp
A30
SOCP
A18
V14_RF
B18
VDD1V8P
B4
LX
A11
VDD1V8
A8
V14
A6
QSPI_D1/P0_2A3QSPI_D0/P0_1
A2
QSPI_CLK/P0_0
B1
VBUS
B7
LED1
B10
USBP/P2_2
A16
V33
A15
VBAT1
A13
ADC0/P1_2
A27
ADC5/P1_0
B15
ADC2/P1_3
B23
ADC1/P1_4
A26
ADC6/P1_5
A28
NTC/P1_6
B12
P1_7
A25
P2_3
A35
P3_0
A37
P3_1
A12
P3_4A9P3_5
A20
P3_6
A22
P3_7
B14
P4_0
A24
P4_1
B16
P4_2
B17
P4_3
A31
P4_4
A32
P4_5
A33
P4_6
B22
P4_7
A36
P3_2
A10
P3_3
A7
LED2
A19
LED3
B11
SWCLK/ADC7/P2_4
A14
RFIOm
B19
GND
PAD
ESDN
B21
Y2
32.768KHZ
C6
4.7uF
C5
10uF
Z2 10pF
R4 0
C3
4.7uF
Z1
TBD
R5
0.56
R2
10MOhm
R1
0.1
C10
1.0uF
V33
VDDIO
VBUS
V12V18PV18
VBAT+
VBAT-
V18
V14
Battery
connector
VDDIO
FL_CLK
FL_CS
FL_D0
FL_D3
FL_D2
FL_D1
U2
W25Q80EW
VCC
A1
/CS
A2
/HOLD
B1
DO
B2
CLK
C1
/WP
C2
DI
D1
GND
D2
FL_D0
FL_CLK
FL_D3
R3
10.0k
QUAD SPI FLASH
C12
100nF
VDDIO
FL_CS
VDDIO
FL_D2
FL_D1
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5.1 Power section of DA1468x

The DA1468x is supplied from a power source or battery connected to pin VBAT1 and VBAT2. The battery charging is accomplished by connecting an external +5V supply on the VBUS pin. The charging procedure is implemented in the software. When the +5V supply is connected, the DA1468x system operates with or without battery presence. The VBUS voltage range: 4.2V min. and 5.75V max.
The DA1468x SoC contains internally all power management for proper and safe system operation. Below the required external components are shown:
Figure 6: The power section of the DA1468x
VBUS: is the battery CCCV charger input as well as the USB bus voltage. It also supplies the 3.3V USB LDO providing power to the V33 rail. A decoupling capacitor equal to or less than 10 µF must be placed close to the VBUS pin. The absolute maximum allowed voltage for this pin is 6.5V.
It strongly advised to apply a 4.7 µF - 10V decoupling capacitor (C2: 0402 package) in combination with a 0.56 Ohm resistor (R5) in series with the VBUS pin. An alternative combination would be a 10 µF - 10V capacitor and a 0.39 Ohm resistor in series. Please refer to section 5.7.2.
VBAT1: the battery is connected to this pin and supplies the 3.3V VBAT LDO. A minimum value of 1µF for the decoupling capacitor (C10), is required close to the pin (0402 package, 10V). The voltage range for VBAT1 is 1.7V to 4.75V. The absolute maximum allowed voltage for this pin is 6V.
VBAT2: is the input supply pin for the SIMO DCDC converter. It is connected externally to VBAT1. As minimum, a 1 µF decoupling capacitor (C11), is required nearby the pin (0402 package, 10V).
V33: the 3.3V LDO output rail. Supplied by the VBAT1 or the VBUS pin. A ceramic decoupling capacitor of 4.7 µF (C3), should be added (0402 package, 6.3V). The V33 LDOs are capable to deliver up to 100 mA in active mode and up to 3 mA (DA14680/681) or 10 mA (DA14682/683) in sleep mode. The V33 rail cannot be turned off (it’s required for e.g. the bandgap reference).
SIMO DC/DC converter outputs when active are: V18P, V18, V14 and V12. The inductor needed for DCDC operation is connected externally. The low RDC inductor (L1) of 470nH, size 0805 is connected to the LX/ LY pins.
V18 & V18P: these supply rails can deliver power to external devices, even when the system is in sleep mode. Decoupling ceramic capacitors (C4 & C5) of 10µF (0603 package, 16V) must be placed as close as possible to the V18 and V18P pins. The V18 (VDD1V8) rail is assigned to supply the external QSPI Flash memory. The V18P (VDD1V8P) rail is assigned to be used for supplying external devices like sensors or a RF power amplifier. The V18P supply rail is also used to supply the GPIOs when these are set to use the
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1.8V supply. The current delivery capability of the V18 and V18P’s rails in active mode is 75mA, whereas in sleep mode it is 3 mA (DA14680/681) or 10 mA (DA14682/683). Please note that when not used, the V18 and V18P supply rails can be switched off completely.
V12: this power rail supplies the digital core of the DA1468x and delivers up to 50 mA at 1.2 V when in active mode. This rail should not be used for supplying external devices. A 4.7µF decoupling capacitor (C6), is required (0402 package, 10V).
V14: this output rail delivers up to 20 mA at 1.4V and should not be used for supplying other devices. A 4.7µF decoupling capacitor (C7), is required to be placed close to the V14 pin (0402 size, 10V).
V14_RF: the BLE radio supply input pin. It is connected to the V14 rail. The V14_RF supplies the internal RF circuits via a number of dedicated internal 1.2V LDOs. A 4.7µF decoupling capacitor (C8), is required, and should be placed as close to the V14_RF pin as possible. A good decoupling of this RF supply is important for a good and stable RF-performance (0402 package, 10V).
VDDIO: the Flash QSPI interface supply voltage. It connects to the supply rail used by the flash, normally V18. For the SoCs having the embedded flash memory, the VDDIO pin must be connected to V18. A 1µF decoupling capacitor (C1), needs to be placed at this pin (0402 package, 6.3V).
Note: The DA14682/683 chips have the capability to discharge both 1.8V rails and the 1.4V rail by a HW-Reset or by SW. Please refer to Section 5.1.2 or to the DA14682/683 datasheet [1] for details.
Table 5: Suggested decoupling capacitors for the power section
Reference Description Value Package Manufacturer Part Number
C1
CAP CER 6.3V 10%
X5R
1.0 µF 0402 muRata GRM155R60J105KE19
C10, C11
CAP CER 10V 10%
X5R
1.0 µF 0402 muRata GRM155R61A105KE5J
C3
CAP CER 6.3V 20%
X5R
4.7 µF 0402 muRata GRM155R60J475ME47
C2, C6, C7, C8
CAP CER 10V 20%
X5R
4.7 µF 0402
muRata ZRB15XR61A475ME01
or GRM155R61A475MEAA
C4, C5
CAP CER 16V 20%
X5R
10 µF 0603 muRata GRM188R61C106MA73
Note: please consider 0603 size for C2, C10 and C11 for larger effective capacitance at 5V or 4V.
Table 6: SIMO DC/DC inductor examples and characteristics
Part Number
Taiyo Yuden
CKP2012NR47M-T
Taiyo Yuden
BRL2012TR47M6
SunLord
MPM201206SR47
muRata
DFE160808S-R47
Value 0.47 µH 0.47 µH 0.47 µH 0.47 µH
DC Resistance RDC 0.08 Ω max 0.063 Ω max 0.086 Ω max 0.064 Ω max
Saturation Current 1.2 A 1.5 A 2.0 A 2.4 A
Size L x W x H (mm) 2.0 x 1.2 x 1.0 2.0 x 1.25 x 1.0 2.0 x 1.2 x 0.6 1.6 x 0.8 x 0.8
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A 470nH power inductor is used for the SIMO DCDC converter. The DC resistance affects the efficiency as well as the ripple of the DCDC converter outputs. An inductor having a saturation current of at least 1A and a RDC of maximum 0.1 Ohm guarantees a good performance. For the PRO­development kit, an inductor with saturation current of 1.2A and DC resistance of 0.06 Ohm is used.
The ceramic capacitors are placed as close as possible to the pins of the chip for reducing the parasitic inductance and improving the performance. Where it is available a small package (0402) was used. The capacitor values and working voltages have been selected for covering the capacitance de-rating phenomenon when a DC bias voltage is applied on the ceramic capacitor. The capacitance de-rating is highly dependent on the rated voltage, the technology (e.g. X5R vs. X7R) and the size of the multi-layer ceramic capacitor. In Figure 7, the capacitance de-rating for two different packages 0402 and 0603 of a 4.7µF/6.3V/X5R ceramic capacitor of Murata are presented. Quite a similar difference can be seen for 0402 sized 4.7µF/X5R capacitors, but having a rated voltage of 6.3V or 10V: the capacitance values at 5V are respectively 1µF and 2µF. To compensate or reduce the negative effect of this DC-bias derating, it is advised to either apply a larger size (0603 instead of 0402), a type having a higher rated voltage, e.g. 10V instead of 6.3V, or just a larger value.
Figure 7: 4.7µF- 6.3V capacitance change for 0402 (purple) and 0603 (blue)

5.1.1 Supplying external loads

There are different ways to supply external loads from the DA1468x- SoC :
- V33 power rail. The V33 voltage is generated from VBUS or VBAT using the internal 3.3V LDOs.
External loads up to 100 mA can be supplied by the V33 supply in active mode. The current capability of the V33 rail in sleep mode is 10 mA (DA14682/683). For the DA14680/681, the V33 rail current capability during sleep is less: 3mA.
- V18 and V18P power rail: the V18 (VDD1V8) rail is used for supplying the QSPI flash memory.
The V18P (VDD1V8P) rail is used to supply peripherals like sensors. The current capability of these rails is 75 mA in active mode and 10 mA in sleep mode. With the DA14680/681 chips, the current capability of the two 1.8V rails during sleep is 3 mA.
- The GPIOs supply-rail can be configured to 1.8V or 3.3V. When set to 1.8V, the GPIO is supplied
from V18P, VDD1V8P. Whereas for 3.3V it is supplied from the 3.3V LDO, V33. Refer to Figure 8.
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The GPIO’s output current capability is 4.8 mA. The GPIO supply power delivered to the load needs to be taken into consideration into the power budget of the total system. The GPIOs can be used for supplying light loads, e.g. a LED, NTC resistor network or a low-power sensor. The maximum source or sink current per GPIO is 4.8 mA. The system designer must take into consideration the current capability of the voltage rails that supplies the GPIOs during sleep mode.
Figure 8: DA1468x power management unit block diagram
Table 7: DA1468x supply rail capabilities overview
Supply rails
DA14680/681
DA14682/683
V18 / V18P active
75 mA
75 mA
V18 / V18P sleep
3 mA
10 mA
V33 active
100 mA
100 mA
V33 sleep
3 mA
10 mA
Always on
Software Enabled
Hardware enabled
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5.1.2 Supply rails discharging

Device:
DA14680
DA14681
DA14682
DA14683
Rail discharging
✗ ✗ ✓
✓
The DA14682/683 chips have the capability to discharge both 1.8V rails and the 1.4V rail by a HW­Reset (PMU_RESET_RAIL_REG) or by SW (DISCHARGE_RAIL_REG). The DA14680/681 chips don’t possess this function. Below Figure 9 shows the rails being discharged by a HW-Reset. The whole discharge – charge cycle takes about 4 msec. Figure 10 shows the FSM timing diagram. For details about the rail discharging functionality, please refer to the ‘Rails Discharging’ section of the ‘Reset and BOD’ chapter in the DA14682 and the DA14683 datasheet.
Figure 9: V14, V18, V18P rails discharging by HW Reset
Figure 10: Discharging rails FSM timing
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5.1.3 SIMO Buck DC/DC Characteristics

The general properties of the DA1468x Buck DC/DC converter: DC/DC type: Single Inductor Multiple Outputs (SIMO)
Operation mode: Discontinuous Conduction Mode (DCM) Reference voltage: 1.20 V Switching Frequency: 2 MHz typically, depends on the loads Inductor ripple current: 1 A maximum, depends on the loads FET switches On resistance: 0.5 Ohm nominal Start-Up time: 10 µsec typical
The DA1468x buck DC/DC Converter is tailored for the DA1468x application and works different from most stand-alone buck DC/DC converters that use Continuous Conduction Mode (CCM) and have either voltage- or current feedback. Instead, in the DA1468x buck DC/DC each rail has its own comparator. Please refer to Figure 11 below. If the output voltage of a rail is too low, a charge cycle is triggered. Additionally, the rails are not charged in a fixed sequence, the sequence dynamically can be changed depending on the rail priority. The converter tries to charge each output every 2 µsec, and since there are four outputs there’s one pulse every 0.5 µsec, leading to a typical switching frequency of 2 MHz.
Figure 11: SIMO BUCK DC/DC Block Diagram
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It does this by measuring the time between pulses and adjusting the inductor current limit to keep the rail voltage within certain limits. However, since there is a minimum current limit there is a point where it cannot regulate lower and the frequency will have to decrease. Likewise, if the current is at its maximum and the load is increased further there comes a point where the frequency has to increase in order to deliver enough charge. The highest frequency is expected to stay below 4 MHz.
The DCM operation mode leads to a DC/DC inductor (ripple) current that switches from 0 A to the maximum current, which is 1 A maximum for the 1.8 V rails, and about 400 mA for the 1.2 V and 1.4 V rails. This sets the requirement for the saturation current of the DC/DC inductor: 1 A minimum.
The DC/DC inductor was chosen as a compromise between switching frequency and voltage ripple:
- Switching frequency: a smaller inductance results in a faster build-up of inductor current and
means that for a given current limit less charge is dumped in the capacitor per cycle so a higher frequency is required.
- Voltage ripple: a bigger inductance means more charge is delivered per cycle means higher
ripple. There are many optimizations possible here, but a 470 nH inductor seemed most suited for the buck DC/DC in the DA1468x application.
The buck DC/DC takes about 10 µs to start up when its enable signal is set. It then immediately starts supplying the outputs, the L-C values are of no importance for that. The DC/DC’s dynamic behaviour, overshoot, undershoot, etc.is a bit more difficult to describe mathematically than for a current or voltage feedback converter. As mentioned, the DA1468x buck DC/DC converter uses a different mechanism to regulate the outputs. In short: it samples all four outputs and will start a charge cycle if it finds one or more are too low, it then measures how long it takes until a new cycle is required and adjusts the current limit to try and keep this time constant. Because of this mechanism, it takes several cycles to get to the new current limit when a load step is presented at an output, meaning it will be a bit slower than a converter with a proportional feedback path. It also means the voltage transient at one output depends on the load on all other outputs, since only one output can be active at any given time. In general the buck DC/DC inductor value (470 nH) is pretty optimal for the DA1468x design, and increasing the output capacitor values will reduce the voltage ripple and the magnitude of the load transients.
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5.2 I/O pins

The DA1468x has software-configurable I/O pin assignment, organized into ports Port 0, Port1, Port2 Port 3 and Port 4. Only ports 0, 1 and 2 are available for the WLCSP53 package. All ports are available in the AQFN60 package. Very useful, for system design characteristics for the I/O pins operation are:
- Fully programmable pin assignment:
Pxy_MODE_REGs provide, (through PID) a multiplexing function to the IOs of the on-chip peripherals as well as the direction of the pin. A pin can be assigned to a general purpose port (PID=00), to UART, to other serial interfaces or PWM output.
- Selectable 25 KOhm pull-up or pull-down resistors per pin.
- GPIOs can be configured individually as 1.8V or 3.3V. The 1.8V is provided by V18P.
- Programmable open-drain functionality.
- Fixed assignment for analog pins ADC[7:0], QSPI, JTAG, USB and NTC.
- Pins retain their last state when system enters the Sleep or Deep Sleep mode.
- P0_6 is kept powered while in sleep/deep-sleep mode, controlled by Timer1 PWM5 signal.
Figure 12: PAD I/O configuration
NOTES
Please observe the following guidelines when using the GPIOs:
● To use P1_1 in GPIO mode, USBPAD_REG[USBPAD_EN] must be set.
● To use P2_2 in GPIO mode, USBPAD_REG[USBPAD_EN] must be set
● On all DA1468x SoCs, P1_1 and P2_2 (USB pad by default) cannot be configured as generic
GPIO output mode if they need to be kept active in sleep mode. In sleep mode these pins go to High-Z (reset state). For this reason P1_1 and P2_2 must not be used for supplying purposes. And use these GPIOs with 3.3V supply only.
● P1_0 and P1_5 will affect the radio performance and PLL96M stability when toggling quickly.
It is recommended to toggle these pins at a low rate only and not at all while the radio is active or the PLL96M is used.
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5.3 Crystals and clocks

The DA1468x SoC is equipped with two Digitally Controlled Crystal Oscillators (DXCO), one at 16 MHz or 32 MHz (XTAL16M/XTAL32M), and a second at 32.768 KHz (XTAL32K). The 32.768 KHz crystal oscillator has no trimming capabilities and can be used as the low power clock for the Extended/Deep Sleep modes. The 16 MHz/32 MHz crystal oscillator can be trimmed using the internal capacitor bank. The allowed load-capacitance of the crystal ranges from 4 pF to 12 pF.

5.3.1 16 MHz and 32 MHz clock

Device:
DA14680
DA14681
DA14682
DA14683
16 MHz crystal
✓ ✓ ✓
✓
32 MHz crystal
✗ ✗ ✓
✓
The DA1468x requires an accurate clock for a proper operation. The clock can be generated either by using an external 16 MHz or 32 MHz crystal, or by applying an external 16 MHz clock signal.
The 16/32 MHz crystal oscillator can be trimmed. No external components are required other than the crystal itself. If the crystal has a case connection, it is advised to connect the case to ground. Register CLK_FREQ_TRIM_REG controls the trimming of the 16/32 MHz crystal oscillator. Usage of a 32 MHz crystal is only supported by the DA14682 and the DA14683 versions of the chip, not by the DA14680 and DA14681 chip versions.
The crystal or the external clock must meet the 16 MHz or 32 MHz crystal oscillator recommended operating conditions as listed below in below tables.
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Figure 13: 16 MHz or 32 MHz crystal oscillator, recommended operating conditions
Figure 14: Connection of the crystal (left) and external 16 MHz clock (right) for AQFN package
In Table 8 and in Table 9 below there are examples of some 16 MHz and 32 MHz crystals that meet the specification described above in Figure 13.
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Table 8: 16 MHz crystal examples and characteristics
Part Number TXC 8Y16070015
River Eletec FCX-06
LF 16.000 MHz
Kyocera
CX2016DB16000F0FLLC1
NDK NX2520SA TXC 7M16070029
Frequency 16.000 MHz 16.000 MHz 16.000 MHz 16.000 MHz 16.000 MHz
Accuracy (please check for other possible types)
±10 ppm ±10 ppm ±10 ppm ±10 ppm ±10 ppm
Load Capacitance (CL) 10 pF 10 pF 10 pF 10 pF 10 pF
Shunt Capacitance (C0) 2 pF max. 0.5 pF typ. 0.6 pF typ. 0.7 pF typ. 3 pF max.
Equivalent Series Resistance (ESR)
100 Ω max. 80 Ω max. 100 Ω max. 80 Ω max. 50 Ω max.
Drive Level (PD) 100 μW < 200 μW 100 μW 100 μW 100 μW
Size L x W x H (mm) 2.0 x 1.6 x 0.5 2.0 x 1.6 x 0.5 2.0 x 1.6 x 0.45 2.5 x 2.0 x 0.5 3.2 x 2.5 x 0.7
Table 9: 32 MHz crystal examples and characteristics
Part Number
River Eletec
FCX-06 32000
Kyocera
CX2016DB32000
NDK NX2016SA
32000
EPSON FA-128
2016
TXC 8Q32070005
Frequency 32.000 MHz 32.000 MHz 32.000 MHz 32.000 MHz 32.000 MHz
Accuracy (please check for other possible types)
±10 ppm ±10 ppm ±20 ppm ±10 ppm ±10 ppm
Load Capacitance (CL) 5 pF 8 ~ 11 pF 6.5 ~ 8 pF 6 ~ 8 pF 6 pF
Shunt Capacitance (C0) 0.64 pF typ. ? 0.6 pF typ. < 3 pF -
Equivalent Series Resistance (ESR)
60 Ω max. 60 Ω max. 60 Ω max. 60 Ω max. 60 Ω max.
Drive Level (PD) 100 μW 100 μW < 200 μW 100 μW 100 μW
Size L x W x H (mm) 2.0 x 1.6 x 0.5 2.0 x 1.6 x 0.4 2.0 x 1.6 x 0.45 2.0 x 1.6 x 0.5 1.6 x 1.2 x 0.35

5.3.2 32.768 KHz clock

Device:
DA14680
DA14681
DA14682
DA14683
10 MOhm at XTAL32Kp required?
✓ ✓ ✗
✗
The DA1468x utilizes a low power, low frequency clock for extended and deep sleep modes. This can be achieved with either the 32.768 KHz crystal oscillator (using an external 32.768 KHz crystal) or the internal RCX oscillator. When using the RCX oscillator, no crystal is needed. The utilization of the external crystal provides a tighter timing, better accuracy, but adds the cost of the crystal. This crystal oscillator cannot be trimmed. The DA1468x offers a load-capacitance of 7 pF, and typically no external load capacitors are required. The DA14680 and DA14681 chips require a 10 MOhm resistor from the XTAL32Kp pin to ground, the DA14682 and DA14683 do not need this. The external crystal must meet the recommended operating conditions as indicated below:
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Figure 15: 32.768 KHz crystal oscillator, recommended operating conditions
In Table 10, there are examples of crystals that meet the specification described above.
Table 10: 32.768 KHz crystal examples and characteristics
Part Number
Abracon ABS07-
32.768KHZ-7-T
Abracon ABS06-
32.768kHz-7-T
NDK NX3215SA-
32.768K-STD-MUA-14
ECS Inc. ECX­12_32.768KHz
Hosonic
ETDG003270003E
Frequency 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz
Accuracy ± 20 ppm ± 20 ppm ± 20 ppm ± 20 ppm ± 20 ppm
Load Capacitance (CL) 7 pF 7 pF 6 pF 7 pF 7 pF
Shunt Capacitance (C0) 0.9~1.2 pF 1.5 pF 1.5 pF max. 1.3 pF 1.0 pF
Equivalent Series Resistance (ESR)
70 KΩ max. 90 KΩ max. 70 KΩ max. 90 KΩ max. 90 KΩ max.
Drive Level (PD) < 0.5 µW < 0.5 µW < 0.5 µW < 0.5 µW < 0.5 µW
Size L x W x H (mm) 3.2 x 1.5 x 0.9 2.0 x 1.2 x 0.6 3.2 x 1.5 x 0.8 2.0 x 1.2 x 0.6 2.0 x 1.2 x 0.6
For applying a 32.768 KHz square wave clock signal having an amplitude of 1.8Vpp from an external source (e.g. MCU) to the P2_0 pin of the DA1468x, the following procedure needs to be applied:
• XTAL32K oscillator must be disabled by applying:
CLK_32K_REG [XTAL32K_ENABLE] = 0x0
• CLK32K_SOURCE must be set to select external clock signal:
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CLK_CTRL_REG [CLK32K_SOURCE] = 0x3
• P2_0 must be set into GPIO function:
P20_MODE_REG [PID] =0x0
• Direction of the pin must be input:
P20_MODE_REG [PUPD] =0x0

5.3.3 Generating a clock output from the DA1468x

The DA1468x SoC can output one clock signal at a time, the output GPIO selection is flexible. Assuming we want to output the 16 MHz clock at GPIO P1_0, following must be set:
- P10_MODE_REG: PUPD set to 0x3 - Set P1_0 as Output
- P10_MODE_REG: PID set to 0x34 (52) for CLOCK.
- GPIO_CLK_SEL: FUNC_CLOCK_SEL set to 0x3 for the 16MHz Xtal clock.
Please find below the tables showing the P1_0 register settings: P10_MODE_REG (0x5000302E), and GPIO Clock Selection: FUNC_CLOCK_SEL (0x500030D0).
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Figure 16: Clock output, P10_MODE_REG - PUPD and PID selection
Figure 17: Clock output, GPIO_CLK_SEL - FUNC_CLK_SEL, clock selection

5.4 UART

Table 11: Default UART pins
Function
Pin
name
AQFN60
Pin
WLCSP
Pin
UART
UART transmit (UTX)
P1_3
B23
B6
UART receive (URX)
P2_3
A35
B5

5.5 SWD (JTAG)

P0_6 and P2_4 are assigned to the SWDIO and SWCLK signals respectively. P0_6 and P2_4 can be used as GPIOs when they will not be used as SWD (serial wire debugging) interface.
Table 12: JTAG pins
Function
Pin
name
AQFN60
Pin
WLCSP
Pin
JTAG JTAG data (SWDIO)
P0_6
B8
F4
JTAG clock (SWCLK)
P2_4
A14
F5
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5.6 QSPI Flash memory

Device:
DA14680
DA14681
DA14682
DA14683
Embedded QSPI Flash
✓ ✗ ✓
✗
The DA14680/682 chip versions contain an embedded low power 8Mbit QSPI flash, which is used to directly execute code from it (using the CPU cache) or mirror the contents from it into the SysRAM. Please note that for these DA14680/682 chips, the corresponding six QSPI signals are not connected to pins P0_0 thru P0_5.
The VDDIO pin though, needs to be connected to the 1.8V power supply, which is the DA14680/682’s
V18 rail. The DA14681/683 SoCs can use an external low power Quad-SPI FLASH.
The recommended part, also used on the PRO development kit, is the W25Q80EW (8Mbit) QSPI flash memory, WLCSP package. This is a power efficient QSPI flash having a supply voltage of 1.8V. As the maximum operating frequency of the QSPI interface is 96 MHz, for achieving the best performance, a suitable QSPI Flash memory that can operate at this clock frequency is strongly suggested.
For avoiding signal integrity issues, keep the distance between the processor and the flash memory as short as possible. If needed, apply 47Ω to 56Ω termination series resistors in all six QSPI lines. The in Figure 3 and in Figure 4 indicated 10K pull-up resistor at the QSPI Flash CS pin is not mandatory, the DA14681/683 QSPI_CS port will also pull the CS line high.
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5.7 USB and VBUS

The USB interface is an integrated USB controller compatible with the USB 1.1 FS specification. It’s advised not to apply series termination resistors in the DA1468x USBP and USBN data lines like commonly done, the DA1468x doesn’t need these resistors and they will negatively affect the USB’s signal integrity, deteriorating the rise- and fall-times too much when using longer USB cables. The USB transceiver module is accessed through the USBP (D+) and USBN (D-) signals which are multiplexed with the P2_2 and P1_1 GPIOs respectively. It is important to configure P1_1 and P2_2 as USB pins before the USB block is enabled, or USB block may be damaged if voltage applied to the pins (when they are configured as GPIOs). For using P1_1 and P2_2 in GPIO mode, USBPAD_REG [USBPAD_EN] must be set.
Figure 18: Recommended topology for USB functionality

5.7.1 USB ESD measures

In Figure 18, a recommended configuration is illustrated, and an ESD protection circuit like the ESD diode PRTR5V0U2X must be in place for ESD protection of the USB lines. In case USB functionality is not required but charging functionality is wished, charger contact pins can be applied in the application for instance to provide +5 V to the VBUS pin of the DA1468x device. For ESD reasons, make sure an ESD protection device is applied directly between the two charger pins. The ESD diode at the +5 V VBUS supply should have a high enough reverse stand-off voltage or maximum reverse working voltage to make sure it’s not conducting at expected and allowed VBUS voltages: e.g. 5.75 V. Please make sure to have a short and solid ground connection, having a low impedance, to the ground terminal of the ESD protection device. Please read also section 5.9 for layout related ESD topics.
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5.7.2 VBUS circuitry.

The suggested VBUS R-C filter circuit, consisting of R6 and C2, is explained here. The USB port is used for the charger supply and the USB cable provides power to the VBUS pin of the DA1468x SoC. The USB cable exhibits mainly an inductor L, and its value is related to the length of the cable. At the VBUS pin of the DA1468x chip, there is a ceramic supply decoupling capacitor (C2). When the USB cable is plugged-in at the connector, there is a step-voltage applied to the LC series resonator. Depending on the quality of this resonator, a voltage of twice the initial USB voltage can be present on this VBUS pin (2 x 5V = 10V). This can result in damaging the circuits inside the DA14680
and must therefore be avoided !
A way of protecting the DA1468x against high peak voltages during USB-cable insertion is to lower the Q factor of the resonator circuit by adding a series resistor in the line: R6. This series resistor increases the “Damping” of the LC circuit. For an L-C series circuit the damping is
defined as: 𝐷𝑎𝑚𝑝𝑖𝑛𝑔 =
𝑅6
2
𝑥
√
𝐶2
𝐿
It is beneficial to have a large capacitor on the VBUS pin. A larger capacitor value results in a lower value of the series resistor when a certain amount of damping is required.
Figure 19: Relation between damping and step-response of a series LC resonator
When the inductance has increased because of a longer cable and the series resistance is not adapted, the step-response will show more ringing (with a higher amplitude). Next plots are taken from a system with sufficient damping for a 60 cm cable connection, whereas, when the length of the cable is increased to 150 cm, the damping reduces leading to larger voltage overshoots.
Figure 20: used USB circuit for testing
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The pink coloured traces show the VBUS voltage, the blue traces show the VBUS current.
Figure 21: Step response with 60 cm (left) and 150 cm (right) cable (non USB-cable).
A damping network of 0.39 Ω and 10 μF capacitor on VBUS is used.
For a longer cable length (300 cm), the ringing (and overshoot) gets worse:
Figure 22: Step response with 300 cm cable (non USB-cable) and the same
damping network as above (0.39 Ω and 10 μF capacitor on VBUS).
The construction of an USB cable (where the positive and negative wires are close together) is much better regarding the amount of inductance. When a 1.5 meter USB cable is used in the same situation as above gives the below step-response: Figure 22.
So the 0.39 Ω series resistor and a 10 µF capacitor on the VBUS will give sufficient damping for short to middle length USB-cables. This configuration is recommended for typical cases. When longer cables are used, higher resistor values might be needed to achieve sufficient damping. Maximum charge current and allowed voltage drop over the series resistor can limit the amount of damping in that case.
Selection of the resistor value must be done with care. With a high value resistor, the input VBUS voltage could be decreased to a level that eventually the required charging voltage level cannot be reached anymore. Also a high peak current (e.g. due to vibrator motor operation) will cause a sudden drop on the VBUS input and possibly trigger an unexpected USB detach interrupt.
Alternatively to the mentioned 0.39 Ω and 10 µF parts, a 0.56 Ω resistor and a 4.7 µF capacitor, or a
0.47 Ω and a 6.8 µF can be used. These R-C combinations will result in the same damping value.
Preferably the capacitors should be at least 10 V types.
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Figure 23: Step response of VBUS with 0.39 Ω and 10 μF for a 1.5 m USB cable.

5.8 Hibernation Mode and wakeup

For shipment purposes, applications with the DA1468x SoC can be put into hibernation mode, which is also called “shipping mode”. In this ultra-low power mode, there is no RAM retained, no clocks running (so no RTC), and all domains are off to minimize power consumption and to avoid discharging the onboard battery. The V33 and the V12 power rails are supplied from low power clamps which are programmable and can be lowered during hibernation to reduce power dissipation as much as possible.
The system can wake up from hibernation by HW Reset, Power-On Reset (POR) or Wake-Up controller (GPIO trigger).
● HW Reset: it is triggered by making the RST pin high.
● Power-On Reset (POR).
● Using the Wake-Up Controller (GPIO Trigger): the Wake-Up Controller can be programmed to
wake up the DA1468x from extended-sleep (clocked) mode as well as from clockless sleep modes (deep-sleep, hibernation mode).
The device wakes up from hibernation when a triggering event appears (rising or falling edge on GPIO) and starts execution as if a HW reset has occurred, since there is no retained memory. The GPIOs can be latched to any configurations (input, input pull-up, or input pull-down) and retains their states during hibernation. The wake-up can occur from different sources, such as buttons or an external controller.
The wake-up controller can also be used for waking up the DA1468x from hibernation-mode when a USB cable is plugged in to the device. In this case, a resistor divider from VBUS is used and the circuit schematic is shown in Figure 24. When the USB cable is plugged in to the device, the GPIO state changes (via the voltage divider) from Low to High and the device wakes up from Hibernation mode (Figure 25). The voltage divider (R1 = R2 = 620 kΩ) divides the USB voltage by two in hibernation mode where the GPIO is configured as input. Since this is intended to be a one-time wakeup, when the system exits hibernation mode the application must either disable the wakeup controller on that GPIO or configure the GPIO as input pull-down (adding the internal 25 kΩ resistor
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in parallel to R2). This reduces the voltage divider output (below 0.2 V) and prevents the device from waking up every time a USB cable is plugged in.
Figure 24: Wakeup from Hibernation by VBUS voltage using GPIO trigger
Figure 25: GPIO set as Input (no pull)
Note: since the DA14680-01 and the DA14681-01 SoCs are not clockless when in ‘shipping mode’, these SoCs can be woken up directly by applying a voltage to the VBUS input of the SoC by means of plugging in the USB cable. These SoCs use the LDO_VBAT_RET instead of the ~2V Clamp).
The above method (Figure 24) needs to be applied to the DA14682-00 and the DA14683-00 only. These SoCs are clockless when in ‘shipping’ or hibernation mode and need the Wake-Up Controller to wake up from this clockless mode (using the ~2V LDO_Ret Low Power Clamp).
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5.9 RFIO port

The DA1468x provides a single ended RFIO port, matched to 50 Ω. The RFIO port consists of the RFIOp and RFIOm pins, where RFIOm is connected to ground. A copper trace with a characteristic impedance of 50 Ω interconnects the RF port and the antenna. A pi-network (Z1, Z2, Z3) close to the antenna feedpoint is added for antenna matching purposes.
Figure 26: RF matching circuit must be placed as close as possible to the antenna
Minimize the transmission line length between radio IC and antenna in the PCB layout.
o The characteristic impedance of the transmission line should match the required radio
impedance: 50 Ohm.
o Place the antenna matching components (Z1, Z2, Z3) as close as possible to the
feeding point of the antenna.
o Make sure that the component’s GND are connected on the same GND plane (left-
hand side of the transmission line in Figure 28 and right-hand side in Figure 33).

5.10 PCB layout

The DA1468x PCB layout is mainly dependent on the chip’s package. The fine pitch of WLCSP package is suitable for microvias approach whereas for AQFN package, a PTH-vias approach can be implemented.
Microvias or PTH vias: Microvias and especially microvias on chip pads, make board design easier because of their small size. Copper filled vias offer low dc resistance. The thickness of the dielectric layer depends on microvias aspect ratio (hole diameter to microvias depth), a pcb manufacturer capability. Assuming that microvias diameter is 100 µm, then for an aspect ratio 1:0.8, the dielectric layer can’t be higher than 80 µm. The cost of producing a PCB with microvias is higher in comparison to a PCB with PTH vias. For copper filled vias, cost and production time are significantly higher.
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Figure 27: WLCSP53 PCB stackup
ESD considerations: Please consider these measures for a good ESD performance of your application. See also the USB section 5.7.1 for ESD measures on the USB connector.
- If charger contact pins are used, place an ESD protection device directly between the two charger
connections: VBUS and ground. ESD testing according IEC 61000-4-2 means that ESD shooting at the charger contact pins will be done. At least upto 6KV level according the Human Body Model.
- Isolate the 16MHz Xtal ground connections from the ground used by the ESD protection devices.
- It's strongly advised to connect the battery ground terminal to the same ground point or ground
plane as the Vbus ground connection.
- If any GPIO or the antenna can be touched by the user, provide an ESD protection device at these.
- Please read also AN-B-056 - DA14680_681 Recovery from System Level ESD Events [3].

5.10.1 PCB layout for WLCSP53 package

An example pcb layout, where all signals are extracted, is presented below (Figure 28). This is a 4 layers pcb, in 1-2-1 configuration. Microvias, 100 µm - 250 µm were used between layers Top (L1) – L2 and L3- Bottom (L4). No buried vias have been used. Finally the PTH vias are 200 µm - 450 µm (drill diameter - pad diameter).
On the top layer, the signals of the external row are routed. Layer 2, is used for routing the pins of the internal row. Layer 3 is the reference GND plane (normal ground vias connect to this layer directly; 50 ohms microstrip line uses this layer as a ground reference).
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Generic guidelines for the WLCSP53 PCB layout are:
• Active components operating at high frequency should have their layout made as compact as
possible. This will prevent the cross-coupling between lines and also minimizes the parasitic effects which will have a negative impact on the operating parameters.
• Always provide a solid grounding to the radio IC. Use as many vias as possible to create a
solid GND under the IC itself and connect it to inner and bottom GND layers.
• Place the 16 MHz or 32 MHz crystal used as reference for the BLE radio as close as
possible to the IC. This will minimize any additional capacitive load on the input pins and reduces the chance of crosstalk and interference with other signals on the board. For the same reason, please provide openings in the nearest ground layer under the ‘hot’ pads of the 16 MHz or 32 MHz crystal. Please refer to Figure 28.
Figure 28: WLCSP53 PCB layout, top side
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Figure 29: WLCSP53 PCB layout, layer 2
Figure 30: WLCSP53 PCB layout, layer 3, reference GND
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Special attention must be given to the routing of the GND pins at the center of the package. PTH vias are used whereas the RFIOm and PSUB_RF signals are separated from the rest of the VSS pins on top layer:
1. RFIOM (A3), PSUB_RF (B4) and ESDN (A5)
o Create a GND island on TOP layer, as it is illustrated on Figure 31. o Use 2 traces (as short as possible) to connect to 2 PTH vias (not microvias). The
PTH vias are connected to layer 2 (ground plane used for 50 Ohms microstrip line).
2. GND_RF2 (C3), GND_RF1 (D3), AVS1 (D4) and SOCN (E3):
o Create the GND island on TOP layer as shown on Figure 31 o Connect this island with a PTH via (not microvia) to the layer 2
3. VSS1 (C6) , VSS2 (D5), VSS3 (D6), VSSIO1 (E6), VSSIO2 (E5) and AVS2 (E4):
o Create the GND island on TOP layer as shown on the draft PCB below o Connect this island with a PTH via (not microvia) to the layer 2.
4. GND_BUCK (G7)
o Connect to GND as presented on Figure 31 o A decoupling cap should be placed very close to GND_BUCK and VBAT1, as is
presented on Figure 28.
Figure 31: Ground connectivity Top (left) and layer 2 (right)
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5.10.2 PCB layout for AQFN60 package

The PCB layout for the AQFN60 package, is implemented in a 4 layers PCB. No microvias required. The PTH vias are 200 µm - 450 µm (drill diameter – pad diameter). The PCB layer 2 is the reference ground: the ground vias connect to this layer, and the 50 Ohm microstrip line uses this layer as a ground reference.
Figure 32: AQFN60 PCB stackup
General guidelines are:
• Active components operating at high frequency should have their layout made as compact as
possible. This will prevent the cross-coupling between lines and also minimize the parasitic effects which will have a negative impact on the operating parameters.
• Always provide a solid ground to the chip’s ground pins. In particular the DCDC_BUCK
ground is a critical ground connection. Apply multiple vias to create a solid GND under the IC itself and connect it to the inner and the bottom GND layers. A 3x3 via matrix in the chip’s ground is considered good.
• Place the 16 MHz or 32 MHz crystal as close as possible to the IC. This will minimize any
additional capacitive load on the input pins and reduces the chance of crosstalk and interference with other signals on the board.
For the same reason, please provide openings in the nearest ground layer under the ‘hot’
pads of the 16 MHz or 32 MHz crystal. Please refer to Figure 33.
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Special care must be given to the grounding of the following pins:
• RFIOM (pin 51): Route using a minimum length line to an independent normal ground via (do
not connect with the ground paddle to prevent noise to be coupled into the RF circuits). This normal ground via connects to the ground plane (2nd layer).
• ESDN: (pin 53): Route using a minimum in length line to an independent standard ground via
(do not connect with the ground paddle). This standard ground via connects to the ground plane (2nd layer).
• The ground paddle (at the bottom of the aQFN package): use a matrix of 3x3 or 4x4 normal
vias to the ground-plane (2nd layer). This paddle measures about 3.5 mm x 3.5 mm. Please make sure the ground-pad shape follows the shape of the paddle, including the exposed paddle parts. In order to avoid potential BOD problems when the SIMO BUCK DCDC is active (lifting of the internal BOD reference voltage caused by large DCDC peak currents), a ground via connected to a solid ground-plane near the DCDC_BUCK exposed ground stub must be present. In Figure 33 it’s the most bottom-left placed via in the ground under the chip. This Buck DCDC_Ground is located between the VBAT2, VBAT1 and VBUS pins: between pins B6 and B7.
Figure 33: AQFN60 PCB layout, top layer
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Figure 34: AQFN60 PCB layout, layer2, reference ground

5.11 AQFN60 - Package Outline (POD) Information

Please refer to Section 39 of the DA14680-01, DA14681-01 and DA14682-00, DA14683-00 datasheets for information on the AQFN60 package outline. [1]

5.12 WLCSP53 - Package Outline (POD) Information

Please refer to Section 39 of the DA14680-01, DA14681-01 and DA14682-00, DA14683-00 datasheets for information on the WLCSP53 package outline. [1]
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Appendix: AQFN60 assembly and soldering guidelines

A.1 PCB

There are two types of land patterns are chosen for user PCB design, one is Solder Mask Defined (SMD), solder mask openings smaller than metal pads. The other is Non-Solder Mask Defined (NSMD), solder mask openings larger than metal pads. Better control of the copper etching process as compared to the solder masking process makes NSMD preferable. Also, the SMD pad definition can introduce stress concentrations near the solder mask overlap region that can result in solder joints cracking under extreme fatigue conditions.
Using NSMD instead improves the reliability of solder joints as solder is allowed to “wrap
around” the sides of the metal pads on the board.
NSMD is recommended to use on SMT assembly, the pad size used on the Dialog boards as
showing below:
Terminal pad: 0.25 x 0.25 mm ; Terminal solder mask: 0.4 x 0.4 mm
Figure 35: PCB footprint data
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A.2 Stencil Design

• Basic concept: Aspect Ratio ( W/T, 2R/T) > 1.5, Area Ratio (W/4T, R/2T) > 66%
• Trapezoidal Aperture: Bottom Opening 25~50 microns larger than the Top, Well design for paste
release
• Use laser cutting followed by electro-polishing for stencil fabrication.
• The recommended stencil apertures are the same as the PCB land pattern, thickness is 0.1mm
• Use Type 4 solder paste (25 to 45 micron particle size range) or finer for solder printing, and
SAC305 is a common used solder paste. Senju M705-S101-S4 is recommended solder paste.
• For the thermal paddle stencil opening, using array of 2x2 opening and 20% opening of PCB
thermal paddle area is recommended to avoid void resident inside thermal paddle and can get
better solderability.
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Stencil Thickness: 0.1 mm
Figure 36: Recommend of stencil opening of thermal

A.3 Component Placement

For placing the AQFN, following methods can be used for recognition and positioning:
• Vision system to locate package outline.
• Vision system to locate individual bumps. It is recommended that the side-lighting option on the
pick and place machine’s vision system be used when attempting to use an individual bump recognition approach to ensure better contrast for bump recognition
• It is preferred to use a machine with fine-pitch placement for better accuracy.
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A.4 Reflow Profile

Below reflow-profile, based on using solder paste SAC305
Figure 37: Reflow profile for solder paste SAC305
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Revision history

Revision
Date
Description
1.0
22-Feb-2016
Initial version.
1.1
20-Apr-2016
Updated with ESD and Layout suggestions, and several minor changes and additions.
1.2
02-Jun-2016
Several corrections and changes in sections 5 and A.1
1.3
22-Jul-2016
Updated section 4, 5.8 and 5.9.
1.4
26-Aug-2016
Added information on USB signal integrity in section 5.7.
1.5
24-Jun-2017
Adding SIMO DCDC inductor examples in Table 6. 16 MHz crystal examples in Table 7 and 32.768 KHz crystal examples in Table 8. A number of corrections and changes in Table 5.
1.6
24-Jan-2018
Added information on the DA1468x SIMO Buck DCDC in section 5.1.
1.7
14-Feb-2018
Removing DA14681-00, adding the DA14682-00 and DA14683-00
1.8
23-Jul-2018
Added ‘Feature Available?’ checkboxes on top of relevant sections
1.9
28-Mar-2019
Removed the POD drawings, instead referring to the datasheets Added the Hibernation Mode and Wakeup section 5.8.
Change details: v1.1
● Table 1 adapted: DA14680 available in AQFN package only.
● ESD measures in section 5.9.
● Additional PCB layout guidelines in section 5.9.2.
Change details: v1.2
● Corrections in section 5.1 for VDD1V8 (V18) and VDD1V8P (V18P) usage.
● Section A.1: PCB terminal pad size changed from 0.3 mm to 0.25 mm.
Change details v1.5
● Table 5: the rated voltage of capacitors C6, C7 and C8 have been corrected to 10V.
And rated voltage of C2, C10 and C11 changed to 10V in order to have larger effective capacitance.
● 32 MHz crystal references removed in section 5.3.1
Change details v1.7
● This application note is to be used with the DA14680-01/681-01 and DA14682-00/683-00 SoCs.
● Added a table with 32 MHz crystal examples (DA14682/683 support 32 MHz crystal operation)
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