Desktop Motherboard M630 Schematics
5
4
3
2
1
ABIT - M630 SCHEMATICS
D D
C C
TITLE SHEET
COVER SHEET
SYSTEM & POWER BLOCK DIAGRAM
RST/PWB/PWROK MAP
GPIO SETTING
CLOCK SYNTHESIZER
P4 LGA775 PART
MCH_Part
DDRII Channel A/B
PCIEX16
ICH9
PCIEX1 SLOT 1,2 & SATA
PCIE TO PATA
MODIFY
1
2
3
4
5
6,7
8,9,10
11,12,13
14
15,16,17
18
19
Version: 0.22
IP35/IP35-E
Model Features
Silent OTES 2, Dual DDR2 800
PATA, GbE, (IEEE-1394 IP35 only)
7.1-Channel HD Audio
HD AUDIO
B B
PCIE TO GLAN
PCI SLOT 1,2,3
PCI TO IEEE1394
LPC SIO & FDC
FPIO, FWH, SMB ,ATX
KB, MS, FP-USB
VCCP PWM
A A
DC TO DC CONVERT 1/2
http://laptop-motherboard-schematic.blogspot.com/
FAN, THERMAL, CPU CHG
5
4
3
20
21
22
23
24
25
26
27
28,29
30
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
2
Wednesday, April 11, 2007
M630
1
/COVER SHEET
132
0.22
5
4
3
2
1
POWER DESIGN DIAGRAM
D D
VCCP
RT8802A
4 PHASE
SWITCHING
POWER
VRD 11
CPU VCCP
VRD 11
BLOCK DIAGRAM
P4 LGA775
ADDR
CTRL
DATA
CK505
5VDUAL
AGTL+ BUS
W83320G
VDDIO
LR3
C C
W83320G
SWITCHING
SWITCHING
DDR2
VDDMEM
NB/SB
V1P25_MCH
PCI EXPRESS X16
GRAPHICS
X16
ADDR
Intel IP35
FSB 800/1066
CTRL
DATA
MCH
4 DIMM DDR2
VCC3
PCI CNTRL
PCI ADDR/DATA
PCI EXPRESS X1
3 PCI CON
2 PCI EXPRESS X1 CON
LR1+LR2
ACPI CONTROLLER
W83304CG
3V/5V<=>5VSB
ICH
V1P5_ICHIO
VCC3
MOSFET
VCC5SB
VCC5
5VDUAL
SATA 3Gb
6 PORTS
USB 2.0
12PORTS
DMI
SATA/3Gb
ICH9/R
USB
B B
VLDT
VCCP
PROTECT
VAGP
LR4
V1P2_VTT
1.2V
V1P25_MCH
3VDUAL
FirmWare Hub
SIO
LPC
Azalia
HD AUDIO
ALC888
V1P05_ICH
VDDMEM
W83310DG
A A
LDO
V1P5_ICHIO
VTTMEM
1/2 VDDMEM
Floopy
KB/MS
7.1 Channel
S/PDIF IN/OUT
PCI
PCI EXPRESS X1
IEEE1394
TI
TSB43AB22
REALTEK RTL8110SC
GbE LAN
PATA
JMICRON JMB368
PATA
1 PORT
RJ45
http://laptop-motherboard-schematic.blogspot.com/
VCC3
RT9179
5
LDO
H_VCCPLL
( 1.50V)
4
3
2
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/SYSTEM & POWER BLOCK DIAGRAM
232
0.22
5
PLTRST#
SYS_RESETB
ICH9
P_PCIRST#
D D
4
PCI SLOT
PCI SLOT1/2/3
IEEE 1394
PCI IEEE1394
PLTRST#
LRESET#
PCIE_OB_RST#
PCIE_SL_RST#
SIO
MCH
WDTO#
3
GLAN
PCIEX1 GLAN
PCIE X1
SLOT
PCIEX1 SLOT1/2
2
PCI BUS ROUTE
IDSEL
REQ/GNT
INTA
INTB
INTC
INTD
PCIE BUS ROUTE JMB363
SOURCE
BUS #
1394 PCI1 PCI2 PCI3
18 19 20 21
0123
PIRQ#E PIRQ#F
X
X
X
PIRQ#G
PIRQ#H
PIRQ#E
G-LAN PCIE1 PCIE2 PCIE X16
SB SB SB NB
SB
2341
CLK GROUP1 ROUTE
SRC1
SRC2 SRC3 SRC4 SRC5 SRC6 SRC7 SRC8 SRC9 SRC10 SRC11SRC0
PIRQ#G
PIRQ#H
PIRQ#F
PIRQ#E
1
BUS ROUTE
PIRQ#H
PIRQ#F
PIRQ#G
PIRQ#E
0~15
PCIE X16
FWH
RST
FP_RSTSW#
C C
FPIO
FP_PWRSW#
PSIN# PSOUT# W83627_PWRSW# PWRBTNB
PSON#
S3#
RESET MAP
DELAY 64msex
SIO
ICH9
S3#
PCIEX1 S1
PCIEX1 S2
PCIE MCH
PCIE ICH
ICH SATA
JMB363
G-LAN
CLK GROUP2 ROUTE
PCI0
PCI S1
PCI S2
http://laptop-motherboard-schematic.blogspot.com/
PCI1
PCI2 PCI3 PCI4 PCI5 USB48 REF14
PCI S3
S3#
PS_IN#
PWRBTN#
304CG
PS_OUT#
PSON#
ATXPWR
ICH
FWH
SIO
1394
SIO48
ICH48
B B
PWRON MAP
ICH14
After ATX PWROK
1.2v Level 3.3v Level
VIDPWRGD
CPU
VTT > 0.7v
A A
5
Delay 8.7msec
Delay 196usec
EN
Chipset PWROK SEQ
4
PWM
VR_READY
Adjustable Dealy
3
Delay 6.6msec
2
ALL_PWROK
for NB/ SB VRMPWRGD
ALL_PWROK_DELAY
for SB PWROK
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/BLOCK DIAGRAM
332
0.22
5
4
3
2
1
W83304CG Voltage Adjust Table
ICH9 GPIO SETTING
Pin Name Power Well Usage Default
GPIO0 3.3V Core ACZ_DET GPI
GPIO1 3.3V Core TACH1 GPI
D D
C C
B B
A A
GPIO2 5V Core PIRQ#E GPI
GPIO3 5V Core PIRQ#F GPI
GPIO4 5V Core PIRQ#G GPI
GPIO5 5V Core PIRQ#H GPI
GPIO6 3.3V Core TACH2 GPI
GPIO7 3.3V Core TACH3 GPI
GPIO8 3.3V Sus LPC_PME# GPI
GPIO9 3.3V Sus WOL_EN Native
GPIO10 3.3V Sus GPIO10 GPI
GPIO11 3.3V Sus SMBALERT# Native
GPIO12 3.3V Sus LAN_PME# GPI
GPIO13 3.3V Sus 1394_PME# GPI
GPIO14 3.3V Sus CLGPIO2 GPI
GPIO15 3.3V Sus STP_PCI# Native
GPIO16 3.3V Core FWH_WP# GPO
GPIO17 3.3V Core TACH0 GPI
GPIO18 3.3V Core GPIO18 GPO
GPIO19 3.3V Core SATA1GP GPI
GPIO20 3.3V Core GPIO20 GPO
GPIO21 3.3V Core SATA0GP GPI
GPIO22 3.3V Core SCLOCK Native
GPIO23 3.3V Core LDRQ1# Native
GPIO24 3.3V Sus CLGPIO0 GPO
GPIO25 3.3V Sus STP_CPU# Native
GPIO26 3.3V Sus S4_SATE# GPO
GPIO27 3.3V Sus EL_STATE0 GPO
GPIO28 3.3V Sus EL_STATE1 GPO
GPIO29 3.3V Sus OC5# Native
GPIO30 3.3V Sus OC6# Native
GPIO31 3.3V Sus OC7# Native
GPIO32 3.3V Core GIPO32 GPO
GPIO33 3.3V Core BORAD ID GPO
GPIO34 3.3V Core BOARD ID GPO
GPIO35 3.3V Core SATACLKREQ# GPO
GPIO36 3.3V Core SATA2GP GPI
GPIO37 3.3V Core SATA3GP GPI
GPIO38 3.3V Core SLOAD GPI
GPIO39 3.3V Core SDATAOUT0 GPI
GPIO40 3.3V Sus OC1# Native
GPIO41 3.3V Sus OC2# Native
GPIO42 3.3V Sus OC3# Native
GPIO43 3.3V Sus OC4# Native
GPIO44~47 N/A Not implemented N/A
GPIO48 3.3V Core SDATAOUT0 GPI
GPIO49 V_CPU_IO CPUPWRGD Native
GPIO50 5.5V Core REQ1# Native
GPIO51 3.3V Core GNT1# Native
GPIO52 5.5V Core REQ2# Native
GPIO53 3.3V Core GNT2# Native
GPIO54 5.5V Core REQ3# Native
GPIO55 3.3V Core GNT3# Native
GPIO56 3.3V Sus CLK_PWRDN# GPI
GPIO57 3.3V Sus Unused Native
GPIO58 3.3V Sus Unused Native
GPIO59 3.3V Sus OC0# Native
GPIO60 3.3V Sus Unused Native
5
4
a.V1P25 MCH(CR07/VLR3)
V1P25_OV
1
1
1
1
1
Bit3
000
00
0
0100
Bit2 Bit1 Bit0 V1P25_MCH
0
00
0
1
1
1
1
1
1
0
0
0
0
b.V1p05 MCH(CR02/VAGP)
Bit2
00
0
00
0
0110
0111
1000
1
11
00
00
0001
0100
1010
0110
Bit1 B it0 V1p05
0
01
1
1
1
100
101
11
11
c.V1p5 ICH(CR05/VLR2)
Bit6
Bit5 Bit4 V1p5
00
0
00
0
01
1
1
0
1
http://laptop-motherboard-schematic.blogspot.com/
0
1
100
101
11
11
d.V1p2 VTT(CR05/VLR1)
Bit2
Bit1 Bit0 V1p5
00
0
00
0
01
1
1
0
1
0
1
100
101
11
11
3
0
1
2
1
10
+0mv
+40mv
+70mv
+100mv
+130mv
+200mv
+270mv
+330mv
+0mv
+50mv
+100mv
+150mv
+200mv
+300mv
+400mv
+500mv
+0mv
+37.5mv
+75mv
+112.5mv
+150mv
+225mv
+300mv
+375mv
0
1
+0mv
+40mv
+80mv
1
+120mv
+160mv
1010
+200mv
+240mv
+280mv
+320mv
1
+400mv
+480mv
+560mv
+640mv
+720mv
+800mv
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/GPIO SETTING
432
0.22
5
3VDUAL
LF
D D
CLK_PW RDN#16
V0.21
VCC3_CLK_IO
C C
SMBDATA11,12,14,16,18,22,25,28
SMBCLK11,12,14,16,18,22,25,28
B B
VCC3_CLK
FSB
CKPWRGD
CLK_XI
CLK_XO
CHRPMP
R670
x10K
12
20
26
36
45
49
15
11
23
29
42
58
52
8
19
2
9
16
39
55
61
57
56
63
64
60
59
LF
DS
Q74
x2N7002N
G
FET-SOT23
200mA_5Ohm
SOT23
60V
U12
VDD_IO
VDD_PLL3_IO
VDD_SRC_IO1
VDD_SRC_IO2
VDD_SRC_IO3
VDD_CPU_IO
VSS_IO
VSS_48MHz
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF
VSS_CPU
VSS_PCI
VSS_PLL3
VDD_PCI
VDD_48MHz
VDD_PLL3
VDD_SRC
VDD_CPU
VDD_REF
FSB/TEST_MODE
CKPWRGD/PD#
SDA
SCL
XTAL_IN
XTAL_OUT
ICS9LPR501 TSSOP64-0_5
VCC3_CLK
R671
x10K
G
SOT23
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
REF/FSC/TEST_SEL
VCC12
R672 x10K
DS
Q73
x2N7002N
FET-SOT23
200mA_5Ohm
60V
CPUT0
CPUC0
CPUT1
CPUC1
DOT96T/SRCT0
DOT96C/SRCC0
SRCT1/SE1
SRCC1/SE2
SATAT/SRCT2
SATAC/SRCC2
SRCT3/CR#_C
SRCC3/CR#_D
SRCT4
SRCC4
SRCT6
SRCC6
SRCT7/CR#_F
SRCC7/CR#_E
SRCT8/CPU_ITPT
SRCC8/CPU_ITPC
SRCT9
SRCC9
SRCT10
SRCC10
SRCT11/CR#_H
SRCC11/CR#G
PCI0/CR#_A
PCI1/CR#B
PCI2/TME
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
USB_48/FSA
IO_VOUT
LF
4
30V
D-SOT23-A1KA2
xBAT54C
SOT23
A1
K
A2
D19
3VDUAL
CK_H_CPU_P_R
54
CK_H_CPU_N_R
53
CK_H_MCH_P_R
51
CK_H_MCH_N_R
50
CK_PE_S2_P_R
13
CK_PE_S2_N_R
14
17
18
CK_ICH_SATA_P_R
21
CK_ICH_SATA_N_R
22
CK_PE_363_P_R
24
CK_PE_363_N_R
25
CK_PE_ICH_P_R
27
CK_PE_ICH_N_R
28
38
37
CK_PE_S1_P_R
41
CK_PE_S1_N_R
40
CK_PE_LAN1_P_R
44
CK_PE_LAN1_N_R
43
47
46
CK_PE_X16_P_R
30
CK_PE_X16_N_R
31
CK_PE_MCH_P_R
34
CK_PE_MCH_N_R
35
33
32
CK_PCI0_R
1
CK_PCI1_R
3
CK_PCI2_R
4
CK_PCI3_R
5
CK_PCI4_R
6
CK_PCI5_R
7
FSA
10
FSC
62
48
25V
50A_8.6mOhm
TO252
FET-TO252
xIPD09N03LAG
G
Q72
D S
RN8A 33_4P2R
1 4
RN8B 33_4P2R
2 3
RN9A 33_4P2R
1 4
RN9B 33_4P2R
2 3
RN17B 33_4P2R
2 3
RN17A 33_4P2R
1 4
RN15B 33_4P2R
2 3
RN15A 33_4P2R
1 4
RN10B 33_4P2R
2 3
RN10A 33_4P2R
1 4
RN13B 33_4P2R
2 3
RN13A 33_4P2R
1 4
RN16A 33_4P2R
1 4
RN16B 33_4P2R
2 3
RN11A 33_4P2R
1 4
RN11B 33_4P2R
2 3
RN14B 33_4P2R
2 3
RN14A 33_4P2R
1 4
RN12B 33_4P2R
2 3
RN12A 33_4P2R
1 4
R421 12
R422 12
R420 33
R417 33
R416 33
R419 33
R418 33
R423 12
R424 12
R375 33
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
FB42
x30 OHM/100MHz
L0805±25% 3A
V0.21
FB15
30 OHM/100MHz
L0805±25% 3A
C447
x10PF
0603
NPO
50V
0603
C451
x10PF
NPO
50V
0805
C374
10UF
Y5V
10V
3
VCC3_CLK
0603
C379
0.1UF
Y5V
16V
0603
C380
0.1UF
Y5V
16V
0603
C377
0.1UF
Y5V
16V
0603
C425
0.01UF
Y5V
16V
0603
C424
0.01UF
Y5V
16V
0603
http://laptop-motherboard-schematic.blogspot.com/
C449
C450
0603
C448
x10PF
NPO
50V
0603
x10PF
NPO
50V
0603
x10PF
NPO
50V
0603
C452
x10PF
NPO
50V
0603
C446
x10PF
NPO
50V
C422
0.01UF
Y5V
16V
0603
2
VCC3_CLK VCC3_CLK_IO
30 OHM/100MHz
C364
C454
C453
x10PF
NPO
50V
0603
x10PF
NPO
50V
0603
x10PF
NPO
50V
FB14
1
C376
C375
L0805±25% 3A
0.1UF
0603
0603
Y5V
16V
0.1UF
0603
Y5V
16V
CK_H_CPU_P 6
CK_H_CPU_N 6
CK_H_MCH_P 8
CK_H_MCH_N 8
CK_PE_S2_P 18
CK_PE_S2_N 18
CK_ICH_SATA_P 15
CK_ICH_SATA_N 15
CK_PE_363_P 19
CK_PE_363_N 19
CK_PE_ICH_P 15
CK_PE_ICH_N 15
CK_PE_S1_P 18
CK_PE_S1_N 18
CK_PE_LAN1_P 21
CK_PE_LAN1_N 21
CK_PE_X16_P 14
CK_PE_X16_N 14
CK_PE_MCH_P 8
CK_PE_MCH_N 8
CK_33M_FWH 25
CK_33M_SIO 24
CK_33M_S3 22
CK_33M_S1 22
CK_33M_S2 22
CK_33M_1394 23
CK_33M_ICH 15
CK_48M_SIO 24
CK_48M_ICH_USB 15
CK_14M_ICH 16
C378
0.1UF
Y5V
16V
0603
C421
0.01UF
Y5V
16V
0603
C423
0.01UF
Y5V
16V
0603
C360
0.01UF
Y5V
16V
LF
FSA
C401
0603
27PF
NPO
50V
C414
0603
27PF
NPO
50V
LF
FSC
CK_PWRGD16
4
Y2
49US
14.318MHZ
XTAL-49US
49US
¡?0ppm_32PF
R354 1K
CLK_XI
CLK_XO
LF
CKPWRGD
3
VCC3_CLK
R405
LF
10K
R406
LF
10K
R407
LF
10K
CK_PCI4_R
CK_PCI5_R
CK_PCI2_R
CK_PCI4_R High: SRC5 Enabled
Low: CPU and PCI Stop#
CK_PCI5_R High: CPU_ITP Enabled and SRC8 Disabled
Low: CPU_ITP Disabled and SRC8 Enabled
CK_PCI2_R High: Overclock ing Disabled
Low: Overclocking Enabled
2
VCC3_CLK
R443
R376
LF
LF
47K
47K
CK_14M_ICH
CK_48M_ICH_USB
R361
R442
LF
LF
33K
33K
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/CLOCK SYNTHESIZER
532
0.22
B
SOT23
FSB
R410 1K
Q60
PMBS3904
TR-SOT23
200mA
E C
40V
R401
LF
1K
B
SOT23
LF
Q58
PMBS3904
TR-SOT23
200mA
E C
40V
LF
CPU_FSA6,24
CPU_FSB6,24
R396 4.7K
R362 1K
VCC3_CLK
B
SOT23
R360 1K
Q47
PMBS3904
TR-SOT23
200mA
E C
40V
R355
LF
B
SOT23
1K
Q46
PMBS3904
TR-SOT23
200mA
E C
40V
A A
LF
CPU_FSC6,24
R356 4.7K
5
5
4
3
2
1
H_FERR#
H_VCCPLL
VRD_VIDSEL
1%
TCK
TDI
TMS
TRST#
H_BPM0
H_BPM1
H_BPM2
H_BPM3
H_BPM4
H_BPM5
CPU_FSA
CPU_FSB
CPU_FSC
VTT_OUT_RIGHT
R108
LF
49.9_1%
1%
R105
LF
100_1%
1%
SK1C
P2
SMI#
K3
A20M#
R3
FERR#
K1
LINT_0
L1
LINT_1
N2
IGNNE#
M3
STPCLK#
A23
VCCA
B23
VSSA
C23
VCC_IOPLL
D23
VCC_PLL
AM2
VID_0
AL5
VID_1
AM3
VID_2
AL6
VID_3
AK4
VID_4
AL4
VID_5
AM5
VID_6
AM7
VID_7
AN7
VID_SELECT
F28
BCLK_0
G28
BCLK_1
AE8
SKTOCC#
AL1
THERMDA
AK1
THERMDC
AN3
VCC_SENSE
AN4
VSS_SENSE
AN5
VCC_MB_REGULATION
AN6
VSS_MB_REGULATION
G5
PECI
F6
IMPSEL
LGA775
SK-C775P
SK1D
AE1
TCK
AD1
TDI
AF1
TDO
AC1
TMS
AG1
TRST#
AJ2
BPM_0#
AJ1
BPM_1#
AD2
BPM_2#
AG2
BPM_3#
AF2
BPM_4#
AG3
BPM_5#
AC2
DBR#
AK3
ITP_CLK_0
AJ3
ITP_CLK_1
G29
BSEL_0
H30
BSEL_1
G30
BSEL_2
AM6
VTTPWRGD
1
H1
2
H2
3
H3
4
H4
LGA775
SK-C775P
3
GTLREF VOLTAGE SHOULD BE 0.67 x VTT = 0.8V
0603
LF
R122 10
C65
1UF
Y5V
16V
0603
C79
x220PF
X7R
16V
CPU_GTLREF_1
Close to PIN H2
TESTHI00
TESTHI_0
TESTHI_1
TESTHI_2
TESTHI_3
TESTHI_4
TESTHI_5
TESTHI_6
TESTHI_7
TESTHI_8
TESTHI_9
TESTHI_10
TESTHI_11
TESTHI_12
TESTHI_13
PWRGOOD
FORCEPR#
PROCHOT#
THERMTRIP#
COMP_0
COMP_1
COMP_2
COMP_3
COMP_4
COMP_5
COMP_6
COMP_7
COMP_8
FC5
F26
W3
F25
G25
G27
G26
G24
F24
G3
G4
H5
P1
W2
L2
N1
AK6
AL2
M2
A13
T1
G2
R1
J2
T2
Y3
AE3
B13
F2
R186 49.9_1%
TESTHI01
R118 49.9_1%
TESTHI02
R175 49.9_1%
TESTHI8
R131 49.9_1%
TESTHI9
R130 49.9_1%
TESTHI10
R134 49.9_1%
TESTHI11
R132 49.9_1%
TESTHI12
R109 49.9_1%
TESTHI13
R121 49.9_1%
TESTHI12
R115 0
H_PWRGD
FORCEPR#
PROCHOT#
THRMTRIP#
COMP0
R192 49.9_1%
COMP1
R125 49.9_1%
COMP2
R127 49.9_1%
COMP3
R128 49.9_1%
COMP4
R129 x49.9_1%
COMP5
R120 x49.9_1%
COMP6
R103 x49.9_1%
COMP7
R91 x49.9_1%
COMP8
R191 24.9_1%
CPU_GTLREF_1
H_PWRGD 16
THRMTRIP# 15
V0.2
LF
1%
R106 49.9_1%
W1
MSID_0
MSID_1
BOOTSELECT
LL_ID_0
LL_ID_1
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
V1
Y1
V2
AA2
A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30
AA1
J1
F27
LF
1%
R114 49.9_1%
LF
1%
R98 x49.9_1%
V0.2
V1P2_VTT
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
VTT_SEL 28
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
LF
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
1%
VTT_OUT_LEFT
V1P2_VTT
CPU_U1 7
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_OUT_LEFT
2
H_TEST7
CPU_G17
VTT_OUT_LEFT
C73
0.1UF
0603
Y5V
16V
H_VCCPLL
H_VCCPLL
0603
C173
0.01UF
Y5V
16V
0603
0.1UF
Y5V
16V
0603
C182
1UF
Y5V
16V
C177
V1P2_VTT
CPU_FSA
CPU_FSB
CPU_FSC
VTT_SEL
LF
R182 470
LF
R172 470
LF
R178 470
LF
R251 1K
VTT_OUT_LEFT
H_BR#
CPU_G1
H_TEST
LF
1%
R126 60.4_1%
LF
1%
R119 49.9_1%
LF
1%
R133 49.9_1%
VTT_OUT_RIGHT
H_CPURST#
H_IERR#
VIDPWRGD
PROCHOT#
FORCEPR#
H_BPM0
H_BPM1
H_BPM2
H_BPM3
H_BPM4
H_BPM5
TDI
TMS
VRD_VIDSEL
CPU_G1
TRST#
TCK
LF
1%
R75 60.4_1%
LF
1%
R100 60.4_1%
LF
R67 1K
LF
R72 150
LF
R78 150
LF
1%
R83 49.9_1%
LF
1%
R79 49.9_1%
LF
1%
R93 49.9_1%
LF
1%
R80 49.9_1%
LF
1%
R88 49.9_1%
LF
1%
R87 49.9_1%
LF
1%
R96 60.4_1%
LF
1%
R97 60.4_1%
LF
R69 1K
LF
R90 x0
LF
1%
R92 60.4_1%
LF
1%
R94 60.4_1%
KENTSFIELD SUPPORT
TESTHI8 H_BPM3
TESTHI9 H_BPM2
H_TEST
CPU_G1
C69
C70
1UF
1UF
0603
0603
Y5V
16V
Y5V
16V
LF
R82 x0
LF
R101 x0
LF
R81 x0
LF
R86 x0
VTT_OUT_RIGHT
VTT_OUT_RIGHT
0603
H_BPM1
H_BPM0
C62
0.1UF
Y5V
16V
0603
C59
1UF
Y5V
16V
0603
C60
1UF
Y5V
16V
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/P4 LGA775 PART A
632
0.22
VTT_OUT_RIGHT
R113
LF
GTLREF VOLTAGE SHOULD BE 0.67 x VTT = 0.8V
49.9_1%
1%
LF
0603
D2
C2
D4
H4
G8
B2
C1
E4
H_IERR#
AB2
P3
C3
E3
AD3
G7
AB3
U2
U3
H_BR#
F3
J16
H15
H16
J17
CPU_GTLREF_0
H1
CPU_GTLREF_1
H2
E24
H29
H_CPURST#
G23
B3
F5
A3
G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G19
G20
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
C17
A16
R123 10
C66
1UF
Y5V
16V
Close to PIN H1
H_D32
H_D33
H_D34
H_D35
H_D36
H_D37
H_D38
H_D39
H_D40
H_D41
H_D42
H_D43
H_D44
H_D45
H_D46
H_D47
H_D48
H_D49
H_D50
H_D51
H_D52
H_D53
H_D54
H_D55
H_D56
H_D57
H_D58
H_D59
H_D60
H_D61
H_D62
H_D63
D D
H_REQ[0..4]8
H_A[3..35]8
H_D[0..63]8
H_ADSTB08
C C
H_ADSTB18
B B
H_DBI08
H_STBP08
H_STBN08
A A
H_DBI18
H_STBP18
H_STBN18
H_REQ[0..4]
H_A[3..35]
H_D[0..63]
H_REQ0
H_REQ1
H_REQ2
H_REQ3
H_REQ4
H_D0
H_D1
H_D2
H_D3
H_D4
H_D5
H_D6
H_D7
H_D8
H_D9
H_D10
H_D11
H_D12
H_D13
H_D14
H_D15
H_D16
H_D17
H_D18
H_D19
H_D20
H_D21
H_D22
H_D23
H_D24
H_D25
H_D26
H_D27
H_D28
H_D29
H_D30
H_D31
5
H_A3
H_A4
H_A5
H_A6
H_A7
H_A8
H_A9
H_A10
H_A11
H_A12
H_A13
H_A14
H_A15
H_A16
H_A17
H_A18
H_A19
H_A20
H_A21
H_A22
H_A23
H_A24
H_A25
H_A26
H_A27
H_A28
H_A29
H_A30
H_A31
H_A32
H_A33
H_A34
H_A35
AB6
AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
AH5
AJ5
AJ6
AD5
A10
A11
B10
C11
B12
C12
D11
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G11
E12
G12
L5
P6
M5
L4
M4
R4
T5
U6
T4
U5
U4
V5
V4
W5
R6
W6
Y6
Y4
K4
J5
M6
K6
J6
B4
C5
A4
C6
A5
B6
B7
A7
D8
A8
B9
C8
G9
F8
F9
E9
D7
SK1A
A_3#
A_4#
A_5#
A_6#
A_7#
A_8#
A_9#
A_10#
A_11#
A_12#
A_13#
A_14#
A_15#
A_16#
ADSTB_0#
A_17#
A_18#
A_19#
A_20#
A_21#
A_22#
A_23#
A_24#
A_25#
A_26#
A_27#
A_28#
A_29#
A_30#
A_31#
A_32#
A_33#
A_34#
A_35#
ADSTB_1#
REQ_0#
REQ_1#
REQ_2#
REQ_3#
REQ_4#
LGA775
SK-C775P
SK1B
D_0#
D_1#
D_2#
D_3#
D_4#
D_5#
D_6#
D_7#
D_8#
D_9#
D_10#
D_11#
D_12#
D_13#
D_14#
D_15#
DBI_0#
STBP_0#
STBN_0#
D_16#
D_17#
D_18#
D_19#
D_20#
D_21#
D_22#
D_23#
D_24#
D_25#
D_26#
D_27#
D_28#
D_29#
D_30#
D_31#
DBI_1#
STBP_1#
STBN_1#
LGA775
SK-C775P
LF
1%
ADS#
BNR#
HIT#
RSP#
BPRI#
DBSY#
DRDY#
HITM#
IERR#
INIT#
LOCK#
TRDY#
BINIT#
DEFER#
MCERR#
AP_0#
AP_1#
BR_0#
DP_0#
DP_1#
DP_2#
DP_3#
GTLREF_0
GTLREF_1
GTLREF_2
GTLREF_SEL
RESET#
RS_0#
RS_1#
RS_2#
D_32#
D_33#
D_34#
D_35#
D_36#
D_37#
D_38#
D_39#
D_40#
D_41#
D_42#
D_43#
D_44#
D_45#
D_46#
D_47#
DBI_2#
STBP_2#
STBN_2#
D_48#
D_49#
D_50#
D_51#
D_52#
D_53#
D_54#
D_55#
D_56#
D_57#
D_58#
D_59#
D_60#
D_61#
D_62#
D_63#
DBI_3#
STBP_3#
STBN_3#
R104
100_1%
CPU_GTLREF_0_R16
CPU_GTLREF_0
C80
x220PF
0603
X7R
16V
H_ADS# 8
H_BNR# 8
H_HIT# 8
H_BPRI# 8
H_DBSY# 8
H_DRDY# 8
H_HITM# 8
H_INIT# 15
H_LOCK# 8
H_TRDY# 8
H_DEFER# 8
H_BR# 8
MCH_CPU_GTLREF 8
H_CPURST# 8
H_RS0# 8
H_RS1# 8
H_RS2# 8
H_DBI2 8
H_STBP2 8
H_STBN2 8
H_DBI3 8
H_STBP3 8
H_STBN3 8
4
CPU_GTLREF_0 7
CK_H_CPU_P5
CK_H_CPU_N5
H_SLOTOCC#30
FP_RSTSW#16,25
CPU_FSA/B/C TABLE
CBA
00
1
00
00
1800
H_SMI#15
H_A20M#15
H_FERR#15
H_INTR15
H_NMI15
H_IGNNE#15
H_STPCLK#15
H_VCCA7
H_VSSA7
H_VCCIOPLL7
CPUVID027
CPUVID127
CPUVID227
CPUVID327
CPUVID427
CPUVID527
CPUVID627
CPUVID727
VRD_VIDSEL27
THRMDA24,30
THRMDC24,30
VCCSENSE27
VSSSENSE27
PECI24
CPU_FSA5,24
CPU_FSB5,24
CPU_FSC5,24
VIDPWRGD27
FSB Freq.
0
CPU_GTLREF_1_R16
LF
R137 49.9_1%
http://laptop-motherboard-schematic.blogspot.com/
1333
1066
5
4
3
2
1
H_TEST 6
CPU_GTLREF_0 6
VCCP
1206
VCCP
1206
VCCP
1206
VCCP
1206
C82
10UF
X5R
6.3V
C94
10UF
X5R
6.3V
C48
10UF
X5R
6.3V
C67
10UF
X5R
6.3V
1206
1206
1206
1206
C83
10UF
X5R
6.3V
C95
10UF
X5R
6.3V
C39
10UF
X5R
6.3V
C2
10UF
X5R
6.3V
1206
1206
1206
1206
C84
10UF
X5R
6.3V
C96
10UF
X5R
6.3V
C47
10UF
X5R
6.3V
C125
10UF
X5R
6.3V
1206
1206
1206
1206
C85
10UF
X5R
6.3V
C101
10UF
X5R
6.3V
C3
10UF
X5R
6.3V
C109
10UF
X5R
6.3V
1206
1206
1206
1206
C86
10UF
X5R
6.3V
C102
10UF
X5R
6.3V
C61
10UF
X5R
6.3V
C100
10UF
X5R
6.3V
1206
1206
1206
1206
C87
10UF
X5R
6.3V
C103
10UF
X5R
6.3V
C40
10UF
X5R
6.3V
C1
10UF
X5R
6.3V
1206
1206
1206
1206
C91
10UF
X5R
6.3V
C104
10UF
X5R
6.3V
C46
10UF
X5R
6.3V
C119
10UF
X5R
6.3V
http://laptop-motherboard-schematic.blogspot.com/
V1P2_VTT
V1P2_VTT
TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MIL
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
PLL SUPPLY FILTER
L9 10uH_0805
10uH_±20%
125mA_700mO
L10 10uH_0805
10uH_±20%
125mA_700mO
0805
LF
R187
x0
C139
10UF
Y5V
10V
CPU_E5
CPU_J3
C137
10UF
0805
Y5V
10V
R136 x1K
R135 x1K
0603
LF
LF
Y5V
16V
Y5V
16V
C131
C132
0.1UF
1UF
0603
1206
1206
1206
1206
C92
10UF
X5R
6.3V
C105
10UF
X5R
6.3V
C81
10UF
X5R
6.3V
C111
10UF
X5R
6.3V
C93
10UF
1206
X5R
6.3V
C106
10UF
1206
X5R
6.3V
C76
10UF
1206
X5R
6.3V
C88
10UF
1206
X5R
6.3V
H_VCCIOPLL 6
H_VCCA 6
H_VSSA 6
VCCP
D D
C C
B B
A A
W23
W24
W25
W26
W27
W28
W29
W30
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
K25
K26
K27
K28
K29
K30
M23
M24
M25
M26
M27
M28
M29
M30
N23
N24
N25
N26
N27
N28
N29
N30
T23
T24
T25
T26
T27
T28
T29
T30
U23
U24
U25
U26
U27
U28
U29
U30
W8
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
SK1E
J8
VCC_0
J9
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
K8
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
L8
VCC_30
M8
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
N8
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
P8
VCC_49
R8
VCC_50
T8
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
U8
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
V8
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
Y8
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
LGA775
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCCP VCCP
AA8
AB8
AC8
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AD8
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AE9
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AF8
AF9
AF11
AF12
AF14
AF15
AF18
AF19
AF21
AF22
AG8
AG9
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30
AH8
AH9
AH11
AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30
AJ8
AJ9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AK8
AK9
AK11
AK12
SK-C775P
SK1F
AK14
VCC_176
AK15
VCC_177
AK18
VCC_178
AK19
VCC_179
AK21
VCC_180
AK22
VCC_181
AK25
VCC_182
AK26
VCC_183
AL8
VCC_184
AL9
VCC_185
AL11
VCC_186
AL12
VCC_187
AL14
VCC_188
AL15
VCC_189
AL18
VCC_190
AL19
VCC_191
AL21
VCC_192
AL22
VCC_193
AL25
VCC_194
AL26
VCC_195
AL29
VCC_196
AL30
VCC_197
AM8
VCC_198
AM9
VCC_199
AM11
VCC_200
AM12
VCC_201
AM14
VCC_202
AM15
VCC_203
AM18
VCC_204
AM19
VCC_205
AM21
VCC_206
AM22
VCC_207
AM25
VCC_208
AM26
VCC_209
AM29
VCC_210
AM30
VCC_211
AN8
VCC_212
AN9
VCC_213
AN11
VCC_214
AN12
VCC_215
AN14
VCC_216
AN15
VCC_217
AN18
VCC_218
AN19
VCC_219
AN21
VCC_220
AN22
VCC_221
AN25
VCC_222
AN26
VCC_223
AN29
VCC_224
AN30
VCC_225
A2
VSS_0
A6
VSS_1
A9
VSS_2
A12
VSS_3
A15
VSS_4
A18
VSS_5
A21
VSS_6
A24
VSS_7
B1
VSS_8
B5
R204
LF
x1K
B11
B14
B17
B20
B24
C10
C13
C16
C19
C22
C24
D12
D15
D18
D21
D24
E11
E14
B8
C4
C7
D3
D5
D6
D9
E2
E8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
LGA775
SK-C775P
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
E17
E20
E25
E26
E27
E28
E29
F4
F7
F10
F13
F16
F19
F22
G1
H3
H6
H7
H8
H9
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
J4
J7
K2
K5
K7
L3
L6
L7
L23
L24
L25
L26
L27
L28
L29
L30
M1
M7
N3
N6
N7
P4
P7
P23
P24
P25
P26
P27
P28
P29
P30
R2
R5
R7
R23
R24
R25
R26
R27
R28
R29
R30
T3
T6
T7
U1
U7
V3
V6
V7
V23
R181
LF
x1K
CPU_G1 6
CPU_U1 6
LF
R117
x0
V24
V25
V26
V27
V28
V29
V30
AA3
AA7
AA6
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
AB7
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC3
AC6
AC7
AD4
AD7
AE2
AE5
AE7
AE10
AE13
AE16
AE17
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AF3
AF6
AF7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AG7
AG10
AG13
AG16
AG17
AG20
AG23
AG24
AH1
AH3
AH6
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AJ4
W4
W7
Y2
Y5
Y7
SK1G
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
LGA775
SK-C775P
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AK2
AK5
AK7
AK10
AK13
AK16
AK17
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AL7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AM1
AM4
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AN1
AN2
AN10
AN13
AN16
AN17
AN20
AN23
AN24
AN27
AN28
A20
C9
D1
D14
D16
CPU_E5
E5
E6
E7
E23
F23
F29
H_SLEWCTRL
G6
CPU_GTLREF_0
G10
CPU_J3
J3
N4
N5
P5
AC4
AE4
AE6
AH2
AH7
AJ7
AL3
NC
LF
R73
x0
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
5
4
3
2
Wednesday, April 11, 2007
M630
1
/P4 LGA775 PART B
732
0.22
5
H_A3
H_A4
H_A5
H_A6
H_A7
D D
C C
H_ADSTB06
H_ADSTB16
H_STBP06
H_STBN06
H_DBI06
H_STBP16
H_STBN16
H_DBI16
H_STBP26
H_STBN26
H_DBI26
H_STBP36
H_STBN36
H_DBI36
H_ADS#6
H_TRDY#6
H_DRDY#6
H_DEFER#6
H_HITM#6
H_HIT#6
B B
H_LOCK#6
H_BR#6
H_BNR#6
H_BPRI#6
H_DBSY#6
H_RS0#6
H_RS1#6
H_RS2#6
H_CPURST#6 CK_H_MCH_P 5
H_A8
H_A9
H_A10
H_A11
H_A12
H_A13
H_A14
H_A15
H_A16
H_A17
H_A18
H_A19
H_A20
H_A21
H_A22
H_A23
H_A24
H_A25
H_A26
H_A27
H_A28
H_A29
H_A30
H_A31
H_A32
H_A33
H_A34
H_A35
H_REQ0
H_REQ1
H_REQ2
H_REQ3
H_REQ4
U7H
BRLK_B_CRB
M38
M36
AA37
M34
M42
M43
M40
W40
W41
AA42
W42
AA41
K42
N32
N34
N37
R34
N35
N38
U37
N39
R37
P42
R39
V36
R38
U36
U33
R35
V33
V35
Y34
V42
V38
Y36
Y38
Y39
F40
L35
L38
G43
U34
G35
H33
G27
H27
G29
B38
C38
E33
Y40
T43
Y43
U42
V41
G39
U40
U41
U39
C31
J42
L39
J40
L37
L36
J37
J33
H_REQ[0..4]
H_A[3..35]
H_D[0..63]
U7B
FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35
FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4
FSB_ADSTBB_0
FSB_ADSTBB_1
FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2
FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3
FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB
BRLK_B_CRB
U1MCH
FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7
FSB_DB_8
FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63
FSB_SWING
FSB_RCOMP
FSB_SCOMP
FSB_SCOMPB
FSB_DVREF
FSB_ACCVREF
HPL_CLKINP
HPL_CLKINN
1 OF 10
H_REQ[0..4] 6
H_A[3..35] 6
H_D[0..63] 6
H_D0
R40
H_D1
P41
H_D2
R41
H_D3
N40
H_D4
R42
H_D5
M39
H_D6
N41
H_D7
N42
H_D8
L41
H_D9
J39
H_D10
L42
H_D11
J41
H_D12
K41
H_D13
G40
H_D14
F41
H_D15
F42
H_D16
C42
H_D17
D41
H_D18
F38
H_D19
G37
H_D20
E42
H_D21
E39
H_D22
E37
H_D23
C39
H_D24
B39
H_D25
G33
H_D26
A37
H_D27
F33
H_D28
E35
H_D29
K32
H_D30
H32
H_D31
B34
H_D32
J31
H_D33
F32
H_D34
M31
H_D35
E31
H_D36
K31
H_D37
G31
H_D38
K29
H_D39
F31
H_D40
J29
H_D41
F29
H_D42
L27
H_D43
K27
H_D44
H26
H_D45
L26
H_D46
J26
H_D47
M26
H_D48
C33
H_D49
D35
H_D50
E41
H_D51
B41
H_D52
D42
H_D53
C40
H_D54
C35
H_D55
B40
H_D56
D38
H_D57
D37
H_D58
B33
H_D59
D33
H_D60
C34
H_D61
B35
H_D62
A32
H_D63
D32
HSWING
B25
HRCOMP
D23
HSCOMP
C25
HSCOMPB
D25
MCH_GTLREF
D24
B24
R32
U32
DDR3
8 OF 10
NC
A A
DDR3_DRAMRST
DDR3_DRAM_PWROK
DDR3_A_CSB1
DDR3_A_MA0
DDR3_A_WEB
DDR3_B_ODT3
TEST0
TEST1
TEST2
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
B2
B43
B42
BB1
BB2
5
BB43
BC2
BC42
N20
A43
BC1
BC43
AW32
BB34
BB29
AY37
BC16
AN15
R288 0
LF
4
V0.22
CK_H_MCH_N 5
CL_PWROK15
ALL_PWROK16,29
V0.2
4
3
U1MCH
PCIE
DMI
MISC VGA
5 OF 10
3
GEXP_TXP_[0..7]
GEXP_TXN_[0..7]
GEXP_TXP_[8..15]
GEXP_TXN_[8..15]
PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2
PEG_TXN_2
PEG_TXP_3
PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7
PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9
PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3
DMI_TXN_3
EXP_COMPO
EXP_COMPI
2 OF 10
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_REDB
CRT_GREENB
CRT_BLUEB
CRT_DDC_DATA
CRT_DDC_CLK
CRT_IREF
DPL_REFCLKINP
DPL_REFCLKINN
RESERVED_34
RESERVED_35
RESERVED_36
RSTINB
PWROK
ICH_SYNCB
RESERVED_37
VCC
VSS
D11
D12
B11
A10
C10
D9
B9
B7
D7
D6
B5
B6
B3
B4
F2
E2
F4
G4
J4
K3
L2
K1
N2
M2
P3
N4
R2
P1
U2
T2
V3
U4
V7
V6
W4
Y4
AC8
AC9
Y2
AA2
AC11
AC12
NC
GEXP_TXP_[8..15] 14
GEXP_TXN_[8..15] 14
GEXP_TXP_0
GEXP_TXN_0
GEXP_TXP_1
GEXP_TXN_1
GEXP_TXP_2
GEXP_TXN_2
GEXP_TXP_3
GEXP_TXN_3
GEXP_TXP_4
GEXP_TXN_4
GEXP_TXP_5
GEXP_TXN_5
GEXP_TXP_6
GEXP_TXN_6
GEXP_TXP_7
GEXP_TXN_7
GEXP_TXP_8
GEXP_TXN_8
GEXP_TXP_9
GEXP_TXN_9
GEXP_TXP_10
GEXP_TXN_10
GEXP_TXP_11
GEXP_TXN_11
GEXP_TXP_12
GEXP_TXN_12
GEXP_TXP_13
GEXP_TXN_13
GEXP_TXP_14
GEXP_TXN_14
GEXP_TXP_15
GEXP_TXN_15
GRCOMP
C15
E15
B18
C19
B20
C18
D19
D20
R307 2.2K
L13
R306 2.2K
M13
A20
R276 10K
C14
R277 10K
D13
L12
L12
M11
H18
F17
A14
AM18
AM17
J13
A42
R20
1
DMI_TXP0 15
DMI_TXN0 15
DMI_TXP1 15
DMI_TXN1 15
DMI_TXP2 15
DMI_TXN2 15
DMI_TXP3 15
DMI_TXN3 15
VCC3
LF
LF
LF
V1P25_MCH
LF
L12
PLTRST# 16,24,25
ALL_PWROK 16,29
ICH_SYNC# 16
MCH1
HSINK-NORTH
BLACK
V0.2 DCN
2
0603
0603
0603
LF
CL_VREF
GEXP_RXP_[0..7]
GEXP_RXN_[0..7]
GEXP_RXP_[8..15]
GEXP_RXN_[8..15]
U7A
F13
PEG_RXP_0
E13
PEG_RXN_0
K15
PEG_RXP_1
J15
PEG_RXN_1
F12
PEG_RXP_2
E12
PEG_RXN_2
J12
PEG_RXP_3
H12
PEG_RXN_3
J11
PEG_RXP_4
H11
PEG_RXN_4
F7
PEG_RXP_5
E7
PEG_RXN_5
E5
PEG_RXP_6
F6
PEG_RXN_6
C2
PEG_RXP_7
D2
PEG_RXN_7
G6
PEG_RXP_8
G5
PEG_RXN_8
L9
PEG_RXP_9
L8
PEG_RXN_9
M8
PEG_RXP_10
M9
PEG_RXN_10
M4
PEG_RXP_11
L4
PEG_RXN_11
M5
PEG_RXP_12
M6
PEG_RXN_12
R9
PEG_RXP_13
R10
PEG_RXN_13
T4
PEG_RXP_14
R4
PEG_RXN_14
R6
PEG_RXP_15
R7
PEG_RXN_15
W2
DMI_RXP_0
V1
DMI_RXN_0
Y8
DMI_RXP_1
Y9
DMI_RXN_1
AA7
DMI_RXP_2
AA6
DMI_RXN_2
AB3
DMI_RXP_3
AA4
DMI_RXN_3
B12
EXP_CLKINP
B13
EXP_CLKINN
G17
SDVO_CTRLDATA
E17
SDVO_CTRLCLK
BRLK_B_CRB
U7E
G20
BSEL0
J20
BSEL1
J18
BSEL2
K20
ALLZTEST
F20
XORTEST
G18
MTYPE
E18
EXP_SLR
K17
RESERVED_12
J17
EXP_EN
G15
RFU_G15
L17
RESERVED_14
E20
TCEN
N18
RESERVED_16
N15
RESERVED_17
N17
RESERVED_18
L15
RESERVED_19
L18
RESERVED_20
M18
RESERVED_21
AD12
CL_DATA
AD13
CL_CLK
AM5
CL_VREF
AA12
CL_RSTB
AM15
CL_PWROK
AA10
RESERVED_22
AA9
RESERVED_23
AA11
RESERVED_24
Y12
RESERVED_25
U30
RESERVED_26
U31
RESERVED_27
R29
RESERVED_28
R30
RESERVED_29
U12
RESERVED_30
U11
RESERVED_31
R12
RESERVED_32
R13
RESERVED_33
BRLK_B_CRB
GEXP_RXP_[0..7]14 GEXP_TXP_[0..7] 14
GEXP_RXN_[0..7]14 GEXP_TXN_[0..7] 14
GEXP_RXP_[8..15]14
GEXP_RXN_[8..15]14
GEXP_RXP_0
GEXP_RXN_0
GEXP_RXP_1
GEXP_RXN_1
GEXP_RXP_2
GEXP_RXN_2
GEXP_RXP_3
GEXP_RXN_3
GEXP_RXP_4
GEXP_RXN_4
GEXP_RXP_5
GEXP_RXN_5
GEXP_RXP_6
GEXP_RXN_6
GEXP_RXP_7
GEXP_RXN_7
GEXP_RXP_8
GEXP_RXN_8
GEXP_RXP_9
GEXP_RXN_9
GEXP_RXP_10
GEXP_RXN_10
GEXP_RXP_11
GEXP_RXN_11
GEXP_RXP_12
GEXP_RXN_12
GEXP_RXP_13
GEXP_RXN_13
GEXP_RXP_14
GEXP_RXN_14
GEXP_RXP_15
GEXP_RXN_15
DMI_RXP015
DMI_RXN015
DMI_RXP115
DMI_RXN115
DMI_RXP215
DMI_RXN215
DMI_RXP315
DMI_RXN315
CK_PE_MCH_P5
CK_PE_MCH_N5
SDVO_CTRL_DATA14
SDVO_CTRL_CLK14
EXP_PRSNT14
CL_DATA15
CL_CLK15
CL_RST#15
LF
R42 0
R258 0
R264 0
R269 0
R268 x1K
R673
LF
1K
R_CPU_FSA24
R_CPU_FSB24
R_CPU_FSC24
LF
R304 0
LF
R305 x0
2
V1P25_MCH
2
HSCOMP
HSCOMPB
HRCOMP
V1P2_VTT
R248
LF
301_1%
1%
R253
LF
100_1%
1%
V1P2_VTT
R247
LF
100_1%
1%
R256
LF
200_1%
1%
Need to double check!!
V1P25_MCH
R298
LF
1K_1%
1%
R286
LF
392_1%
1%
http://laptop-motherboard-schematic.blogspot.com/
1
LF
R249 49.9_1%
C219
x3.3PF
0603
NPO
50V
LF
R250 49.9_1%
C217
x3.3PF
0603
NPO
50V
LF
R263 16.5_1%
HRCOMP
5 mils trace, 5 mils space
>250 mils, 10 mils trace, 7 mils space
R255 49.9_1%
C213
0.1UF
0603
Y5V
16V
V1P2_VTT
1%
HSCOMP
4 mils trace, 14 mils space
V1P2_VTT
1%
HSCOMPB
4 mils trace, 14 mils space
1%
LF
1%
HSWING
10 mils trace, 10 mils space
HSWING
MCH_GTLREF VOLTAGE SHOULD BE 0.67 x VTT = 0.8V
LF
LF
R259 49.9_1%
C220
1UF
0603
Y5V
16V
R260 0
1%
MCH_GTLREF
C223
220PF
0603
X7R
16V
MCH_CPU_GTLREF 6
Close to PIN D24 & B24
MCH_GTLREF
10 mils trace, 7 mils space
0.349V
CL_VREF
C263
0.1UF
0603
Y5V
16V
V1P25_PCIE
GRCOMP
LF
1%
R279 24.9_1%
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/MCH BearLake A
832
0.22
5
4
3
2
1
http://laptop-motherboard-schematic.blogspot.com/
U7D
DDR_B
U1MCH
DDR_B_DQS_0
DDR_B_DQSB_0
DDR_B_DM_0
DDR_B_DQ_0
DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7
DDR_B_DQS_1
DDR_B_DQSB_1
DDR_B_DM_1
DDR_B_DQ_8
DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15
DDR_B_DQS_2
DDR_B_DQSB_2
DDR_B_DM_2
DDR_B_DQ_16
DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQS_3
DDR_B_DQSB_3
DDR_B_DM_3
DDR_B_DQ_24
DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31
DDR_B_DQS_4
DDR_B_DQSB_4
DDR_B_DM_4
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39
DDR_B_DQS_5
DDR_B_DQSB_5
DDR_B_DM_5
DDR_B_DQ_40
DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47
DDR_B_DQS_6
DDR_B_DQSB_6
DDR_B_DM_6
DDR_B_DQ_48
DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55
DDR_B_DQS_7
DDR_B_DQSB_7
DDR_B_DM_7
DDR_B_DQ_56
DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63
4 OF 10
BRLK_B_CRB
AV6
AU5
AR7
AN7
AN8
AW5
AW7
AN5
AN6
AN9
AU7
AR12
AP12
AW9
AT11
AU11
AP13
AR13
AR11
AU9
AV12
AU12
AP15
AR15
AW13
AU15
AV13
AU17
AT17
AU13
AM13
AV15
AW17
AT24
AU26
AP23
AV24
AT23
AT26
AP26
AU23
AW23
AR24
AN26
AW39
AU39
AU37
AW37
AV38
AN36
AN37
AU35
AR35
AN35
AR37
AL35
AL34
AM37
AM35
AM38
AJ34
AL38
AR39
AM34
AL37
AL32
AG35
AG36
AG39
AG38
AJ38
AF35
AF33
AJ37
AJ35
AG33
AF34
AC36
AC37
AD38
AD36
AC33
AA34
AA36
AD34
AF38
AC34
AA33
M_DQS_P_B0
M_DQS_N_B0
M_DQM_B0
M_DATA_B0
M_DATA_B1
M_DATA_B2
M_DATA_B3
M_DATA_B4
M_DATA_B5
M_DATA_B6
M_DATA_B7
M_DQS_P_B1
M_DQS_N_B1
M_DQM_B1
M_DATA_B8
M_DATA_B9
M_DATA_B10
M_DATA_B11
M_DATA_B12
M_DATA_B13
M_DATA_B14
M_DATA_B15
M_DQS_P_B2
M_DQS_N_B2
M_DQM_B2
M_DATA_B16
M_DATA_B17
M_DATA_B18
M_DATA_B19
M_DATA_B20
M_DATA_B21
M_DATA_B22
M_DATA_B23
M_DQS_P_B3
M_DQS_N_B3
M_DQM_B3
M_DATA_B24
M_DATA_B25
M_DATA_B26
M_DATA_B27
M_DATA_B28
M_DATA_B29
M_DATA_B30
M_DATA_B31
M_DQS_P_B4
M_DQS_N_B4
M_DQM_B4
M_DATA_B32
M_DATA_B33
M_DATA_B34
M_DATA_B35
M_DATA_B36
M_DATA_B37
M_DATA_B38
M_DATA_B39
M_DQS_P_B5
M_DQS_N_B5
M_DQM_B5
M_DATA_B40
M_DATA_B41
M_DATA_B42
M_DATA_B43
M_DATA_B44
M_DATA_B45
M_DATA_B46
M_DATA_B47
M_DQS_P_B6
M_DQS_N_B6
M_DQM_B6
M_DATA_B48
M_DATA_B49
M_DATA_B50
M_DATA_B51
M_DATA_B52
M_DATA_B53
M_DATA_B54
M_DATA_B55
M_DQS_P_B7
M_DQS_N_B7
M_DQM_B7
M_DATA_B56
M_DATA_B57
M_DATA_B58
M_DATA_B59
M_DATA_B60
M_DATA_B61
M_DATA_B62
M_DATA_B63
2
VDDMEM
R300
LF
1K_1%
1%
LF
1%
R299
1K_1%
0603
C276
0.1UF
Y5V
16V
SVREF
PLACE CLOSE TO MCH
R296 19.1_1%
R223 19.1_1%
R280 19.1_1%
R231 19.1_1%
C201
1UF
0603
Y5V
16V
0603
0603
C211
1UF
Y5V
16V
LF
LF
LF
LF
1%
1%
1%
1%
C264
0.01UF
Y5V
16V
C265
0.01UF
Y5V
16V
0603
SRCOMP1
SRCOMP3
SMRCOMPVOH
SMRCOMPVOL
C221
1UF
0603
Y5V
16V
C234
1UF
Y5V
16V
0603
C240
1UF
Y5V
16V
VDDMEM
0603
SRCOMP0
SRCOMP2
VDDMEM
0603
VDDMEM
0603
VDDMEM
LF
1%
LF
1%
LF
1%
C197
1UF
Y5V
16V
C257
0.1UF
Y5V
16V
C181
0.1UF
Y5V
16V
R295
1K_1%
R293
3.01K_1%
R294
1K_1%
0603
MCH Memory Decoupling
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
Wednesday, April 11, 2007
M630
1
/MCH BearLake B
932
0.22
3 OF 10
U1MCH
DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DM_0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DM_1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DM_2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DM_3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DM_4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DM_5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DM_6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DM_7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
BRLK_B_CRB
AP2
AP3
AN2
AM1
AN3
AR2
AR3
AL3
AM2
AR5
AR4
AW2
AW1
AW3
AV4
AV3
BA4
BB3
AU2
AU1
AY2
AY3
AY7
BA6
BB6
BB5
AY6
BA9
BB9
BA5
BB4
BC7
AY9
AT20
AU18
AN18
AT18
AR18
AU21
AT21
AP17
AN17
AP20
AV20
AR41
AR40
AU43
AV42
AU40
AP42
AN39
AV40
AV41
AR42
AP41
AL41
AL40
AM43
AN41
AM39
AK42
AK41
AN40
AN42
AL42
AL39
AG42
AG41
AG40
AJ40
AH43
AF39
AE40
AJ42
AJ41
AF41
AF42
AC42
AC41
AC40
AD40
AD43
AB41
AA40
AE42
AE41
AC39
AB42
M_DQS_P_A0
M_DQS_N_A0
M_DQM_A0
M_DATA_A0
M_DATA_A1
M_DATA_A2
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A6
M_DATA_A7
M_DQS_P_A1
M_DQS_N_A1
M_DQM_A1
M_DATA_A8
M_DATA_A9
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
M_DATA_A15
M_DQS_P_A2
M_DQS_N_A2
M_DQM_A2
M_DATA_A16
M_DATA_A17
M_DATA_A18
M_DATA_A19
M_DATA_A20
M_DATA_A21
M_DATA_A22
M_DATA_A23
M_DQS_P_A3
M_DQS_N_A3
M_DQM_A3
M_DATA_A24
M_DATA_A25
M_DATA_A26
M_DATA_A27
M_DATA_A28
M_DATA_A29
M_DATA_A30
M_DATA_A31
M_DQS_P_A4
M_DQS_N_A4
M_DQM_A4
M_DATA_A32
M_DATA_A33
M_DATA_A34
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
M_DATA_A39
M_DQS_P_A5
M_DQS_N_A5
M_DQM_A5
M_DATA_A40
M_DATA_A41
M_DATA_A42
M_DATA_A43
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47
M_DQS_P_A6
M_DQS_N_A6
M_DQM_A6
M_DATA_A48
M_DATA_A49
M_DATA_A50
M_DATA_A51
M_DATA_A52
M_DATA_A53
M_DATA_A54
M_DATA_A55
M_DQS_P_A7
M_DQS_N_A7
M_DQM_A7
M_DATA_A56
M_DATA_A57
M_DATA_A58
M_DATA_A59
M_DATA_A60
M_DATA_A61
M_DATA_A62
M_DATA_A63
4
M_MAA_B[0..14]
M_DQM_B[0..7]
M_DQS_P_B[0..7]
M_DQS_N_B[0..7]
M_DATA_B[0..63]
M_WE_B12,13
M_CAS_B12,13
M_RAS_B12,13
M_SBA_B012,13
M_SBA_B112,13
M_SBA_B212,13
M_SCS_B012,13
M_SCS_B112,13
M_SCS_B212,13
M_SCS_B312,13
M_SCKE_B012,13
M_SCKE_B112,13
M_SCKE_B212,13
M_SCKE_B312,13
M_SODT_B012,13
M_SODT_B112,13
M_SODT_B212,13
M_SODT_B312,13
CK_M_DDR_P_B012
CK_M_DDR_N_B012
CK_M_DDR_P_B112
CK_M_DDR_N_B112
CK_M_DDR_P_B212
CK_M_DDR_N_B212
CK_M_DDR_P_B312
CK_M_DDR_N_B312
CK_M_DDR_P_B412
CK_M_DDR_N_B412
CK_M_DDR_P_B512
CK_M_DDR_N_B512
M_MAA_B[0..14] 12,13
M_DQM_B[0..7] 12
M_DQS_P_B[0..7] 12
M_DQS_N_B[0..7] 12
M_DATA_B[0..63] 12
M_MAA_B0
M_MAA_B1
M_MAA_B2
M_MAA_B3
M_MAA_B4
M_MAA_B5
M_MAA_B6
M_MAA_B7
M_MAA_B8
M_MAA_B9
M_MAA_B10
M_MAA_B11
M_MAA_B12
M_MAA_B13
M_MAA_B14
SVREF
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
SMRCOMPVOL
SMRCOMPVOH
3
AW15
BB15
BA15
AY15
BA14
BB14
AW12
BA13
BB13
AY13
BA17
AY12
BA11
AY27
BB11
BB25
AW26
AY24
BB17
AY17
AY11
BA25
BA29
BA26
BA30
AW11
BC12
BA10
BB10
BB27
AW29
BA27
AY29
AW31
AV31
AU27
AT27
AV32
AT32
AR29
AU29
AV29
AW27
AN33
AP32
BA2
AW42
AN32
AM31
AG32
AF32
AP21
AA39
AM21
AM6
BB40
BA40
AM8
AM10
AL4
AL2
DDR_B_MA_0
DDR_B_MA_1
DDR_B_MA_2
DDR_B_MA_3
DDR_B_MA_4
DDR_B_MA_5
DDR_B_MA_6
DDR_B_MA_7
DDR_B_MA_8
DDR_B_MA_9
DDR_B_MA_10
DDR_B_MA_11
DDR_B_MA_12
DDR_B_MA_13
DDR_B_MA_14
DDR_B_WEB
DDR_B_CASB
DDR_B_RASB
DDR_B_BS_0
DDR_B_BS_1
DDR_B_BS_2
DDR_B_CSB_0
DDR_B_CSB_1
DDR_B_CSB_2
DDR_B_CSB_3
DDR_B_CKE_0
DDR_B_CKE_1
DDR_B_CKE_2
DDR_B_CKE_3
DDR_B_ODT_0
DDR_B_ODT_1
DDR_B_ODT_2
DDR_B_ODT_3
DDR_B_CK_0
DDR_B_CKB_0
DDR_B_CK_1
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_CKB_2
DDR_B_CK_3
DDR_B_CKB_3
DDR_B_CK_4
DDR_B_CKB_4
DDR_B_CK_5
DDR_B_CKB_5
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10
DDR_VREF
DDR_RCOMPXPD
DDR_RCOMPXPU
DDR_RCOMPYPD
DDR_RCOMPYPU
DDR_RCOMPVOL
DDR_RCOMPVOH
U7C
M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
D D
M_WE_A11,13
M_CAS_A11,13
M_RAS_A11,13
M_SBA_A011,13
M_SBA_A111,13
M_SBA_A211,13
M_SCS_A011,13
M_SCS_A111,13
M_SCS_A211,13
M_SCS_A311,13
M_SCKE_A011,13
M_SCKE_A111,13
M_SCKE_A211,13
M_SCKE_A311,13
M_SODT_A011,13
C C
B B
M_SODT_A111,13
M_SODT_A211,13
M_SODT_A311,13
CK_M_DDR_P_A011
CK_M_DDR_N_A011
CK_M_DDR_P_A111
CK_M_DDR_N_A111
CK_M_DDR_P_A211
CK_M_DDR_N_A211
CK_M_DDR_P_A311
CK_M_DDR_N_A311
CK_M_DDR_P_A411
CK_M_DDR_N_A411
CK_M_DDR_P_A511
CK_M_DDR_N_A511
M_MAA_A[0..14]
M_DQM_A[0..7]
M_DQS_P_A[0..7]
M_DQS_N_A[0..7]
M_DATA_A[0..63]
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_MAA_A14
M_MAA_A[0..14] 11,13
M_DQM_A[0..7] 11
M_DQS_P_A[0..7] 11
M_DQS_N_A[0..7] 11
M_DATA_A[0..63] 11
BB30
AY25
BA23
BB23
AY23
BB22
BA22
BB21
AW21
BA21
BB31
AY21
BC20
AY38
BA19
BA33
AW35
AY33
BA31
AY31
AY20
BA34
AY35
BB33
BB38
AY19
AW18
BB19
BA18
BB35
BA38
BA35
BA39
AR31
AU31
AP27
AN27
AV33
AW33
AP29
AP31
AM26
AM27
AT33
AU33
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
DDR_A_WEB
DDR_A_CASB
DDR_A_RASB
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1
DDR_A_CK_2
DDR_A_CKB_2
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4
DDR_A_CK_5
DDR_A_CKB_5
DDR_A
A A
5
AN21
RESERVED_1
5
AG7
AG8
AG9
AH1
AH2
AH4
AJ10
AJ11
AJ12
AJ5
AJ6
AJ7
AJ8
AJ9
C13
C9
D4
F11
F9
G2
J2
J3
J6
L6
N11
N12
N3
N6
N8
N9
P14
P15
P20
R14
R15
R17
R18
U10
U13
U14
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U3
U6
U9
V10
V12
V13
V14
V15
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V9
W17
W18
W19
W21
W23
W25
W26
W27
Y11
Y13
Y14
Y15
Y17
Y18
Y20
Y22
Y24
Y26
Y27
Y6
FB11
30 OHM/100MHz
V1P25_MCH V1P2_VTT
VCCA_DPLLB
L0805±25% 3A
0805
V1P25_MCH
AA13
VCC_1
AA14
VCC_2
FB9
30 OHM/100MHz
L0805
±25% 3A
AA15
AA17
AA19
AA21
AA23
AA25
AA26
AA27
AA3
AB17
AB18
AB20
AB22
AB24
AB26
AB27
AC13
AC14
AC15
AC17
AC19
AC21
AC23
AC25
AC26
AC27
AC6
AD14
AD15
AD17
AD18
AD20
AD22
AD24
AD26
AD27
AE17
AE19
AE21
AE23
AE25
AE26
AE27
AF1
AF11
AF12
AF13
AF14
AF15
AF17
AF18
AF2
AF20
AF22
AF24
AF25
AF26
AF3
AG10
AG11
AG12
AG13
AG14
AG15
AG17
AG18
AG19
AG2
AG20
AG21
AG22
AG23
AG24
AG3
AG4
AG5
AG6
B21
C21
B15
A24
C23
B17
A16
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCCDQ_CRT
VCCD_CRT
VCCAPLL_EXP
VCCA_MPLL
VCCA_HPLL
VCC3_3
VCCA_EXP
5
D D
C C
B B
VCCA_GPLL
VCCA_MPLL VCCA_DPLLA
VCCA_HPLL
VCC3
A A
U7F
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_104
VCC_105
POWER
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
6 OF 10
VCC_171
BRLK_B_CRB
http://laptop-motherboard-schematic.blogspot.com/
V1P25_MCH V1P25_MCH_CL
VDDMEM
C625
10UF
Y5V
10V
AV18
AV26
AW20
AW24
AY32
BB12
BB16
BB18
BB20
BB24
BB26
BB28
BB32
BB37
BB39
BC14
BC18
BC22
BC26
BC30
BC34
BC39
AD10
AD11
C27
C29
C30
D27
D28
D29
E23
E26
E27
E29
F23
F24
F26
G23
G24
G26
H23
H24
K23
K24
M23
M24
M29
N23
N24
N26
N29
P23
P24
P26
P27
P29
R23
R24
R26
R27
AC2
AC3
AC4
AD1
AD2
AD4
AD5
AD6
AD7
AD8
AD9
C22
A22
B16
C17
4
A28
A30
B27
B28
B29
B30
J23
J24
L23
L24
4
VTT_FSB_1
VTT_FSB_2
VTT_FSB_3
VTT_FSB_4
VTT_FSB_5
VTT_FSB_6
VTT_FSB_7
VTT_FSB_8
VTT_FSB_9
VTT_FSB_10
VTT_FSB_11
VTT_FSB_12
VTT_FSB_13
VTT_FSB_14
VTT_FSB_15
VTT_FSB_16
VTT_FSB_17
VTT_FSB_18
VTT_FSB_19
VTT_FSB_20
VTT_FSB_21
VTT_FSB_22
VTT_FSB_23
VTT_FSB_24
VTT_FSB_25
VTT_FSB_26
VTT_FSB_27
VTT_FSB_28
VTT_FSB_29
VTT_FSB_30
VTT_FSB_31
VTT_FSB_32
VTT_FSB_33
VTT_FSB_34
VTT_FSB_35
VTT_FSB_36
VTT_FSB_37
VTT_FSB_38
VTT_FSB_39
VTT_FSB_40
VTT_FSB_41
VTT_FSB_42
VTT_FSB_43
VTT_FSB_44
VTT_FSB_45
VTT_FSB_46
VCC_DDR_1
VCC_DDR_2
VCC_DDR_3
VCC_DDR_4
VCC_DDR_5
VCC_DDR_6
VCC_DDR_7
VCC_DDR_8
VCC_DDR_9
VCC_DDR_10
VCC_DDR_11
VCC_DDR_12
VCC_DDR_13
VCC_DDR_14
VCC_DDR_15
VCC_DDR_16
VCC_DDR_17
VCC_DDR_18
VCC_DDR_19
VCC_DDR_20
VCC_DDR_21
VCC_DDR_22
VCC_EXP_1
VCC_EXP_2
VCC_EXP_3
VCC_EXP_4
VCC_EXP_5
VCC_EXP_6
VCC_EXP_7
VCC_EXP_8
VCC_EXP_9
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
VCC_EXP_13
VCCA_DPLLB
VCCA_DPLLA
VCCA_DAC_1
VCCA_DAC_2
U7I
VCC_CL_PLL
VCC_CL_1
VCC_CL_2
VCC_CL_3
VCC_CL_4
VCC_CL_5
VCC_CL_6
VCC_CL_7
VCC_CL_8
VCC_CL_9
VCC_CL_10
VCC_CL_11
VCC_CL_12
VCC_CL_13
VCC_CL_14
VCC_CL_15
VCC_CL_16
VCC_CL_17
VCC_CL_18
VCC_CL_19
VCC_CL_20
VCC_CL_21
VCC_CL_22
VCC_CL_23
VCC_CL_24
VCC_CL_25
VCC_CL_26
VCC_CL_27
VCC_CL_28
VCC_CL_29
VCC_CL_30
VCC_CL_31
VCC_CL_32
VCC_CL_33
VCC_CL_34
VCC_CL_35
VCC_CL_36
VCC_CL_37
VCC_CL_38
VCC_CL_39
VCC_CL_40
VCC_CL_41
VCC_CL_42
VCC_CL_43
VCC_CL_44
VCC_CL_45
VCC_CL_46
VCC_CL_47
VCC_CL_48
VCC_CL_49
VCC_CL_50
VCC_CL_51
VCC_CL_52
VCC_CL_53
VCC_CL_54
VCC_CL_55
VCC_CL_56
VCC_CL_57
VCC_CL_58
VCC_CL_59
VCC_CL_60
VCC_CL_61
VCC_CL_62
VCC_CL_63
VCC_CL_64
VCC_CL_65
VCC_CL_66
VCC_CL_67
VCC_CL_68
VCC_CL_69
VCC_CL_70
VCC_CL_71
VCC_CL_72
VCC_CL_73
VCC_CL_75
VCC_CL_76
VCC_CL_77
VCC_CKDDR_1
VCC_CKDDR_2
VCC_CKDDR_3
VCC_CKDDR_4
VCC_CKDDR_5
9 OF 10
BRLK_B_CRB
3
V1P25_MCH
FB10
1 2
1uH_1210
1uH_±10%
370mA
L18
0.82uH_0805
0.82uH_±10%
150mA_1000mO
FB7
1 2
1uH_1210
1uH_±10%
370mA
R270 SHORT_1206
R274 SHORT_1206
V1P25_MCH V1P25_PCIE
30 mils trace
PCI EXPRESS FILTER
VDDMEM
L11
0.82uH_0805
0.82uH_±10%
150mA_1000mO
V1P2_VTTV1P25_PCIE
C206
0.1UF
0603
Y5V
16V
V1P25_MCH
EC28
+
1000UF
6.3V
LF
R275 1
LF
R266
1
R216
1
0603
0805
0805
C224
10UF
Y5V
10V
C169
10UF
Y5V
10V
C207
0.1UF
Y5V
16V
0805
0603
0805
0805
LF
LF
0805
C238
10UF
Y5V
10V
C228
1UF
Y5V
16V
R265
1
C233
x10UF
Y5V
10V
C236
x10UF
Y5V
10V
0805
R219
1
C154
10UF
Y5V
10V
C237
0.1UF
0603
Y5V
16V
C231
1UF
0603
Y5V
16V
C226
0.1UF
0603
Y5V
16V
C229
x0.1UF
0603
Y5V
16V
C232
x0.1UF
0603
Y5V
16V
C262
10UF
Y5V
10V
VDDMEM_CLK
C172
0.1UF
0603
Y5V
16V
0805
C203
10UF
Y5V
10V
R674 1
LF
R297 SHORT_1206
LF
C205
0.1UF
0603
Y5V
16V
Caps for FSB Generic Decoupling
VCCA_GPLL
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
0805
0805
C256
10UF
Y5V
10V
C204
10UF
Y5V
10V
Y32
AA29
AA30
AA31
AA32
AC29
AC30
AC31
AC32
AD29
AD30
AD31
AD32
AF27
AF29
AF30
AF31
AG25
AG26
AG27
AG29
AG30
AG31
AJ13
AJ14
AJ15
AJ17
AJ18
AJ2
AJ20
AJ21
AJ23
AJ24
AJ26
AJ27
AJ29
AJ3
AJ30
AJ31
AJ4
AK1
AK14
AK15
AK17
AK18
AK2
AK20
AK21
AK23
AK24
AK26
AK27
AK29
AK3
AK30
AL10
AL11
AL12
AL13
AL15
AL17
AL18
AL20
AL21
AL23
AL24
AL26
AL27
AL29
AL5
AL6
AL7
AL8
AL9
Y29
Y30
Y31
AY42
BA42
BA43
BB41
BB42
V1P25_MCH_CL
SHORT
R281
VDDMEM_CLK
Copy from the 946DSG !! Just for Referance!!
No Internal Graphics Connection Recommendations
Tie directly to
RED
Tie directly to
RED#
Tie directly to
GREEN
GREEN#
Tie directly to REFSET
BLUE
Tie directly to
BLUE#
Tie directly to
NC
HSYNC
GND
GND
GND
GND
GND
GND
3
VSYNC
VCCADAC
VSSADAC
VCCDQ_CRT
VCCD_CRT
VCCA_DPL_A
NC
Tie directly to
Tie directly to
Tie directly to
Tie directly to
Tie directly to
VCCA_DPL_B Tie directly to VCC
NC
GND
DREFCLKN Tie directly to GND
DREFCLKP Pull High 10K to 1.25V
GND
GNDTie directly to
SDVO_CNTRLCLK NC GND
GND
SDVO_CNTRLDATA NC NC
GND
DDC_CLK Tie directly to VCC3
VCC
DDC_DATA Tie directly to VCC3
2
U7G
A12
A18
A26
A34
A39
A41
AA18
AA20
AA22
AA24
AA35
AA38
AA5
AA8
AB1
AB19
AB2
AB21
AB23
AB25
AB43
AC10
AC18
AC20
AC22
AC24
AC35
AC38
AC5
AC7
AD19
AD21
AD23
AD25
AD33
AD35
AD37
AD39
AD42
AE18
AE2
AE20
AE22
AE24
AE3
AE4
AF10
AF19
AF21
AF23
AF36
AF37
AF43
AF5
AF6
AF7
AF8
AF9
AG34
AG37
AH42
AJ32
AJ33
AJ36
AJ39
AK43
AL31
AL33
AL36
AM11
AM20
AM23
A3
A5
A7
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
BRLK_B_CRB
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
GND
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
7 OF 10
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
AM24
AM29
AM33
AM36
AM4
AM40
AM42
AM7
AM9
AN11
AN12
AN13
AN20
AN23
AN24
AN29
AN31
AN38
AN4
AP1
AP18
AP24
AP43
AR17
AR20
AR21
AR23
AR26
AR27
AR32
AR33
AR38
AR6
AR9
AT12
AT13
AT15
AT29
AT31
AU20
AU24
AU32
AU38
AU4
AU42
AU6
AV11
AV17
AV2
AV21
AV23
AV27
AV35
AV37
AV7
AV9
AW41
AW43
AY4
AY40
AY41
B10
B14
B19
B22
B23
B26
B31
B32
B37
BA1
BB7
BC10
BC24
BC28
Title : Page :
Document Number : Rev :
Date : Size : 16.8" X 11.8"
2
Wednesday, April 11, 2007
M630
U7J
BC3
VSS_151
BC32
VSS_152
BC37
VSS_153
BC41
VSS_154
BC5
VSS_155
C1
VSS_156
C11
VSS_157
C26
VSS_158
C4
VSS_159
C43
VSS_160
C5
VSS_161
C6
VSS_162
D15
VSS_163
D16
VSS_164
D17
VSS_165
D21
VSS_166
D3
VSS_167
D31
VSS_168
D40
VSS_169
E1
VSS_170
E11
VSS_171
E21
VSS_172
E24
VSS_173
E3
VSS_174
E32
VSS_175
E43
VSS_176
E9
VSS_177
F15
VSS_178
F18
VSS_179
F21
VSS_180
F27
VSS_181
F3
VSS_182
F35
VSS_183
F37
VSS_184
G1
VSS_185
G11
VSS_186
G12
VSS_187
G13
VSS_188
G21
VSS_189
G32
VSS_190
G38
VSS_191
G42
VSS_192
G7
VSS_193
G9
VSS_194
H13
VSS_195
H15
VSS_196
H17
VSS_197
H20
VSS_198
H21
VSS_199
H29
VSS_200
H31
VSS_201
J21
VSS_202
J27
VSS_203
J32
VSS_204
J35
VSS_205
J38
VSS_206
J5
VSS_207
J7
VSS_208
J9
VSS_209
K12
VSS_210
K13
VSS_211
K18
VSS_212
K2
VSS_213
K21
VSS_214
K26
VSS_215
K43
VSS_216
L11
VSS_217
L20
VSS_218
L21
VSS_219
L29
VSS_220
L3
VSS_221
L31
VSS_222
L32
VSS_223
L33
VSS_224
L40
VSS_225
BRLK_B_CRB
V1P25_MCH_CL
1
1
VSS_226
VSS_227
VSS_228
VSS_229
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
GND
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
10 OF 10
LF
R668 x0
R669 SHORT
*****
L5
L7
M1
M10
M15
M17
M20
M21
M27
M33
M35
M37
M7
N10
N13
N21
N27
N31
N33
N36
N5
N7
P17
P18
P2
P21
P30
P43
R11
R21
R3
R31
R33
R36
R5
R8
T1
T42
U27
U29
U35
U38
U5
U7
U8
V11
V2
V29
V32
V34
V37
V39
V43
V5
V8
W20
W22
W24
W3
Y1
Y10
Y19
Y21
Y23
Y25
Y33
Y35
Y37
Y42
Y5
Y7
V30
0.22
/MCH BearLake C
10 32
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