HD45 / HD46 - 68 - V2.4
Example: CRC computation for the message formed by the two information bytes
0000 0010 (02h) and 0000 0111 (07h).
CRC initialization (step 1) 1111 1111 1111 1111
First information byte 0000 0010
XOR computation (step 2) 1111 1111 1111 1101
1st right shift (step 3) 0111 1111 1111 1110 | 1
Fixed value (1 is the shifted out bit) 1010 0000 0000 0001
XOR computation (step 4) 1101 1111 1111 1111
2nd right shift (step 3) 0110 1111 1111 1111 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1100 1111 1111 1110
3rd right shift (step 3) 0110 0111 1111 1111 | 0
4
th
right shift (step 3) 0011 0011 1111 1111 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1001 0011 1111 1110
5th right shift (step 3) 0100 1001 1111 1111 | 0
6
th
right shift (step 3) 0010 0100 1111 1111 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1000 0100 1111 1110
7
th
right shift (step 3) 0100 0010 0111 1111 | 0
8
th
right shift (step 3) 0010 0001 0011 1111 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1000 0001 0011 1110
Second information byte 0000 0111
XOR Computation (step 2) 1000 0001 0011 1001
1st right shift (step 3) 0100 0000 1001 1100 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1110 0000 1001 1101
2nd right shift (step 3) 0111 0000 0100 1110 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1101 0000 0100 1111
3rd right shift (step 3) 0110 1000 0010 0111 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001
XOR Computation 1100 1000 0010 0110
4th right shift (step 3) 0110 0100 0001 0011 | 0
5
th
right shift (step 3) 0011 0010 0000 1001 | 1
Fixed value (step 4, shifted out bit is 1) 1010 0000 0000 0001