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DFZM TT211
User Manual
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Delta Electronics orporated DFZM TT211 User Manual

DFZM-TT2xx
Data sheet
DFZM-TT2xx
Data Sheet Sheet 1 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
DFZM-TT2xx
Contents
1. Features............................................................................................................................................... 4
2. Zigbee Model No. Definition.............................................................................................................. 6
3. Architecture......................................................................................................................................... 7
3-1.Block Diagram..............................................................................................................................7
3-2.Block Diagram Description.......................................................................................................... 8
3-2-1.Overview...........................................................................................................................8
3-2-2.CPU and Memory............................................................................................................ 8
3-2-3.AES Engine with 128, 192 256 Bit Key Support........................................................... 9
3-2-4.Peripherals.....................................................................................................................10
3-3.Power Management....................................................................................................................14
4. Pin-out and Signal Description.........................................................................................................17
4-1.Device Pin-out Diagram (Module top view) ..............................................................................17
4-2.Module Pins Description ............................................................................................................ 18
5. Electrical Characteristics ..................................................................................................................20
5-1.Absolute Maximum Rating.........................................................................................................20
5-2.Recommended Operating Conditions.........................................................................................20
5-3.Power Consumption....................................................................................................................20
5-4.DC Characteristics......................................................................................................................22
5-5.Wake-up and Timing................................................................................................................... 22
5-6.Radio Parameters........................................................................................................................23
5-7.ADC Parameters......................................................................................................................... 24
5-8.Control Input AC Characteristics................................................................................................26
5-9.USB Interface DC Characteristics..............................................................................................26
6. Package and Layout Guidelines........................................................................................................27
6-1.Recommended PCB Footprint and Dimensions...................................................................27
6-2.Layout Guidelines.......................................................................................................................29
6-2-1.Surface Mount Assembly ................................................................................................ 30
6-3.Recommended Stencil Aperture .................................................................................................32
7. Reference Design Schematic ............................................................................................................ 33
8. DUT Setup........................................................................................................................................ 33
Data Sheet Sheet 2 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
9. Federal Communications Commission (FCC) Statement.................................................................38
DFZM-TT2xx
Data Sheet Sheet 3 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
T
DFZM-TT2xx
DFZM-TT2xx IEEE802.15.4 System-On-Chip ZigBee Module
HIS DOCUMENT
based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity for embedded devices for a variety of applications, such as wireless sensors and energy monitoring. It combines ARM Cotex-M3 based processors, in-system programable flash memory, 32-KB RAM, 512KB flash memory and off module certified antenna options, and various RF front end options for end customer range needs in order to provide a Zigbee and regulatory certified. The module has various operating modes, making it highly suit for system where ultralow power consumption is required. Short transition times between operating modes further ensure low energy consumption.
describes the DFZM-TT2xx Zigbee module hardware specification. The CC2538
1. Features
►
Family of modules with different antenna and output power options:
• DFZM-TT2xx 29.3 mm by 19.8 mm by 3.3mm (Length * Width * Height) 42-pin Dual Flat pack PCB
Surface Mount Package.
• DFZM-TT220, DFZM-TT221, DFZM-TT210, and DFZM-TT211 are all pin to pin compatible (see
section 7 Ordering Information), and the user has to account only for power consumption.
• Simple API for embedded markets covering large areas of applications.
►
Compliant with IEEE 802.15.4 and regulatory domains:
• RoHS compliant.
►
Microcontroller:
• Powerful ARM Cortex™ M3 with code prefetch.
• 512KB In-Syctem-Programmable Flash.
• Up to 32KB RAM (16-kB With Retention in All Power Modes).
• Supports On-Chip Over-the-Air Upgrade(OTA).
Data Sheet Sheet 4 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
• Hardware debug support.
►
Interfaces:
• On board antenna or external antenna options.
• µDMA.
• 4 × General-Purpose Timers (Each 32-Bit or 2 × 16-Bit).
• USB 2.0 Full-Speed Device (12 Mbps).
• 2 × SPI.
• Two universal asynchronous receiver/transmitters (UARTs) with IrDA, 9-bit (one UART with modem
flow control).
• I2C.
• Four 32-bit timers (up to eight 16-bit) with pulse width modulation (PWM) capability and
synchronization.
• Up to 28 configurable general purpose I/Os.
DFZM-TT2xx
• Single 3.3V supply option:
o Wide supply voltage range 2.0 ~ 3.6V.
• One 12-bit ADC with 8 Channels and Configurable Resolution.
►
Embedded RTC (Real Time Clock) can run directly from battery.
►
Low-power mode operations.
►
Power mode 0,1, 2, 3.
Data Sheet Sheet 5 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
DT= Delta Define
2. Zigbee Model No. Definition
DFZM-TT2xx
D F Z M - T T 2 2 0 - DT 0 R
E=Pb free
Free-lead
Serial no.
R=RoHS N=NG L=Process with Lead
0~9 then A~Z
Customer code
Antenna Version
0= External Antenna 1= Onboard Antenna
Power Version
1= High Power 2= Low Power
Frequency
2= 2.4GHz
Chip Type
T=CC2538
Chip Vendor
T=TI
Product-type
M= Module
Property
Z= Zigbee
Data Sheet Sheet 6 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
Substrate
Company
F= FR4
D= DELTA
3. Architecture
3-1.Block Diagram
ANT
DFZM-TT2xx
ANT
Balun
CC2591
32K X’tal
Figure 3-1: DFZM-TT22x Block Diagram
32M X’tal
Digital I/O
VCC
Digital I/O
VCC
32K X’tal
32M X’tal
Figure 3-2: DFZM-TT21x Block Diagram
Data Sheet Sheet 7 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
DFZM-TT2xx
3-2.Block Diagram Description
3-2-1.Overview
DFZM-TT2xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following:
• The module includes TI CC2538 SoC, which contains CPU- and memory-related, peripherals-related, clocks
and power management-related in a single package.
• The module features an IEEE802.15.4-compliant radio transceiver with onboard 32 KHz & 32 MHz crystal
circuitries, RF, and certified on board antenna or external antenna options.
o The low power module option has a capability of +7dBm output power at the antenna (see Figure 3-1). o The high power module option has a capability of +18.5dBm output power at the antenna (see Figure
3-2).
• Variety of interfaces are available such as two USART and SPI, four TIMER, one 12 bit ADC, Operational
amperifier and GPIO.
• DFZM-TT2xx contains single power supply (VCC).
3-2-2.CPU and Memory
The CC2538 is designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications.
• Outstanding processing performance combined with fast interrupt handling.
• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM core in
a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes
of memory for microcontroller-class applications. – Single-cycle multiply instruction and hardware divide. – Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control.
– Unaligned data access, enabling data to be efficiently packed into memory.
• Fast code execution permits slower processor clock or increases sleep mode time.
Data Sheet Sheet 8 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
• Harvard architecture characterized by separate buses for instruction and data.
• Efficient processor core, system and memories.
• Hardware division and fast multiplier.
• Deterministic, high-performance interrupt handling for time-critical applications.
• Memory protection unit (MPU) provides a privileged mode for protected operating system functionality.
• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes.
• cJTAG reduces the number of pins required for debugging.
• Ultra-low power consumption with integrated sleep modes.
• 32-MHz operation.
The CC2538 provides a 16KB block of single-cycle on-chip SRAM with full retention in all power modes. In addition, some variants offer an additional 16KB of single-cycle on-chip SRAM without retention in the lowest power modes. Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic
DFZM-TT2xx
operation. Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.
The flash block provides in-circuit programmable nonvolatile program memory for the device. The flash memory is organized as a set of 2KB pages that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In addition to holding program code and constants, the nonvolatile memory allows the application to save data that must be preserved such that it is available after restarting the device. Using this feature one can, for example, use saved network-specific data to avoid the need for a full start-up and network find-and-join process.
The ROM is preprogrammed with a serial boot loader (SPI or UART). For applications that require in-field programmability, the royalty-free CC2538 boot loader can act as an application loader and support in-field firmware updates.
3-2-3.AES Engine with 128, 192 256 Bit Key Support
• CCM, GCM, CTR, CBC-MAC, ECB modes of operation
• SHA-256 hash function.
Data Sheet Sheet 9 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
• Secure key storage memory.
• High throughput, low latency.
• Public key accelerator.
• Elliptic Curve Cryptography (ECC) and RSA-2048.
• Support for RSA-2048 makes it ideal for ESIs.
• Keeps the key exchange algorithms out of the CPU cycle budget and reduces energy consumption.
DFZM-TT2xx
3-2-4.Peripherals
The CC2538 device supports both asynchronous and synchronous serial communications with:
• USB 2.0 FS device.
• Two UARTs with 9-bit.
• I2C module.
• Two SSI.
The following sections provide more detail on each of these communications functions.
Universal serial bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface. The CC2538 device supports the USB 2.0 FS configuration in device mode and has the following features:
• Complies with USB-IF certification standards.
• USB 2.0 full speed (12 Mbps) operation with integrated PHY.
• 4 transfer types: control, interrupt, bulk, and isochronous.
• Five IN and five OUT configurable endpoints.
• Support for packet sizes between 8 to 256 bytes and remote wake-up.
• 1KB of dedicated endpoint memory flexibly assigned to the different endpoints.
• Efficient transfers using the µDMA controller.
A UART is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The CC2538 microcontroller includes two fully programmable 16C550-type UARTs. Although the functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART can generate individually masked interrupts from the receive (RX), transmit (TX), modem flow control, and error conditions. The module generates a single combined interrupt when any of the interrupts are asserted and are unmasked.
Data Sheet Sheet 10 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
The two UARTs have the following features:
• Programmable baud-rate generator allowing speeds up to 2 Mbps for regular speed (divide by 16) and 4 Mbps
for high speed (divide by 8).
• Separate 16x8 TX and RX FIFOs to reduce CPU interrupt service loading.
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered
interface.
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8.
• Standard asynchronous communication bits for start, stop, and parity.
• Line-break generation and detection.
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits. – Even, odd, stick, or no-parity bit generation and detection. – 1 or 2 stop-bit generation.
• Full modem handshake support (on UART1).
• Modem flow control (on UART1).
DFZM-TT2xx
• LIN protocol support.
• EIA-485 9-bit support.
• Standard FIFO-level and end-of-transmission (EoT) interrupts.
• Efficient transfers using the µDMA controller:
– Separate channels for TX and RX. – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level. – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level.
The I2C bus provides bidirectional data transfer through a 2-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacturing. Each device on the I2C bus can be designated as a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave and can operate simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts. The CC2538 microcontroller includes an I2C module with the following features:
• Devices on the I2C bus can be designated as either a master or a slave:
Data Sheet Sheet 11 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
– Supports both transmitting and receiving data as either a master or a slave. – Supports simultaneous master and slave operation.
• Four I2C modes:
– Master transmit. – Master receive. – Slave transmit. – Slave receive.
• Two transmission speeds: Standard (100 Kbps) and fast (400 Kbps).
• Clock low time-out interrupt.
• Dual slave address capability.
• Master and slave interrupt generation:
– Master generates interrupts when a TX or RX operation completes (or aborts due to an error). – Slave generates interrupts when data is transferred or requested by a master or when a START or STOP
condition is detected.
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode.
DFZM-TT2xx
An SSI module is a 4-wire bidirectional communications interface that converts data between parallel and serial. The SSI performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The SSI can be configured as either a master or slave device. As a slave device, the SSI can also be configured to disable its output, which allows coupling of a master device with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs. The SSI also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the input clock of the SSI. Bit rates are generated based on the input clock, and the maximum bit rate is determined by the connected peripheral. The CC2538 includes two SSI modules with the following features:
• Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces.
• Master or slave operation.
• Programmable clock bit rate and prescaler.
• Separate TX and RX FIFOs, each 16 bits wide and 8 locations deep.
• Programmable data frame size from 4 to 16 bits.
• Internal loopback test mode for diagnostic and debug testing.
• Standard FIFO-based interrupts and EoT interrupt.
Data Sheet Sheet 12 of 39 Feb. 3, 2016
Proprietary Information and Specifications are Subject to Change
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