Delta Electronics orporated DFZM TS210 Users manual
DFZM-TS2xx
Data sheet
DFZM-TS2xx
An IEEE 802.15.4 System–On-Chip Zigbee
module
Data Sheet Sheet 1 of 37 AUG 22, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-TS2xx
Contents
1. Features............................................................................................................................................... 4
2. Zigbee Model No. Definition..............................................................................................................6
3. Architecture......................................................................................................................................... 7
3-1.Block Diagram..............................................................................................................................7
3-2.Block Diagram Description..........................................................................................................8
3-2-1.Overview...........................................................................................................................8
3-2-2.CPU and Memory.............................................................................................................. 8
3-2-3.Clocks and Power Management........................................................................................ 9
3-2-4.Peripherals.........................................................................................................................9
3-3.Power Management....................................................................................................................13
4. Pin-out and Signal Description.........................................................................................................15
4-1.Device Pin-out Diagram (Module top view) ..............................................................................15
4-2.Module Pins Description ............................................................................................................ 16
5. Electrical Characteristics ..................................................................................................................18
5-1.Absolute Maximum Rating.........................................................................................................18
5-2.Recommended Operating Conditions.........................................................................................18
5-3.Power Consumption....................................................................................................................18
5-4.DC Characteristics...................................................................................................................... 20
5-5.Wake-up and Timing...................................................................................................................20
5-6.Radio Parameters........................................................................................................................ 21
5-7.ADC Parameters.........................................................................................................................22
5-8.SPI AC Characteristics ...............................................................................................................24
6. Package and Layout Guidelines........................................................................................................26
6-1.Recommended PCB Footprint and Dimensions.........................................................................26
6-2.Layout Guidelines.......................................................................................................................30
6-2-1.Surface Mount Assembly ................................................................................................ 32
6-3.Recommended Stencil Aperture.................................................................................................34
7. Ordering Information........................................................................................................................ 36
Data Sheet Sheet 2 of 37 AUG 22, 2013
Proprietary Information and Specifications are Subject to Change
2. Module
Revision History
DFZM-TS2xx
Version
0.1 2013/3/11 Initial release Fred
0.2 2013/4/26 Add Peripheral I/O Pin Mapping Fred
0.3 2013/7/1
0.4 2013/8/22 Update power consumption and radio parameters JunRu
Date Reason of change Maker
Add “Not available for DFZM-TS21X-DT0R” at 4-
JunRu
Pins Description( Pins 10、13、25)
Data Sheet Sheet 3 of 37 AUG 22, 2013
Proprietary Information and Specifications are Subject to Change
T
DFZM-TS2xx
DFZM-TS2xx
IEEE802.15.4 System-On-Chip Zigbee Module
HIS DOCUMENT
based modules provide cost effective, low power, and flexible platform to add Zigbee connectivity
for embedded devices for a variety of applications, such as wireless sensors and energy monitoring. It
combines 8051-based processors, in-system programable flash memory, 8-KB RAM, 256KB flash
memory and off module certified antenna options, and various RF front end options for end customer
range needs in order to provide a Zigbee and regulatory certified. The module has various operating
modes, making it highly suit for system where ultralow power consumption is required. Short transition
times between operating modes further ensure low energy consumption.
describes the DFZM-TS2xx Zigbee module hardware specification. The CC2530
1. Features
►
Family of modules with different antenna and output power options:
• DFZM-TS22x 22 mm by 16 mm by 3.3mm (Length * Width * Height) 28-pin Dual Flat pack PCB
Surface Mount Package.
• DFZM-TS21x 27 mm by 16 mm by 3.3 mm (Length * Width * Height) 28-pin Dual Flat pack PCB
Surface Mount Package.
• DFZM-TS220, DFZM-TS221, DFZM-TS210, and DFZM-TS211 are all pin to pin compatible (see
section 7 Ordering Information), and the user has to account only for power consumption, module
outline, and PCB antenna keep out (if used) to accommodate “one size fits all” for various end
applications.
• Simple API for embedded markets covering large areas of applications.
►
Compliant with IEEE 802.15.4 and regulatory domains:
• RoHS compliant.
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• FCC/NCC Certified.
DFZM-TS220 DFZM-TS221 DFZM-TS210 DFZM-TS211
FCC ID H79DFZM-TS220 H79DFZM-TS220 TBD TBD
NCC ID CCAJ12LP2570T7 CCAJ12LP2571T9 TBD TBD
►
Microcontroller:
• High-Performance and Low Power 8051 Microcontroller core with code prefetch .
• 256KB In-Syctem-Programmable Flash.
• 8KB RAM with Retention in all power mode.
• Hardware debug support.
►
Interfaces:
• Chip antenna or external antenna options.
• Two powerful USART with support for several serial protocols.
DFZM-TS2xx
• Up to 21 configurable general purpose I/Os.
• Single 3.3V supply option:
o Wide supply voltage range 2.0 ~ 3.3V.
• One PWM output.
• One 7~ 12-bit ADC with 30KHz~40KHz bandwidth resolution.
►
Embedded RTC (Real Time Clock) can run directly from battery.
►
Low-power mode operations.
►
Power mode 1, 2, 3.
Data Sheet Sheet 5 of 37 AUG 22, 2013
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DT= Delta Define
2. Zigbee Model No. Definition
DFZM-TS2xx
D F Z M - T S 2 2 0 - DT 0 R
E=Pb free
Free-lead
Serial no.
R=RoHS
N=NG
L=Process with Lead
0~9 then A~Z
Customer code
Antenna Version
0= External Antenna
1= Onboard Chip Antenna
Power Version
1= High Power
2= Low Power
Frequency
2= 2.4GHz
Chip Type
S=CC2530
Chip Vendor
T=TI
Product-type
M= Module
Property
Z= Zigbee
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Substrate
Company
F= FR4
D= DELTA
3. Architecture
3-1.Block Diagram
DFZM-TS2xx
ANT
Balun
32K X’tal
Figure 3-1: DFZM-TS22x Block Diagram
32K X’tal
32M X’tal
Digital I/O
VCC
32M X’tal
Digital I/O
ANT
CC2591
VCC
Figure 3-2: DFZM-TS21x Block Diagram
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DFZM-TS2xx
3-2.Block Diagram Description
3-2-1.Overview
DFZM-TS2xx module is a highly integrated Zigbee system-on-chip (SOC) that contains the following:
• The module includes TI CC2530 SoC, which contains CPU- and memory-related, peripherals-related, clocks
and power management-related in a single package.
• The module features an IEEE802.15.4-compliant radio transceiver with onboard 32 KHz & 32 MHz crystal
circuitries, RF, and certified chip antenna or external antenna options.
o The low power module option has a capability of +4.5dBm output power at the antenna (see
Figure 3-1).
o The high power module option has a capability of +18.5dBm output power at the antenna (see
Figure 3-2).
• Variety of interfaces are available such as two USART and SPI, four TIMER, one 7~12 bit ADC,
Operational amperifier and GPIO.
• DFZM-TS2xx contains single power supply (VCC).
3-2-2.CPU and Memory
The 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core. It has three
different memory-access buses (SFR, DATA and CODE/XDATA) with single-cycle access to SFR, DATA, and
the main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (power
modes 1–3).
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory access points, access of
which can map to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. It
is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
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Proprietary Information and Specifications are Subject to Change
physical memory.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The 8-KB
SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off (power
modes 2 and 3). This is an important feature for low-power applications.
The 256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces. In addition to holding program code and constants, the
non-volatile memory allows the application to save data that must be preserved such that it is available after
restarting the device. Using this feature one can, e.g., use saved network-specific data to avoid the need for a full
start-up and network find-and-join process.
DFZM-TS2xx
3-2-3.Clocks and Power Management
The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator. It provides power
management functionality that enables low power operation for long battery life using different power modes.
Five different reset sources exist to reset the device.
3-2-4.Peripherals
The CC2530 includes many different peripherals that allow the application designer to develop advanced
applications.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it ispossible
to perform in-circuit debugging and external flash programming elegantly.
The device contains flash memory for storage of program code. The flash memory is programmable from the
user software and through the debug interface. The flash controller handles writing and erasing the embedded
flash memory. The flash controller allows page-wise erasure and 4-bytewise programming.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
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as an input or output and if a pullup or pulldown resistor in the pad is connected. CPU interrupts can be enabled
on each pin individually. Each peripheral that connects to the I/O pins can choose between two different I/O pin
locations to ensure flexibility in various applications.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors anywhere in
memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achieve
highly efficient operation by using the DMA controller for data transfers between SFR or XREG addresses and
flash/SRAM.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR Generation Mode where it counts Timer 3 periods and the output is ANDed with
DFZM-TS2xx
the output of Timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
Timer 2 (the MAC Timer) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slotted
protocol in software. The timer has a configurable timer period and a 24-bit overflow counter that can be used to
keep track of the number of periods that have transpired. A 40-bit capture register is also used to record the exact
time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission ends, as
well as two 16-bit output compare registers and two 24-bit overflow compare registers that can send various
command strobes (start RX, start TX, etc.) at specific times to the radio modules.
Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable
prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of
the counter channels can be used as a PWM output.
The sleep timer is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz RC oscillator periods.
The sleep timer runs continuously in all operating modes except power mode 3 (PM3). Typical applications of
this timer are as a real-time counter or as a wake-up timer to come out of power mode 1 (PM1) or 2 (PM2).
Data Sheet Sheet 10 of 37 AUG 22, 2013
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The ADC supports 7 to 12 bits of resolution in a 30 kHz to 4 kHz bandwidth, respectively. DC and audio
conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as single-ended or
differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The
ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or
conversion over a sequence of channels.
The operational amplifier is intended to provide front-end buffering and gain for the ADC. Both inputs as well
as the output are available on pins, so the feedback network is fully customizable. A chopper-stabilized mode is
available for applications that need good accuracy with high gain.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin
interrupt.
DFZM-TS2xx
The random-number generator uses a 16-bit LFSR to generate pseudorandom numbers, which can be read by
the CPU or used directly by the command strobe processor. It can be seeded with random data from noise in the
radio ADC.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The core is able to support the AES operations required by IEEE 802.15.4 MAC security, the
ZigBee network layer, and the application layer.
A built-in watchdog timer allows the CC2530 to reset itself in case the firmware hangs. When enabled by
software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. It can
alternatively be configured for use as a general 32-kHz timer.
USART 0 and USART 1 are each configurable as either a SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each has its own high-precision baud-rate generator, thus leaving the ordinary timers free for other
uses.
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Note that peripheral units have two alternative locations for their I/O pins; see Table 3-1. Priority can be set
between peripherals if conflicting settings regarding I/O mapping are present . All combinations not causing
conflicts can be used.
DFZM-TS2xx
Table 3-1: DFZM-TS2xx Peripheral I/O Pin Mapping
Data Sheet Sheet 12 of 37 AUG 22, 2013
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