Delta Electronics orporated DFZM E8210 Users manual
DFZM-E82xx
Data sheet
DFZM-E82xx
An IEEE 802.15.4 System–On-Chip ZigBee
module
Data Sheet Sheet 1 of 41 Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
Contents
1. Features .................................................................................................................................... ........... 4
2. ZigBee Model No. Definition .......................................................... ..... ..... ... ..... ...... .. ...... ..... ... . .... ...... 6
3. Architecture ........................................................................................................................ ................. 7
3-1.Block Diagram ............................................................................................................................. . 7
3-2.Block Diagram Description .......................................................................................................... 8
3-2-1.Overview ..................... ............................................. .............................................. ........... 8
3-2-2.CPU and Memory .............................................................................................................. 8
3-2-3.Clocks and Power Management ...................................................................................... 10
3-2-4.Peripherals .............................................................................................................. ......... 12
4. Pin-out and Signal Description .......... ................................................................ ... ............................ 15
4-1.Device Pin-out Diagram (Module top view) .. ................................ ... ......................................... 15
4-2.Module Pins Description ..................... ....................................................................................... 16
5. Electrical Characteristics ........................... ... ..... ...... .. ...... ..... ..... ... ..... ...... .. ...... ..... ... ..... ..... ... ............ 23
5-1.Absolute Maximum Rating......................................................................................................... 23
5-2.Recommended Operating Conditions ......................................................................................... 23
5-3.Power Consumption........... ................................................................................................ ......... 24
5-4.Digital I/O and nRESET Pin Specifications ............................................................................... 25
5-5.Wake-up and Timing ............................................................................................................... .... 26
5-6.Radio Parameters ................................................................................................................. ....... 27
5-7.ADC Parameters .................................................................................. ... ................................ .... 28
6. Package and Layout Guidelines ........................................................................................................ 29
6-1.Recommended PCB Footprint and Dim ensions .......................................... ............................... 29
6-2.Layout Guidelines ...................................... .. ...... ..... ... ..... ..... ... ..... ...... ..... ... ..... ..... ... ..... ... ............ 32
6-2-1.Surface Mount Assembly ................................................................................................ 33
6-3.Recommended Stencil Aperture ................................................................................................. 35
7. Ordering Information ............................................................................................................... ......... 36
8. Package ...................................... ........................................ ........................................ ....................... 36
8-1.Information of carrier tape direction&packaging dimension .............. ...................... ................. 36
8-
2.Reel dimension ....................... ... ............................................................................................. .... 38
8-3.Total Package .............................................................................................................................. 39
Data Sheet Sheet 2 of 41 Dec 31, 2013
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DFZM-E82xx
Revision History
Version Date Reason of change Maker
0.1 2013/12/31 Initial release Monch
1. Add RF exposure warning statement including FCC
0.2 2014/06/27
statement.
2. Modify 5.6 Radio Parameter for DFZM-E821x .
Monch
Data Sheet Sheet 3 of 41 Dec 31, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E82xx
DFZM-E82xx
IEEE802.15.4 System-On-Chip ZigBee Module
HIS DOCUMENT describes the DFZM-E82xx ZigBee module hardware specification. The EM3587
T
based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity
for embedded devices for a variety of applications, such as wireless sensors、energy and security
monitoring、building( or home ) automation and control . It combines 32-bit A RM Corte x-M3 pro cess or,
in-system programable flash memory, 64-KB RAM, 512KB flash memory and off module certified
antenna options, and various RF front end options for end customer range needs in order to provide a
ZigBee and regulatory certified. The module has various operating modes, making it highly suit for
system where ultralow power consumption is required. Short transition times between operating modes
further ensure low energy consumption.
1. Features
► Family of modules with different antenna and output power options:
DFZM-E82xx 27 mm by 16 mm by 3.3 mm (Length * Width * Height) 28-pin Dual Flat pack PCB
Surface Mount Package.
DFZM-E8220, DFZM-E8221, DFZM-E8210, and DFZM-E8211 are all pin to pin compatible (see
section 7 Ordering Information), and the user has to account only for power consumption for various
end applications.
Simple API for embedded markets covering large areas of applications.
► Compliant with IEEE 802.15.4-2003 and regulatory domains:
RoHS compliant.
► Microcontroller:
Industry-leading ARM Cortex-M3 processor.
512KB Flash with optional read protection.
64KB RAM memory.
Data Sheet Sheet 4 of 41 Dec 31, 2013
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DFZM-E82xx
Flexible nested vectored interrupt controller.
► Interfaces:
Internal antenna or external antenna options.
Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers.
Up to 24 configurable general purpose I/Os.
Single voltage operation: 2.1~3.6V
► Embedded RTC (Real Ti me Clock) can run directly from battery.
Data Sheet Sheet 5 of 41 Dec 31, 2013
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DFZM-E82xx
2. ZigBee Model No. Definition
D F Z M - E 8 2 2 0 -DT0 R
E=Pb free
Free-lead
Serial no.
R=RoHS
N=NG
L=Process with Lead
0~9 then A~Z
Customer code
DT= Delta Define
Antenna Version
0= External Antenna
1=PCB printed Antenna
Power Version
1= High Power
2= Low Power
Frequency
2= 2.4GHz
Chip Type
8=EM3587
Chip Vendor
E=Ember(Silicon Labs)
Product-type
M= Module
Property
Z= ZigBee
Data Sheet Sheet 6 of 41 Dec 31, 2013
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Substrate
Company
F= FR4
D= DELTA
3. Architecture
3-1.Block Diagram
DFZM-E82xx
Figure 3-1: DFZM-E822x Block Diagram
ANT
SE2432L
24M X’tal
Digital I/O
VCC
Figure 3-2: DFZM-E821x Block Diagram
Data Sheet Sheet 7 of 41 Dec 31, 2013
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DFZM-E82xx
3-2.Block Diagram Description
3-2-1.Overview
DFZM-E82xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following:
The module includes Silicon Labs EM3587 SoC, which contains CPU- and memory-related,
peripherals-related, clocks and power management-related in a single package.
The module features an IEEE802.15.4 -compliant radi o transceiver with onboard 24 MHz crystal circuitries,
RF, and certified antenna or external antenna options.
o The low power module option has a capability of +8dBm output power at the antenna (see Figure
3-1).
o The high power module option has a capability of +18.5dBm output power at the antenna (see
Figure 3-2).
Variety of interfaces are available such as UART, SPI, TIMER, ADC, Operational amperifier and GPIO.
DFZM-E82xx contains single power supply (VCC).
3-2-2.CPU and Memory
The EM3587 integrates the ARM® Cortex-M3 microprocessor. The ARM® Cortex-M3 is an advanced 32-bit
modified Harvard architecture processor that has separate internal program and data buses, but p resents a unified
program and data address space to software. The word width is 32 bits for both the program and data sides. The
ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficiently-packed data
structures.
The ARM® Cortex-M3 clock speed is configurable to 6 , 12 , or 24 MHz. For normal operation 24 MHz is
preferred over 12 MHz due to improved performance for all applications and improved duty cycling for
applications using sleep modes. The 6 MHz operation can only be used w hen radio operations are not required
since the radio requires an accurate 12 MHz clock.
The ARM® Cortex-M3 in the EM3587 has also been enhanced to support two separate memory protection levels.
Basic protection is available without using the MPU, but no rmal operation uses the MPU. The MPU allows for
protecting unimplemented areas of the memory map to prevent common software bugs from interfering with
software operation. The architecture could also allow for separation of the networking stack from the application
code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the
Data Sheet Sheet 8 of 41 Dec 31, 2013
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DFZM-E82xx
developer to assist in tracking down and fixing issues. Figure 3.3 shows the EM357 ARM® Cortex-M3 memory
map.
Figure 3-3: DFZM-E82xx memory map
Data Sheet Sheet 9 of 41 Dec 31, 2013
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DFZM-E82xx
3-2-3.Clocks and Power Management
The DFZM-E82xx integrates three oscillators:
12 MHz RC oscillator
24 MHz crystal oscillator
10 kHz RC oscillator
Figure 3-4 shows a block diagram of the clocks in the DFZM-E82xx. This simplified view shows all the clock
sources and the general areas of the chip to which they are routed
Figure 3-4: DFZM-E82xx block diagram of the clocks
Data Sheet Sheet 10 of 41 Dec 31, 2013
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DFZM-E82xx
The DFZM-E82xx’s power management system is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The DFZM-E82xx
has four main sleep modes:
Idle Sleep: Puts the CPU into an idle state where execution is suspen ded until any interrupt occurs. All power
domains remain fully powered and nothing is reset.
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down and
the sleep timer is active.
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this mode th e
sleep timer cannot wake up the DFZM-E82xx.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip e mulates a true deep sleep without powering
down the core domain. Instead, the core domain remains powered and all peripherals except the system debug
components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow DF ZM-E82xx
software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints.
The power management state diagram in Figure 3-5 shows the basic operation of the power management
controller.
Figure 3-5: DFZM-E82xx power management state diagram
Data Sheet Sheet 11 of 41 Dec 31, 2013
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DFZM-E82xx
3-2-4.Peripherals
The DFZM-E82xx has 24 multipurpose GPIO pins, which may be individually configured as:
General purpose output
General purpose open-drain output
Alternate output controlled by a peripheral device
Alternate open-drain output controlled by a peripheral device
Analog
General purpose input
General purpose input with pull-up or pull-down resistor
The GPIO signal assignments are shown in Table 3-1.
GPIO Analog Alternate Output Input Output Current Drive
PA0 TIM2C31, SC2MOSI TIM2C31, SC2MOSI Standard
PA1 TIM2C31, SC2MISO, SC2SDA TIM2C31, SC2MISO, SC2SDA Standard
PA2 TIM2C41, SC2SCLK, SC2SCL TIM2C41, SC2SCLK, SC2SCL Standard
PA3 TIM2C21 TIM2C21, SC2nSSEL Standard
PA4 ADC4 PTI_EN, TRACEDATA2 Standard
PA5 ADC5 PTI_DATA, TRACEDATA3 nBOOTMODE
2
Standard
PA6 TIM1C3 TIM1C3 High
PA7 TIM1C4, REG_EN
3
TIM1C4 High
TRACEDATA2, TIM2MSK,
PB0 VREF TRACEDATA2
Standard
IRQA,TIM1CLK
PB1
TIM2C1
4
, SC1TXD, SC1MOSI,
TIM2C1
4
, SC1SDA Standard
SC1MISO, SC1SDA
PB2 TIM2C24, SC1SCL
TIM2C2
4
, SC1MISO, SC1MOSI,
Standard
SC1SCL, SC1RXD
PB3 TIM2C34, SC1SCLK TIM2C34, SC1SCLK, SC1nCTS Standard
PB4 TIM2C44, SC1nRTS TIM2C44, SC1nSSEL Standard
PB5 ADC0 TIM2CLK, TIM1MSK Standard
PB6 ADC1 TIM1C1 TIM1C1, IRQB High
PB7 ADC2 TIM1C2 TIM1C2, IRQC High
Data Sheet Sheet 12 of 41 Dec 31, 2013
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DFZM-E82xx
PC0 TRACEDATA1 JRST, IRQD
High
PC1 ADC3 TRACEDATA3 Standard
PC2 JTDO6, SWO , TRACEDATA0 Standard
PC3 TRACECLK JTDI
PC4 SWDIO
7
SWDIO7, JTMS
5 ,
TRACECLK
7
Standard
Standard
PC5 TX_ACTIVE Standard
Notes:
1.Default signal assignment (not remapped).
2. Overrides during reset as an input with pull up.
3. Overrides after reset as an open-drain output.
4. Alternate signal assignment (remapped).
5. Overrides in JTAG mode as a input with pull up.
6. Overrides in JTAG mode as a push-pull output.
7. Overrides in Serial Wire mode as either a push-pull output, or a floating input, controlled by the debugger.
Table 3-1: DFZM-E82xx GPIO signal assignments
The DFZM-E82xx has two serial controllers, SC1 and SC2, which provide several options for full-duplex
synchronous and asynchronous serial communications.
SPI (Serial Peripheral Interface), master or slave
TWI (Two Wire serial Interface), master only
UART (Universal Asynchronous Receiver/Transmitter), SC1 only
Receive and transmit FIFOs and DMA channels, SPI and UART modes
Before using a serial controller, configure and initialize it as follows:
1. Set up the parameters specific to the operating mode (master/slave for SPI, baud rate for UART, etc.).
2. Configure the GPIO pins used by the serial controller as shown in Tables 3-2 and 3-3.
3. If using DMA, set up the DMA and buffers.
4. If using interrupts, select edge- or level-triggered interrupts with the SCx_INTMODE register, enable the
desired second-level interrupt sources in the INT_SCxCFG register, and finally enable the top-level SCx interrupt
in the NVIC.
5. Write the serial interface operating mode (SPI, TWI, or UART) to the SCx_MODE register
Data Sheet Sheet 13 of 41 Dec 31, 2013
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