Proprietary Information and Specifications are Subject to Change
DFZM-E72xx
Contents
1. Features ............................................................................................................................................... 4
2. ZigBee Model No. Definition ............................................................................................................. 6
HIS DOCUMENT describes the DFZM-E72xx ZigBee module hardware specification. The EM357
based modules provide cost effective, low power, and flexible platform to add ZigBee connectivity
for embedded devices for a variety of applications, such as wireless sensors and energy monitoring. It
combines 32-bit ARM Cortex-M3 processor, in-system programable flash memory, 12-KB RAM,
192KB flash memory and off module certified antenna options, and various RF front end options for end
customer range needs in order to provide a ZigBee and regulatory certified. The module has various
operating modes, making it highl y suit for system where ultralow power consumption i s required. Short
transition times between operating modes further ensure low energy consumption.
1. Features
► Family of modules with different antenna and output power options:
• DFZM-E72xx 27 mm by 16 mm by 3.3 mm (Length * Width * Height) 28-pin Dual Flat pack PCB
Surface Mount Package.
• DFZM-E7220, DFZM-E7221, DFZM-E7210, and DFZM-E7211 are all pin to pin compatible (see
section 7 Ordering Information), and the user has to account only for power consumption for various
end applications.
• Simple API for embedded markets covering large areas of applications.
► Compliant with IEEE 802.15.4 and reg ulatory domains:
• RoHS compliant.
► Microcontroller:
• Industry-leading ARM Cortex-M3 processor.
• 192KB Flash with optional read protection.
• 12KB RAM memory.
• Flexible nested vectored interru pt cont ro lle r.
Data Sheet Sheet 4 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E72xx
►Interfaces:
• Internal antenna or external antenna options.
• Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers.
• Up to 22 configurable general purpose I/Os.
• Single voltage operation: 2.1~3.6V
►Embedded RTC (Real Time Clock) can run directly from battery.
Data Sheet Sheet 5 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E72xx
1= High Power
0= External Antenna
DT= Delta Define
7=EM357
0~9 then A~Z
Serial no.
2. ZigBee Model No. Definition
D F Z M - E 7 2 2 0 - DT 0 R
E=Pb free
Free-lead
R=RoHS
N=NG
L=Process with Lead
Customer code
Antenna Version
1= Onboard Chip Antenna
Power Version
2= Low Power
Frequency
2= 2.4GHz
Chip Type
Chip Vendor
E=Ember(Silicon Labs)
Product-type
M= Module
Property
Z= ZigBee
Substrate
Company
Data Sheet Sheet 6 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
F= FR4
D= DELTA
VCC
3. Architecture
3-1.Block Diagram
DFZM-E72xx
ANT
ANT
Balun
24M X’tal
Digital I/O
VCC
Figure 3-1: DFZM-E722x Block Diagram
24M X’tal
SE2432L
Figure 3-2: DFZM-E721x Block Diagram
Data Sheet Sheet 7 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
Digital I/O
DFZM-E72xx
3-2.Block Diagram Description
3-2-1.Overview
DFZM-E72xx module is a highly integrated ZigBee system-on-chip (SOC) that contains the following:
• The module includes Silicon Labs EM357 SoC, which contains CPU- and memory-related,
peripherals-related, clocks and power management-related in a single package.
• The module features an IEEE802.15.4-compliant radio transceiver with onboard 24 MHz crystal circuitries,
RF, and certified antenna or external antenna options.
o The low power module option has a capability of +8dBm output power at the antenna (see Figure
3-1).
o The high power module option has a capability of +18.5dBm output power at the antenna (see
Figure 3-2).
• Variety of interfaces are available such as UART, SPI, TIMER, ADC, Operational amperifier and GPIO.
• DFZM-E72xx contains single power supply (VCC).
3-2-2.CPU and Memory
The EM357 integrates the ARM® Cortex-M3 microprocessor. The ARM® Cortex-M3 is an advanced 32-bit
modified Harvard architecture processor that has separate internal program and data buses, but presents a unified
program and data address space to software. The word width is 32 bits for both the program and data sides. The
ARM® Cortex-M3 allows unaligned word and half-word data accesses to support efficiently-packed data
structures.
The ARM® Cortex-M3 clock speed is configurable to 6 , 12 , or 24 MHz. For normal operation 24 MHz is
preferred over 12 MHz due to improved performance for all applications and improved duty cycling for
applications using sleep modes. The 6 MHz operation can only be used when radio operations are not required
since the radio requires an accurate 12 MHz clock.
The ARM® Cortex-M3 in the EM357 has also been enhanced to support two separate memory protection levels.
Basic protection is available without using the MPU, but normal operation uses the MPU. The MPU allows for
protecting unimplemented areas of the memory map to prevent common software bugs from interfering with
software operation. The architecture could also allow for separation of the networking stack from the application
code using a fine granularity RAM protection module. Errant writes are captured and details are reported to the
Data Sheet Sheet 8 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E72xx
developer to assist in tracking down and fixing issues. Figure 3.3 shows the EM357 ARM® Cortex-M3 memo ry
map.
Figure 3-3: DFZM-E72xx memory map
Data Sheet Sheet 9 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
Figure 3-4 shows a block diagram of the clocks in the DFZM-E72xx. This simplified view shows all the clock
sources and the general areas of the chip to which they are routed
Figure 3-4: DFZM-E72xx block diagram of the clocks
Data Sheet Sheet 10 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E72xx
The DFZM-E72xx’s power management system is designed to achieve the lowest deep sleep current consumption
possible while still providing flexible wakeup sources, timer activity, and debugger operation. The DFZM-E72xx
has four main sleep modes:
Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All power
domains remain fully powered and nothing is reset.
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down and
the sleep timer is active.
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this mode the
sleep timer cannot wake up the DFZM-E72xx.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without powering
down the core domain. Instead, the core domain remains powered and all peripherals except the system debug
components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow DFZM-E72xx
software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints.
The power management state diagram in Figure 3-5 shows the basic operation of the power management
controller.
Figure 3-5: DFZM-E72xx power management state diagram
Data Sheet Sheet 11 of 40 Sep 16, 2013
Proprietary Information and Specifications are Subject to Change
DFZM-E72xx
3-2-4.Peripherals
The DFZM-E72xx has 22 multipurpose GPIO pins, which may be individually configured as:
General purpose output
General purpose open-drain output
Alternate output controlled by a peripheral device
Alternate open-drain output controlled by a peripheral device
Analog
General purpose input
General purpose input with pull-up or pull-down resistor
The GPIO signal assignments are shown in Table 3-1.
GPIO Analog Alternate Output Input Output Current Drive
PA0 TIM2C11, SC2MOSI TIM2C11, SC2MOSI Standard
PA1 TIM2C31, SC2MISO, SC2SDA TIM2C31, SC2MISO, SC2SDA Standard
PA2 TIM2C41, SC2SCLK, SC2SCL TIM2C41, SC2SCLK Standard
PA3 TIM2C21, TRACECLK TIM2C21, SC2nSSEL Standard
PA4 ADC4 P TI_EN, TRACEDATA2 Standard
PA5 ADC5 PT I_DATA, TRACEDATA3 nBOOTMODE
2
Standard
PA6 TIM1C3 TIM1C3 High
PA7 TIM1C4, REG_EN
3
TIM1C4 High
PB0 VREF TRACECLK TIM1CLK, TIM2MSK, IRQA Standard
PB1
TIM2C1
4
, SC1TXD, SC1MOSI,
TIM2C1
4
, SC1SDA Standard
SC1MISO, SC1SDA
PB2 TIM2C24, SC1SCLK
TIM2C2
4
, SC1MISO, SC1MOSI,
Standard
SC1SCL, SC1RX D
PB3 TIM2C34, SC1SCLK TIM2C34, SC1SCLK, SC1nCTS Standard
PB4 TIM2C44, SC1nRTS TIM2C44, SC1nSSEL Standard
PB5 ADC0 TIM2CLK, TIM1MSK Standard
PB6 ADC1 TIM1C1 TIM1C1, IRQB High
PB7 ADC2 TIM1C2 TIM1C2 High
PC0 TRACEDATA1 JRST
5
High
Data Sheet Sheet 12 of 40 Sep 16, 2013
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