Dell studio 1558 Schematics
1
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7
8
FM9 HANKS Intel PARK Discrete GFX
A A
FAN & THERMAL
SMSC1422
POWER
AC/BATT
CONNECTOR
PG 53
B B
DDR3-SODIMM1
PG 13
DDR3-SODIMM2
PG 14
E-SATA Combo
C C
with USB CONN
SYSTEM
RESET CIRCUIT
BATT
CHARGER
RUN POWER SW
+3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V
Dual Channel DDR3
800/1066/1333 1.5V
SATA-ODD
SATA-HDD
& Fall Sensor
SN75LVCP412
PG 35
PG 35
PG 33PG 33
PG 42
PG 45
PG 52
SATA
SATA
SATA
IHDA
USB2.0
Arrandale/
Clarksfield
( rPGA 989 )
PCH
CLOCK
SLG8SP585VTR
(QFN-32)
PCIEx16
DDR3 x 4
(1G)
PG 20
PG 3,4,5,6
DMI X 4FDI
USB2.0 x 3
PCIEx1
PCIEx1
USB2.0
PCIEx2
USB2.0
PG 38
PG 15
ATI PARK-S3
PCI EXPRESS GFX
PG 16,17,18,19,21,22
AUDIO/AMP
92HD73C
PG 39
Audio
SPK conn
Audio
Jacks x3
PG 39 PG 40
D D
1
Camera + D-MIC
PG 40
USER
INTERFACE
PG 37
2
KBC
ITE8502
SPI PS/2
FLASH
1Mbyts
PG 30
LPC
3
PG 29
Touchpad
PG 36
PG 7,8,9,10,11,12
FLASH
4Mbyts
17X8
Keyboard
SPI
PG 30
PG 36
4
USB2.0
5
POWER
+1.5V_SUS/+0.75V_DDR_VTT
+1.05V
+1.1V_DDR_VTT
LVDS
HDMI
VGA
USB conn x 3
PG 33, 34
6
PG 47
PG 48
P49
DC/DC
+3.3V_ALW/+5V_ALW /
+15V_ALW
VGA Core
Panel Connector
HDMI CONN.
CRT CONN.
LAN
RTL8111DL\RJ45\Transformer
EXPRESS/Card Reader/1394
R5U230
MINI-CARD
CPU VRREGULATOR
WLAN
MINI-CARD
WWAN
Bluetooth BTB Conn
Title
Title
Title
Schematic Block Diagram1
Schematic Block Diagram1
Schematic Block Diagram1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
FM9 3B
FM9 3B
FM9 3B
Date: Sheet of
Date: Sheet of
Date: Sheet
PG 32
PG 31
PG 32
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
7
PG 24
PG 24
PG 25
PWA:
PWB:
PG 41
PG 26,28
166Tuesday, October 06, 2009
166Tuesday, October 06, 2009
166Tuesday, October 06, 2009
PG 51
PG 46
PG 50
8
of
VER : 1A
1
2
3
4
5
6
7
8
Table of Contents Power States
PAGE DESCRIPTION
Schematic Block Diagram
1
2
Front Page
3-6
Clark sfield/Auburndale
7-12
PCH
13-14
A A
B B
C C
DDRIII SO-DIMM(204P)
Clock Generator
15
M92-S3-XT
16-22
BLANK PAGE
23
LCD CONN / HDMI CONN
24
CRT CONN
25
26
R5U230
BLANK PAGE
27
Express/CRard/1394
28
29
SIO (ITE8502)
30
FLASH / RTC
31
MINI-Card (WWAN)
32
MINI-Card (WLAN\WPAN)
Left PUSB/ESATA
33
34
Right USB
35
SATA (HDD & CD_ROM)
TP / KEYBOARD
36
SWITCH / /LED
37
FAN / THERMAL
38
39
Azelia CODEC
40
AUDIO CONN
41
LAN(RTL8111DL/RJ-45)
42
System Reset Circuit
Blank Page
43
1.8V_RUN(RT9018/RT9024)
44
Charger (MAX8731)
45
46
3V/5V (TPS51427A)
1.5_DDR/0.75(TPS51116)
47
1.05V_PCH(TPS51218)
48
49
1.1_VTT(TPS51218)
50
VGA_M92-XT(MAX8792)
51
CPU CORE(MAX17036)
52
Run Power Switch
DCin & Batt
54
PAD & SCREW
55
EMI CAP
56
SMBUS BLOCK
THERMAL MAP
57
58
Power Block Diagram
59
Power sequence Block
XDP
60
POWER PLANE
+PWR_SRC
+RTC_CELL
10V~+19V
+3.0V~+3.3V
24,30,45,46,47,48,49,50,51
08,11,29,30
DESCRIPTION
MAIN POWER
RTC
LARGE POWER S0~S537,46,52,53 MAIN POWER+5V+5V_ALW2
+5V_ALW
+3.3V_ALW
+5V_SUS
+3.3V_SUS
+1.5V_SUS
+0.75V_DDR_VTT
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.8V_RUN_GFX
+1.5V_RUN
+VCC_GFX_CORE
+5V
+5V
+3.3V
+1.5V
+0.75V
+5V
+3.3V
+1.8V
+1.5V
+0.9V~+1.2V RUN_ON
13,33,44,46,47,48,49,50,51,52
29,30,35,36,37,42,44,45,46,47,51,52,53
11,33,34,37,51,52
07,08,09,10,11,13,14,19,24,28,29,37,41,42,44
,48,49,50,52
03,05,13,14,47,50,52
13,14,47,52
11,18,24,25,35,36,38,39,40,51,52
3,7,8,9,10,11,13,14,15,17,24,25,26,28,29,30
,31,32,33,35,37,38,39,40,41,42,46,51,52,60
05,11,44,52
11,18,19,20,28,31,32,52
18,21,50
LARGE POWER
8051 POWER 3.3V_ALW_ON S0~S5+3.3V
SLP_S5# CTRLD POWER
SLP_S5# CTRLD POWER
SODIMM POWER
SODIMM POWER
SLP_S3# CTRLD POWER
SLP_S3# CTRLD POWER
SDVO POWER
VGA POWER+1.8V 17,18,21,22,44,52
VGA POWER
VGA POWER
+1.05V_PCH PCH POWER+1.05V 08,09,11,15,48 RUN_ON
+VCC_CORE
+LCDVCC
+5V_MOD
+5V_HDD
+0.7V~+1.77V
+3.3V
+5V
+5V
+1.1V_VTT 03,05,10,11,49,60+1.1V
+1.1V_GFX_PCIE
+1.1V 18,50
GND PLANE PAGE
GND
ALL53
05,51
24
35
35
DESCRIPTION
CPU CORE POWER
LCD Power
MOD Power
HDD Power
CPU POWER
VGA POWER
CONTROL
SIGNAL
ALW_ON
SUS_ON
SUS_ON
SUS_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON
IMVP_VR_ON
LCDVCC_TST_EN
& ENVDD
MODC_EN
HDDC_EN
RUN_ON
GFX_ON
ACTIVE INVOLTAGE PAGE
S0~S5
S0~S5
S0~S5
D D
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
1
2
3
4
5
6
Date: Sheet
COMPUTER
Index & Power Status
Index & Power Status
Index & Power Status
FM9 3B
FM9 3B
FM9 3B
7
266Tuesday, October 06, 2009
266Tuesday, October 06, 2009
266Tuesday, October 06, 2009
of
8
5
4
3
2
1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
SC(V1.0),P11: Should be shorted at the pins
and then routed to one end of the 49.9-ȍ ±1%
resistor, pulled-down to GND on the board.
U34A
U34A
DMI_TXN07
D D
C C
DMI_TXN17
DMI_TXN27
DMI_TXN37
DMI_TXP07
DMI_TXP17
DMI_TXP27
DMI_TXP37
DMI_RXN07
DMI_RXN17
DMI_RXN27
DMI_RXN37
DMI_RXP07
DMI_RXP17
DMI_RXP27
DMI_RXP37
R10291KR1029
1K
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
R711KR71
1K
0214
DG(V1.0),P79: should be tied to GND
(through 1K ±5% resistors),
if these signals are left floating,
there are nofunctional impacts
but a small amount of power (~15 mW)
maybe wasted.
DG(V1.1) P83:
FDI_FSYNC[0], FDI_FSYNC[1],
FDI_LSYNC[0],FDI_LSYNC[1]
B B
can be ganged together
with one resistor.
PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N15
Processor
Pullups
A A
H_CATERR#
H_PROCHOT#_D
H_CPURST#
R100
R100
49.9/F
49.9/F
C554 0.1U16 C554 0.1U16
C557 0.1U16 C557 0.1U16
C559 0.1U16 C559 0.1U16
C562 0.1U16 C562 0.1U16
C566 0.1U16 C566 0.1U16
C575 0.1U16 C575 0.1U16
C579 0.1U16 C579 0.1U16
C584 0.1U16 C584 0.1U16
C587 0.1U16 C587 0.1U16
C595 0.1U16 C595 0.1U16
C597 0.1U16 C597 0.1U16
C601 0.1U16 C601 0.1U16
C605 0.1U16 C605 0.1U16
C612 0.1U16 C612 0.1U16
C614 0.1U16 C614 0.1U16
C618 0.1U16 C618 0.1U16
+1.1V_VTT
R121
R121
49.9/F
49.9/F
5
Clarksfield/A uburndale
Clarksfield/A uburndale
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15
SC(1.0V),P17:
H_PROCHOT#D
use: pull to 68 ohm
R122
R122
if it isn'tt used: pull to 50 ohm
*68_NC
*68_NC
SC(1.0V),P17:
H_CATERR#
49.9-ȍ ±1% Pull-Up to the VTT rail
(+V1.1S_VTT)
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
DMI Intel(R) FDI
DMI Intel(R) FDI
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PCIE_MTX_GRX_N[0..15] 16 PCIE_MTX_GRX_P [0..15] 16
PEG_ICOMPI
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
R412 49.9/FR412 49. 9/F
R413 750/FR413 750/F
PCIE_MRX_GTX_N15
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_P 15
PCIE_MRX_GTX_P 14
PCIE_MRX_GTX_P 13
PCIE_MRX_GTX_P 12
PCIE_MRX_GTX_P 11
PCIE_MRX_GTX_P 10
PCIE_MRX_GTX_P 9
PCIE_MRX_GTX_P 8
PCIE_MRX_GTX_P 7
PCIE_MRX_GTX_P 6
PCIE_MRX_GTX_P 5
PCIE_MRX_GTX_P 4
PCIE_MRX_GTX_P 3
PCIE_MRX_GTX_P 2
PCIE_MRX_GTX_P 1
PCIE_MRX_GTX_P 0
PCIE_MTX_GRX_C_N15
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_P 15
PCIE_MTX_GRX_C_P 14
PCIE_MTX_GRX_C_P 13
PCIE_MTX_GRX_C_P 12
PCIE_MTX_GRX_C_P 11
PCIE_MTX_GRX_C_P 10
PCIE_MTX_GRX_C_P 9
PCIE_MTX_GRX_C_P 8
PCIE_MTX_GRX_C_P 7
PCIE_MTX_GRX_C_P 6
PCIE_MTX_GRX_C_P 5
PCIE_MTX_GRX_C_P 4
PCIE_MTX_GRX_C_P 3
PCIE_MTX_GRX_C_P 2
PCIE_MTX_GRX_C_P 1
PCIE_MTX_GRX_C_P 0
PCIE_MTX_GRX_C_P 0
PCIE_MTX_GRX_C_P 1
PCIE_MTX_GRX_C_P 2
PCIE_MTX_GRX_C_P 3
PCIE_MTX_GRX_C_P 4
PCIE_MTX_GRX_C_P 5
PCIE_MTX_GRX_C_P 6
PCIE_MTX_GRX_C_P 7
PCIE_MTX_GRX_C_P 8
PCIE_MTX_GRX_C_P 9
PCIE_MTX_GRX_C_P 10
PCIE_MTX_GRX_C_P 11
PCIE_MTX_GRX_C_P 12
PCIE_MTX_GRX_C_P 13
PCIE_MTX_GRX_C_P 14
PCIE_MTX_GRX_C_P 15
PCIE_MRX_GTX_N[0..15] 16
PCIE_MRX_GTX_P [0..15] 16
SC(V1.0),P17,35:
This signal should be connected to
the processor's VCCPWRGOOD_1
and VCCPWRGOOD_0 input to
indicate when the
processor power is valid.
VTTPWRGOOD
SC(V1.0)P18:
VTT_1.1 VR power good signal
to processor. Signal voltage level
is 1.1 V.
+1.5V_SUS
R171
R171
1.1K/F
1.1K/F
R97
R97
3K/F
3K/F
C553 0.1U16 C553 0.1U16
C555 0.1U16 C555 0.1U16
C558 0.1U16 C558 0.1U16
C560 0.1U16 C560 0.1U16
C563 0.1U16 C563 0.1U16
C568 0.1U16 C568 0.1U16
C576 0.1U16 C576 0.1U16
C580 0.1U16 C580 0.1U16
C585 0.1U16 C585 0.1U16
C588 0.1U16 C588 0.1U16
C596 0.1U16 C596 0.1U16
C599 0.1U16 C599 0.1U16
C602 0.1U16 C602 0.1U16
C606 0.1U16 C606 0.1U16
C613 0.1U16 C613 0.1U16
C616 0.1U16 C616 0.1U16
Processor Compensation Signals
R72
R72
R123
R123
49.9/F
49.9/F
49.9/F
49.9/F
DG(V1.0),P17:
COMP[0.1] 49.9-ȍ ±1% pull-down to GND
COMP[2.3] 20-ȍ ±1% pull-down to GND
4
R124
R124
20/F
20/F
PM_DRAM_PWRGD
PCIE_MTX_GRX_P 0
PCIE_MTX_GRX_P 1
PCIE_MTX_GRX_P 2
PCIE_MTX_GRX_P 3
PCIE_MTX_GRX_P 4
PCIE_MTX_GRX_P 5
PCIE_MTX_GRX_P 6
PCIE_MTX_GRX_P 7
PCIE_MTX_GRX_P 8
PCIE_MTX_GRX_P 9
PCIE_MTX_GRX_P 10
PCIE_MTX_GRX_P 11
PCIE_MTX_GRX_P 12
PCIE_MTX_GRX_P 13
PCIE_MTX_GRX_P 14
PCIE_MTX_GRX_P 15
H_COMP0
H_COMP1
H_COMP2
H_COMP3
R125
R125
20/F
20/F
U34B
H_COMP3
H_COMP2
H_COMP1
11
H_CPUDET#29
H_PECI10
H_THERM10
H_CPURST#60
PM_SYNC7
H_PWRGOOD10,60
PM_DRAM_PWRGD7
H_VTTPWRGD42
H_PWRGD_XDP60
PLTRST#9,16,26,28,29,31,32,41
RSTIN#:
DG(V1.11)(Doc.# 414044),P10:
Need a voltage divider
network to scale down from
3.3V (PCH driven) to 1.05V/1.1V (Clarksfield/Auburndale)
R188 *0_shortR188 *0_short
R131 *0_shortR131 *0_short
R137 *0_shortR137 *0_short
R164 1.5K/FR164 1.5K/F
H_COMP0
TP_SKT0CC#
H_CATERR#
H_PECI_ISO
H_PROCHOT#_D
H_CPURST#
PM_DRAM_PWRGD
R163
R163
750/F
750/F
U34B
AT23
AT24
G16
AT26
AH24
AK14
AT15
AN26
AK15
AP26
AL15
AN14
AN27
AK13
AM15
AM26
AL14
Clarksfield/A uburndale
Clarksfield/A uburndale
0214
CRB(V1.0) P11:
is it necessery?
DDR3 Compensation Signals
R95
R95
130/F
130/F
3
COMP3
COMP2
COMP1
COMP0
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
RSTIN#
H_THERM
MMST3904-7-F
MMST3904-7-F
T18T18
T17T17
R94
R94
R89
R89
100/F
100/F
24.9/F
24.9/F
DG(V1.0),P83:
SM_RCOMP[0] 100-ȍ ±1% pull-down to GND
SM_RCOMP[1] 24.9-ȍ ±1% pull-down to GND
SM_RCOMP[2] 130-ȍ ±1% pull-down to GND
MISC THERMAL
MISC THERMAL
PWR MANAGEMENT
PWR MANAGEMENT
+3.3V_RUN
R144
R144
10M
10M
12
2
Q28
Q28
1 3
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
R158 *51_NCR158 *51_NC
R493 *51_NCR493 *51_NC
R157 *51_NCR157 *51_NC
R156 *51_NCR156 *51_NC
Layout Note: Place
these resistors
near Processor
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
2
C313
C313
0.1U
0.1U
16
16
2
31
+1.1V_VTT
Q29
Q29
2N7002W-7-F
2N7002W-7-F
PRDY#
PREQ#
TRST#
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
PM_THRMTRIP# 46
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
SM_RCOMP_0
AL1
SM_RCOMP_1
AM1
SM_RCOMP_2
AN1
AN15
AP15
AT28
XDP_PREQ#
AP27
XDP_TCLK
AN28
TCK
XDP_TMS
AP28
TMS
XDP_TRST#
AT27
XDP_TDI_R
AT29
TDI
XDP_TDO_R
AR27
TDO
XDP_TDI_M
AR29
XDP_TDO_M
AP29
H_DBR#_R
AN25
XDP_OBS0_R
AJ22
XDP_OBS1_R
AK22
XDP_OBS2_R
AK24
XDP_OBS3_R
AJ24
XDP_OBS4_R
AJ25
XDP_OBS5_R
AH22
XDP_OBS6_R
AK23
XDP_OBS7_R
AH23
DBR#:
SC(V1.0) P22:Connected to the DBR# pin of the Processor.50-ȍ to 5-kȍ pull-up to 3.3VS
CRB(V1.0) P11,P71:CRB uses a 1-kȍ pull-up to 3.3VS.
On the CRB this signal is ANDed with Master Reset to generate SYS_RESET.
DBR#:(Intell feedback)
Nothing wrong w/ CRB design. If you want to
connect it to PCH directly, make sure pull high
to 3.3V (S0) main power.
CLK_CPU_BCLK 10
CLK_CPU_BCLK# 10
BCLK_ITP 60
BCLK_ITP# 60
CLK_PCIE_3GPLL 9
CLK_PCIE_3GPLL# 9
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND
on Auburndale directly if motherboard
only supports discrete graphics.
DDR3_DRAMRST# 13,14
R132
R132
*12.4K/F_NC
*12.4K/F_NC
+1.1V_VTT
PM_EXTTS#0 13
PM_EXTTS#1 14
XDP_DBRESET# 7,60
XDP_OBS[0:7] 60
R135 10KR135 10K
R134 10KR134 10K
R136 *0_shor tR136 *0_short
R133 *0_shor tR133 *0_short
XDP_PRDY# 60
XDP_PREQ# 60
XDP_TCLK 60
XDP_TMS 60
XDP_TRST# 60
T19T19
T50T50
T51T51
R147 *0_shortR147 *0_short
R128 *0_shortR128 *0_short
R146 *0_shortR146 *0_short
R126 *0_shortR126 *0_short
R148 *0_shortR148 *0_short
R129 *0_shortR129 *0_short
R149 *0_shortR149 *0_short
R127 *0_shortR127 *0_short
R130 *0_shortR130 *0_short
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
12
12
JTAG MAPPING
XDP_TDI_R
XDP_TDO_M
XDP_TDI_M
XDP_TDO_R
Scan Chain
(Default)
CPU Only
GMCH Only
DG(v1.0) table 27
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R494 0R494 0
R497 *0_NCR497 *0_NC
R4960R496
0
R495 *0_NCR495 *0_NC
R498 0R498 0
STUFF -> R780, R783, R786
NO STUFF -> R781, R785
STUFF -> R780, R781
NO STUFF -> R783, R785, R786
STUFF -> R785, R786
NO STUFF -> R780, R781, R783
TRST#
SC(V1.0)P22:
should be routed as a single
daisy chain to all loads and
terminated at the end of the trace.
51 ȍ ± 5% pull down resistor.
CRB()V1.0)P11
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
AUBURNDA 1/4
AUBURNDA 1/4
AUBURNDA 1/4
FM9 3B
FM9 3B
FM9 3B
1
CRB(v0.71) P.11
XDP_TDI 60
XDP_TDO 60
XDP_TRST#
R49951R499
51
of
of
of
366Tuesday, October 06, 2009
366Tuesday, October 06, 2009
366Tuesday, October 06, 2009
5
4
3
2
1
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)
U34D
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
AB1
AC5
AC6
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
G1
G5
K2
M1
K5
K4
M4
N5
W5
R7
Y7
J6
J3
J2
J1
J5
L3
U34D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
W8
SB_CK[0]
W9
SB_CK#[0]
M3
SB_CKE[0]
V7
SB_CK[1]
V6
SB_CK#[1]
M2
SB_CKE[1]
AB8
SB_CS#[0]
AD6
SB_CS#[1]
AC7
SB_ODT[0]
AD1
SB_ODT[1]
M_B_DM0
D4
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_CLK0 14
M_B_CLK0# 14
M_B_CKE0 14
M_B_CLK1 14
M_B_CLK1# 14
M_B_CKE1 14
M_B_CS0# 14
M_B_CS1# 14
M_B_ODT0 1 4
M_B_ODT1 1 4
M_B_DM[7:0] 14
M_B_DQS#[7:0] 14
M_B_DQS[7:0] 14
M_B_A[15 :0] 14
U34C
U34C
AA6
SA_CK[0]
D D
M_A_DQ[63:0]13
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_BS013
M_A_BS113
M_A_BS213
M_A_CAS#13
M_A_RAS#13
M_A_WE #13
A10
C10
B10
D10
E10
F10
H10
G10
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
AC3
AB2
AE1
AB3
AE9
C7
D8
C6
G8
G7
J10
M6
M8
N8
U7
A7
A8
E6
F7
E9
B7
E7
K7
J8
J7
L7
L9
L6
K8
P9
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLK0 13
M_A_CLK0# 13
M_A_CKE0 13
M_A_CLK1 13
M_A_CLK1# 13
M_A_CKE1 13
M_A_CS0# 13
M_A_CS1# 13
M_A_ODT0 1 3
M_A_ODT1 1 3
M_A_DM[7:0] 13
M_A_DQS#[7:0] 13
M_A_DQS[7:0] 13
M_A_A[15:0] 13
M_B_DQ[63:0]14
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60M_A_A0
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_BS014
M_B_BS114
M_B_BS214
M_B_CAS#14
M_B_RAS#14
M_B_W E#14
Clarksfield/Auburndale
Clarksfield/Auburndale
A A
5
Channel A DQ[15,32,48,54], DM[5]
Requires minimum 12mils spacing
with all other signals, including data signals.
4
Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.
3
Clarksfield/Auburndale
Clarksfield/Auburndale
2
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
COMPUTER
AUBURNDA 2/4
AUBURNDA 2/4
AUBURNDA 2/4
FM9 3B
FM9 3B
FM9 3B
466Tuesday, October 06, 2009
466Tuesday, October 06, 2009
466Tuesday, October 06, 2009
1
of
5
U34F
CPU Core Power
+VCC_CORE
D D
C C
B B
A A
U34F
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Clarksfield/A uburndale
Clarksfield/A uburndale
1.1V RAIL POWER
1.1V RAIL POWER
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
PROC_DPRSLPVR
CPU VIDS
CPU VIDS
VTT_SELECT
VSS_SENSE_VTT
SENSE LINES
SENSE LINES
AH14
VTT0_1
AH12
VTT0_2
AH11
VTT0_3
AH10
VTT0_4
J14
VTT0_5
J13
VTT0_6
H14
VTT0_7
H12
VTT0_8
G14
VTT0_9
G13
VTT0_10
G12
VTT0_11
G11
VTT0_12
F14
VTT0_13
F13
VTT0_14
F12
VTT0_15
F11
VTT0_16
E14
VTT0_17
E12
VTT0_18
D14
VTT0_19
D13
VTT0_20
D12
VTT0_21
D11
VTT0_22
C14
VTT0_23
C13
VTT0_24
C12
VTT0_25
C11
VTT0_26
B14
VTT0_27
B12
VTT0_28
A14
VTT0_29
A13
VTT0_30
A12
VTT0_31
A11
VTT0_32
AF10
VTT0_33
AE10
VTT0_34
AC10
VTT0_35
AB10
VTT0_36
Y10
VTT0_37
W10
VTT0_38
U10
VTT0_39
T10
VTT0_40
J12
VTT0_41
J11
VTT0_42
J16
VTT0_43
J15
VTT0_44
VTT0_43,VTT0_44:
CRB(V1.0)P13
Why add 0ohm?? Is it trace width control??
VTT0_43,VTT0_44:(Intel feedback)
They are connected to hidden page for
intel validation purpose.
AN33
PSI#
VID0
AK35
VID[0]
VID1
AK33
VID[1]
VID2
AK34
VID[2]
VID3
AL35
VID[3]
VID4
AL33
VID[4]
VID5
AM33
VID[5]
VID6
AM35
VID[6]
DPRSLPVR
AM34
G15
AN35
ISENSE
AJ34
VCC_SENSE
AJ35
VSS_SENSE
B15
VTT_SENSE
TP_VSS_SENSE_VTT
A15
VSS_SENSE_VTT:
SC(V1.0)P20
Connect VSS_SENSE_VTT to GND
or can be left floating.
Note: CRB has the VSS_SENSE_VTT floating.
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)
5
C628
C628
10U
10U
C591
C591
22U
22U
4
C216
C216
10U
10U
C551
C551
22U
22U
H_PSI# 51
VID0 51
VID1 51
VID2 51
VID3 51
VID4 51
VID5 51
VID6 51
DPRSLPVR 51
H_VTTVID1 49
I_MON 51
VTT_SENSE 49
T40T40
4
+1.1V_VTT
C525
C228
C228
10U
10U
C189
C189
10U
10U
+1.1V_VTT
C525
C541
C541
10U
10U
10U
10U
+1.1V_VTT
VTT_SELECT:
High level 1.05V for Auburndale
Low level 1.1V for Clarksfield
+VCC_CORE
R446
R446
100/F
100/F
R447
R447
100/F
100/F
PROC_DPRSLPVR:
SC(V1.0)P19:
It is important to have the resistor stuffing options
in the design for the Turbo functionality.
The stuffing and no-stuffing of the resistors
will depend on the POC configuration of AUB
and CFD
CRB(V1.0)P67:
uses 1K pull-up and pull-down resistors
CRB default setting is "1"
C593
C593
C515
C515
*10U_NC
*10U_NC
10U
10U
+1.1V_VTT
C540
C540
C552
C552
22U
22U
22U
22U
C633
C633
22U
22U
C622
C622
C617
C617
22U
22U
22U
22U
VCC_SENSE & VSS_SENSE:
SC(V1.0)P19
100- ±1% pull-down to GND near processor
VCCSENSE 51
VSSSENSE 51
C514
C514
22U
22U
C592
C592
*10U_NC
*10U_NC
C590
C590
22U
22U
C242
C242
22U
22U
3
AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
U34G
U34G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
C611
C611
22U
22U
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
Clarksfield/A uburndale
Clarksfield/A uburndale
Note:
For Validating IMVP VR R814 should be STUFF
and R827 NO_STUFF
3
GRAPHICS
GRAPHICS
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
VID0
VID1
VID2
VID3
VID4
VID5
VID6
DPRSLPVR
H_PSI#
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_IMON
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
VCCPLL1
VCCPLL2
VCCPLL3
R4511KR451
1K
R452
R452
*1K_NC
*1K_NC
R4481KR448
1K
R449
R449
*1K_NC
*1K_NC
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
GFX_DPRSLPVR
GRAPHICS VIDs
GRAPHICS VIDs
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
1.1V1.8V
1.1V1.8V
R145 *1K/F_NCR145 *1K/F_NC
+1.1V_VTT
R4541KR454
R458
R458
1K
*1K_NC
*1K_NC
R455
R455
R4591KR459
*1K_NC
*1K_NC
1K
2
4
GFX_VID[0..6],GFX_VR_EN,GFX_DPRSLPVR,GFX_IMON:
Could this be left unconnected when not in use?
GFX_VID[0..6],GFX_VR_EN,GFX_DPRSLPVR,GFX_IMON:(Intel feedback)
Yes, see DG rev1.5
Pop it when Arrandale Graphics disable.
+1.5V_SUS
C169
C169
10U
10U
C603
C603
22U
22U
C2371UC237
1U
C184
C184
2.2U
2.2U
R462
R462
*1K_NC
*1K_NC
R4631KR463
1K
+
+
+
+
C518
C518
*330U_NC
*330U_NC
7343
7343
2.5
2.5
C2431UC243
1U
C646
C646
330U
330U
7343
7343
2.5
2.5
+1.1V_VTT
+1.8V_RUN
C195
C195
4.7U
4.7U
R4651KR465
1K
R466
R466
*1K_NC
*1K_NC
C1961UC196
1U
C253
C253
22U
22U
C589
C589
22U
22U
R469
R469
*1K_NC
*1K_NC
R4701KR470
1K
+VCC_CORE
C218
C218
22U
22U
C244
C244
22U
22U
C544
C544
22U
22U
C220
C220
C269
C269
10U
10U
10U
10U
C249
C249
C252
C252
10U
10U
10U
10U
+
+
C262
C262
*470U_NC
*470U_NC
Title
Title
Title
AUBURNDA 3/4
AUBURNDA 3/4
AUBURNDA 3/4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
FM9 3B
FM9 3B
FM9 3B
Date: Sheet
Date: Sheet
Date: Sheet
C2121UC212
1U
C1621UC162
1U
R460
R460
*1K_NC
*1K_NC
R4611KR461
1K
C209
C209
10U
10U
C524
C524
22U
22U
C1971UC197
1U
C1701UC170
1U
R4721KR472
1K
R473
R473
*1K_NC
*1K_NC
2
1
C511
C511
C517
C517
22U
22U
22U
22U
C202
C202
C227
C227
22U
22U
22U
22U
C267
C267
C241
C241
10U
10U
10U
10U
C221
C221
C215
C215
10U
10U
10U
10U
+
+
C37
C37
*470U_NC
*470U_NC
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
1
C238
C238
10U
10U
C211
C211
10U
10U
C512
C512
22U
22U
C208
C208
22U
22U
C621
C621
10U
10U
C263
C263
10U
10U
C543
C543
C523
C523
22U
22U
22U
22U
C624
C624
C516
C516
22U
22U
22U
22U
C627
C627
C632
C632
10U
10U
10U
10U
C264
C264
C610
C610
10U
10U
10U
10U
of
of
of
566Tuesday, October 06, 2009
566Tuesday, October 06, 2009
566Tuesday, October 06, 2009
5
4
3
2
1
AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)
U34H
U34H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
AR23
VSS7
AR20
VSS8
AR17
D D
C C
B B
VSS9
AR15
VSS10
AR12
VSS11
AR9
VSS12
AR6
VSS13
AR3
VSS14
AP20
VSS15
AP17
VSS16
AP13
VSS17
AP10
VSS18
AP7
VSS19
AP4
VSS20
AP2
VSS21
AN34
VSS22
AN31
VSS23
AN23
VSS24
AN20
VSS25
AN17
VSS26
AM29
VSS27
AM27
VSS28
AM25
VSS29
AM20
VSS30
AM17
VSS31
AM14
VSS32
AM11
VSS33
AM8
VSS34
AM5
VSS35
AM2
VSS36
AL34
VSS37
AL31
VSS38
AL23
VSS39
AL20
VSS40
AL17
VSS41
AL12
VSS42
AL9
VSS43
AL6
VSS44
AL3
VSS45
AK29
VSS46
AK27
VSS47
AK25
VSS48
AK20
VSS49
AK17
VSS50
AJ31
VSS51
AJ23
VSS52
AJ20
VSS53
AJ17
VSS54
AJ14
VSS55
AJ11
VSS56
AJ8
VSS57
AJ5
VSS58
AJ2
VSS59
AH35
VSS60
AH34
VSS61
AH33
VSS62
AH32
VSS63
AH31
VSS64
AH30
VSS65
AH29
VSS66
AH28
VSS67
AH27
VSS68
AH26
VSS69
AH20
VSS70
AH17
VSS71
AH13
VSS72
AH9
VSS73
AH6
VSS74
AH3
VSS75
AG10
VSS76
AF8
VSS77
AF4
VSS78
AF2
VSS79
AE35
VSS80
Clarksfield/Auburndale
Clarksfield/Auburndale
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
U34I
U34I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
Clarksfield/Auburndale
Clarksfield/Auburndale
VSS
VSS
NCTF
NCTF
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
+M_VREF_DQ_DIMM0
+M_VREF_DQ_DIMM1
R414 *0_shortR414 *0_short
R415 *0_shortR415 *0_short
CFG0
CFG3
CFG4
CFG7
TP_RSVD17_R
TP_RSVD18_R
U34E
U34E
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
SA_DIMM_VREF
H17
SB_DIMM_VREF
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
AM30
CFG[0]
AM28
CFG[1]
AP31
CFG[2]
AL32
CFG[3]
AL30
CFG[4]
AM31
CFG[5]
AN29
CFG[6]
AM32
CFG[7]
AK32
CFG[8]
AK31
CFG[9]
AK28
CFG[10]
AJ28
CFG[11]
AN30
CFG[12]
AN32
CFG[13]
AJ32
CFG[14]
AJ29
CFG[15]
AJ30
CFG[16]
AK30
CFG[17]
H16
RSVD_TP_86
B19
RSVD15
A19
RSVD16
A20
RSVD17
B20
RSVD18
U9
RSVD19
T9
RSVD20
AC9
RSVD21
AB9
RSVD22
C1
RSVD_NCTF_23
A3
RSVD_NCTF_24
J29
RSVD26
J28
RSVD27
A34
RSVD_NCTF_28
A33
RSVD_NCTF_29
C35
RSVD_NCTF_30
B35
RSVD_NCTF_31
Clarksfield/Auburndale
Clarksfield/Auburndale
RSVD_NCTF_37
RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD_TP_59
RSVD_TP_60
RESERVED
RESERVED
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD38
RSVD39
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD58
KEY
RSVD62
RSVD63
RSVD64
RSVD65
VSS
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
AP1
AT2
AT3
AR1
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
D15
C15
AJ15
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
RSVD64_R
RSVD65_R
Can be left NC is Intel CRM
R476
R476
implementation; ESD/DG
*0_short
*0_short
recommendation t o GND
R98 *0_shortR98 *0_short
R99 *0_shortR99 *0_short
CFG4
A A
The Clarkfield processor's PCI Express interface may
not meet PCI Express 2.0 jitter specifications. Intel
recommends placing a 3.01K +/- 5% pull down resistor to
VSS on CFG[7] pin for both rPGA and BGA components.
This pull down resistor should be removed when this
issue is fixed.
5
CFG0
CFG3
CFG4
CFG7
4
R154 *3.01K/F_NCR154 *3.01K/F_NC
R101 3.01K/FR101 3.01K/F
R155 *3.01K/F_NCR155 *3.01K/F_NC
R153 *3.01K/F_NCR153 *3.01K/F_NC
(Display Port
Presence)
CFG0
(PCI-Epress
Configuration Select)
CFG3
(PCI-Epress Static
Lane Reversal)
Disabled; No Physical Display Port
attached to Embedded Diplay Port
Single PEG
Normal Operation Lane Numbers Reversed
3
Enabled; An external Display port
device is connect ed to the Embedded
Display port
Bifurcation enabled
2
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
COMPUTER
AUBURNDA 4/4
AUBURNDA 4/4
AUBURNDA 4/4
FM9 3B
FM9 3B
FM9 3B
1
666Tuesday, Oc tober 06, 2009
666Tuesday, Oc tober 06, 2009
666Tuesday, Oc tober 06, 2009
of
of
of
10
5
4
3
2
1
IBEX PEAK-M (DMI,FDI,GPIO)
U42C
U42C
DMI_RXN03
D D
CS(V1.0) P32
PWROK and SYS_PWROK should be tied
together on the platform.MEPWROK can be connected
C C
to PCH_PWROK pin on PCH when Intel AMT
is not enabled.
B B
MEPWROK
SC(V1.0)P32:
It can be connected to PCH_PWROK pin
on PCH when Intel AMT is not enabled.
A A
DMI_RXN13
DMI_RXN23
DMI_RXN33
DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33
DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33
DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33
+1.05V_PCH
XDP_DBRESET#3,60
PCH_PWRGD29
PM_DRAM_PWRGD3
ICH_RSMRST#29
SUS_PWR_ACK29
SIO_PWRBTN#29
AC_PRESENT29
CLKRUN#
XDP_DBRESET#
PCH_PWRGD
ICH_RSMRST#
LAN_RST#
LAN_RST#
DG(V1.0) P311
If integrated LAN is not used, recommend
to connect LAN_RST# to GND via an 8.2-kȍ
to 10-kȍ pull-down resistor.
EDS(V1.0)P64
must be grounded if Intel LAN is disabled.
R545 49.9/FR545 49.9/F
R302 *0_s hortR302 *0_short
R581 *0_s hortR581 *0_short
R304 *0_s hortR304 *0_short
+3.3V_RUN
R555 10KR555 10K
R490 1KR490 1K
R582 10KR582 10K
R321 10KR321 10K
R591 10KR591 10K
5
DMI_ZCOMP
XDP_DBRESET#
SYS_PWROK
PWROK
MEPWROK
LAN_RST#
ICH_RSMRST#
PM_BATLOW#
PM_RI#
BC24
DMI0RXN
BJ22
DMI1RXN
AW20
DMI2RXN
BJ20
DMI3RXN
BD24
DMI0RXP
BG22
DMI1RXP
BA20
DMI2RXP
BG20
DMI3RXP
BE22
DMI0TXN
BF21
DMI1TXN
BD20
DMI2TXN
BE18
DMI3TXN
BD22
DMI0TXP
BH21
DMI1TXP
BC20
DMI2TXP
BD18
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
T6
SYS_RESET#
M6
SYS_PWROK
B17
PWROK
K5
MEPWROK
A10
LAN_RST#
D9
DRAMPWROK
C16
RSMRST#
M1
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
F14
RI#
IbexPeak- M_R1P0
IbexPeak- M_R1P0
PM_RI#
PCIE_WAKE#
PWROK
SC(V1.0)P32:
8.2 kȍ to 10 kȍ pull-down resistor to GND.
PWROK and SYS_PWROK should be tied together on the platform.
R326 10KR326 10K
R325 1KR325 1K
System Power Management
System Power Management
+3.3V_SUS
4
DMI
FDI
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_LAN# / GPIO29
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
BA18
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
WAKE#
SLP_S4#
SLP_S3#
SLP_M#
TP23
PMSYNCH
PM_BATLOW#
PM_BATLOW#:
EDS(V1.0)P95: 15K~40K (+3.3V_SUS)
CRB(V1.0)P25: 8.2K (+3.3V_ALW)
PM_BATLOW#:(Intel feedback)
15K ~ 40K is a simulation result,
the expected value should be 20K
internal pull high in PCH.
8.2K is external pull high.
DG(V1.0)P185:
BH17
BD16
If the LVDS interface is not implemented,
BJ16
all signals associated with the interface can
BA16
be left as No Connects. The supply pins
BE14
VccTX_LVDS and VCCA_LVD can be
BA14
connected to ground.
BC12
DG(V1.1) P83:FDI_FSYNC[0], FDI_FSYNC[1],
BB18
FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT
BF17
signals on PCH side can be left as
BC16
no connect without any power
BG16
or functional impact.
AW16
BD14
BB14
BD12
BJ14
BF13
BH13
BJ12
BG14
J12
CLKRUN#
Y1
RSV_LPCPD#
P8
ICH_SUSCLK
F3
SLP_S5#_R
E4
SLP_S4#_R
H7
SLP_S3#_R
P12
SLP_M#_R
K8
N2
BJ10
PM_SLP_LAN#_R
F6
R577 8.2K/FR577 8.2K/F
T28T28
T34T34
R307 *0_shortR307 *0_short
T70T70
T38T38
T56T56
T36T36
+3.3V_SUS
PCIE_WAKE# 28,32,41
CLKRUN# 29
11
SIO_SLP_S5# 29
SIO_SLP_S3# 29
PM_SYNC 3
5
3
DG(V1.0)P189:
If the CRT interface is not implemented,
all signals associated with the interface can
be left as No Connects. The pins
CRT_IRTN Connect this signals to GND
and DAC_IREF Connect to GND
via a 1.0 k ±0.5% pull-down resistor
R2691KR269
1K
IBEX PEAK-M (LVDS,DDI)
U42D
U42D
Y48
AB48
Y45
AB46
V48
AP39
AP41
AT43
AT42
AV53
AV51
BB47
BA52
AY48
AV47
BB48
BA50
AY49
AV48
AP48
AP47
AY53
AT49
AU52
AT53
AY51
AT48
AU50
AT51
AA52
AB53
AD53
V51
V53
Y53
Y51
AD48
AB51
T48
T47
L_BKLTEN
L_VDD_EN
L_BKLTC TL
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
IbexPeak- M_R1P0
IbexPeak- M_R1P0
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
CRT
CRT
2
BJ46
BG46
BJ48
BG48
BF45
SDVO_INTN
BH45
SDVO_INTP
T51
T53
BG44
BJ44
AU38
DDPB_HPD
BD42
DDPB_0N
BC42
DDPB_0P
BJ42
DDPB_1N
BG42
DDPB_1P
BB40
DDPB_2N
BA40
DDPB_2P
AW38
DDPB_3N
BA38
DDPB_3P
Y49
AB49
BE44
BD44
AV40
DDPC_HPD
BE40
DDPC_0N
BD40
DDPC_0P
BF41
DDPC_1N
BH41
DDPC_1P
BD38
DDPC_2N
BC38
DDPC_2P
BB36
DDPC_3N
BA36
DDPC_3P
U50
U52
BC46
BD46
AT38
DDPD_HPD
BJ40
DDPD_0N
BG40
DDPD_0P
BJ38
DDPD_1N
BG38
DDPD_1P
BF37
DDPD_2N
BH37
DDPD_2P
BE36
DDPD_3N
BD36
DDPD_3P
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
SDVO
Display port BDisplay port CDisplay port D
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
IBEX PEAK-M 2/6
IBEX PEAK-M 2/6
IBEX PEAK-M 2/6
FM9 3B
FM9 3B
FM9 3B
766Tuesday, October 06, 2009
766Tuesday, October 06, 2009
766Tuesday, October 06, 2009
of
of
1
of
5
4
3
2
1
C747
C747
*27P_NC
*27P_NC
50
50
No Reboot strap.
Low = Default.
High = No Reboot.
Res. of TDO
PCH ES1 stage : NC
PCH ES2 stage : pop
+RTC_CELL
ACZ_BIT_ CLK
ACZ_SYN C
ACZ_RS T#
ACZ_SD OUT
R5891MR589
1M
R593 20KR593 20K
C7491UC749
1U Y5
R583 20KR583 20K
C7461UC746
1U
INTVRMEN(Internal Voltage Regulator Enable) :
This signal enables the internal 1.05 V regulators.
This signal must be always pulled-up to VccRTC.
Flash Descriptor Security Override
Low = Enabled
GPIO33
High = Disabled
R315 *1K_NCR315 *1K_NC
1 2
GPIO33
(Internal 20K/F pull high to +3.3V_RUN)
Note : GPIO33 is a signal used for Flash
Descriptor Security Override/ME Debug
Mode.This signal should be only asserted
lowthrough an external pull-down in
manufacturing or debug environments
ONLY.
R1013 51R1013 51
Note : Only pop when PCH is production
stage & need "JTAG boundary Scan".
Remember to depop XDP side Res.
PCH_JTAG_TCK_BUF
4
C751 15P/50VC751 15P/50V
23
R580
R580
10M
32.768KHZY532.768KHZ
C750 15P/50VC750 15P/50V
Cap values depend on Xtal
+RTC_CELL
JTAG
Test Pads are need to put on
the same side of mother board.
R592 330KR592 330K
ICH_AZ_CODEC_SDIN039
KB_LED_DET36
10M
4 1
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BIT_ CLK
ACZ_SYN C
T55T55
T57T57
T58T58
T59T59
T60T60
SPI_CLK30
SPI_CS0#30
SPI_SI30
SPI_SO30
SPKR
ACZ_RS T#
ACZ_SD OUT
GPIO33
PCH_JTAG_TCK_BUF
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#
T52T52
3
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_SI
SPI_SO
SPKR39
IBEX PEAK-M (HDA,JTAG,SATA)
U42A
U42A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
TRST#
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IbexPeak-M_R1 P0
IbexPeak-M_R1 P0
RTCIHDA
RTCIHDA
SPI JTAG
SPI JTAG
FWH4 / LFRAME#
LDRQ1# / GPIO23
LPC
LPC
SATA
SATA
SATA0GP / GPIO21
SATA1GP / GPIO19
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED#
D33
B33
C32
A32
C34
A34
F34
AB9
AK7
AK6
AK11
AK9
AH6
AH5
AH9
AH8
AF11
AF9
AF7
SATA port 2/3 are not support in HM55 .
AF6
They are only in PM 55
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
AF15
SATA_ACT#
T3
R273 10KR273 10K
Y9
R556 10KR556 10K
V1
2
SATA_COMP
1 2
1 2
R266 37.4/FR266 37.4/F
R568 100KR568 100K
+3.3V_RUN
LPC_LAD0 29,32
LPC_LAD1 29,32
LPC_LAD2 29,32
LPC_LAD3 29,32
LPC_LFRAME# 29,32
IRQ_S ERIRQ 29
SATA_RX0- 35
SATA_RX0+ 35
SATA_TX0- 35
SATA_TX0+ 35
SATA_RX1- 35
SATA_RX1+ 35
SATA_TX1- 35
SATA_TX1+ 35
SATA_RX4- 33
SATA_RX4+ 33
SATA_TX4- 33
SATA_TX4+ 33
+1.05V_PCH
+3.3V_RUN
SATA_ACT# 29
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet
Date: Sheet
SATA HDD
SATA ODD
Distance between the PCH and
cap on the "P" signal should be
identical distace between the
PCH and cap on the "N" signal
for the same pair.
E-SATA
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
IBEX PEAK-M 1/6
IBEX PEAK-M 1/6
IBEX PEAK-M 1/6
FM9 3B
FM9 3B
FM9 3B
1
of
of
866Tuesday, October 06, 2009
866Tuesday, October 06, 2009
866Tuesday, October 06, 2009
D D
R1008
R1008
*20K_NC
*20K_NC
R1017
R1017
*10K_NC
*10K_NC
R587 33R587 33
R586 33R586 33
R313 33R313 33
R585 33R585 33
SPKR
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#
NC all Res. when
PCH is
production stage.
ICH_AZ_CODEC_BITCLK39
C C
ICH_AZ_CODEC_SYNC39
ICH_AZ_CODEC_RST#29,39
ICH_AZ_CODEC_SDOUT39
Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.
+3.3V_RUN
B B
A A
+3.3V_SUS
R1005
R1005
*200_NC
*200_NC
R1014
R1014
*100_NC
*100_NC
1 2
R284 *1K_NCR284 *1K_NC
Res. of TDI near PCH
R1006
R1006
*200_NC
*200_NC
R1015
R1015
*100_NC
*100_NC
R1007
R1007
*200_NC
*200_NC
R1016
R1016
*100_NC
*100_NC
SPKR
5
5
4
3
2
1
IBEX PEAK-M (PCI,USB,NVRAM)
Place TX DC blocking caps close PCH.
U42E
U42E
H40
AD0
N34
AD1
C44
AD2
A38
AD3
C36
AD4
J34
AD5
A40
AD6
D45
D D
PCI_PIRQA#
T35T35
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
T62T62
C C
USB_MCARD1_DET#32
GNT3#10
PCH_IRQH_GPIO235
BT_DET#32
PCIRST#:
DG(V1.0) P277
Can be left unconnected.
PAR:
SC(V1.0) P36
Can be left unconnected
if not using PCI.
PME:
DG(V1.0) P277
Can be left unconnected.
CLK_LPC_DEBUG32
B B
CLK_PCI_850229
CLKOUT_PCI[0..4]:
22 ohm series resistor is recommend
(single & double load) on PDG v1.1
Reserve capacitor pads for
improving WWAN.
CLK_LPC_DEBUG
CLK_PCI_8502
Non-iAMT
C768 0.047U
C768 0.047U
A A
PCI_PLTRST#
0214
R566 22/FR566 22/F
R277 22/FR277 22/F
CLK_PCI_FB C LK_PCI_FB_C
R564 22/FR564 22/F
50
50
C738 *27P_NC
C738 *27P_NC
50
50
C437 *27P_NC
C437 *27P_NC
Add Buffers as needed for
Loading and fanout concerns.
+3.3V_SUS
5
U43
U43
2
10
10
1
TC7SZ32FU(T5L,F,T)
TC7SZ32FU(T5L,F,T)
T61T61
T63T63
T32T32
T37T37
T54T54
T71T71
T33T33
T27T27
RSV_SMBALERT#
RSV_ICH_CL_RST1#
ICH_SMBCLK
ICH_SMBDATA
SMB_CLK_ME0
SMB_DATA_ME0
SMB_CLK_ME1
SMB_DATA_ME1
LPD_SPI_INTR#
PEG_CLKREQ#
4
PLTRST# 3,16,26,28,29,31,32,41
5
PCI_REQ0#
REQ1#
SB_WW AN_PCIE_RST#
USB_MCARD1_DET#
PCI_GNT0#
GNT#1
GNT#2
PCH_IRQH_GPIO2
SB_WLAN_PCIE_RST #
BT_DET#
PCH_IRQH_GPIO5
PCI_RST#
PCI_SERR#
PCI_PERR#
PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#
PCI_PLOCK#
PCI_STOP#
PCI_TRDY#
PME#
PCI_PLTRST#
CLK_LPC_DEBUG_C
CLK_PCI_8502_C
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
J50
G42
H47
G34
G38
H51
B37
A44
F51
A46
B45
M53
F48
K45
F36
H53
B41
K53
A36
A48
K6
E44
E50
A42
H44
F46
C46
D49
D41
C48
M7
D5
N52
P53
P46
P51
P48
IbexPeak-M_R1P0
IbexPeak-M_R1P0
+3.3V_SUS
R59010K R59010K
R29310K R29310K
R3202.2K R3202.2K
R3222.2K R3222.2K
R5792.2K R5792.2K
R3102.2K R3102.2K
R6002.2K R6002.2K
R6012.2K R6012.2K
R28110K R28110K
R57310K R57310K
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#
STOP#
TRDY#
PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NVRAM
NVRAM
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
PCI
PCI
USB
USB
BT_DET#
PCH_IRQH_GPIO2
SB_WW AN_PCIE_RST#
SB_WLAN_PCIE_RST #
OC7#
OC5#
OC4#
OC3#
+3.3V_SUS
PCH_IRQH_GPIO5
PCI_REQ0#
PCI_PIRQB#
USB_MCARD1_DET#
+3.3V_RUN
PCI_STOP#
PCI_PIRQA#
PCI_PIRQC#
PCI_IRDY#
+3.3V_RUN
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_WR#0_RE#
NV_WR#1_RE#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC6# / GPIO10
OC7# / GPIO14
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
NV_WE#_CK0
NV_WE#_CK1
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC5# / GPIO9
RP9
RP9
6
7
8
9
10
10P8R-8.2K
10P8R-8.2K
RP10
RP10
6
7
8
9
10
10P8R-8.2K
10P8R-8.2K
RP8
RP8
6
7
8
9
10
10P8R-8.2K
10P8R-8.2K
4
AY9
BD1
AP15
BD8
AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
BD3
AY6
AU2
AV7
AY8
AY5
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
B25
D25
N16
J16
F16
L16
E14
G16
F12
T15
NV_ALE 10
NV_CLE 10
ICH_USBP0- 33
ICH_USBP0+ 33
ICH_USBP1- 33
ICH_USBP1+ 33
ICH_USBP2- 34
ICH_USBP2+ 34
ICH_USBP4- 32
ICH_USBP4+ 32
ICH_USBP5- 31
ICH_USBP5+ 31
USB port 6/7 are not support in HM55 .
They are only in PM 55
ICH_USBP8- 32
ICH_USBP8+ 32
ICH_USBP9- 28
ICH_USBP9+ 28
ICH_USBP11- 40
ICH_USBP11+ 40
ICH_USBP12- 37
ICH_USBP12+ 37
USB_BIAS
R584 22.6/FR584 22.6/F
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#
OC0#~OC7#:
DG(V1.0)P214
Pin Default Port Mapping
OC0# Port0,Port1
OC1# Port2,Port3
R588 8.2KR588 8.2K
R578 8.2KR578 8.2K
R576 8.2KR576 8.2K
R570 8.2KR570 8.2K
5
4
3
2
1
5
4
3
2
1
5
4
3
2
1
OC2#
OC6#
OC1#
OC0#
PCI_TRDY#
PCI_FRAME#
REQ1#
PCI_PIRQD#
PCI_SERR#
PCI_PERR#
PCI_PLOCK#
PCI_DEVSEL#
OC0# 33
OC1# 34
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_RUN
Min iWWAN
MiniWLAN
Express Card
Card Reader
Giga Bit LOM
Left Side pair Top
Left Side pair bottom
Right Side pair top (Cable)
Mini Card (WLAN)
Mini Card (WWAN)
Mini Card (WPAN)
Express Card
Camera
Touch Screen Module
Note : place these
resistors near to PCIe
Slots
Express Card
Giga Bit LOM
PCIE Clock Request
+3.3V_SUS
+3.3V_RUN
PCIECLKRQ{0,3,4,5,6,7}# should have a
10K pull-up to +V3.3A.PCIECLKRQ{1,2}
should have a 10K pull-up to +3.3S
Boot BIOS Strap
PCI_GNT0# GNT#1
00
0
1
11
PCIE_RX6-/GLAN_RX-41
PCIE_RX6+/GLAN_RX+41
MiniWLAN
Card Reader
Min iWWAN
R324 10KR324 10K
R288 10KR288 10K
R309 10KR309 10K
R287 10KR287 10K
R278 10KR278 10K
R272 10KR272 10K
R290 10KR290 10K
R294 *1K_NCR294 *1K_NC
R291 *1K_NCR291 *1K_NC
1
0
3
PCIE_RX1-31
PCIE_RX1+31
PCIE_TX1-31
PCIE_TX1+31
PCIE_RX2-32
PCIE_RX2+32
PCIE_TX2-32
PCIE_TX2+32
PCIE_RX4-28
PCIE_RX4+28
PCIE_TX4-28
PCIE_TX4+28
PCIE_RX5-26
PCIE_RX5+26
PCIE_TX5-26
PCIE_TX5+26
PCIE_TX6-/GLAN_T X-41
PCIE_TX6+/GLAN_T X+41
PCI-E port 7/8 are not support in HM55 .
They are only in PM 55
CLK_PCIE_ MINI1#32
CLK_PCIE_ MINI132
MINI1CLK_REQ#32
CLK_PCIE_CARD_READER#26
CLK_PCIE_CARD_READER26
CLK_PCIE_REQ2#26
CLK_PCIE_ MINI2#31
CLK_PCIE_ MINI231
CLK_PCIE_EXPCARD#28
CLK_PCIE_EXPCARD28
CARD_CLK_REQ#28
CLK_PCIE_LOM#41
CLK_PCIE_LOM41
LOM_CLK_REQ#41
CLK_PCIE_REQ3#
CARD_CLK_REQ#_R
CLK_PCIE_REQ5#
CLK_PEG0_REQ#
LOM_CLK_REQ#_R
MINI1CLK_REQ#_R
CLK_PCIE_REQ2#_R
PCI_GNT0#
GNT#1
Boot BIOS Location
LPC
PCI
Reserved (NAND)
SPI
C721 0.1UC721 0.1U
C717 0.1UC717 0.1U
C374 0.1UC374 0.1U
C375 0.1UC375 0.1U
C376 0.1UC376 0.1U
C377 0.1UC377 0.1U
C396 0.1UC396 0.1U
C389 0.1UC389 0.1U
C379 0.1UC379 0.1U
C378 0.1UC378 0.1U
R275 *0_shortR275 *0_short
R292 *0_shortR292 *0_short
R295 0R295 0
R276 *0_shortR276 *0_short
IBEX PEAK-M (PCI-E,SMBUS,CLK)
U42B
U42B
BG30
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN4_C
PCIE_TXP4_C
PCIE_TXN5_C
PCIE_TXP5_C
PCIE_TXN6_C
PCIE_TXP6_C
CLK_PEG0_REQ#
MINI1CLK_REQ#_R
CLK_PCIE_REQ2#_R
CLK_PCIE_REQ3#
CARD_CLK_REQ#_R
CLK_PCIE_REQ5#
LOM_CLK_REQ#_R
PERN1
BJ30
PERP1
BF29
PETN1
BH29
PETP1
AW30
PERN2
BA30
PERP2
BC30
PETN2
BD30
PETP2
AU30
PERN3
AT30
PERP3
AU32
PETN3
AV32
PETP3
BA32
PERN4
BB32
PERP4
BD32
PETN4
BE32
PETP4
BF33
PERN5
BH33
PERP5
BG32
PETN5
BJ32
PETP5
BA34
PERN6
AW34
PERP6
BC34
PETN6
BD34
PETP6
AT34
PERN7
AU34
PERP7
AU36
PETN7
AV36
PETP7
BG34
PERN8
BJ34
PERP8
BG36
PETN8
BJ36
PETP8
AK48
CLKOUT_PCIE0N
AK47
CLKOUT_PCIE0P
P9
PCIECLKRQ0# / GPIO73
AM43
CLKOUT_PCIE1N
AM45
CLKOUT_PCIE1P
U4
PCIECLKRQ1# / GPIO18
AM47
CLKOUT_PCIE2N
AM48
CLKOUT_PCIE2P
N4
PCIECLKRQ2# / GPIO20
AH42
CLKOUT_PCIE3N
AH41
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
AM51
CLKOUT_PCIE4N
AM53
CLKOUT_PCIE4P
M9
PCIECLKRQ4# / GPIO26
AJ50
CLKOUT_PCIE5N
AJ52
CLKOUT_PCIE5P
H6
PCIECLKRQ5# / GPIO44
AK53
CLKOUT_PEG_B_N
AK51
CLKOUT_PEG_B_P
P13
PEG_B_CLK RQ# / GPIO56
IbexPeak-M_R1P0
IbexPeak-M_R1P0
CLKOUT_PEG_A_P/N,CLKOUT_PEG_B_P/N,
CLKOUT_DMI_P/N,support GEN-1 and GEN-2
2
PCI-E*
PCI-E*
SMBALERT# / GPIO11
SML0ALERT # / GPIO60
SML1ALERT # / GPIO74
SMBus
SMBus
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
Controller
Controller
PEG_A_CLKR Q# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
PEG
PEG
CLKOUT_ DP_N / CLKOUT_ BCLK1_N
CLKOUT_D P_P / CLKOUT_ BCLK1_P
From CLK BUFFER
From CLK BUFFER
Clock Flex
Clock Flex
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / C KSSCD_P
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFL EX0 / GPIO64
CLKOUTFL EX1 / GPIO65
CLKOUTFL EX2 / GPIO66
CLKOUTFL EX3 / GPIO67
RSV_SMBALERT#
B9
ICH_SMBCLK
H14
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DAT A1
CL_RST1#
REFCLK14IN
XTAL25_IN
ICH_SMBDATA
C8
RSV_ICH_CL_RST1#
J14
SMB_CLK_ME0
C6
SMB_DATA_ME0
G8
LPD_SPI_INTR#
M14
SMB_CLK_ME1
E10
SMB_DATA_ME1
G12
T13
T11
T9
PEG_CLKREQ#
H1
AD43
AD45
AN4
AN2
AT1
AT3
AW24
BA24
AP3
AP1
F18
E18
AH13
AH12
P41
CLK_PCI_FB
J42
AH51
AH53
AF38
T45
P43
T42
N50
SMB_CLK_ME1
SMB_DATA_ME1
Title
Title
Title
IBEX PEAK-M 3/6
IBEX PEAK-M 3/6
IBEX PEAK-M 3/6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
FM9 3B
FM9 3B
FM9 3B
Date: Sheet
Date: Sheet
Date: Sheet
R1031 *0_shortR1031 *0_short
XCLK_RCOMP
CLK_FLEX0
CLK_FLEX1
CLK_FLEX2
CLK_FLEX3
CLKOUTFLEX3:
EDS(V1.0) :support 48MHz
33MHz and 14.31818MHz.
CLKOUTFLEX[0..3]:
PDG v1.1: 22 ohm series resistor is
recommend (PCI & non PCI routing,
single & double load)
+3.3V_SUS
+3.3V_SUS
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
ICH_SMBCLK 32,41,60
ICH_SMBDATA 32,41, 60
T30T30
T31T31
SML0CLK/SML0DATA:
DG(V1.1) P255: The 82577 SMBus
signals
(SMB_DATA and SMB_CLK) cannot be
connected to any other
devices other than the PCH.
Connect the SMB_DATA and SMB_CLK
pins
to the PCH SML0DATA and SML0CLK
pins,
respectively.
CLK_PCIE_VGA# 1 6
CLK_PCIE_VGA 16
CLK_PCIE_3GPLL# 3
CLK_PCIE_3GPLL 3
CLK_BUF_PCIE_3GPLL# 15
CLK_BUF_PCIE_3GPLL 15
CLK_BUF_BCLK_N 15
CLK_BUF_BCLK_P 15
CLK_BUF_DREFCLK# 15
CLK_BUF_DREFCLK 15
CLK_BUF_DREFSSCLK# 15
CLK_BUF_DREFSSCLK 15
CLK_ICH_14M 15
CLKIN_PCILOOPBACK:
PDG (V1.1): 22 ohm series resistor
is recommend
0214
R259 90.9/FR259 90.9/F
+1.05V_PCH
T26T26
T29T29
T25T25
T53T53
0214
Q52
Q52
2
2N7002W-7-F
2N7002W-7-F
31
Q53
Q53
2
2N7002W-7-F
2N7002W-7-F
31
1
SMBCLK1 29
SMBDAT1 29
966Tuesday, October 06, 2009
966Tuesday, October 06, 2009
966Tuesday, October 06, 2009
of
of
of
5
4
3
2
1
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
U42F
S_GPIO
SIO_EXT_SMI#29
SIO_EXT_SCI#29
TEST_WOOFER_EN39
PCIE_MCARD2_DET#31
USB_MCARD2_DET#31
WLAN_ RADIO_DIS#32
+3.3V_SUS
SIO_EXT_WAKE#29
R602 *0_NCR602 *0_NC
R319 *0_shortR319 *0_short
R255 *10K_NCR255 *10K_NC
R571 *0_shortR571 *0_short
11
R256 *0_shortR256 *0_short
R263 *0_shortR263 *0_short
14
D D
LAN_PCIE_PWR_CTRL29,41
PCIE_MCARD1_DET#32
GPIO24 register not cleared by CF9h reset event.
GPIO27 reserve for internal VR.
BT_RADIO_DIS#32
C C
WWAN_RADIO_DIS#31
CRIT_TEMP_ REP#29
VGA Strap
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
RSV_WOL_EN
LAN_PHY_PWR_CTRL
TEST_WOOFER_EN
SATA4GP
PCIE_MCARD1_DET#_R
PCIE_MCARD2_DET#
GPIO27
TP_PCH_GPIO28
USB_MCARD2_DET#
GPIO35
SATA2GP
SATA3GP
WLAN_ RADIO_DIS#
CRB_SV_DET
GPIO45
GPIO46
SV_SET_UP
SATA5GP
VGA_TYPE
18
M92-XT
B B
Park
R329
R329
*10K_NC
*10K_NC
R364
R364
*10K_NC
*10K_NC
VGA_TYPE
U42F
Y3
BMBUSY# / GPIO0
C38
TACH1 / GPIO1
D37
TACH2 / GPIO6
J32
TACH3 / GPIO7
F10
GPIO8
K9
LAN_PHY_PWR_CTRL / GPIO12
T7
GPIO15
AA2
SATA4GP / GPIO16
F38
TACH0 / GPIO17
Y7
SCLOCK / GPIO22
H10
GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
V6
SATACLKREQ# / GPIO35
AB7
SATA2GP / GPIO36
AB13
SATA3GP / GPIO37
V3
SLOAD / GPIO38
P3
SDATAOUT0 / GPIO39
H3
PCIECLKRQ6# / GPIO45
F1
PCIECLKRQ7# / GPIO46
AB6
SDATAOUT1 / GPIO48
AA4
SATA5GP / GPIO49
F8
GPIO57
A4
VSS_NCTF_1
A49
VSS_NCTF_2
A5
VSS_NCTF_3
A50
VSS_NCTF_4
A52
VSS_NCTF_5
A53
VSS_NCTF_6
B2
VSS_NCTF_7
B4
VSS_NCTF_8
B52
VSS_NCTF_9
B53
VSS_NCTF_10
BE1
VSS_NCTF_11
BE53
VSS_NCTF_12
BF1
VSS_NCTF_13
BF53
VSS_NCTF_14
BH1
VSS_NCTF_15
BH2
VSS_NCTF_16
BH52
VSS_NCTF_17
BH53
VSS_NCTF_18
BJ1
VSS_NCTF_19
BJ2
VSS_NCTF_20
BJ4
VSS_NCTF_21
BJ49
VSS_NCTF_22
BJ5
VSS_NCTF_23
BJ50
VSS_NCTF_24
BJ52
VSS_NCTF_25
BJ53
VSS_NCTF_26
D1
VSS_NCTF_27
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1
VSS_NCTF_30
E53
VSS_NCTF_31
IbexPeak-M_R1P0
IbexPeak-M_R1P0
MISC
MISC
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
GPIO
GPIO
CPU
CPU
NCTF
NCTF
RSVD
RSVD
CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
A20GATE
PECI
RCIN#
PROCPWRGD
THRMTRIP#
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
NC_2
NC_3
NC_4
NC_5
INIT3_3V#
TP24
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
AH45
AH46
AF48
AF47
U2
AM3
AM1
BG10
T1
BE10
BD10
BA22
AW22
BB22
AY45
AY46
AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39
P6
C10
PCH_THRMTRIP#_R
SIO_A20GATE 29
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
H_PECI 3
SIO_RCIN# 29
H_PWRGOOD 3,60
R235 56/FR235 56/F
(Both these should be close to PC H)
+1.1V_VTT
R234
R234
56/F
56/F
TEST_WOOFER_EN
RSV_WOL_EN
TP_PCH_GPIO28
GPIO45
GPIO46
LAN_PHY_PWR_CTRL
SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
PCIE_MCARD2_DET#
PCIE_MCARD1_DET#_R
WLAN_ RADIO_DIS#
CRB_SV_DET
SIO_RCIN#
H_THERM 3
SIO_A20GATE
SATA2GP
SATA5GP
SATA3GP
SATA4GP
USB_MCARD2_DET#
DMI Termination Voltage
NV_CLE
NV_ALE9
NV_CLE9
Set to Vcc when LOW
Set to Vcc/2 when HIGH
R553 *1K_NCR553 *1K_NC
R246 *1K_NCR246 *1K_NC
Danbury Technology Enabled
NV_ALE
High = Enable
Low = Disable
R271 1KR271 1K
R331 10KR331 10K
R274 10KR274 10K
R574 10KR574 10K
R575 10KR575 10K
R603 10KR603 10K
R317 10KR317 10K
R316 10KR316 10K
R289 10KR289 10K
R258 10KR258 10K
R318 10KR318 10K
R557 10KR557 10K
R569 10KR569 10K
R565 10KR565 10K
R563 10KR563 10K
R254 10KR254 10K
R264 10KR264 10K
R268 10KR268 10K
R554 10KR554 10K
R303 10KR303 10K
+3.3V_SUS
+3.3V_RUN
+NVRAM_VCCQ
+3.3V_RUN
R267 10KR267 10K
A A
R572 *1K_NCR572 *1K_NC
A16 swap override Strap/Top-Block
Swap Override jumper
GNT3#
GPIO35
Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default
5
GNT3# 9
R1009 *1K_NCR1009 *1K_NC
RSV_WOL_EN
Integrated Clock Chip Enable
(Reserve to validate for future platforms)
RSV_WOL_EN
4
Enable when sampled low
Disable when sampled high
S_GPIO
SV_SET_UP
R270 10KR270 10K
R257 10KR257 10K
SV_SET_UP 1-X High = Strong (Default)
3
BMBUSY#:(Intel feedback)
Follow CRB checklist, 1K is
for intel BIOS validation purpose.
BMBUSY#:
If not used, require a weak pull-up
(8.2- Kȍ to 10 kȍ) to Vcc3_3.
CRB(V1.0)P28: it has 1K PU and
100 ohm on this net for validation purpose.
2
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
COMPUTER
IBEX PEAK-M 4/6
IBEX PEAK-M 4/6
IBEX PEAK-M 4/6
FM9 3B
FM9 3B
FM9 3B
10 66Wednesday, October 07, 2009
10 66Wednesday, October 07, 2009
10 66Wednesday, October 07, 2009
of
of
1
of
5
U42G
IBEX PEAK-M (POWER)
D D
VCCAPLLEXP = 100mA max
VCCAPLLEXP:
This pin can be left as no connect in
On-Die VR enabled mode (default).
+1.05V_PCH
+1.05V_PCH
VCCIO = 3.208A max
C C
L64 *1uH_NCL64 *1uH_NC
C716
C716
10U
10U
10
10
805
805
+1.05V_PCH
+1.05V_PCH
C7151UC715
1U
+3.3V_RUN
VCCCORE=1.524A max
C4241UC424
C412
C412
10U
10U
1U
10
10
805
805
+1.05V_LAN_VCCAPLL_EXP
C718
C718
*10U_NC
*10U_NC
C3921UC392
1U
C3911UC391
1U
C4001UC400
1U
VCC3_3 = 0.357A max
C408
C408
0.1U
0.1U
VCCFDIPLL = 100mA max
+1.05V_PCH
B B
A A
L63 *1uH_NCL63 *1uH_NC
5
VCCVRM = 0.035A max
+1.5VS_1.8VS
+1.05V_VCCFDIPLL
+1.05V_PCH
C720
C720
*10U_NC
*10U_NC
VCCIO = 3.208A max
+1.05V_PCH
U42G
AB24
VCCCORE[1]
AB26
VCCCORE[2]
AB28
VCCCORE[3]
AD26
VCCCORE[4]
AD28
VCCCORE[5]
AF26
VCCCORE[6]
AF28
VCCCORE[7]
AF30
VCCCORE[8]
AF31
VCCCORE[9]
AH26
VCCCORE[10]
AH28
VCCCORE[11]
AH30
VCCCORE[12]
AH31
VCCCORE[13]
AJ30
VCCCORE[14]
AJ31
VCCCORE[15]
AK24
VCCIO[24]
BJ24
VCCAPLLEXP
AN20
VCCIO[25]
AN22
VCCIO[26]
AN23
VCCIO[27]
AN24
VCCIO[28]
AN26
VCCIO[29]
AN28
VCCIO[30]
BJ26
VCCIO[31]
BJ28
VCCIO[32]
AT26
VCCIO[33]
AT28
VCCIO[34]
AU26
VCCIO[35]
AU28
VCCIO[36]
AV26
VCCIO[37]
AV28
VCCIO[38]
AW26
VCCIO[39]
AW28
VCCIO[40]
BA26
VCCIO[41]
BA28
VCCIO[42]
BB26
VCCIO[43]
BB28
VCCIO[44]
BC26
VCCIO[45]
BC28
VCCIO[46]
BD26
VCCIO[47]
BD28
VCCIO[48]
BE26
VCCIO[49]
BE28
VCCIO[50]
BG26
VCCIO[51]
BG28
VCCIO[52]
BH27
VCCIO[53]
AN30
VCCIO[54]
AN31
VCCIO[55]
AN35
VCC3_3[1]
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO[1]
IbexPeak-M_R1 P0
IbexPeak-M_R1 P0
+1.8V_RUN
+3.3V_RUN
L36 10uHL36 10uH
L32 10uHL32 10uH
R228 *0_NCR228 *0_NC
R230 *0_NCR230 *0_NC
R229 0R229 0
R243 0R243 0
R238 *0_NCR238 *0_NC
+1.05V_PCH
PCH EDS(V1.0) P84
+NVRAM_VCCQ:
1.8 V supply for Dual Channel NAND interface.
This power is supplied by core
well. If unused, this pin should
be connected to Vcc3_3.
4
POWER
POWER
VCC CORE
VCC CORE
PCI E*
PCI E*
+1.1V_VCCADPLLA
+
+
C398
C398
220U
220U
3528
3528
+1.1V_VCCADPLLB
+
+
C388
C388
220U
220U
3528
3528
4
L66
+VCCA_DAC_1_2
AE50
VCCADAC[1]
AE52
VCCADAC[2]
AF53
VSSA_DAC[1]
VSSA_DAC[2]
VCCALVDS
VSSA_LVDS
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
VCCVRM[2]
VCCDMI[1]
VCCDMI[2]
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
AF51
AH38
AH39
AP43
AP45
AT46
AT45
AB34
AB35
AD35
AT24
AT16
AU16
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
AM8
AM9
AP11
AP9
CRTLVDS
CRTLVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
HVCMOS
HVCMOS
DMI
DMI
NAND / SPI
NAND / SPI
FDI
FDI
VCCME3_3:
EDS(V1.0)P84:supply for the Intel Management Engine.This is a separate power plane
that may or may not be powered in S3–S5 states.
This plane must be on in S0
and other times the Intel Management Engine is used.
+1.5VS_1.8VS+1.5V_RUN
+NVRAM_ VCCQ
C3971UC397
1U
C3871UC387
1U
C732
C732
0.01U
0.01U
VCC3_3 = 0.357A max
+3.3V_RUN
C431
C431
0.1U
0.1U
VCCVRM = 0.035A max
+1.5VS_1.8VS
VCCDMI = 0.061A max
C3731UC373
1U
VCCPNAND = 0.156A max
+NVRAM_ VCCQ
C410
C410
0.1U
0.1U
VCCME3_3 = 0.085A max
+3.3V_RUN
C407
C407
0.1U
0.1U
HCB1608KF-181T15
HCB1608KF-181T15
C730
C730
C731
C731
0.1U
0.1U
*10U_NC
*10U_NC
6.3
6.3
+1.05V_PCH
R232 0R232 0
R231 *0_NCR231 *0_NC
L66
L65 *10uH_NCL65 *10uH_NC
VCCME = 1.998A max
+1.05V_PCH
+1.05V_PCH
+1.1V_ VTT
+1.05V_PCH
3
VCCADAC = 100mA max
+3.3V_RUN
VCCACLK = 100mA max
+1.1V_LAN_VCCA_CLK
C4151UC415
1U
C416
C416
C436
C436
22U
22U
22U
22U
C439 0.1UC439 0.1U
+1.5VS_1.8VS
VCCADPLLA = 0.072A max
+1.1V_ VCCADPLL A
VCCADPLLB = 0.073A max
+1.1V_ VCCADPLL B
VCCIO = 3.208A max
+1.05V_PCH
C4221UC422
1U
C442 0.1UC442 0.1U
C443 0.1UC443 0.1U
VCCSUS3_3 = 0.163A max
+3.3V_SUS
VCC3_3 = 0.357A max
+3.3V_RUN
V_CPU>1mA
+1.1V_ VTT
C394
C394
4.7U
4.7U
+RTC_CELL
VCCRTC = 2mA max
3
C726
C726
*10U_NC
*10U_NC
DCPSUSBYP
C438
C438
0.1U
0.1U
C4341UC434
C4231UC423
1U
C405
C405
0.1U
0.1U
C7451UC745
1U
1U
DCPRTC
C4261UC426
1U
DCPSST
DCPSUS
C448
C448
0.1U
0.1U
C430
C430
0.1U
0.1U
C404
C404
0.1U
0.1U
C741
C741
0.1U
0.1U
C724
C724
*1U_NC
*1U_NC
C752
C752
0.1U
0.1U
AP51
AP53
AF23
AF24
AD38
AD39
AD41
AF43
AF41
AF42
AU24
BB51
BB53
BD51
BD53
AH23
AJ35
AH35
AF34
AH34
AF32
AT18
AU18
U42J
U42J
VCCACLK[1]
VCCACLK[2]
VCCLAN[1]
VCCLAN[2]
Y20
DCPSUSBYP
VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
V39
VCCME[7]
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
VCCME[12]
V9
DCPRTC
VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[2]
VCCIO[3]
VCCIO[4]
V12
DCPSST
Y22
DCPSUS
P18
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
U20
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
V_CPU_IO[1]
V_CPU_IO[2]
A12
VCCRTC
IbexPeak-M_R1 P0
IbexPeak-M_R1 P0
2
POWER
POWER
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
USB
USB
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCSUS3_3[28]
Clock and Miscellaneous
Clock and Miscellaneous
PCI/GPIO/LPC
PCI/GPIO/LPC
VCCSATAPLL[1]
VCCSATAPLL[2]
SATA
SATA
PCI/GPIO/LPC
PCI/GPIO/LPC
CPU
CPU
RTC
RTC
HDA
HDA
2
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[56]
V5REF_SUS
V5REF
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCIO[9]
VCCVRM[4]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
V24
V26
Y24
Y26
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
U23
V23
F24
K49
J38
L38
M36
N36
P36
U35
AD13
AK3
AK1
AH22
AT20
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
AA34
Y34
Y35
AA35
L30
C4331UC433
1U
C451
C451
0.1U
0.1U
+1.05V_PCH
+V5REF_SUS
C7561UC756
1U
+V5REF
C4461UC446
1U
C445
C445
0.1U
0.1U
C421
C421
0.1U
0.1U
+1.05V_VCCSATAPLL
C418
C418
C413
C413
*1U_NC
*1U_NC
*10U_NC
*10U_NC
VCCVRM = 0.035A max
+1.5VS_1.8VS
+1.05V_PCH
R285 *0_shortR285 *0_short
C4471UC447
1U
1
VCCIO = 3.208A max
+1.05V_PCH
VCCSUS3_3 = 0.163A max
+3.3V_SUS
C444
C444
0.1U
0.1U
VCCIO = 3.208A max
R596 100R596 100
1 2
D24 SDM10K45-7-FD24 SDM10K45-7-F
R286 100R286 100
D16 SDM10K45-7-FD16 SDM10K45-7-F
21
1 2
21
+3.3V_RUN
L35 *10uH_NCL35 *10uH_NC
+5V_SUS
V5REF_SUS>1mA
+3.3V_SUS
V5REF>1mA
+5V_RUN
+3.3V_RUN
VCC3_3 = 0.357A max
+1.05V_PCH
VCCIO = 3.208A max
+1.05V_PCH
C4251UC425
1U
VCCME = 1.998A max
VCCSUSHDA = 6mA max
+3.3V_SUS
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
COMPUTER
IBEX PEAK-M 5/6
IBEX PEAK-M 5/6
IBEX PEAK-M 5/6
FM9 3B
FM9 3B
FM9 3B
1
11 66Tuesday, October 06, 2009
11 66Tuesday, October 06, 2009
11 66Tuesday, October 06, 2009
of
of
of
5
IBEX PEAK-M (GND)
D D
U42H
U42H
AB16
VSS[0]
AA19
VSS[1]
AA20
VSS[2]
AA22
VSS[3]
AM19
VSS[4]
AA24
VSS[5]
AA26
VSS[6]
AA28
VSS[7]
AA30
VSS[8]
AA31
VSS[9]
AA32
VSS[10]
AB11
VSS[11]
AB15
VSS[12]
AB23
VSS[13]
AB30
VSS[14]
AB31
VSS[15]
AB32
VSS[16]
AB39
VSS[17]
AB43
VSS[18]
AB47
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AF12
AH49
AF35
AP13
AN34
AF45
AF46
AF49
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AJ19
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AK12
AM41
AN19
AK26
AK22
AK23
AK28
AB5
AB8
AC2
AD7
AE2
AE4
Y13
AU4
AF5
AF8
AG2
AH7
AT5
AJ2
AJ4
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
IbexPeak- M_R1P0
IbexPeak- M_R1P0
C C
B B
A A
5
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
4
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
4
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
G10
G14
G18
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BB5
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G2
3
U42I
U42I
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
IbexPeak- M_R1P0
IbexPeak- M_R1P0
3
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
2
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
COMPUTER
IBEX PEAK-M 6/6
IBEX PEAK-M 6/6
IBEX PEAK-M 6/6
FM9 3B
FM9 3B
FM9 3B
1
of
of
of
12 66Tuesday, October 06, 2009
12 66Tuesday, October 06, 2009
12 66Tuesday, October 06, 2009
1
5
4
3
2
1
JDIM1A
M_A_A[15:0]4
D D
M_A_BS04
M_A_BS14
M_A_BS24
M_A_CS0#4
M_A_CS1#4
M_A_CLK04
M_A_CLK0#4
M_A_CLK14
M_A_CLK1#4
M_A_CKE04
M_A_CKE14
M_A_CAS#4
M_A_RAS#4
R177 10KR177 10K
R178 10KR178 10K
C C
B B
M_A_WE#4
WLAN_SMBCLK14,28,31,32,35
WLAN_SMBDATA14,28,31,32,35
M_A_ODT04
M_A_ODT14
M_A_DM[7:0]4
M_A_DQS[7:0]4
M_A_DQS#[7:0]4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
DIMM0_SA0
DIMM0_SA1
WLAN_SMBCLK
WLAN_SMBDATA
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
JDIM1A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
AS0A626-UARN-7F
AS0A626-UARN-7F
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
158
(204P)
(204P)
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ[63:0] 4
PM_EXTTS#03
DDR3_DRAMRST#3,14
+SMDDR_VREF_DIMM0
+1.5V_SUS +DDR_VTTREF
R1003
R1003
1K/F
1K/F
12
R1004
R1004
1K/F
1K/F
+3.3V_RUN
+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM0
R1025
R1025
*0_NC
*0_NC
C1002
C1002
0.1U
0.1U
16
16
+1.5V_SUS
PM_EXTTS#0
JDIM1B
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
AS0A626-UARN-7F
AS0A626-UARN-7F
(204P)
(204P)
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
G1
G1
G2
G2
+3.3V_RUN
R510 *10K/F_NCR510 *10K/F_NC
Intel is requesting that customers implement
all methods (M1 and M2 and M3
described below) to generate and control
Reference voltage for Data/Strobe inputs
(VREFDQ) on Clarksfield based platforms.
for fine tuning of the VREFDQ levels to
optimize the voltage and timing margins.
M1:Fixed voltage resistor divider or
DDR Voltage Regulator drives the Vref
M2:A set of Digital potentiometers
and op amps are added on the motherboard (one pair
for each channel). This circuit is controlled by
SMBUS (SMB_CLK & SMB_DATA) on PCH.
M3:Intel investigating future processor
VREF_DQ generation to replace M1 and M2. This
would require routing processor signal balls
J17 and H17 to SO-DIMM connectors
directly.
+0.75V_DDR_VTT
11
PM_EXTTS#0
+1.5V_SUS
C619
C619
10U
10U
C229
C229
10U
10U
C190
C190
10U
10U
A A
+3.3V_RUN
C323
C323
2.2U/6.3V/0603
2.2U/6.3V/0603
Place these Caps near So-Dimm1.
C583
C327
C327
0.1U
0.1U
C583
10U
10U
5
C623
C623
10U
10U
C239
C239
10U
10U
+0.75V_DDR_VTT
C3391UC339
1U
C607
C607
0.1U
0.1U
C171
C600
C600
0.1U
0.1U
C171
0.1U
0.1U
C250
C250
0.1U
0.1U R26
C3331UC333
1U
C251
C251
0.1U
0.1U
C3401UC340
1U
+SMDDR_VREF_DIMM0
+
+
C278
C278
C615
C615
330U
330U
0.1U
0.1U
7343
7343
2.5
2.5
C3341UC334
1U
4
C274
C274
2.2U/6.3V/0603
2.2U/6.3V/0603
C354
C354
10U
10U
10
10
805
805
C346
C346
10U
10U
10
10
805
805
C270
C270
0.1U
0.1U
C273
C273
2.2U/6.3V/0603
2.2U/6.3V/0603
C344
C344
10U
10U
10
10
805
805
for ARD CPU pop M1, NC M3 component.
for CFD CPU pop M3, NC M1 component
+1.5V_SUS
R26
1K/F
1K/F
R20
R20
1K/F
1K/F
+DDR_VTTREF
R1018
R1018
*0_NC
*0_NC
12
C27
C27
0.1U
0.1U
16
16
3
R25 *0_NCR25 *0_NC
M1 VREF M3 VREF
+SMDDR_VREF_DQ0 +M_VREF_DQ_DIMM0
+SMDDR_VREF_DQ0
R24 0R24 0
VREF_DQ
R25 R24 R204 R1018
M1
Stuff
M2
X
M3
X
XXXXX
Stuff
Stuff
2
(+DDR_VTTREF)
X
X
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
COMPUTER
DDR3 DIMM-0
DDR3 DIMM-0
DDR3 DIMM-0
FM9 3B
FM9 3B
FM9 3B
13 66Tuesday, October 06, 2009
13 66Tuesday, October 06, 2009
13 66Tuesday, October 06, 2009
1
5
4
3
2
1
+3.3V_RUN
+1.5V_SUS
PM_EXTTS#1
JDIM2B
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
AS0A626-U2RN-7F
AS0A626-U2RN-7F
(204P)
(204P)
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
G1
G1
G2
G2
+0.75V_DDR_VTT
+3.3V_RUN
R175
R175
*10K/F_NC
*10K/F_NC
12
PM_EXTTS#1
JDIM2A
M_B_A[15:0]4
D D
M_B_BS04
M_B_BS14
M_B_BS24
M_B_CS0#4
M_B_CS1#4
M_B_CLK04
M_B_CLK0#4
M_B_CLK14
M_B_CLK1#4
M_B_CKE04
M_B_CKE14
M_B_CAS#4
M_B_RAS#4
R161 10KR161 10K
R160 10KR160 10K
+3.3V_RUN
C C
B B
M_B_WE#4
WLAN_SMBCLK13,28,31,32,35
WLAN_SMBDATA13,28,31,32,35
M_B_ODT04
M_B_ODT14
M_B_DM[7:0]4
M_B_DQS[7:0]4
M_B_DQS#[7:0]4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
DIMM1_SA0
DIMM1_SA1
WLAN_SMBCLK
WLAN_SMBDATA
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
JDIM2A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
AS0A626-U2RN-7F
AS0A626-U2RN-7F
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
158
(204P)
(204P)
DQ46
160
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ[63:0] 4
PM_EXTTS#13
DDR3_DRAMRST#3,13
+SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM1
+1.5V_SUS +DDR_VTTREF
R1028
R1028
1K/F
1K/F
12
R1026
R1026
1K/F
1K/F
+SMDDR_VREF_DIMM1
R1027
R1027
*0_NC
*0_NC
C1003
C1003
0.1U
0.1U
16
16
+1.5V_SUS
C240
C240
10U
10U
C247
C247
10U
10U
C236
C236
10U
10U
A A
+3.3V_RUN
C324
C324
2.2U/6.3V/0603
2.2U/6.3V/0603
Place these Caps near So-Dimm2.
C246
C330
C330
0.1U
0.1U
C246
10U
10U
C223
C223
10U
10U
+0.75V_DDR_VTT
5
C143
C143
10U
10U
C3361UC336
1U
C217
C217
0.1U
0.1U
C210
C210
0.1U
0.1U
C3261UC326
1U
C203
C203
0.1U
0.1U
C213
C213
0.1U
0.1U
C219
C219
0.1U
0.1U
C3251UC325
1U
+SMDDR_VREF_DIMM1
+
+
C565
C565
C272
C272
330U
330U
7343
7343
0.1U
0.1U
2.5
2.5
C3411UC341
1U
4
C318
C318
10U
10U
10
10
805
805
C276
C276
2.2U/6.3V/0603
2.2U/6.3V/0603
C271
C271
0.1U
0.1U
C347
C347
10U
10U
10
10
805
805
C275
C275
2.2U/6.3V/0603
2.2U/6.3V/0603
C317
C317
10U
10U
10
10
805
805
for ARD CPU pop M1, NC M3 component.
for CFD CPU pop M3, NC M1 component
+1.5V_SUS +DDR_VTTREF
R1022
12
R1022
*0_NC
*0_NC
C1001
C1001
0.1U
0.1U
16
16
3
R1020
R1020
1K/F
1K/F
R1021
R1021
1K/F
1K/F
R1019 *0_NCR1019 *0_NC
M1 VREF
VREF_DQ
M1
M2
M3
R28 0R28 0
R1019XR28XR202
Stuff
X
X
X
X
Stuff
M3 VREF
+M_VREF_DQ_DIMM1+SMDDR_VREF_DQ1 +SMDDR_VREF_DQ1
R1022
(+DDR_VTTREF)
X
Stuff
X
2
QUANTA
QUANTA
QUANTA
X
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
COMPUTER
COMPUTER
COMPUTER
DDR3 DIMM-1
DDR3 DIMM-1
DDR3 DIMM-1
FM9 3B
FM9 3B
FM9 3B
1
14 66Tuesday, October 06, 2009
14 66Tuesday, October 06, 2009
14 66Tuesday, October 06, 2009
5
D D
4
3
2
1
Realtek: 0.1uFx6pcs, 22uFx1pcs
+3.3V_RUN
L40 BLM21PG600SN1D
L40 BLM21PG600SN1D
805
805
C C
CK_PWRGD_R42
CLK_ICH_14M9
IDT: 0.1uFx5pcs, 10uFx1pcs
C469
C469
C472
C472
10U
10U
0.1uF near the every power pin.
+3.3V_RUN
CLK_ICH_14M
Place the 33 ohm
resistors close to the CK 505
0.1U
0.1U
C461
C461
0.1U
0.1U
R335 10KR335 10K
R299 33R299 33
C465
C465
0.1U
0.1U
U27
U27
C460
C460
0.1U
0.1U
+3.3V_CLK_VDD
+VDDIO_CLK
CPU_SEL
XTAL_OUT
XTAL_IN
EC_SMBDAT0
EC_SMBCLK0
1
VDD_USB
5
VDD_LCD
17
VDD_SRC
24
VDD_CPU
29
VDD_REF
15
VDD_SRC_IO
18
VDD_CPU_IO
9
VSS_SATA
2
VSS_USB
8
VSS_LCD
12
VSS_SRC
21
VSS_CPU
26
VSS_REF
16
CPU_STOP#
25
CK_PWRGD/PD#_3.3
30
REF_0/CPU_SEL
27
XOUT
28
XIN
31
SDATA
32
SCLK
SLG8SP585VTR
SLG8SP585VTR
CK505
CK505
QFN32
QFN32
CPU-0
CPU-0#
CPU-1
CPU-1#
DOT96T_LPR
DOT96C_LPR
SRC-1
SRC-1#
SATA
SATA#
27MHz_nonSS
27MHz_SS
GND
23
22
20
19
3
4
13
14
10
11
6
7
33
40mil
C453
C453
0.1U
0.1U
EC_SMBDAT038
EC_SMBCLK038
Place within 0.5" of CLKGEN
CLK_BUF_BCLK_P
CLK_BUF_BCLK_N
CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#
CLK_BUF_PCIE_3GPLL
CLK_BUF_PCIE_3GPLL#
CLK_BUF_DREFSSCLK
CLK_BUF_DREFSSCLK#
CLK_VGA_27M_R
CLK_VGA_27M_SS_R
R314 33R314 33
R327 33R327 33
Realtek: 0.1uFx3pcs, 22uFx1pcs
CLK_BUF_BCLK_P 9
CLK_BUF_BCLK_N 9
CLK_BUF_DREFCLK 9
CLK_BUF_DREFCLK# 9
CLK_BUF_PCIE_3GPLL 9
CLK_BUF_PCIE_3GPLL# 9
CLK_BUF_DREFSSCLK 9
CLK_BUF_DREFSSCLK# 9
CLK_VGA_27M 17
CLK_VGA_27M_SS 17
IDT: 0.1uFx2pcs, 10uFx1pcs
+3.3V_RUN
Add capacitor pads for improving WWAN.
C441
C441
*27P_NC
*27P_NC
50
50
CLK_ICH_14M
B B
XTAL_IN XTAL_OUT
C454
C454
33P
33P
50
50
Y3
Y3
21
14.318MHZ
14.318MHZ
C455
C455
33P
33P
1 2
50
50
R346 *0_NCR346 *0_NC
+1.05V_PCH
R353 *0_shortR353 *0_short
SLG,IDT: +1.05V
Realtek: +3.3V
L41 BLM21PG600SN1D
L41 BLM21PG600SN1D
805
805
HP: 10u x2pcs
Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.
C478
C478
10U
10U
40mil
C475
C475
0.1U
0.1U
+VDDIO_CLK
C467
C467
0.1U
0.1U
+VDDIO_CLK:
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
+3.3V_RUN
R300
R300
*4.7K_NC
*4.7K_NC
A A
1 2
CPU_SEL
R301
R301
4.7K
4.7K
1 2
5
C452
C452
*10P/50V_NC
*10P/50V_NC
EMI Capacitor
PIN 30 CPU_0 CPU_1
0(default)
1(0.7V-1.5V)
133MHz
100MHz 100MHz
133MHz
4
CPU_SEL:
SLG date sheet (V0.2) P15:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
Realtek date sheet(V1.2) P11:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
IDT date sheet(V0.7) P10:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
3
2
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
COMPUTER
Clock Generator
Clock Generator
Clock Generator
FM9 3B
FM9 3B
FM9 3B
of
of
of
15 66Tuesday, October 06, 2009
15 66Tuesday, October 06, 2009
15 66Tuesday, October 06, 2009
1
5
PCIE_MTX_GRX_N[0..15]3 PCIE_MRX_GTX_N[0..15]3
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
D D
C C
B B
100 MHz (+/-300 ppm) input frequency, 0-0.7 V single-ended swing.
clock must be provided less than 400ns
after CLKREQ# is asserted
CLK_PCIE_VGA9
CLK_PCIE_VGA#9
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15
AF30
AE31
AE29
AD28
AD30
AC31
AC29
AB28
AB30
AA31
AA29
W31
W29
U31
U29
N29
M28
M30
AK30
AK32
Y28
Y30
V28
V30
T28
T30
R31
R29
P28
P30
N31
L31
L29
K30
4
U32A
U32A
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
PART 1 OF 10
PART 1 OF 10
AH30
PCIE_TX0P
AG31
PCIE_TX0N
AG29
PCIE_TX1P
AF28
PCIE_TX1N
AF27
PCIE_TX2P
AF26
PCIE_TX2N
AD27
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
AD26
AC25
AB25
Y23
Y24
AB27
AB26
Y27
Y26
W24
W23
V27
U26
U24
U23
T26
T27
T24
T23
P27
P26
P24
P23
M27
N26
AA22
Y22
PCI-EXPRESS INTERFACE
PCI-EXPRESS INTERFACE
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_CALRN
PCIE_CALRP
PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N15
PCIE_CALRN
PCIE_CALRP
3
(1.1V)
+PCIE_VDDC
R622.0K R622.0K
R511.27K R511.27K
2
PCIE_MRX_GTX_P[0..15]3PCIE_MTX_GRX_P[0..15]3
PCIE_MRX_GTX_P0 PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
C870.1U 16C870.1U 16
C940.1U 16C940.1U 16
C920.1U 16C920.1U 16
C880.1U 16C880.1U 16
C1000.1U 16C1000.1U 16
C1030.1U 16C1030.1U 16
C1080.1U 16C1080.1U 16
C1150.1U 16C1150.1U 16
C1310.1U 16C1310.1U 16
C1480.1U 16C1480.1U 16
C1360.1U 16C1360.1U 16
C1670.1U 16C1670.1U 16
C1400.1U 16C1400.1U 16
C1800.1U 16C1800.1U 16
C1500.1U 16C1500.1U 16
C1680.1U 16C1680.1U 16
C900.1U 16C900.1U 16
C960.1U 16C960.1U 16
C950.1U 16C950.1U 16
C910.1U 16C910.1U 16
C1050.1U 16C1050.1U 16
C1070.1U 16C1070.1U 16
C1140.1U 16C1140.1U 16
C1280.1U 16C1280.1U 16
C1180.1U 16C1180.1U 16
C1590.1U 16C1590.1U 16
C1420.1U 16C1420.1U 16
C1810.1U 16C1810.1U 16
C1470.1U 16C1470.1U 16
C1660.1U 16C1660.1U 16
C1600.1U 16C1600.1U 16
C1820.1U 16C1820.1U 16
PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_N15
1
AL27
PLTRST#3,9,26,28,29,31,32,41
A A
5
PERSTB
PARK-S3
PARK-S3
4
M92-S2 XT AJ072800T04 100-CG1675(216-0728004)
M92-S2 AJ072800T03 100-CG1643(216-0728003)
3
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
COMPUTER
VGA-M92-XT (PCIe)
VGA-M92-XT (PCIe)
VGA-M92-XT (PCIe)
FM9 3B
FM9 3B
FM9 3B
1
16 66Tuesday, Oc tober 06, 2009
16 66Tuesday, Oc tober 06, 2009
16 66Tuesday, Oc tober 06, 2009
of
of
of
5
MEMORY APERTURE SIZE SELECT
MEMORY
SIZE
128MB
256MB
64MB
512MB
D D
+3.3V_DELAY
GPIO Straps
table
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
HSYNC
C C
(AH26)
VSYNC
(AJ27)
+3.3V_DELAY
R430 *10K_NCR430 *10K_NC
R426 *10K_NCR426 *10K_NC
R61 *10K_NCR61 *10K_NC
R429 *10K_NCR429 *10K_NC
R428 *10K_NCR428 *10K_NC
R68 *10K_NCR68 *10K_NC
R55 10KR55 10K
R438 *10K_NCR438 *10K_NC
R432 10KR432 10K
R384 10KR384 10K
R383 *10K_NCR383 *10K_NC
R1001 10KR1001 10K
R1002 10KR1002 10K
R440 10KR440 10K
B B
A A
DAC1_VGAVSYNC
DAC1_VGAHSYNC
0\0
0\1
1\0
1\1
+1.8V_RUN_GFX
Memory Straps
800MHz
512MB(64M*16) Samsung
800MHz
512MB(64M*16) Hynix
Park XT S3:IC CTRL(631)100-CK3374(216-0774009)FCBGA Non-Consign QCI PN : AJ077400T04
800MHz
1GB(128M*16) Samsung
800MHz
1GB(128M*16) Hynix
CFG2
CFG3
GPIO9 GPIO13 GPIO12 GPIO11
0
001
010
100
R436 10KR436 10K
1 2
R435 *10K_NCR435 *10K_NC
1 2
R437 *10K_NCR437 *10K_NC
1 2
DESCRIPTION OF DEFAULT SETTINGS
GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enab le)
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enab le)
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled (Default setting for Desktop)
GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable)
0 : Default. (Driver Controlled Gen2)1 : Strap Controlled Gen2
ATI reserved configuration straps.
ATI reserved configuration straps.
GPIO_5_AC_BATT
0 : Battery saving mode = 0.0 V
1 : AC (Performance mode) = 3.3 V
ATI Internal use only
00: No Audio function
01: Audio for DisplayPort only
10: Audio for DisplayPort only and HDMI if dongle is detected.
11: Audio for both DisplayPort and HDMI.
HDMI must only be enabled on systems that are legally
entitled. it is the responsibillity of the system
designer to ensure that the system is entitled
to support this feature
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
HD Audio straps
No audio function
Audio for DisplayPort only
Audio for DisplayPort and HDMI if dongle is detected
Audio for both DisplayPort and HDMI
R56 10KR56 10K
1 2
R422 *10K_NCR422 *10K_NC
1 2
R419 *10K_NCR419 *10K_NC
1 2
RAM_TYPE
_CFG2
CFG0
CFG1
00
RAM_CFG0
RAM_CFG1
RAM_CFG2
FM9
setting
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
HDMI_HD_EN
TEMP_ FAIL
GFX_CLKREQ#
VGAVSYNC
VGAHSYNC
DAC1_VGAVSYNC
DAC1_VGAHSYNC
TEMP_ FAIL
010
15
RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2
RAM_TYPE
RAM_TYPE
_CFG0
_CFG1
001
Quanta PN
(QuantaBuy)
AKD5LGGT502
AKD5LZGTW00
111
101
+3.3V_DELAY +3.3V_RUN
10
0
0
0
0
0
0
0
11
OSC_SPREAD
CLK_VGA_27M_SS15
GPIO26_CLK
10
CLK_VGA_27M15
OSC_OUT
12
Spread Spectrum
If U4, the discrete spread spectrum chip
is not used, then pop R48 in order to
pull-down BXTALOUT for EMI reasons.
R393 *10K_NCR393 *10K_NC
OSC_OUT
R411 *0_NCR411 *0_NC
1 2
OSC_SPREAD
Quanta PN
(WinBuy)
AKD5LGGT505
AKD5LZGTW03
AKD5MGGT501
from CLK Gen
NC List:
R4,R392,R404,Y4,
R394, C534, C535,
R477, R88, R80
POP R45,R410
R417=100/F
101
100
5
4
R32 *0_short
R32 *0_short
603
603
GPU 27 MHz CLK source
from Crystal
NC List:
R410,R45
Pop List
R4,R392,R404,
R394,C534,C535,Y4
R477,R88,R80
R417=0 ohm
R408 *0_NCR408 *0_NC
1 2
1 2
1 2
R4 0R4 0
R417 0R417 0
R410 *120/F_NCR410 *120/F_NC
Y4
27MHZY427MHZ
R394 1MR394 1M
12
C535
C535
27P
27P
50
50
U31
U31
1
XIN/CLKIN
2
VSS
3
SO
4
SSCLK
*P1819GF-08SR_NC
*P1819GF-08SR_NC
R416 *0_NCR416 *0_NC
21
XOUT
VDD
PD#
REFCLK
1 2
12
R406
R406
*1M_NC
*1M_NC
C534
C534
27P
27P
50
50
R390
R390
*10K_NC
*10K_NC
R45 *0_NCR45 *0_NC
1 2
1 2
R404 0R404 0
1 2
R392 0R392 0
+3.3V_RUN
8
7
6
5
CLK_VGA_27M_SSIN_R
R391
R391
*10K_NC
*10K_NC
S0
-1.75% (DOWN) 0
Vendor PN 31 Level ASS'
K4W1G1646E-HC12
H5TQ1G63BFR-12C
31FM9MB0000_CF
31FM9MB0040_AD
31FM9MB0010_CF
31FM9MB0030_AD
QCI PN : AJ077400T05Park XT S3:IC CTRL(631)100-CK3374(216-0774009)FCBGA WIN BSQ
31FM9MB0080_CF
K4W2G1646B-HC12
4
31FM9MB0060_AD
31FM9MB0070_CF
31FM9MB0050_AD
R46 *221/F_NCR46 *221/F_NC
+3VL
C531
C531
12
*10U_NC
*10U_NC
805
805
10
10
12
R409
R409
*10K_NC
*10K_NC
3
U32B
U32B
R431 0R431 0
R423 0R423 0
R427 0R427 0
R433 *0_NCR433 *0_NC
GPIO26_CLK
R477 10KR477 10K
12
1 2
R396 249/FR396 249/F
C527 0.1UC527 0.1U
1 2
R1034 0R1034 0
+3.3V_DELAY
R50
R50
10K
10K
TEST_EN19
AF24 is TESTEN on both
M92S2 and ParkS3.
Implement 10K ohm PU
and PD for both and
connected to K7 pin
1 2
1 2
1 2
RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
HDMI_HD_EN
RAM_CFG0
RAM_CFG1
RAM_CFG2
CLK_VGA_27M_SSIN_R
1 2
TEMP_ FAIL
GFX_CLKREQ#
R439 10KR439 10K
HPD1
1 2
R1011 10KR1011 10K
1 2
R395 *0_shortR395 *0_short
R88 10KR88 10K
R42 10KR42 10K
1
For Park S3:
Install All components in this Box
R431,R423,R427,L52,C545,L23,C111
For M92-S2: DO NOT Install any Component
in this Box.
+1.8V_RUN_GFX +1.8V_RUN_GFX
L52 BLM15BD121SN1DL52 BLM15BD121SN1D
+PCIE_VDDC
L23 BLM15BD121SN1DL23 BLM15BD121SN1D
XTALIN 25
L54
L54
12
*BLM11A05S_NC
*BLM11A05S_NC
C542
C542
*0.1U_NC
*0.1U_NC
10
10
+3.3V_RUN
+1.8V_RUN_GFX_R
C5451UC545
1U
C1111UC111
1U
+1.8V_RUN_GFX_R
GFX_CORE_CNTRL250
GFX_CORE_CNTRL050
GFX_CORE_CNTRL150XTALOUT 21
10
PANEL_BKEN29
THERMAL_INT#19
+3.3V_DELAY
+1.8V_RUN_GFX
For M92: No stuff R1011
For Park: Stuff R1011
1
R64 10KR64 10K
ENVDD24
BIA_PWM24
BB_ENA18
R382 499/FR382 499/F
13
3
T45 PADT45 PAD
T46 PADT46 PAD
T8 PADT8 PAD
T10 PADT10 PAD
T49 PADT49 PAD
T13 PADT13 PAD
T5 PADT5 PAD
T44 PADT44 PAD
T41 PADT41 PAD
T43 PADT43 PAD
T2 PADT2 PAD
T14 PADT14 PAD
T11 PADT11 PAD
T3 PADT3 PAD
12
12
VREFG
XO_IN2
XO_IN
AC10
AB13
AD10
AC14
AC16
AB22
AC22
AB16
AB12
AB11
AF24
U1
AC7
Y2
U5
AA1
Y4
Y7
V2
Y8
V4
AB7
W1
AB8
W3
AB9
W5
AC6
W6
AD7
AA3
AC8
AA5
AE8
AA6
AE9
AB4
AD9
AB2
AC5
U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
L6
L5
L3
L1
K4
W8
W9
W7
N10
L9
N9
PART 2 OF 10
PART 2 OF 10
DVP PORT DAC1
DVP PORT DAC1
DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
I/O
I/O
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
HPD1
VREFG
RESERVED
RESERVED
NC_PWRGOOD
RSVD#8
RSVD#9
NC#1
NC#2
RSVD#3
RSVD#2
RSVD#1
TESTEN
PARK-S3
PARK-S3
2
AM26
R
AK26
RB
AL25
G
AJ25
GB
AH24
B
AG25
BB
AH26
HSYNC
AJ27
VSYNC
AG24
AVDD
AE22
AVSSQ
AE23
VDD1DI
AD23
VSS1DI
AD22
RSET
DAC2
DAC2
AM12
R2
AK12
R2B
AL11
G2
AJ11
G2B
AK10
B2
AL9
B2B
AL13
H2SYNC
AJ13
V2SYNC
AH12
C
AM10
Y
AJ9
COMP
AE20
A2VDD
AE17
A2VDDQ
AE19
A2VSSQ
Keep A2VSSQ away from noisy ground.
AD19
VDD2DI
AC19
VSS2DI
AG13
R2SET
2
DAC1_VGAHSYNC
DAC1_VGAVSYNC
RSET
R49 499RR49 499R
C548
C548
0.1U
0.1U
+VDD2DI
R2SET
R401 715R401 715
C101
C101
0.1U
0.1U
C112
C112
*0.1U_NC
*0.1U_NC
VGA_RED
VGA_GRN
VGA_BLU
+A2VDDQ
C528
C528
0.1U
0.1U
AVDD=70mA max
+1.8V_RUN_GFX
VDD1DI=45mA max
VGA_RED 25
VGA_GRN 25
VGA_BLU 25
VGAHSYNC
VGAVSYNC
+A2VDD
C547
C547
0.1U
0.1U
Place very close to ASIC balls.
VGAHSYNC 25
VGAVSYNC 25
C5221UC522
1U
1
DIS only
HPD1
VGA_BLU
VGA_GRN
VGA_RED
R399
R399
R398
R398
R400
R400
150/F
150/F
R425
R425
10K
10K
2
Q60
Q60
+3.3V_DELAY
Layout Note:
Place 150 ohm
termination resistors
close to ATI CHIP.
+3.3V_DELAY
R424
R424
10K
10K
2
Q59
Q59
1 3
DTC114TUAT106
DTC114TUAT106
12
150/F
150/F
150/F
150/F
1 3
MMST3904-7-F
MMST3904-7-F
A2VDD=130mA max
L48 BLM15BD121SN1DL48 BLM15BD121SN1D
+1.8V_RUN_GFX
A2VDDQ=1.5mA max
+1.8V_RUN_GFX
VDD2DI=50mA max
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
COMPUTER
Title
Title
Title
VGA-M92-XT (PCIe)
VGA-M92-XT (PCIe)
VGA-M92-XT (PCIe)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
FM9 3B
FM9 3B
FM9 3B
Date: Sheet
Date: Sheet
Date: Sheet of
1
R420
R420
100K
100K
17 66Tuesday, October 06, 2009
17 66Tuesday, October 06, 2009
17 66Tuesday, October 06, 2009
HDMI_DET 24
of
of
+1.5V_RUN
C173
C173
0.01U
0.01U
D D
C C
B B
+VCC_GFX_CORE
R10120R1012
1 2
0
BB_ENA17
A A
5
layout note: close to VDDR1#[1:17]
C204
C207
C207
0.01U
0.01U
C2011UC201
1U
C254
C254
10U
10U
+1.5V_RUN
C204
0.01U
0.01U
C1851UC185
1U
C255
C255
10U
10U
+1.8V_RUN_GFX
For M92-S2:No stuff R53
Stuff R57,R54,R66
Park:No stuff R57,R54,R66
Stuff R53
C192
C192
C198
C198
0.01U
0.01U
0.1U
0.1U
C1991UC199
1U
+1.5V_RUN
C158
C158
10U
10U
BLM15BD121SN1D
BLM15BD121SN1D
C2001UC200
C1791UC179
1U
1U
L17
L17
+3.3V_DELAY
+1.8V_RUN_GFX
VDDR4#[1..4] & VDDR5#[1..4]=340mA max
L56 *BLM15BD121SN1D_NCL56 *BLM15BD121SN1D_NC
C188
C188
0.1U
0.1U
C186
C186
0.1U
0.1U
VDD_CT#[1..4]=110mA max
C46
C46
10U
10U
VDDR3#[1..4]=50mA max
C137
C137
10U
10U
2
For PARK:No stuff L56,C609,C608
For M92: Stuff L56,C609,C608
+BBP
Q18
Q18
3
12
C152
C152
*1U_NC
*1U_NC
402
402
6.3
6.3
R67
R67
*10K_NC
*10K_NC
2
1
*SI2301BDS-T-GE3_NC
*SI2301BDS-T-GE3_NC
2
31
Q19
Q19
*2N7002W-7-F_NC
*2N7002W-7-F_NC
+1.8V_RUN_GFX
For PARK: Stuff R1012
No stuff C152,Q18,Q20,R63,Q19,R67
For M92: Stuff C152,Q18,Q20,R63,Q19,R67
No stuff R1012
3 1
2
C49
C49
0.1U
0.1U
C113
C113
10U
10U
C1301UC130
1U
C609
C609
*1U_NC
*1U_NC
Q20
Q20
*2N7002W-7-F_NC
*2N7002W-7-F_NC
1 2
R63 100KR63 100K
C5561UC556
1U
2
C205
C205
0.1U
0.1U
4
VDDR1#[1..17]=2A max
C193
C193
0.1U
0.1U
+1.5V_RUN
+VDD_CT
C721UC72
C581UC58
1U
C577
C577
0.1U
0.1U
C83
C83
1U
0.1U
0.1U
C1251UC125
1U
R53 150/FR53 150/F
2
C120
C120
C1461UC146
0.1U
0.1U
1U
+VDDRH1
C608
C608
*1U_NC
*1U_NC
(0.9~1.2V)
+VCC_GFX_CORE
+5V_RUN
U32D
12
R57 *0_NCR57 *0_NC
1 2
R54 *0_NCR54 *0_NC
1 2
R66 *0_NCR66 *0_NC
1 2
AA20
AA21
AB20
AB21
AA17
AA18
AB17
AB18
AA11
AA12
U32D
H13
VDDR1#1
H16
VDDR1#2
H19
VDDR1#3
J10
VDDR1#4
J23
VDDR1#5
J24
VDDR1#6
J9
VDDR1#7
K10
VDDR1#8
K23
VDDR1#9
K24
VDDR1#10
K9
VDDR1#11
L11
VDDR1#12
L12
VDDR1#13
L13
VDDR1#14
L20
VDDR1#15
L21
VDDR1#16
L22
VDDR1#17
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
VDDR4#1
VDDR4#2
Y11
VDDR4#3
Y12
VDDR4#4
U11
VDDR5#1
U12
VDDR5#2
V11
VDDR5#3
V12
VDDR5#4
L17
VDDRHA
L16
VSSRHA
PARK-S3
PARK-S3
PART 4 OF 10
PART 4 OF 10
POWER
POWER
layout note: close to VDDC#[1:25]
C1411UC141
C1781UC178
1U
1U
C1101UC110
C1531UC153
1U
1U
C138
C138
10U
10U
C1091UC109
1U
(0.9~1.2V)
+VCC_GFX_CORE
C116
C116
10U
10U
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
C1221UC122
1U
C1211UC121
1U
C117
C117
10U
10U
C1331UC133
1U
C1451UC145
1U
3
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
AA15
M11
M12
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20
V21
Y13
Y16
Y18
Y21
M13
M15
M16
M17
M18
M20
M21
N20
PCIE_VDDR#[1..8]=400mA max
C991UC99
1U
(0.9~1.2V)
+VCC_GFX_CORE
C172
C172
0.1U
0.1U
DDCI=2A max
+VDDCI
(0.9~1.2V)
(0.9~1.2V)
+VCC_GFX_CORE
C1541UC154
1U
C1241UC124
C1391UC139
1U
1U
C119
C119
C1351UC135
C132
1U
+BBP
C132
0.01U
0.01U
C731UC73
1U
0.1U
0.1U
C851UC85
1U
VDDC#[2..3]=120mA max
C1631UC163
1U
C1341UC134
1U
2
+1.8V_RUN_GFX
C102
C102
10U
10U
PCIE_VDDC#[1..12]=2A max
C591UC59
C1761UC176
1U
1U
U32E
U32E
AA27
PCIE_VSS#1
AB24
PCIE_VSS#2
AB32
PCIE_VSS#3
AC24
PCIE_VSS#4
AC26
PCIE_VSS#5
AC27
PCIE_VSS#6
AD25
PCIE_VSS#7
AD32
PCIE_VSS#8
AE27
PCIE_VSS#9
AF32
PCIE_VSS#10
AG27
PCIE_VSS#11
AH32
PCIE_VSS#12
K28
PCIE_VSS#13
K32
PCIE_VSS#14
L27
PCIE_VSS#15
M32
PCIE_VSS#16
N25
PCIE_VSS#17
N27
PCIE_VSS#18
P25
PCIE_VSS#19
P32
PCIE_VSS#20
R27
PCIE_VSS#21
T25
PCIE_VSS#22
T32
PCIE_VSS#23
U25
PCIE_VSS#24
U27
PCIE_VSS#25
V32
PCIE_VSS#26
W25
PCIE_VSS#27
W26
PCIE_VSS#28
W27
PCIE_VSS#29
Y25
PCIE_VSS#30
Y32
PCIE_VSS#31
A3
GND#1
A30
GND#2
AA13
GND#3
AA16
GND#4
AB10
GND#5
AB15
GND#6
AB6
GND#7
AC9
GND#8
AD6
GND#9
AD8
GND#10
AE7
GND#11
AG12
GND#12
AH10
GND#13
AH28
GND#14
B10
GND#15
B12
GND#16
B14
GND#17
B16
GND#18
B18
GND#19
B20
GND#20
B22
GND#21
B24
GND#22
B26
GND#23
B6
GND#24
B8
GND#25
C1
GND#26
C32
GND#27
E28
GND#28
F10
GND#29
F12
GND#30
F14
GND#31
F16
GND#32
PARK-S3
PARK-S3
(0.9~1.2V)
C157
C157
0.1U
0.1U
C501UC50
1U
C861UC86
1U
PART 5 OF 10
PART 5 OF 10
GND
GND
+VDDCI
C156
C156
1U
0.1U
0.1U
C1771UC177
1U
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
C1651UC165
L12 BLM18PG121SN1DL12 BLM18PG121SN1D
(1.1V)
+PCIE_VDDC
C42
C42
10U
10U
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U3
U9
V13
V16
V18
V6
Y10
Y15
Y17
Y20
Y6
T11
R11
A32
AM1
AM32
C1551UC155
C161
C161
1U
10U
10U
L25
L25
C40
C40
10U
10U
603
603
1 2
6.3
6.3
C41
C41
10U
10U
603
603
1 2
6.3
6.3
+VCC_GFX_CORE
BLM18EG221SN1D
BLM18EG221SN1D
1
(PCIE_VDDC 1.0~1.1V +/- 5%@ 2A )
(1.1V)
12
C68
C68
1U
1U
402
402
6.3
6.3
12
C45
C45
1U
1U
402
402
6.3
6.3
+PCIE_VDDC+1.1V_GFX_PCIE
C54
C54
0.1U
0.1U
16
16
C79
C79
0.1U
0.1U
16
16
(0.9~1.2V)
QUANTA
QUANTA
QUANTA
COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
COMPUTER
VGA-M92-XT (PCIe)
VGA-M92-XT (PCIe)
VGA-M92-XT (PCIe)
FM9 3B
FM9 3B
FM9 3B
1
of
of
of
18 66Tuesday, October 06, 2009
18 66Tuesday, October 06, 2009
18 66Tuesday, October 06, 2009
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