DELL OZ965 Schematics

High-Efficiency Inverter Controller

FEATURES

• Single-stage power conversion, requiring only a +5 V voltage source

• Reduces the number of components and board size by 30% compared with conventional design

• Supports both floating and grounded secondary designs

• 90% efficiency vs. typical 75% efficiency of conventional designs

• Internal open-lamp and short-circuit protections

• Wide dimming range

• Supports multiple CCFLs

• Simple and reliable 2-winding transformer

design

• Eliminates leakage current when used in a floating secondary design

• Constant-frequency design eliminates interference with LCDs

ORDERING INFORMATION

OZ965G - 16-pin plastic SOP OZ965R - 16-pin plastic TSSOP OZ965IG - 16-pin plastic SOP

IR - 16-pin plastic TSSOP

OZ965

GENERAL DESCRIPTION

The OZ965 is a single chip, high-efficiency, Cold Cathode Fluorescent Lamp (CCFL) backlight inverter controller whose primary function is to convert +5 volt DC power to approximately 600 VAC. Additionally, the OZ965 performs the lamp

Figure 1. Typical Application Circuit

ENA

DIM

GND

100k R1

0.1u

R4 20k

R5 15k

REF

HCLMP

LCLMP

SCP

ADJ

CMP

0.01u

R16 100k

C12

0.1u

GND8SST OZ965

0.1u

R2 22

R3 150k

C3 10u

0.1u

59.0k

VDD

OPS

470p

ENA

NDR

PDR

C10

2.2u

R13

C11

510k

0.1u

C2 22u

2 1

4 3 5

Si4532

OZ965

dimming function with an analog voltage or low frequency Pulse Width Modulation (PWM) control.

Operating Principle: The CCFL tube, transformer secondary, and capacitor form a resonant circuit. The OZ965 utilizes the low energy loss resonate mode principle to deliver a very high efficiency inverter.

The OZ965 drives the transformer primary with a variable pulse width voltage directly from the +5v supply. The resultant primary drive current is alternately reversing with zero-voltage-switching. Because of the transformer leakage inductance and the secondary resonant circuit, the secondary voltage and current are approximately sinusoidal. This sinusoid results in very little harmonic emi/rfi emissions.

The OZ965 operates at a single, constant frequency in a PWM mode. Typical operating frequency ranges between 30 KHz to 200 KHz, dependent upon the CCFL and transformer characteristics. Intelligent open-lamp protection provides design flexibility so various transformer models/manufacturers may be used.

Its high driving capability allows the OZ965 to drive high power MOSFETs.

The single stage design results in a low cost, reliable transformer without expensive, less reliable secondary fold-back treatment. The transformer does not require a more expensive center tapped primary.

The OZ965 is available in 16-pin SOP and TSSOP packages. It is specified over the commercial temperature range of 0°C to +70°C, and the industrial temperature range of -40°C to +85°C.

2 7

17:2200

5 6

8 7

C7 10u

CR3 BAV99L

R15

1 3

4.3k

R17

1.02k

RTN

68p 3kv

06/20/00 OZ965-SF-3.0 Page 1

OZ965

FUNCTIONAL BLOCK DIAGRAM

Refer to the functional block diagram in Figure 2, below, and the Pin Description Table on page 3.

Power is transferred to the transformer primary by the N-MOSFET, driven by the MOSFET gate driver out of pin NDR. The P-MOSFET resets the primary field, driven by pin PDR. The usual design results in approximately 50% duty cycle at full lamp intensity. Terminating the NDR signal earlier than the full brightness lamp pulse width performs lamp dimming, using the analog dimming. The voltages on pins HCLMP and LCLMP set a threshold voltage for the ramp comparator setting the maximum duty cycle for NDR.

A pulse generator circuit creates the clock signal with the frequency determined by an external, constant current setting resistor (RT) and timing capacitor (CT).

The “soft-start” circuit ensures a reliable and long lamp life starting condition.

REF

HCLMP

LCLMP

SCP

ADJ

2.50V

Vset

CMP

70k

630k

GND

Note:

OVP – Over Voltage Protection SCP – Short-Circuit Protection UVL – Under Voltage Lockout

2.5V

Vmax=2.6V-Vset

COMP

IBIAS

REFERENCE

Vmax

POFF

Vmin (fix value)

V>Vmax -- -> Vmax Vmin<V<Vmax ->V V<Vmin -- ->Vmin

SS1

(slow start)

OLPROT

Figure 2. Functional Block Diagram

RESET

UVLO

PROTECTION

POFF

“Soft start” gradually increases the energy delivered to the secondary.

When the OZ965 is enabled at pin ENA, the capacitor on pin SST determines the duration of the “soft-start” period, gradually increasing the NDR pulse width to the regulated brightness. The “soft-start” period provides sufficient time for the lamp to ignite.

For system reliability there are several circuit protections provided. To ensure a controlled output, the secondary current is monitored on pin FB and is compared to a reference voltage on pin ADJ. The NDR signal is shortened or lengthened dependent upon this feedback. Protection is provided by the resultant signal, CMP, monitoring for a lamp removal condition. Short circuit protection is provided at pin SCP. The OPS signal selects either HCLMP or LCLMP providing current protection against an “Open Lamp” condition at start-up. The OPS signal also allows adjustment to different transformer models.

To reduce power dissipation, the switch (MOSFET) drive signals are “break-before-make” with a short, fixed off time between activation of NDR or PDR.

RAMP COMP.

Vdd

UNDER VOLTAGE

LOCKOUT

t1+t2

V_SS2

(slow start)

SS2

RAMP COMP. PULSE

ZVS

CONTROLLER

PULSE GEN

CLK

ENABLE

Pgate

Ngate

2.5V

COMP

0.5V

0.6V

LAMP

COMP

ON/OFF

COMP

PDRV

NDRV

SS1

POFF

Vdd

OPS

ENA

300k

ACTIVE

"HIGH"

1.5V

PDR

NDR

I=2.5uAI=12uA

SST

4K MN1

OZ965-SF-3.0 Page 2

PIN DESCRIPTION

Names Pin No. I/O Description

REF 1 O Reference voltage output. Nom i nal vol tage is 2.5 V.

HCLMP 2 I Clamping maximum duty cycle under normal operation.

LCLMP 3 I Clamping maximum duty c ycle under open-lamp condition.

SCP 4 I Short-circuit protection input (VTH=0.6V) ADJ 5 I Reference voltage input for di mming control.

FB 6 I Current sense feedback. CMP 7 O Compens ation for the current sense feedbac k. GND 8 GND Ground.

SST 9 I Soft-start ensures lamp current pulses gradually increases to its normal

PDR 10 O Gate drive output for the P-MOSFET. NDR 11 O Gate drive output for the N-MOSFET.

ENA 12 I Enabl e i nput , active high (VTH=1.5V)

OPS 13 I Output current sense (VTH=0.6V)

CT 14 I/O Timing capacitor. CT and RT set the clock frequency.

RT 15 I/O VDD 16 PWR Supply voltage input.

ABSOLUTE MAXIMUM RATINGS

VDD GND +/- 0.3V Logic inputs -0.3 V to VDD+0.3V

OZ965 OZ965I Operating temp. 0oC to 70oC -40oC to 85oC

Operating junction temp. Storage temp. -55oC to 150oC

5.5V

150oC

RECOMMENDED OPERATING RANGE

VDD 5.0 V +/- 5% Fosc 30 KHz to 200 KHz Rosc 50 k to 150 k

value

Timing resistor. Fos c = 1.91 / (Rt

OZ965 OZ965I Power dissipation

- 16-pin SOP

- 16-pin TSSOP

Thermal Impedance

- 16-pin SOP

- 16-pin TSSOP

• Ct)

OZ965

.720W .690W

111

115

C/W C/W

.580W .550W

111

115

C/W C/W

OZ965-SF-3.0 Page 3

+ 4 hidden pages