Dell M4010 Schematics

5

4

3

2

1

Ansenal DJ1 UMA Schematics Document

D D

AMD Danube CPU S1G4

RS880M + SB820M

C C

2010-05-25 REV : A00

B B

A A

5

4

DY : Nopop Component

http://hobi-elektronika.net

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Ansenal DJ1 AMD UMA

190Tuesday, May 25, 2010

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Project code : 91.4EK01.001 PCB P/N : 09940 Revision : SC

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Ansenal DJ1 AMD UMA Block Diagram

AMD S1G4 CPU

OUT

8,9,10,11

HyperTransport 16X16

IN

DDR III 800

DDRIII 800/1066

DIMM1

18

DIMM2

19

2

1

CHARGER

BQ24745RHDR

INPUTS

+DC_IN_SS +CHAGER_SRC

OUTPUTS

+PWR_SRC

SYSTEM DC/DC

RT8205BGQW-GP

INPUTS

+PWR_SRC

OUTPUTS

+5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW

46

SYSTEM DC/DC

RT8209EGQW

50

INPUTS OUTPUTS

RT9025

+1.1V_RUN+PWR_SRC

OUTPUTS

+VCC_CORE +VDDNB

OUTPUTS

+1.5V_SUS

OUTPUTS

+1.8V_RUN

42,53

OUTPUTS

+3.3V_RUN+3.3V_ALW

48,51

+1.1V_ALW +CPU_VDDR+1.5V_SUS

47

49

52

CRT

LCD

C C

55

54

RGB CRT

LVDS(Single Channel)

North Bridge

AMD RS880M

CPU I/F LVDS, CRT I/F INTEGRATED GRAHPICS

12,13,14,15

A-LINK 4X4

PCIE x 1

USB 2.0 x 1

PCIE x 1 USB 2.0 x 1

I/O Board

Connector

76

10/100 NIC

ATHEROS AR8132

Left Side: USB x 1

Mini-Card

802.11a/b/g

RJ45 CONN

CPU CORE

ISL6265AHRTZ-T-GP

INPUTS

+PWR_SRC

DDR III SUS&VTT

RT8207GQW-GP

INPUTS

+PWR_SRC

SYSTEM DC/DC

APL5930KAI

INPUTS

CardReader

SD/SDIO/MMC MS/MS Pro/xD

B B

Internal Analog MIC

44

MIC IN

HP OUT

Realtek RTS5138

Azalia CODEC

& OP AMP

92HD79B

32

30

2CH SPEAKER

USB2.0

AZALIA

South Bridge

AMD SB820M

14 USB 2.0 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

4 PCIE GPP 6 SATA ports

ACPI 1.1 LPC I/F

PCI/PCI BRIDGE

SATA

20,21,22,23,24

SATA

USB 2.0

SPI

LPC Bus

KBC

NUVOTON

NPCE781BA0DX

USB 2.0 x 1

37

CAMERA (Option)

Bluetooth

Right Side: USB x 1

+3.3V_ALW

SYSTEM DC/DC

Swithes/RT9013

INPUTS

73

+5V_ALW +5V_RUN +1.5V_SUS +1.5V_RUN +3.3V_RUN +2.5V_RUN

SYSTEM DC/DC

INPUTS OUTPUTS

63

+3.3V_ALW

PCB LAYER

L1: Top L2: VCC L3: Signal L4: Signal L5: GND

A A

HDD

ODD

59 59

http://hobi-elektronika.net

5

4

Flash ROM

2MB

3

Touch PAD

62 68 25

68

KB

ThermalInt.

EMC2102

Fan

58

2

39

Title

Size Document Number Rev

A3

Date: Sheet

Ansenal DJ1 AMD UMA

L6: Bottom

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

290Thursday, May 13, 2010

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A

B

C

D

E

Power Shape

Power Block Diagram

Regulator LDO Switch

4 4

Adapter

AO4407A

Battery

3 3

77.5mA

+3.3V_RTC_LDO

+PWR_SRC

Charger

+PBATT

G547F2P81U

+5V_USB1

RT8205BGQW

+5V_ALW

AO4468

6257.3mA 2000mA2000mA

+5V_RUN

36A 4A 17868mA

10337mA

G547F2P81U

+5V_USB2

ISL6265AHRTZ RT8207GQWRT8209EGQW

+VCC_CORE

+VDDNB(CPU)

+5V_ALW2

AO4468

+3.3V_RUN

+1.1V_RUN

+3.3V_ALW

5966mA

8774mA

PA102FMG

201mA 1320mA

+3.3V_LAN

APL5930

+1.8V_RUN

RT9025

1250mA

VDDR(CPU)

RT9025-25PSP

+1.1V_ALW

1000mA

+0.75V_DDR_VTT

572mA

13480mA

+1.5V_SUS

AO4468

1230mA

+1.5V_RUN

2 2

RESISTER

60mA 1370mA

+PVDD

1 1

A

+AVDD

G5285T11U

606mA 250mA

+LCDVDD

B

RTS5138

+3.3V_RUN_CARD

RT9013-25PB

+2.5V_RUN

http://hobi-elektronika.net

C

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet

Power Block Diagram

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

390Thursday, May 13, 2010

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SB820M SMBus Block Diagram

D D

+3.3V_RUN

SRN2K2J

SB820M

C C

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

SCL0

SDA0

SCL1

SDA1

SCL2

SDA2

SB_SMBCLK

SB_SMBDATA

SMB_CLK

SMB_DATA

SCL2

SDA2

CPU_SIC

CPU_SID

+3.3V_ALW

SRN10K2J

+3.3V_ALW

SRN10K2J

SB_SMBCLK

SB_SMBDATA

SB_SMBCLK

SB_SMBDATA

SB_SMBCLK

SB_SMBDATA

DIMM 1

SCL

SDA

SMBus Address:A0

DIMM 2

SCL

SDA

SMBus Address:A4

MINI CARD

SMB_CLK

SMB_DATA

NPCE781

KBC SMBus Block Diagram

+5V_RUN

SRN10KJ-5-GP

PSDAT1

KBC

PSCLK1

GPIO61/SCL2

GPIO62/SDA2

SCL1

SDA1

TPDATA

TPCLK

BAT_SCL

BAT_SDA

KBC_SCL1

KBC_SDA1

+KBC_PWR

SRN4K7J-8-GP

SRN100J-3-GP

2N7002SPT

PBAT_SMBCLK1

PBAT_SMBDAT1

TPDATA

TPCLK

Battery Conn.

CLK_SMB

DAT_SMB

BQ24745RHDR

SCL

SDA

+3.3V_RUN

TouchPad Conn.

TPDATA

TPCLK

(In I/O Board)

SRN4K7J-8-GP

Thermal

THERM_SCL

SCL

THERM_SDA

SDA

SMBus address:16

SMBus address:12

SMBus address:7A

B B

+1.5V_SUS

SRN1K2J

CPU_SIC

CPU_SID

CPU S1G4

SIC

SID

I2C_CLK

I2C_DATA

LDDC_CLK

LDDC_DATA

+3.3V_RUN

4K7R2J-2-GP

LCD Conn.

SMBus address:98

RS880M

A A

DAC_SCL

DDC_CLK_CON

DAC_SDA

DDC_DATA_CON

5

4

http://hobi-elektronika.net

3

+5V_CRT_RUN

4K7R2J-2-GP

CRT CONN

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

SMBUS BLOCK DIAGRAM

Size Document Number Rev

A2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Ansenal DJ1 AMD UMA

1

490Thursday, May 13, 2010

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D D

C C

Thermal Block Diagram

CPU

DP1

DN1

H_THERMDA

SC470P50V3JN-2GP

H_THERMDC

THERMDA

THERMDC

Thermal EMC2102

DP2

DN2

EMC2102_DP2

SC470P50V3JN-2GP

EMC2102_DN2

System sensor, put

PMBS3904

Audio Block Diagram

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

HP1_PORT_B_L

HP1_PORT_B_R

Codec 92HD79

VREFOUT_A_OR_F

HP0_PORT_A_L

HP0_PORT_A_R

AUD_SPK_L+

AUD_SPK_L-

AUD_SPK_R-

AUD_SPK_R+

AUD_HP1_JACK_L

AUD_HP1_JACK_R

AUD_VREFOUT_B

AUD_EXT_MIC_L

AUD_EXT_MIC_R

60D4R2F

4K7R2J-2-GP

Bead

AUD_HP1_JACK_L1

AUD_HP1_JACK_R1

SPEAKER

60

HP

OUT

60

MIC

IN

60

near DIMM.

B B

EMC2102_DP3

DP3

SC470P50V3JN-2GP

EMC2102_DN3

DN3

System sensor, put CPU.

A A

5

4

PMBS3904

http://hobi-elektronika.net

3

PORT_C_L

PORT_C_R

VREFOUT_C

AUD_INT_MIC_R_L

AUD_VREFOUT_C

30

4K7R2J-2-GP

SC1U10V3KX-3GP

2

INT_MIC_L_R

Internal MIC

60

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL/AUDIO BLOCK DIAGRAM

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

590Thursday, May 13, 2010

1

of

A00

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SB820M Strapping

Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide

Name Strap Name Schematic Note

LPCCLK0

D D

EC_PWM3 EC_PWM2

LPCCLK1

PCICLK1

C C

ECEnableStrap

{ROMTYPE_1, ROMTYPE_0 }

CLKGEN

BIF_GEN2_ COMPLIANCE_Strap

Embedded Controller (EC)

0 V – Disabled

*

3.3 V - Enabled

ROMTYPE_1 ROMTYPE_0 ROM TYPE

3.3V 0V

3.3V 3.3V

0V 0V

0V 3.3V

*

LPC ROM (supports both LPC and PMC ROM types)

Defines clock generator

External clock mode: Use 100-MHz PCIeR

0V –

clock as reference clock and generate i nternal clocks only.

Integrated clock mode: Use 25-MHz crystal

3.3V–

*

clock and generate both internal and external clocks

Set PCIe to Gen II mode

Force PCIe interface at Gen I mode

0V–

PCIe interfacce is at Gen II mode

3.3V-

*

Not Applicable to SB820M but provision for pull-down is required.

SPI ROM

Reserved

Firmware Hub

NB880M Strapping

Capture from 46113_rs880m_ds_nda_1.03

DAC_VSYNC

DAC_HSYNC

SUS_STAT#

STRAP_DEBUG_BUS_GPIO _ENABLE#

SIDE_PORT_EN#

LOAD_EEPROM_STRAPS#

Schematic NoteStrap FunctionName

Enables debug bus access through memory I/O pads and GPIOs. 0: Enable 1: Disable

*

Indicates if memory side-port is available or not 0: Available 1: Not available

*

Selects loading of strap values from EEPROM. 0: I2C master can load strap values from EEPROM if connected, or use default values if EEPROM is not connected. Please refer to RS880M's reference schematics for system level implementation details. 1: Use default values

*

Watchdog function

PCICLK2 BootFailTmrEn

*

Disable the boot fail timer function

0V–

Enable the boot fail timer function

3.3V-

Default Debug Straps

PCICLK3 DefaultStrapMode

*

Disable Debug Straps.

0V–

Select external Debug Straps

3.3V–

CPU/NB HT Clock Selection

PCICLK4 CPUClkSel

*

0V–

Required setting for integrated clock mode.

3.3V–

This strap is not used if the strap CLKGEN is configured for external clock generator mode.

Reserved.

Slow down core clock for low power platform.

AZ_SDOUT CoreSpeedMode

B B

*

0V–

3.3V-

Performance mode

Low Power mode

USB Table

PCIE Routing

USB

Pair

0 1 2 3 4 5 6 7 8 9 10

A A

11 12 13

Device

USB1 USB3 USB2 (I/O Board) Reserve WLAN Reserve Reserve Reserve Reserve BLUETOOTH CARD READER CAMERA Reserve Reserve

5

LANE0

LANE1

LAN

MiniCard WLAN

4

http://hobi-elektronika.net

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Table of Content

Size Document Number Rev

A2

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

Ansenal DJ1 AMD UMA

1

690Thursday, May 13, 2010

A00

of

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator ICS9LPRS480

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

790Thursday, May 13, 2010

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SSID = CPU

D D

+1.1V_RUN

SC10U6D3V5KX-1GP

12

C C

B B

Place close to socket 1.1V(1.5A) for VLDT

SC4D7U6D3V3KX-GP

C801

C802

12

SCD22U10V3KX-2GP

C803

12

C804

SC180P50V2JN-1GP

SCD22U10V3KX-2GP

C805

12

HT_NB_CPU_CAD_H012 HT_NB_CPU_CAD_L012 HT_NB_CPU_CAD_H112 HT_NB_CPU_CAD_L112 HT_NB_CPU_CAD_H212 HT_NB_CPU_CAD_L212 HT_NB_CPU_CAD_H312 HT_NB_CPU_CAD_L312 HT_NB_CPU_CAD_H412 HT_NB_CPU_CAD_L412 HT_NB_CPU_CAD_H512 HT_NB_CPU_CAD_L512 HT_NB_CPU_CAD_H612 HT_NB_CPU_CAD_L612 HT_NB_CPU_CAD_H712 HT_NB_CPU_CAD_L712 HT_NB_CPU_CAD_H812 HT_NB_CPU_CAD_L812 HT_NB_CPU_CAD_H912 HT_NB_CPU_CAD_L912 HT_NB_CPU_CAD_H1012 HT_NB_CPU_CAD_L1012 HT_NB_CPU_CAD_H1112 HT_NB_CPU_CAD_L1112 HT_NB_CPU_CAD_H1212 HT_NB_CPU_CAD_L1212 HT_NB_CPU_CAD_H1312 HT_NB_CPU_CAD_L1312 HT_NB_CPU_CAD_H1412 HT_NB_CPU_CAD_L1412 HT_NB_CPU_CAD_H1512 HT_NB_CPU_CAD_L1512

HT_NB_CPU_CLK_H012 HT_NB_CPU_CLK_L012 HT_NB_CPU_CLK_H112 HT_NB_CPU_CLK_L112

HT_NB_CPU_CTL_H012 HT_NB_CPU_CTL_L012 HT_NB_CPU_CTL_H112 HT_NB_CPU_CTL_L112

SC180P50V2JN-1GP

C806

12

C807

CPU1A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

DANUB

DANUBE

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

1 OF 6

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

HT_CPU_NB_CAD_H0 12 HT_CPU_NB_CAD_L0 12 HT_CPU_NB_CAD_H1 12 HT_CPU_NB_CAD_L1 12 HT_CPU_NB_CAD_H2 12 HT_CPU_NB_CAD_L2 12 HT_CPU_NB_CAD_H3 12 HT_CPU_NB_CAD_L3 12 HT_CPU_NB_CAD_H4 12 HT_CPU_NB_CAD_L4 12 HT_CPU_NB_CAD_H5 12 HT_CPU_NB_CAD_L5 12 HT_CPU_NB_CAD_H6 12 HT_CPU_NB_CAD_L6 12 HT_CPU_NB_CAD_H7 12 HT_CPU_NB_CAD_L7 12 HT_CPU_NB_CAD_H8 12 HT_CPU_NB_CAD_L8 12 HT_CPU_NB_CAD_H9 12 HT_CPU_NB_CAD_L9 12 HT_CPU_NB_CAD_H10 12 HT_CPU_NB_CAD_L10 12 HT_CPU_NB_CAD_H11 12 HT_CPU_NB_CAD_L11 12 HT_CPU_NB_CAD_H12 12 HT_CPU_NB_CAD_L12 12 HT_CPU_NB_CAD_H13 12 HT_CPU_NB_CAD_L13 12 HT_CPU_NB_CAD_H14 12 HT_CPU_NB_CAD_L14 12 HT_CPU_NB_CAD_H15 12 HT_CPU_NB_CAD_L15 12

HT_CPU_NB_CLK_H0 12 HT_CPU_NB_CLK_L0 12 HT_CPU_NB_CLK_H1 12 HT_CPU_NB_CLK_L1 12

HT_CPU_NB_CTL_H0 12 HT_CPU_NB_CTL_L0 12 HT_CPU_NB_CTL_H1 12 HT_CPU_NB_CTL_L1 12

SKT-BGA638H176

1'nd 62.10055.111 2'nd 62.10055.171

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_HT_LINK I/F_(1/4)

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

890Thursday, May 27, 2010

1

of

A00

5

4

3

2

1

SSID = CPU

3 OF 6

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24

E21 E22 H20 H22

Y24 AB24 AB22 AA21

W22 W21

Y22 AA22

Y20 AA20 AA18 AB18 AB21 AD21 AD19

Y18 AD17

W16 W14

Y14

Y17 AB17 AB15 AD15 AB13 AD13

Y12

W11 AB14 AA14 AB12 AA12

E12 C15 E19 F24

AC24

Y19

AB16

Y13 G13

H13 G16 G15 C22 C21 G22

G21 AD23 AC23 AB19 AB20

Y15

W15 W12 W13

J19

3 OF 6

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

SC180P50V2JN-1GP

C916

12

DY

C912

M_A_DQ[63..0]18

4.7UF*4

0.22UF*4

D D

+CPU_VDDR

SC4D7U6D3V3KX-GP

C901

12

SC4D7U6D3V3KX-GP

C902

12

C903

12

Place near to CPU

SCD22U10V3KX-2GP

SC4D7U6D3V3KX-GP

12

C913

C904

12

SCD22U10V3KX-2GP

C914

12

DY

SCD22U10V3KX-2GP

C906

C905

12

SC1000P50V3JN-GP-U

C907

12

1000PF*4 180PF*4

SC1000P50V3JN-GP-U

C915

12

SC1000P50V3JN-GP-U

C908

C909

12

SC180P50V2JN-1GP

C910

12

SC180P50V2JN-1GP

C911

12

DY

0.9V(1.25A) for VDDR

+CPU_VDDR

C C

+1.5V_SUS

R901 39D2R2F-L-GPR901 39D2R2F-L-GP

1 2

R903 39D2R2F-L-GPR903 39D2R2F-L-GP

1 2

12

B B

MEM_MA_ADD[0..15]18

A A

DDR3_A_DRAMRST#18

C917

C917 SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

MEM_MA0_ODT018 MEM_MA0_ODT118

MEM_MA0_CS#018 MEM_MA0_CS#118

MEM_MA_CKE018 MEM_MA_CKE118

MEM_MA_CLK0_P18 MEM_MA_CLK0_N18

MEM_MA_CLK1_P18 MEM_MA_CLK1_N18

MEM_MA_BANK018 MEM_MA_BANK118 MEM_MA_BANK218

MEM_MA_RAS#18 MEM_MA_CAS#18 MEM_MA_WE#18

MEMZP MEMZN

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

0.9V--DDR1066

1.05V---DDR1333 (1.75A)

CPU1B

D10

VDDR

C10

VDDR

B10

VDDR

AD10

VDDR

AF10

MEMZP

AE10

MEMZN

H16

MA_RESET#

T19

MA0_ODT0

V22

MA0_ODT1

U21

MA1_ODT0

V19

MA1_ODT1

T20

MA0_CS#0

U19

MA0_CS#1

U20

MA1_CS#0

V20

MA1_CS#1

J22

MA_CKE0

J20

MA_CKE1

N19

MA_CLK_H5

N20

MA_CLK_L5

E16

MA_CLK_H1

F16

MA_CLK_L1

Y16

MA_CLK_H7

AA16

MA_CLK_L7

P19

MA_CLK_H4

P20

MA_CLK_L4

N21

MA_ADD0

M20

MA_ADD1

N22

MA_ADD2

M19

MA_ADD3

M22

MA_ADD4

L20

MA_ADD5

M24

MA_ADD6

L21

MA_ADD7

L19

MA_ADD8

K22

MA_ADD9

R21

MA_ADD10

L22

MA_ADD11

K20

MA_ADD12

V24

MA_ADD13

K24

MA_ADD14

K19

MA_ADD15

R20

MA_BANK0

R23

MA_BANK1

J21

MA_BANK2

R19

MA_RAS#

T22

MA_CAS#

T24

MA_WE#

DANUB

2 OF 6

VDDR VDDR VDDR

DANUBE

VDDR VDDR

VDDR_SENSE

MEMVREF

MB_RESET#

MB0_ODT0 MB0_ODT1 MB1_ODT0

MB0_CS#0 MB0_CS#1 MB1_CS#0

MB_CKE0 MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8

MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_RAS#

MB_CAS#

MB_WE#

W10 AC10 AB10 AA10 A10

TP_CPU_VDDR_SENSE

Y10 W17 B18 W26

W23 Y26

V26 W25 U22

J25 H26

P22 R22 A17 A18 AF18 AF17 R26 R25

MEM_MB_ADD0

P24

MEM_MB_ADD1

N24

MEM_MB_ADD2

P26

MEM_MB_ADD3

N23

MEM_MB_ADD4

N26

MEM_MB_ADD5

L23

MEM_MB_ADD6

N25

MEM_MB_ADD7

L24

MEM_MB_ADD8

M26

MEM_MB_ADD9

K26

MEM_MB_ADD10

T26

MEM_MB_ADD11

L26

MEM_MB_ADD12

L25

MEM_MB_ADD13

W24

MEM_MB_ADD14

J23

MEM_MB_ADD15

J24 R24

U26 J26

U25 U24 U23

+1.5V_SUS

SCD1U10V2KX-5GP

C918

1KR3F-GP

12

+0.75V_SUS_CPU_M_VREF +V_DDR_REF

TP901TP901

1

DDR3_B_DRAMRST# 19 MEM_MB0_ODT0 19

MEM_MB0_ODT1 19

MEM_MB0_CS#0 19 MEM_MB0_CS#1 19

MEM_MB_CKE0 19 MEM_MB_CKE1 19

MEM_MB_CLK0_P 19 MEM_MB_CLK0_N 19

MEM_MB_CLK1_P 19 MEM_MB_CLK1_N 19

MEM_MB_BANK0 19 MEM_MB_BANK1 19 MEM_MB_BANK2 19

MEM_MB_RAS# 19 MEM_MB_CAS# 19 MEM_MB_WE# 19

MEM_MB_ADD[0..15] 19

SCD1U10V2KX-5GP

SC1000P50V3JN-GP-U

C919

12

CLOSE TO CPU

C920

1KR3F-GP

12

R902

1 2

12

R905

R904

DY

0R3J-0-U-GP

M_A_DM[7..0]18

M_A_DQS018 M_A_DQS#018 M_A_DQS118 M_A_DQS#118 M_A_DQS218 M_A_DQS#218 M_A_DQS318 M_A_DQS#318 M_A_DQS418 M_A_DQS#418 M_A_DQS518 M_A_DQS#518 M_A_DQS618 M_A_DQS#618 M_A_DQS718 M_A_DQS#718

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

http://hobi-elektronika.net

5

4

3

2

CPU1C

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3

DANUBE

MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0

MB_DQS_L0

MB_DQS_H1

MB_DQS_L1

MB_DQS_H2

MB_DQS_L2

MB_DQS_H3

MB_DQS_L3

MB_DQS_H4

MB_DQS_L4

MB_DQS_H5

MB_DQS_L5

MB_DQS_H6

MB_DQS_L6

MB_DQS_H7

MB_DQS_L7

DANUB

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

M_B_DQ0

C11

M_B_DQ1

A11

M_B_DQ2

A14

M_B_DQ3

B14

M_B_DQ4

G11

M_B_DQ5

E11

M_B_DQ6

D12

M_B_DQ7

A13

M_B_DQ8

A15

M_B_DQ9

A16

M_B_DQ10

A19

M_B_DQ11

A20

M_B_DQ12

C14

M_B_DQ13

D14

M_B_DQ14

C18

M_B_DQ15

D18

M_B_DQ16

D20

M_B_DQ17

A21

M_B_DQ18

D24

M_B_DQ19

C25

M_B_DQ20

B20

M_B_DQ21

C20

M_B_DQ22

B24

M_B_DQ23

C24

M_B_DQ24

E23

M_B_DQ25

E24

M_B_DQ26

G25

M_B_DQ27

G26

M_B_DQ28

C26

M_B_DQ29

D26

M_B_DQ30

G23

M_B_DQ31

G24

M_B_DQ32

AA24

M_B_DQ33

AA23

M_B_DQ34

AD24

M_B_DQ35

AE24

M_B_DQ36

AA26

M_B_DQ37

AA25

M_B_DQ38

AD26

M_B_DQ39

AE25

M_B_DQ40

AC22

M_B_DQ41

AD22

M_B_DQ42

AE20

M_B_DQ43

AF20

M_B_DQ44

AF24

M_B_DQ45

AF23

M_B_DQ46

AC20

M_B_DQ47

AD20

M_B_DQ48

AD18

M_B_DQ49

AE18

M_B_DQ50

AC14

M_B_DQ51

AD14

M_B_DQ52

AF19

M_B_DQ53

AC18

M_B_DQ54

AF16

M_B_DQ55

AF15

M_B_DQ56

AF13

M_B_DQ57

AC12

M_B_DQ58

AB11

M_B_DQ59

Y11

M_B_DQ60

AE14

M_B_DQ61

AF14

M_B_DQ62

AF11

M_B_DQ63

AD11

M_B_DM0

A12

M_B_DM1

B16

M_B_DM2

A22

M_B_DM3

E25

M_B_DM4

AB26

M_B_DM5

AE22

M_B_DM6

AC16

M_B_DM7

AD12 C12

B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

Ansenal DJ1 AMD UMA

M_B_DQS0 19 M_B_DQS#0 19 M_B_DQS1 19 M_B_DQS#1 19 M_B_DQS2 19 M_B_DQS#2 19 M_B_DQS3 19 M_B_DQS#3 19 M_B_DQS4 19 M_B_DQS#4 19 M_B_DQS5 19 M_B_DQS#5 19 M_B_DQS6 19 M_B_DQS#6 19 M_B_DQS7 19 M_B_DQS#7 19

CPU_DDR(2/4)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

990Thursday, May 27, 2010

M_B_DQ[63..0] 19

M_B_DM[7..0] 19

A00

of

5

SSID = CPU

D D

+1.5V_RUN

4

RN1001

RN1001 SRN300J-3-GP

SRN300J-3-GP

1

2 3

CPU_LDT_RST#20 CPU_LDT_PWRGD20,42 CPU_LDT_STOP#13,20

C C

+1.5V_RUN

R1012 300R2J-4-GP

1 2

R1013 300R2J-4-GP

R1013 300R2J-4-GP R1014 300R2J-4-GP

R1014 300R2J-4-GP R1016 300R2J-4-GP

R1016 300R2J-4-GP

RN1002 SRN1KJ-7-GPRN1002 SRN1KJ-7-GP

RN1004 SRN1KJ-7-GPRN1004 SRN1KJ-7-GP

X01

+1.5V_SUS

B B

R1026

R1026 1KR2J-1-GP

1KR2J-1-GP

1 2

CPU_TEST27

R1029

R1029 300R2J-4-GP

300R2J-4-GP

DY

1 2

TP1001TP1001 TP1003TP1003 TP1006TP1006 TP1007TP1007

TP_CPU_VDDIO_SUS_FB_H

1

TP_CPU_VDDIO_SUS_FB_L

1

TP_CPU_TEST17

1

TP_CPU_TEST16

1

1 2

R1001 0R0402-PADR1001 0R0402-PAD

1 2

R1002 0R0402-PADR1002 0R0402-PAD

1 2

R1003 0R0402-PADR1003 0R0402-PAD

DY

1 2

DY

1 2

DY

1 2

DY

2 3 1

4

1

4

2 3

RN1003

1

8

2

7

3

6

4 5

SRN1KJ-4-GP

X01

A A

CPU_PROCHOT#_EC37

5

CPU_CLK(200MHz)

CPU_R_LDT_RST# CPU_R_LDT_PWRGD CPU_R_LDT_STOP#

X00

CPU_LDT_REQ#

CPU_DBRDY TP_CPU_TEST14 TP_CPU_TEST15

CPU_TEST18

CPU_TEST19

CPU_TEST24

CPU_TEST22

CPU_TEST23

CPU_TEST12

CPU_TEST20

CPU_TEST21

+3.3V_RUN

10KR2J-3-GP

12

R1040

For HDT DBG

C1008

SCD1U16V2ZY-2GP

C1008

SCD1U16V2ZY-2GP

12

DY

+1.5V_RUN

2K2R2J-2-GP

12

R1039

1

3

2

Q1005

Q1005 PMBS3904-1-GP

PMBS3904-1-GP

CPU_R_LDT_RST#

HDT_RST_R#

510R2F-L-GP

CPU_PROCHOT#

4

SC180P50V2JN-1GP

12

Cloce To CPU

C1005 SC3900P50V2KX-2GPC1005 SC3900P50V2KX-2GP C1006 SC3900P50V2KX-2GPC1006 SC3900P50V2KX-2GP

SCD1U16V2ZY-2GP

Close CPU

EC1001

12

DY

to power IC FB

12

R1019

R1019 510R2F-L-GP

510R2F-L-GP

12

R1022

DY

510R2F-L-GP

+1.5V_SUS

R1018

R1020

CPU_CLK20 CPU_CLK#20

R1009

1 2

DY

0R2J-2-GP

X00

+1.5V_SUS

12

DY

12

1119

RN1005

RN1005 SRN1KJ-7-GP

SRN1KJ-7-GP

CPU_SIC21

CPU_SID21 TALERT#21,39

For old HDT tool (3.3V level)

4

L1001

1 2

C1001

PBY160808T-330Y-N-GP

R1008 169R2F-GPR1008 169R2F-GP

1 2 1 2

+1.1V_RUN

R1010 44D2R2F-GPR1010 44D2R2F-GP R1011 44D2R2F-GPR1011 44D2R2F-GP

CPU_VDD0_RUN_FB_H47 CPU_VDD0_RUN_FB_L47

CPU_VDD1_RUN_FB_H47 CPU_VDD1_RUN_FB_L47

1

23

4

PMBS3904-1-GP

10KR2J-3-GP

12

R1037

DY

3

LYAOUT:ROUTE VDDA TRACE APPROX. 50mils WIDE(USE 2X25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.

+2.5V_RUN_VDDA+2.5V_RUN

2.5V(250mA) for VDDA

SC4D7U6D3V3KX-GP

C1002

12

1 2

SCD1U16V2ZY-2GP

C1007

12

DY

1 2 1 2

R1023

1 2

0R0402-PAD

2K2R2J-2-GP

12

R1032

312

Q1001

+1.8V_RUN+3.3V_RUN

2K2R2J-2-GP

12

DY

312

DY

Q1004 PMBS3904-1-GP

http://hobi-elektronika.net

SC3300P50V2KX-1GP

C1003

SCD22U10V2KX-1GP

C1003

SCD22U10V2KX-1GP

12

1119

CPUCLK_IN CPUCLK_IN#

CPU_R_LDT_PWRGD CPU_R_LDT_STOP# CPU_LDT_REQ#

CPU_SIC CPU_SID CPU_ALERT#

CPU_HTREF0 CPU_HTREF1

CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI

CPU_TEST23 CPU_TEST18

CPU_TEST19 CPU_TEST25_H

CPU_TEST25_L CPU_TEST21

CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27

CPU_TEST9

1KR2J-1-GP

12

R1033

CPU_SIC CPU_SID

CPU_ALERT#

R1036

HDT_RST_R#HDT_RST#

C1004

3

F10

AF4 AF5

AE6

AB6 G10

AA9 AC9 AD9 AF9

AD7 H10

AB8 AF7 AE7 AE8 AC8 AF8

AA6

CPU1D

F8 F9

A9 A8

B7 A7

C6

R6

P6 F6

E6 Y6

G9

E9 E8

C2

A3 A5 B3 B5

C1

DANUB

VDDA VDDA

CLKIN_H CLKIN_L

RESET# PWROK LDTSTOP# LDTREQ#

SIC SID ALERT#

HT_REF0 HT_REF1

VDD0_FB_H VDD0_FB_L

VDD1_FB_H VDD1_FB_L

DBRDY TMS TCK TRST# TDI

TEST23 TEST18

TEST19 TEST25_H

TEST25_L TEST21

TEST20 TEST24 TEST22 TEST12 TEST27

TEST9 TEST6

RSVD#A3 RSVD#A5 RSVD#B3 RSVD#B5 RSVD#C1

CPU_PWRGD_SVID_REG47

2

1

X01

+1.5V_SUS

1119

4 OF 6

M11

VSS

SVC SVD

MEMHOT#

THERMDC THERMDA

DBREQ#

TDO

TEST28_H TEST28_L

TEST17 TEST16 TEST15 TEST14

TEST7

TEST10

TEST8

TEST29_H TEST29_L

RSVD#H18 RSVD#H19 RSVD#AA7

RSVD#D5 RSVD#C5

W18 A6

A4

AF6 AC7 AA8

W7 W8

W9 Y9

H6 G6

E10 AE9

J7 H8

D7 E7 F7 C7

C3 K8

C4

C9 C8

H18 H19 AA7 D5 C5

+KBC_PWR

8K2R2J-3-GP

12

DY

10KR2J-3-GP

12

R1034

RSVD#W18

DANUBE

THERMTRIP#

PROCHOT#

VDDIO_FB_H

VDDIO_FB_L

VDDNB_FB_H

VDDNB_FB_L

H_THERMTRIP#21,37,39,42

X01

4

RN1006

SRN1KJ-7-GP

1

2 3

CPU_THERMTRIP# CPU_PROCHOT# CPU_MEMHOT#

TP_CPU_VDDIO_SUS_FB_H TP_CPU_VDDIO_SUS_FB_L

R1015

CPU_DBREQ# CPU_TDO

TP_CPU_TEST17 TP_CPU_TEST16 TP_CPU_TEST15 TP_CPU_TEST14

CPU_TEST10

CPU_TEST29H CPU_TEST29L

R1027

PMBS3904-1-GP

R1041 0R2J-2-GP

R1015

1 2

300R2J-4-GP

1 2

DY

R1021 300R3-GP

1 2

R1024 80D6R2F-L-GPR1024 80D6R2F-L-GP

+1.5V_RUN

2K2R2J-2-GP

12

R1028

312

Q1002

+1.8V_RUN+3.3V_RUN

2K2R2J-2-GP

12

R1035

Q1003

DY

CPU_R_LDT_PWRGD

2

312

1 2

CPU_THERMTRIP#

+1.5V_SUS

1KR2J-1-GP

300R2J-4-GP

12

R1006

CPU_SVC 47 CPU_SVD 47

1

TP1002TP1002

S1G4 not support MEMHOT

H_THERMDC 39 H_THERMDA 39

CPU_VDDNB_RUN_FB_H 47 CPU_VDDNB_RUN_FB_L 47

+1.5V_SUS

+1.1V_RUN

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

12

R1007

CPU_PROCHOT# 20

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

HDT Connectors

HDT1

1

DY

3

SMC-CONN26A-FP

1

5 7

9 11 13 15 17 19 21 23

of

10 90Thursday, May 27, 2010

CPU_DBREQ#

CPU_DBRDY

CPU_TCK CPU_TMS CPU_TDI

CPU_TRST#

CPU_TDOCPU_TDO

1.5V

CPU_R_LDT_RST#

HDT_RST#

3.3V

+1.5V_SUS

1 2

DY

R1038 0R2J-2-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

CPU_Control&Debug_(3/4)

Ansenal DJ1 AMD UMA

2 4

6 8 10 12 14 16 18 20 22 24 26

A00

5

4

3

2

1

SSID = CPU

D D

6 OF 6

CPU1F

AA4

VSS

AA11

VSS

AA13

VSS

AA15

VSS

AA17

VSS

AA19

VSS

AB2

VSS

AB7

VSS

AB9

VSS

AB23

VSS

AB25

VSS

AC11

VSS

AC13

VSS

AC15

VSS

AC17

VSS

AC19

VSS

AC21

C C

B B

AD6

AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23

B11

B13

B15

B17

B19

B21

B23

B25

D11

D13

D15

D17

D19

D21

D23

D25

F11 F13 F15 F17 F19 F21 F23 F25

H21

H23

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

B4

VSS

B6

VSS

B8

VSS

B9

VSS VSS VSS VSS VSS VSS VSS VSS VSS

D6

VSS

D8

VSS

D9

VSS VSS VSS VSS VSS VSS VSS VSS VSS

E4

VSS

F2

VSS VSS VSS VSS VSS VSS VSS VSS VSS

H7

VSS

H9

VSS VSS VSS

J4

VSS

DANUB

VSS VSS VSS

DANUBE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

+1.5V_SUS

(36A) for 35W S1G4 VDD

+VCC_CORE +VCC_CORE

SC22U6D3V5MX-2GP

Bottom Side Decoupling Bottom Side Decoupling

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

C1101

12

DY

+VDDNB

0.9V(4A) for VDDNB

SC10U6D3V5KX-1GP

SC22U6D3V5MX-2GP

C1115

12

1.5V(3A) for VDDIO

Bottom Side Decoupling

SC10U6D3V5KX-1GP

C1130

C1131

12

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

C1103

C1104

12

22UF *4

0.22UF *1 180PF *1 10nF*1

SC22U6D3V5MX-2GP

C1116

C1117

12

DY

SCD22U10V3KX-2GP

C1133

C1132

12

DY

22UF *2

0.22UF *2 180PF *1

0.01UF *1

0.1UF *2

SCD22U10V3KX-2GP

SCD1U10V2KX-5GP

C1105

C1102

12

22UF *3

SC180P50V2JN-1GP

SCD1U10V2KX-5GP

C1120

C1134

12

DY

SC180P50V2JN-1GP

C1106

C1107

12

DY

SCD01U16V2KX-3GP

SCD1U10V2KX-5GP

C1135

12

CPU1E

G4

VDD

H2

VDD

J9

VDD

J11

VDD

J13

VDD

J15

VDD

K6

VDD

K10

VDD

K12

VDD

K14

VDD

L4

VDD

L7

VDD

L9

VDD

L11

VDD

L13

VDD

L15

VDD

M2

VDD

M6

VDD

M8

VDD

M10

VDD

N7

VDD

N9

VDD

N11

VDD

K16

VDDNB

M16

VDDNB

P16

VDDNB

T16

VDDNB

V16

VDDNB

H25

VDDIO

J17

VDDIO

K18

VDDIO

K21

VDDIO

K23

VDDIO

K25

VDDIO

L17

VDDIO

M18

VDDIO

M21

VDDIO

M23

VDDIO

M25

VDDIO

N17

VDDIO

C1121

DANUB

12

5 OF 6

DANUBE

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2

Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

SCD01U16V2KX-3GP

SC180P50V2JN-1GP

C1108

12

DY

Place near to CPU

SCD01U16V2KX-3GP

SC180P50V2JN-1GP

C1118

12

DY

SC10U6D3V5KX-1GP

SCD22U10V3KX-2GP

C1109

C1110

12

22UF *4

0.22UF *1 180PF *1 10nF*1

SC4D7U6D3V3KX-GP

C1119

12

SC22U6D3V5MX-2GP

C1112

C1111

12

SCD22U10V3KX-2GP

C1123

C1122

12

0.22UF *4

4.7UF *4 180PF *2

SC10U6D3V5KX-1GP

C1141

12

SCD22U10V3KX-2GP

C1125

C1124

12

C1114

SC4D7U6D3V3KX-GP

C1126

C1127

12

DY

+1.5V_SUS

SC4D7U6D3V3KX-GP

C1128

C1129

12

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU_Power_(4/4)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

11 90Thursday, May 13, 2010

1

of

A00

5

4

3

2

1

SSID = N.B

HT_CPU_NB_CAD_H08

HT_CPU_NB_CAD_L08

RS880M : 71.RS880.M05

D D

C C

Place < 1000mils from pin C23 and A24 Place < 1000mils from pin B25 and B24

B B

A A

A-LINK

5

ALINK_NBRX_SBTX_P020 ALINK_NBRX_SBTX_N020 ALINK_NBRX_SBTX_P120 ALINK_NBRX_SBTX_N120 ALINK_NBRX_SBTX_P220 ALINK_NBRX_SBTX_N220 ALINK_NBRX_SBTX_P320 ALINK_NBRX_SBTX_N320

HT_CPU_NB_CAD_H18 HT_CPU_NB_CAD_L18 HT_CPU_NB_CAD_H28 HT_CPU_NB_CAD_L28 HT_CPU_NB_CAD_H38 HT_CPU_NB_CAD_L38 HT_CPU_NB_CAD_H48 HT_CPU_NB_CAD_L48 HT_CPU_NB_CAD_H58 HT_CPU_NB_CAD_L58 HT_CPU_NB_CAD_H68 HT_CPU_NB_CAD_L68 HT_CPU_NB_CAD_H78 HT_CPU_NB_CAD_L78

HT_CPU_NB_CAD_H88 HT_CPU_NB_CAD_L88 HT_CPU_NB_CAD_H98 HT_CPU_NB_CAD_L98 HT_CPU_NB_CAD_H108 HT_CPU_NB_CAD_L108 HT_CPU_NB_CAD_H118 HT_CPU_NB_CAD_L118 HT_CPU_NB_CAD_H128 HT_CPU_NB_CAD_L128 HT_CPU_NB_CAD_H138 HT_CPU_NB_CAD_L138 HT_CPU_NB_CAD_H148 HT_CPU_NB_CAD_L148 HT_CPU_NB_CAD_H158 HT_CPU_NB_CAD_L158

HT_CPU_NB_CLK_H08 HT_CPU_NB_CLK_L08 HT_CPU_NB_CLK_H18 HT_CPU_NB_CLK_L18

HT_CPU_NB_CTL_H08 HT_CPU_NB_CTL_L08 HT_CPU_NB_CTL_H18 HT_CPU_NB_CTL_L18

R1201 301R2F-GPR1201 301R2F-GP

1 2

HT_RXCALP HT_TXCALP HT_RXCALN

Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25

AC24 AC25 AB25 AB24 AA24 AA25

Y22

Y23 W21 W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23 AA22

M22 M23

R21

R20

C23

A24

U1B

D4 C4 A3 B3 C2 C1 E5 F5

G5 G6 H5 H6

J6 J5 J7 J8 L5 L6

M8

L8

P7 M7 P5 M5 R8 P8 R6 R5 P4 P3

T4 T3

AE3

AD4

AE2 AD3 AD1 AD2

V5

W6

U5 U6 U8 U7

AA8

Y8

AA7

Y7 AA5 AA6

W5

Y5

RS880M-1-GP

4

U1A

HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N

HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N

HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N

HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N

HT_RXCALP HT_RXCALN

RS880M-1-GP

GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N

SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

PART 1 OF 6

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N

HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

HT_TXCALP HT_TXCALN

GFX_TX0P

GFX_TX0N

GFX_TX1P

GFX_TX1N

GFX_TX2P

GFX_TX2N

GFX_TX3P

GFX_TX3N

GFX_TX4P

GFX_TX4N

GFX_TX5P

GFX_TX5N

GFX_TX6P

GFX_TX6N

GFX_TX7P

GFX_TX7N

GFX_TX8P

GFX_TX8N

GFX_TX9P

GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

PCIE I/F GFX

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

PCE_CALRP PCE_CALRN

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24

HT_TXCALN

B25

A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

ALINK_NBTX_SBRX_C_P0

AD7

ALINK_NBTX_SBRX_C_N0

AE7

ALINK_NBTX_SBRX_C_P1

AE6

ALINK_NBTX_SBRX_C_N1

AD6

ALINK_NBTX_SBRX_C_P2

AB6

ALINK_NBTX_SBRX_C_N2

AC6

ALINK_NBTX_SBRX_C_P3

AD5

ALINK_NBTX_SBRX_C_N3

AE5

PCE_PCAL

AC8

PCE_NCAL

AB8

http://hobi-elektronika.net

HT_NB_CPU_CAD_H0 8 HT_NB_CPU_CAD_L0 8 HT_NB_CPU_CAD_H1 8 HT_NB_CPU_CAD_L1 8 HT_NB_CPU_CAD_H2 8 HT_NB_CPU_CAD_L2 8 HT_NB_CPU_CAD_H3 8 HT_NB_CPU_CAD_L3 8 HT_NB_CPU_CAD_H4 8 HT_NB_CPU_CAD_L4 8 HT_NB_CPU_CAD_H5 8 HT_NB_CPU_CAD_L5 8 HT_NB_CPU_CAD_H6 8 HT_NB_CPU_CAD_L6 8 HT_NB_CPU_CAD_H7 8 HT_NB_CPU_CAD_L7 8

HT_NB_CPU_CAD_H8 8 HT_NB_CPU_CAD_L8 8 HT_NB_CPU_CAD_H9 8 HT_NB_CPU_CAD_L9 8 HT_NB_CPU_CAD_H10 8 HT_NB_CPU_CAD_L10 8 HT_NB_CPU_CAD_H11 8 HT_NB_CPU_CAD_L11 8 HT_NB_CPU_CAD_H12 8 HT_NB_CPU_CAD_L12 8 HT_NB_CPU_CAD_H13 8 HT_NB_CPU_CAD_L13 8 HT_NB_CPU_CAD_H14 8 HT_NB_CPU_CAD_L14 8 HT_NB_CPU_CAD_H15 8 HT_NB_CPU_CAD_L15 8

HT_NB_CPU_CLK_H0 8 HT_NB_CPU_CLK_L0 8 HT_NB_CPU_CLK_H1 8 HT_NB_CPU_CLK_L1 8

HT_NB_CPU_CTL_H0 8 HT_NB_CPU_CTL_L0 8 HT_NB_CPU_CTL_H1 8 HT_NB_CPU_CTL_L1 8

R1202 301R2F-GPR1202 301R2F-GP

1 2

C1237 SCD1U10V2KX-5GPC1237 SCD1U10V2KX-5GP

1 2

C1238 SCD1U10V2KX-5GPC1238 SCD1U10V2KX-5GP

1 2

C1239 SCD1U10V2KX-5GPC1239 SCD1U10V2KX-5GP

1 2

C1240 SCD1U10V2KX-5GPC1240 SCD1U10V2KX-5GP

1 2

C1241 SCD1U10V2KX-5GPC1241 SCD1U10V2KX-5GP

1 2

C1242 SCD1U10V2KX-5GPC1242 SCD1U10V2KX-5GP

1 2

C1243 SCD1U10V2KX-5GPC1243 SCD1U10V2KX-5GP

1 2

C1244 SCD1U10V2KX-5GPC1244 SCD1U10V2KX-5GP

1 2 1 2

1 2

R1203 1K27R2F-L-GPR1203 1K27R2F-L-GP R1204 2KR2F-3-GPR1204 2KR2F-3-GP

ALINK_NBTX_SBRX_P0 20 ALINK_NBTX_SBRX_N0 20 ALINK_NBTX_SBRX_P1 20 ALINK_NBTX_SBRX_N1 20 ALINK_NBTX_SBRX_P2 20 ALINK_NBTX_SBRX_N2 20 ALINK_NBTX_SBRX_P3 20 ALINK_NBTX_SBRX_N3 20

+1.1V_RUN

Place < 100mils from pin AC8 and AB8

3

A-LINK

Title

AMD-RS880M_HT LINK&PCIe(1/4)

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

12 90Thursday, May 27, 2010

1

A00

of

A00

5

SSID = N.B

RS880M : 71.RS880.M05

+1.1V_RUN

D D

+1.8V_RUN

C C

SC22U6D3V5MX-2GP

B B

A A

L1308

1 2

BLM15AG221SS1D-GP

220 ohm 300mA

-A00

R1323

1 2

0R0402-PAD

-A00

R1324

1 2

0R0402-PAD

R1325

1 2

0R0402-PAD

C1301

12

DY

CPU_LDT_STOP#10,20

ALLOW_LDTSTOP20

+1.8V_VDDA18HTPLL

+1.8V_VDDA18PCIEPLL

300R2J-4-GP

65mA

PLLVDD

SC2D2U6D3V3KX-GP

C1312

12

PLLVDD18

SC1U10V3KX-3GP

C1311

12

Layout Note Trace at least 15 mil

20mA

SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

C1302

12

DY

120mA

SCD1U10V2KX-5GP

SC2D2U6D3V3KX-GP

C1304

12

DY

12

R1309

R1322 0R2J-2-GP

U1301

1 2

SN74LVC2G07DCKR-GP

-A00

R1316 0R0402-PADR1316 0R0402-PAD

1 2

5

C1303

C1305

+1.8V_RUN+1.5V_RUN

1 2

DY

1A GND 2A32Y

6

1Y

5

SCD1U10V2KX-5GP

4

+1.8V_RUN

12

SCD1U10V2KX-5GP

12

R1315

R1315 1KR2J-1-GP

1KR2J-1-GP

NB_ALLOW_LDTSTOP

VCC

ALLOW_LDTSTOP: 1 = LDTSTOP# can be asserted 0 = LDTSTOP# has to be de-asserted

UMA: DAC_CLK and DATA with 5V-tolerant.not need level shift

12

R1311

R1311 2K2R2J-2-GP

2K2R2J-2-GP

NB_LDT_STOP#

C1314

4

-A00

R1342

1 2

0R0603-PAD-1-GP

+1.8V_RUN

M_RED55 M_GREEN55 M_BLUE55

Trace at least 10 mil

LDDC_CLK54 LDDC_DATA54

4

+3.3V_RUN_AVDD+3.3V_RUN

12

C1307

C1307 SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C1306

C1306 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C1308

C1308 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

X00

1 2

R1326 150R2F-1-GPR1326 150R2F-1-GP

1 2

R1327 150R2F-1-GPR1327 150R2F-1-GP

1 2

R1328 150R2F-1-GPR1328 150R2F-1-GP

PLTRST#_NB_GPU20

NB_PWRGD_IN41

X01

+3.3V_RUN

4

RN1302

RN1302 SRN4K7J-8-GP

SRN4K7J-8-GP

1

2 3

12

R1318

R1318 2KR2J-1-GP

2KR2J-1-GP

3

110mA

20mA

4mA

TV_OUT

VGA_HSYNC55 VGA_VSYNC55 DDC_CLK_CON55 DDC_DATA_CON55

CLK_NBHT_CLK20 CLK_NBHT_CLK#20

X01

RN1303

SRN4K7J-8-GP

NB_REFCLK_P20 NB_REFCLK_N20

NB_GPPSB_CLK20 NB_GPPSB_CLK#20

VGA_HSYNC VGA_VSYNC DDC_CLK_CON DDC_DATA_CON

R1306

1 2

715R2F-GP

+1.8V_VDDA18HTPLL +1.8V_VDDA18PCIEPLL

NB_LDT_STOP# NB_ALLOW_LDTSTOP

TP1307TP1307 TP1308TP1308

TP1301TP1301 TP1302TP1302 TP1303TP1303 TP1304TP1304

TP1305TP1305

1 2

R1319 150R2F-1-GPR1319 150R2F-1-GP

NB_GFX_CLK

NB_GFX_CLK#

4

1

2 3

DAC_RSET PLLVDD

PLLVDD18

NB_GFX_CLK NB_GFX_CLK#

NB_GPP_CLK

1

NB_GPP_CLK#

1

TP_NB_DDC_DATA0

1

TP_NB_DDC_CLK0

1

TP_NB_DDC_CLK1

1

TP_NB_DDC_DATA1

1

TP_STRP_DATA TP_NB_RESERVED

1

RS780_AUX_CAL

http://hobi-elektronika.net

3

+3.3V_RUN

3KR2J-2-GP

12

3KR2J-2-GP

12

DY

U1C

F12

AVDD1

E12

AVDD2

F14

AVDDDI

G15

AVSSDI

H15

AVDDQ

H14

AVSSQ

E17

C_Pr

F17

Y

F15

COMP_Pb

G18

RED

G17

REDb

E18

GREEN

F18

GREENb

E19

BLUE

F19

BLUEb

A11

DAC_HSYNC

B11

DAC_VSYNC

F8

DAC_SCL

E8

DAC_SDA

G14

DAC_RSET

A12

PLLVDD

D14

PLLVDD18

B12

PLLVSS

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESET#

A10

POWERGOOD

C10

LDTSTOP#

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN

F11

REFCLK_N

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP

V3

GPPSB_REFCLKN

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N

A8

DDC_CLK0/AUX0P

B7

DDC_CLK1/AUX1P

A7

DDC_DATA1/AUX1N

B10

STRP_DATA

G11

RESERVED

C8

AUX_CAL

RS880M-1-GP

3KR2J-2-GP

R1302

3KR2J-2-GP

R1304

DY

12

R1303

R1305

20mA

120mA

VGA_VSYNC VGA_HSYNC

PART 3 OF 6

NB_SUS_STAT#

2

STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use VGA_VSYNC)

Enables debug bus access through memory I/O pads and GPIOs. 1 : Disable

*

0 : Enable

SIDE_PORT_EN# ( RS880M use VGA_HSYNC)

*

1 = Memory Side port Not available 0 = Memory Side port available

LOAD_EEPROM_STRAPS#(RS880M use SUS_STAT#)

Selects Loading of STRAPS From EEPROM 1 : use Default Values

*

0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected

*DEFAULT

CRT/TVOUT

PM

CLOCKs PLL PWR

MIS.

LVTM

LVDS_ENA_BL

THERMALDIODE_P THERMALDIODE_N

+3.3V_RUN

R1314

R1314 4K7R2J-2-GP

4K7R2J-2-GP

1 2 12

R1321

R1321 3KR2J-2-GP

3KR2J-2-GP

DY

2

TXOUT_L0P TXOUT_L0N TXOUT_L1P TXOUT_L1N TXOUT_L2P TXOUT_L2N TXOUT_L3P TXOUT_L3N

TXOUT_U0P TXOUT_U0N TXOUT_U1P TXOUT_U1N TXOUT_U2P TXOUT_U2N TXOUT_U3P TXOUT_U3N

TXCLK_LP

TXCLK_LN TXCLK_UP TXCLK_UN

VDDLTP18

VSSLTP18

VDDLT18_1 VDDLT18_2 VDDLT33_1 VDDLT33_2

VSSLT1 VSSLT2 VSSLT3 VSSLT4 VSSLT5 VSSLT6 VSSLT7

LVDS_DIGON

LVDS_BLON

TMDS_HPD

HPD

SUS_STAT#

TESTMODE

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

VDDLTP18_R

A13 B13

VDDLT18_R

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

LCDVDD_EN_R

E9

BLON_R

F7

LVDS_BLEN

G12

TMDS_HPD

D9 D10

NB_SUS_STAT#

D12 AE8

AD8

TESTMODE_NB

D13

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

VGA_TXAOUT0+ 54 VGA_TXAOUT0- 54 VGA_TXAOUT1+ 54 VGA_TXAOUT1- 54 VGA_TXAOUT2+ 54 VGA_TXAOUT2- 54

VGA_TXACLK+ 54 VGA_TXACLK- 54

15mA

300mA

C1313

SC4D7U6D3V3KX-GP

C1313

SC4D7U6D3V3KX-GP

C1310

SCD1U10V2KX-5GP

C1310

SCD1U10V2KX-5GP

12

HPD

AMD-RS880M_LVDS&CRT_(2/4)

SC1U10V3KX-3GP

C1309

12

DY

R1332 0R0402-PADR1332 0R0402-PAD

1 2

R1331 0R0402-PADR1331 0R0402-PAD

1 2

R1308 0R0402-PADR1308 0R0402-PAD

1 2

RN1301

1

4

2 3

SRN4K7J-8-GP

1

TP1311TP1311

1

TP1306TP1306

1 2

R1317 0R0402-PADR1317 0R0402-PAD

1K8R2F-GP

12

R1320

Ansenal DJ1 AMD UMA

1

220 ohm 300mA

L1305

1 2

BLM15AG221SS1D-GP

R1329

1 2

0R0603-PAD-1-GP

LCDVDD_EN 54 LBKLT_CTL 54 PANEL_BKEN 37

+1.8V_RUN

-A00

X00

SUS_STAT# 21

-A00

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

13 90Thursday, May 27, 2010

1

A00

5

4

3

2

1

SSID = N.B

D D

U1D

AB12

MEM_A0

AE16

MEM_A1

V11

MEM_A2

AE15

MEM_A3

AA12

MEM_A4

AB16

MEM_A5

AB14

MEM_A6

AD14

MEM_A7

AD13

MEM_A8

AD15

MEM_A9

AC16

C C

AE13 AC14

AD16 AE17 AD17

W12

AD18 AB13 AB18

W14

AE12 AD12

Y14

Y12

V14 V15

MEM_A10 MEM_A11 MEM_A12 MEM_A13

MEM_BA0 MEM_BA1 MEM_BA2

MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT

MEM_CKP MEM_CKN

MEM_COMPP MEM_COMPN

RS880M-1-GP

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC MEM_DQ1/DVO_HSYNC

MEM_DQ2/DVO_DE

MEM_DQ3/DVO_D0

MEM_DQ4 MEM_DQ5/DVO_D1 MEM_DQ6/DVO_D2 MEM_DQ7/DVO_D4 MEM_DQ8/DVO_D3 MEM_DQ9/DVO_D5

MEM_DQ10/DVO_D6 MEM_DQ11/DVO_D7

MEM_DQ12

MEM_DQ13/DVO_D9 MEM_DQ14/DVO_D10 MEM_DQ15/DVO_D11

MEM_DQS0P/DVO_IDCKP MEM_DQS0N/DVO_IDCKN

MEM_DQS1P

MEM_DQS1N

MEM_DM0

MEM_DM1/DVO_D8

SBD_MEM/DVO_I/F

IOPLLVDD18

IOPLLVDD IOPLLVSS

MEM_VREF

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

15mA

+1.8V_RUN +1.1V_RUN

26mA

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

AMD-RS880M_SidePort_(3/4)

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

14 90Thursday, May 13, 2010

1

of

A00

5

4

3

2

1

SSID = N.B

D D

+1.1V_RUN

R1501

1 2

0R0603-PAD-1-GP

+1.1V_RUN

R1502

1 2

0R0603-PAD-1-GP

C C

+1.1V_RUN

+1.8V_RUN

B B

+1.8V_RUN

40 mils

SC4D7U6D3V3KX-GP

C1501

12

40 mils

SC4D7U6D3V3KX-GP

C1511

12

20 mils

SC4D7U6D3V3KX-GP

C1514

12

40 mils

SC4D7U6D3V3KX-GP

C1528

12

DY

15 mils

SCD1U10V2KX-5GP

C1534

12

DY

1.1V(0.6A) for VDDHT

+1.1V_RUN_VDDHT

SCD1U10V2KX-5GP

C1502

12

DY

SCD1U10V2KX-5GP

C1507

12

SCD1U10V2KX-5GP

C1515

12

SC4D7U6D3V3KX-GP

C1529

12

SCD1U10V2KX-5GP

C1506

C1503

12

SCD1U10V2KX-5GP

C1512

12

SCD1U10V2KX-5GP

C1516

12

DY

SCD1U10V2KX-5GP

C1530

12

C1503

C1513

C1517

C1531

12

DY

1.1V(0.7A) for VDDHTRX

+1.1V_RUN_VDDHTRX

SCD1U10V2KX-5GP

12

DY

1.2V(0.4A) for VDDHTTX

SCD1U10V2KX-5GP

12

1.8V(0.7A) for VDDA18PCIE

SCD1U10V2KX-5GP

12

1.8V(0.01A) for VDD18

SCD1U10V2KX-5GP

C1518

12

SCD1U10V2KX-5GP

C1532

12

1207

U1E

J17

VDDHT_1

K16 L16

M16

P16 R16 T16

H18 G19 F20 E21 D22 B23 A23

AE25 AD24 AC23 AB22 AA21

Y20

W19

V18 U17 T17 R17 P17

M17

J10 P10 K10

C1533

12

M10

L10

W9 T10

R10 AA9

AB9

AD9

AE9 U10

AE11 AD11

H9

Y9

F9

G9

VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1 VDD18_MEM2

RS880M-1-GP

PART 5/6

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

POWER

VDD_MEM1

VDD_MEM2

VDD_MEM3

VDD_MEM4

VDD_MEM5

VDD_MEM6

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD33_1 VDD33_2

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

SPM DIS

1.1V(2.5A) for VDDPCIE

SCD1U10V2KX-5GP

C1543

12

DY

0.95~1.1V(10A) for VDDC

SCD1U10V2KX-5GP

C1519

12

DY

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C1544

12

DY

SCD1U10V2KX-5GP

C1520

12

DY

C1509

C1521

SPM DIS

3.3V(0.06A) for VDD33

SCD1U10V2KX-5GP

C1535

C1536

12

C1536

12

+1.1V_RUN_VDDPCIE

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

C1510

12

SC1U6D3V2KX-GP

C1522

12

130 mils

C1505

12

550 mils

SCD1U10V2KX-5GP

C1523

12

15 mils

Layout Note

GAP-CLOSE-PWR

+NB_VCORE

SCD1U10V2KX-5GP

C1525

C1524

12

+1.1V_RUN

G1501

1 2

G1502

1 2

G1503

1 2

G1504

1 2

+NB_VDDC

SC4D7U6D3V3KX-GP

C1526

12

SC4D7U6D3V3KX-GP

C1527

12

+3.3V_RUN

M20 N22

R19 R22 R24 R25 H20 U22

W22 W24 W25

AD25

M14 N13

R11 R14

U14 U11 U15

W11

W15 AC12 AA14

AB11 AB15 AB17 AB19 AE20 AB21

A25 D23 E22 G22 G24 G25 H19

L17 L22 L24 L25

P20

V19

Y21

L12

P12 P15

T12

V12

Y18

K11

J22

U1F

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

RS880M-1-GP

PART 6/6

GROUND

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

Layout Note

1020 Noise coupling for NB

+1.1V_RUN+NB_VDDC

R1507

1 2

0R3J-0-U-GP

R1508

1 2

0R3J-0-U-GP

A A

http://hobi-elektronika.net

5

4

3

0R3J-0-U-GP

R1509

1 2

0R3J-0-U-GP

R1510

1 2

0R3J-0-U-GP

R1511

1 2

0R3J-0-U-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

AMD-RS880M_PWR&GD_(4/4)

Size Document Number Rev

A3

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

15 90Thursday, May 13, 2010

1

A00

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Ansenal DJ1 AMD UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

16 90Thursday, May 13, 2010

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Ansenal DJ1 AMD UMA

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

17 90Thursday, May 13, 2010

of

A00

5

MEM_MA_ADD[0..15]9

D D

MEM_MA_BANK29 MEM_MA_BANK09

MEM_MA_BANK19

M_A_DQ[63..0]9

C C

M_A_DQS#09 M_A_DQS#19 M_A_DQS#29 M_A_DQS#39

B B

+V_DDR_REF

SCD01U50V3KX-4GP

C1811

C1810

12

Place these caps close to VTT1 and

A A

VTT2.

C1801

SC22U6D3V5MX-2GP

M_A_DQS#49 M_A_DQS#59 M_A_DQS#69 M_A_DQS#79

M_A_DQS09 M_A_DQS19 M_A_DQS29 M_A_DQS39 M_A_DQS49 M_A_DQS59 M_A_DQS69 M_A_DQS79

MEM_MA0_ODT09 MEM_MA0_ODT19

SCD1U10V2KX-5GP

12

DDR3_A_DRAMRST#9

12

C1819

SC4D7U6D3V3KX-GP

DY

C1820

SCD1U10V2KX-5GP

+0.75V_DDR_VTT

12

C1821

SCD1U10V2KX-5GP

DY

C1822

12

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

SCD1U16V2KX-3GP

12

DY

4

98 97 96 95 92 91 90 86 89 85

107

84 83

119

80 78 79

109 108

5

7 15 17

4

6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70

129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

10 27 45 62

135 152 169 186

12 29 47 64

137 154 171 188

116 120

126

1 30

203 204

DM1

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

BA0 BA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12

2mA

DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

ODT0 ODT1

VREF_CA

18uA

VREF_DQ RESET#

VTT1

500mA

VTT2

DDR3-204P-41-GP-U

62.10017.N41

62.10017.P41 H =5.2mm

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104

M_A_DM0

11

DM0

M_A_DM1

28

DM1

M_A_DM2

46

DM2

M_A_DM3

63

DM3

M_A_DM4

136

DM4

M_A_DM5

153

DM5

M_A_DM6

170

DM6

M_A_DM7

187

DM7

200

SDA

202

SCL

PM_EXTTS#0

198 199 197

SA0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

3.5A

+1.5V_SUS

MEM_MA_RAS# 9 MEM_MA_WE# 9 MEM_MA_CAS# 9

MEM_MA0_CS#0 9 MEM_MA0_CS#1 9

MEM_MA_CKE0 9 MEM_MA_CKE1 9

MEM_MA_CLK0_P 9 MEM_MA_CLK0_N 9

MEM_MA_CLK1_P 9 MEM_MA_CLK1_N 9

M_A_DM[7..0] 9

SB_SMBDATA 19,21,76 SB_SMBCLK 19,21,76

Layout Note: Place these Caps near SO-DIMMA.

SCD1U10V2KX-5GP

C1802

12

+3.3V_RUN

SODIMM A DECOUPLING (ONE CAP PER POWER PIN)

+1.5V_SUS

C1806

C1805

C1804

C1812

SCD1U10V2KX-5GP

SC10U10V5ZY-1GP

DY

12

C1813

C1814

SC10U10V5ZY-1GP

12

DY

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

PM_EXTTS#0

C1809

C1808

C1807

C1815

SCD1U10V2KX-5GP

12

C1816

C1817

SC10U10V5ZY-1GP

12

DY

12

DY

1 2

DY

X01

12

TC1801

TC1801 SE330U2VDM-L-GP

SE330U2VDM-L-GP

2

+1.5V_SUS

R18064K7R 2J-2-GPDYR18064K7R 2J-2-GP

1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

5

4

3

2

http://hobi-elektronika.net

Size Document Number Rev

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-SODIMM1

Ansenal DJ1 AMD UMA

1

18 90Thursday, May 27, 2010

A00

of

5

MEM_MB_ADD[0..15]9

D D

C C

B B

+V_DDR_REF

Place these caps close to VTT1 and VTT2.

MEM_MB_BANK29 MEM_MB_BANK09

MEM_MB_BANK19

M_B_DQ[63..0]9

M_B_DQS#09 M_B_DQS#19 M_B_DQS#29 M_B_DQS#39 M_B_DQS#49 M_B_DQS#59 M_B_DQS#69 M_B_DQS#79

M_B_DQS09 M_B_DQS19 M_B_DQS29 M_B_DQS39 M_B_DQS49 M_B_DQS59 M_B_DQS69 M_B_DQS79

MEM_MB0_ODT09

SCD01U50V3KX-4GP

MEM_MB0_ODT19

C1905

SCD1U10V2KX-5GP

C1905

SCD1U10V2KX-5GP

C1904

12

C1901

DDR3_B_DRAMR ST#9

+0.75V_DDR_VTT

12

C1918

SC22U6D3V5MX-2GP

DY

12

C1919

C1920

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

DY

C1921

12

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

SCD1U16V2KX-3GP

12

DY

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

62.10017.N11

62.10017.N61

500mA

DDR3-204P-40-GP-U

2mA

18uA

EVENT#

VDDSPD

NC#/TEST

VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

RAS# CAS# CS0#

CS1# CKE0

CKE1

CK0#

CK1#

NC#1 NC#2

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

NP1

NP2

110 113

WE#

115 114

121 73

74 101

CK0

103 102

CK1

104

M_B_DM0

11

DM0

M_B_DM1

28

DM1

M_B_DM2

46

DM2

M_B_DM3

63

DM3

M_B_DM4

136

DM4

M_B_DM5

153

DM5

M_B_DM6

170

DM6

M_B_DM7

187

DM7

200

SDA

202

SCL

PM_EXTTS#1

198 199 197

SA0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

3.5A

+1.5V_SUS

MEM_MB_RAS# 9 MEM_MB_WE# 9 MEM_MB_CAS# 9

MEM_MB0_CS#0 9 MEM_MB0_CS#1 9

MEM_MB_CKE0 9 MEM_MB_CKE1 9

MEM_MB_CLK0_P 9 MEM_MB_CLK0_N 9

MEM_MB_CLK1_P 9 MEM_MB_CLK1_N 9

M_B_DM[7..0] 9

SB_SMBDATA 18,21,76 SB_SMBCLK 18,21,76

+3.3V_RUN

3

C1902

SCD1U10V2KX-5GP

C1902

SCD1U10V2KX-5GP

12

SO-DIMMB is placed farther from the Processor than SO-DIMMA

Layout Note: Place these Caps near SO-DIMMB.

+3.3V_RUN

C1906

C1912

+1.5V_SUS

12

SCD1U10V2KX-5GP

SC10U10V5ZY-1GP

12

DY

2

+1.5V_SUS

PM_EXTTS#1

1 2

DY

R19064K7R2J-2-GPDYR19064K7R2J-2-GP

SODIMM B DECOUPLING (ONE CAP PER POWER PIN)

C1907

C1913

12

C1908

C1909

SCD1U10V2KX-5GP

C1914

C1915

SC10U10V5ZY-1GP

12

DY

12

C1911

C1910

SCD1U10V2KX-5GP

C1917

C1916

SC10U10V5ZY-1GP

12

DY

1

H = 9.2mm

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichi h, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

5

4

3

2

http://hobi-elektronika.net

Size Document Number Rev

Date: Sheet of

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-SODIMM2

Ansenal DJ1 AMD UMA

1

19 90Thursday, May 27, 2010

A00

of

5

SSID = S.B

SB700 A12 : 71.SB820.M02

D D

Place R <100mils form pins AD29,AD28

LAN

WLAN

C C

X01

B B

A A

C2014

SC12P50V2JN-3GP

C2001 SC150P50V2KX-GPC2001 SC150P50V2KX-GP

1 2

ALINK_NBRX_SBTX_P012 ALINK_NBRX_SBTX_N012 ALINK_NBRX_SBTX_P112 ALINK_NBRX_SBTX_N112 ALINK_NBRX_SBTX_P212 ALINK_NBRX_SBTX_N212 ALINK_NBRX_SBTX_P312 ALINK_NBRX_SBTX_N312

ALINK_NBTX_SBRX_P012 ALINK_NBTX_SBRX_N012 ALINK_NBTX_SBRX_P112 ALINK_NBTX_SBRX_N112 ALINK_NBTX_SBRX_P212 ALINK_NBTX_SBRX_N212 ALINK_NBTX_SBRX_P312 ALINK_NBTX_SBRX_N312

+1.1V_RUN_PCIE_VDDR

PCIE_TXP176

PCIE_TXN176

PCIE_TXP076

PCIE_TXN076

X02

NOTE: SB8XX ONLY SUPPORTS 2 GPP PORT 2 AND 3 IS NOT SUPPORTED. (From CRB)

NB_GPPSB_CLK13 NB_GPPSB_CLK#13

NB_REFCLK_P13 NB_REFCLK_N13

CLK_NBHT_CLK13 CLK_NBHT_CLK#13

CPU_CLK10 CPU_CLK#10

CLK_PCIE_MINI176 CLK_PCIE_MINI1#76

CLK_PCIE_LAN76 CLK_PCIE_LAN#76

CLK_48M_CARD32

1nd 82.30020.851 2nd 82.30020.791

R2017 1MR2J-1-GPR2017 1MR2J-1-GP

1 2

X2001

1 2

XTAL-25MHZ-102-GP

12

5

R2024 22R2J-2-GPR2024 22R2J-2-GP

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2003 SCD1U10V2KX-5GPC2003 SCD1U10V2KX-5GP

1 2

C2004 SCD1U10V2KX-5GPC2004 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2007 SCD1U10V2KX-5GPC2007 SCD1U10V2KX-5GP

1 2

C2008 SCD1U10V2KX-5GPC2008 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

LAN

WLAN

12

C2015

C2015 SC12P50V2JN-3GP

SC12P50V2JN-3GP

1 2

R2002 590R2F-GPR2002 590R2F-GP R2007 2KR2F-3-GPR2007 2KR2F-3-GP

1 2 1 2 1 2 1 2

PCIE_RXP176 PCIE_RXN176 PCIE_RXP076 PCIE_RXN076

RN2001

2 3

SRN0J-6-GP

1

RN2002

2 3

SRN22-3-GP

1

RN2003

2 3

SRN0J-6-GP

1

RN2004

2 3

SRN0J-6-GP

1

TP2012TP2012 TP2013TP2013

RN2005

2 3

SRN0J-6-GP

1

RN2006

2 3

SRN0J-6-GP

1

R2019 22R2J-2-GPR2019 22R2J-2-GP

1 2

25M_X1

25M_X2

1 2 1 2

C2018SCD1U10V2KX-5GP C2018SCD1U10V2KX-5GP C2019SCD1U10V2KX-5GP C2019SCD1U10V2KX-5GP C2020SCD1U10V2KX-5GP C2020SCD1U10V2KX-5GP C2021SCD1U10V2KX-5GP C2021SCD1U10V2KX-5GP

ALINK_NBRX_SBTX_C_P0 ALINK_NBRX_SBTX_C_N0 ALINK_NBRX_SBTX_C_P1 ALINK_NBRX_SBTX_C_N1 ALINK_NBRX_SBTX_C_P2 ALINK_NBRX_SBTX_C_N2 ALINK_NBRX_SBTX_C_P3 ALINK_NBRX_SBTX_C_N3

SB_PCIE_CLK SB_PCIE_CLK#

4

DISP_CLKP_R DISP_CLKN_R

4

CLK_NBHT_CLK_R CLK_NBHT_CLK#_R

4

CPU_HT_CLK CPU_HT_CLK#

4

CLK_NB_GFX_SB

1

CLK_NB_GFX#_SB

1

CLK_MINI1_R CLK_MINI1#_R

4

LAN_CLK_R LAN_CLK#_R

4

PCIE_RST#_SB

A_RST#_RA_RST#

SB_PCIE_CALRP SB_PCIE_CALRN

PCIE_C_TXP1

PCIE_C_TXN1

PCIE_C_TXP0

PCIE_C_TXN0

OSC_CLK

25M_X1

25M_X2

4

U2A

P1

PCIE_RST#

L1

A_RST#

AD26

A_TX0P

AD27

A_TX0N

AC28

A_TX1P

AC29

A_TX1N

AB29

A_TX2P

AB28

A_TX2N

AB26

A_TX3P

AB27

A_TX3N

AE24

A_RX0P

AE23

A_RX0N

AD25

A_RX1P

AD24

A_RX1N

AC24

A_RX2P

AC25

A_RX2N

AB25

A_RX3P

AB24

A_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

SB820M-1-GP

3

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT3#/CLK_REQ7#/GPIO46

LDRQ1#/CLK_REQ6#/GPIO49

ALLOW_LDTSTP/DMA_ACTIVE#

CLOCK GENERATOR

CPU

RTC

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

FRAME#

DEVSEL#

REQ1#/GPIO40

PCI INTERFACELPC

GNT1#/GPO44 GNT2#/GPO45

CLKRUN#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LFRAME#

SERIRQ/GPIO48

PROCHOT#

LDT_STP# LDT_RST#

INTRUDER_ALERT#

VDDBT_RTC_G

CBE0# CBE1# CBE2# CBE3#

IRDY#

TRDY#

PAR STOP# PERR# SERR# REQ0#

GNT0#

LOCK#

LAD0 LAD1 LAD2 LAD3

LDRQ0#

LDT_PG

32K_X1 32K_X2

RTCCLK

http://hobi-elektronika.net

3

W2 W1 W3

PCI_CLK3_R

W4 Y1

PCI_RST#

V2

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4

SB_GPIO42

AC12 AD12 AJ5 AH6

SB_GPIO46

AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

H24 H25

LPC_LAD0_R

J27

LPC_LAD1_R

J26

LPC_LAD2_R

H29

LPC_LAD3_R

H28 G28

TP_LPC_LDRQ0#

J25

TP_LPC_LDRQ1#

AA18 AB19

G21 H21 K19 G22 J24

32K_X1

C1

32K_X2_R

C2

RTC_CLK

D2

INTRUDER_ALERT#

B2 B1

R2009 22R2J-2-GPR2009 22R2J-2-GP

1

TP2008TP2008

SB_GPIO_PCIE_RST#21

PCIE_RST#_SB

SB_GPIO28

1

SB_GPIO29

1

SB_GPIO_A_RST#21

1

RN2009 SRN33J-4-GPRN2009 SRN33J-4-GP

1

1 2

1'nd 73.01G08.DHG 2'nd 73.01G08.L04

PCI_AD23 24 VDDR_SEL 24,51 PCI_AD25 24 PCI_AD26 24 PCI_AD27 24

TP2010TP2010 TP2011TP2011

1'nd 73.01G08.DHG 2'nd 73.01G08.L04

A_RST#

TP2003TP2003

TP2004TP2004

RN2008

RN2008 SRN22-3-GP

SRN22-3-GP

2 3 1

1 2 3 4 5

1 1

4 8

7 6

X01

TP2005TP2005 TP2006TP2006

INT_SERIRQ 37

ALLOW_LDTSTOP 13

CPU_PROCHOT# 10 CPU_LDT_PWRGD 10,42 CPU_LDT_STOP# 10,13 CPU_LDT_RST# 10

1 2

R2018 10R2J-2-GPR2018 10R2J-2-GP

TP2007TP2007

SCD1U10V2KX-5GP

C2017

12

DY

2

X01

U2002

SNLVC1G08DCKRG4-GP

1

A

VCC

2

B

DY

GND3Y

U2001

SNLVC1G08DCKRG4-GP

1

A

2

B

DY

GND3Y

1 2

R2021

R2021 0R0402-PAD

0R0402-PAD

LPC Bus Routing first connects to MINICARD then connects to KBC

RTCCLK_KBC 37 RTC_CLK 39

+RTC_CELL

2

PCI_CLK1 24 PCI_CLK2 24 PCI_CLK3 24,70 PCLK_FWH 24

5

4

12

R202533R2J-2-GP R202533R2J-2-GP

+3.3V_ALW

5

VCC

4

PM_CLKRUN# 37

PCLK_KBC 24,37 LPCCLK1 24

LPC_LAD0 37 LPC_LAD1 37 LPC_LAD2 37 LPC_LAD3 37

LPC_LFRAME# 37,70

STRAP PIN

X01

C2013

C2013 SC150P50V2KX-GP

SC150P50V2KX-GP

1 2

SCD1U10V2KX-4GP

C2010

12

DY

PLTRST#

32K_X1

32K_X2_R 32K_X2

Main Source

Title

SB820M_PCIE&PCI_(1/5)

Size Document Number Rev

A3

Date: Sheet

placed CAP closed SB820M

X01

+3.3V_RUN+3.3V_ALW

12

R2026

R2026 10KR2J-3-GP

10KR2J-3-GP

R2028

12

DY

0R2J-2-GP

R2005 0R0402-PADR2005 0R0402-PAD

1 2

R2008 0R0402-PADR2008 0R0402-PAD

1 2

LPC_LAD0_R 70 LPC_LAD1_R 70 LPC_LAD2_R 70 LPC_LAD3_R 70

12

R2014

20MR3-GP

R2016

1 2

0R0402-PAD

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

1

PCI_CLK3

EC2002

PLTRST#_LAN_WLAN 70,76

PLTRST#_NB_GPU 13

PLTRST#_EC 37

X01

1 2

SC18P50V2JN-1-GP

4

1

2 3

X2002

X-32D768KHZ-38GPU

1 2

SC18P50V2JN-1-GP

20 90Thursday, May 27, 2010

1

12

DY

SC10P50V2JN-4GP

NB

KBC

C2011

C2012

of

A00

5

4

3

2

1

USB

SSID = S.B

+3.3V_RUN

RN2101

1 2 3

SRN2K2J-1-GP

D D

+3.3V_ALW

C C

B B

+3.3V_ALW

A A

SRN2K2J-1-GP

1 2

RN2103

1

4

2 3

SRN10KJ-5-GP

R2134

DY

DY DY

DY

DY DY

DY

DY DY

DY

1 2

DY

R2124

10KR2J-3-GP

TP_SB_GPIO64 TP_SB_GPIO63

USB_OC#2_3 USB_OC#0_1

R2134

4K7R2J-2-GP

R2108

R2108 2K2R2J-2-GP

2K2R2J-2-GP R2110

R2110 2K2R2J-2-GP

2K2R2J-2-GP R2112

R2112 2K2R2J-2-GP

2K2R2J-2-GP R2113

R2113 10KR2J-3-GP

10KR2J-3-GP R2114

R2114 10KR2J-3-GP

10KR2J-3-GP R2115

R2115 10KR2J-3-GP

10KR2J-3-GP R2116

R2116 10KR2J-3-GP

10KR2J-3-GP R2117

R2117 10KR2J-3-GP

10KR2J-3-GP

R2118

R2118 10KR2J-3-GP

10KR2J-3-GP R2119

R2119 10KR2J-3-GP

10KR2J-3-GP R2127

R2127 1KR2J-1-GP

1KR2J-1-GP

Close SB

1 2

1 2 1 2 1 2

C2101 SCD1U10V2KX-5GP

4

R2135

10KR2J-3-GP

KBC_RSMRST#

SIO_EXT_WAKE#

SIO_EXT_SCI#

SIO_EXT_SMI#

SB_SDIN_CODEC ACZ_BIT_CLK SP_VRAM_SEL

PM_RSMRST#_R

RN2102

1 2 3 4 5

SRN10KJ-6-GP

1 2

RN2104

1 2 3

SRN10KJ-5-GP

TP2121TP2121

1

TP2122TP2122

1

TP2134TP2134

1

TP2135TP2135

1

5

SB_SMBCLK SB_SMBDATA

MINI1_CLK_REQ#

SMB_DATA

SMB_CLK

TALERT#

SB_TEST2

SB_TEST1

SB_TEST0

PCIE_WAKE#

GBE_MDIO

8

GBE_CRS

7

GBE_COL

6

GBE_RXERR

GBE_PHY_INTR

SCL2

4

SDA2

JTAG_TDI JTAG_RST#

X01

DY

X00

SB_AZ_CODEC_BITCLK30 SB_AZ_CODEC_SDOUT30

SB_AZ_CODEC_SYNC30 SB_AZ_CODEC_RST#30

SIO_RCIN#

12

C2105

SC180P50V2JN-1GP

SB_SDIN_CODEC30

GbE Controller Not Enabled

EC Not Implemented

SIO_EXT_WAKE#37

PM_SLP_S3#37,41,42,49,50,52,54 PM_SLP_S5#37,49

PM_PWRBTN#37 SB_PWRGD41 SUS_STAT#13

SIO_A20GATE37 SIO_RCIN#37 SIO_EXT_SCI#37 SIO_EXT_SMI#37

PCIE_WAKE#76

H_THERMTRIP#10,37,39,42

NB_PWRGD41

KBC_RSMRST#37

SB_GPIO_A_RST#20 SB_GPIO_PCIE_RST#20

ACZ_SPKR30 SB_SMBCLK18,19,76 SB_SMBDATA18,19,76

MINI1_CLK_REQ#76

TALERT#10,39

ACZ_SDATAOUT_R24

1 2 1 2

R2111

R2111 0R0402-PAD

0R0402-PAD

R2125

R2125 0R0402-PAD

0R0402-PAD R2126 0R0402-PADR2126 0R0402-PAD

1130

R2129 0R2J-2-GPR2129 0R2J-2-GP R2130 0R2J-2-GPR2130 0R2J-2-GP

USB_OC#2_363 USB_OC#0_163

33R2J-2-GPR2120 33R2J-2-GPR2120 33R2J-2-GPR2121 33R2J-2-GPR2121

33R2J-2-GPR2122 33R2J-2-GPR2122 33R2J-2-GPR2123 33R2J-2-GPR2123

4

TP2101TP2101

1 2

TP2120TP2120

1 2

DY

1 2

1 2 1 2

not use

TP2113TP2113 TP2118TP2118

SBD DDR RESET

TP2144TP2144

TP2138TP2138 TP2139TP2139

TP2137TP2137 TP2132TP2132 TP2133TP2133

TP2128TP2128 TP2131TP2131 TP2116TP2116 TP2117TP2117

TP_PCI_PME#

1

PM_PWRBTN#_R

R21060R0402-PAD R21060R0402-PAD

SB_TEST0

SB_TEST1 SB_TEST2

SYS_RESET#

1

SB_THERMTRIP#SB_THERMTRIP#

R21090R2J-2-GPDYR21090R2J-2-GP

PM_RSMRST#_R TP_SB_GPIO64

TP_SB_GPIO63

SB_GPIO_A_RST#_R

SB_GPIO_PCIE_RST#_R

12 12

SMB_CLK SMB_DATA

SP_VRAM_SEL

MINI1_CLK_REQ#

SB_GPIO51

1

GEVENT7#

1

SB_OSCIN

1

USB_OC7#

1

USB_OC6#

1

TALERT#

USB_OC4#

1

TP_JTAG_TDO

1

TP_JTAG_TCK

1

USB_OC#2_3 USB_OC#0_1

ACZ_BIT_CLK

ACZ_SYNC_R ACZ_RST#_R

GBE_COL GBE_CRS

GBE_MDIO

GBE_RXERR

GBE_PHY_INTR

TP_DEBUG_DAT

1

TP_DEBUG_CLK

1

SPI_CS2#

1

GPO160

1

SCL0 SDA0

U2D

J2

PCI_PME#/GEVENT4#

K1

RI#/GEVENT22#

D3

SPI_CS3#/GBE_STAT1/GEVENT21#

F1

SLP_S3#

H1

SLP_S5#

F2

PWR_BTN#

H5

PWR_GOOD

G6

SUS_STAT#

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0#

AE21

KBRST#/GEVENT1#

K2

LPC_PME#/GEVENT3#

J29

LPC_SMI#/GEVENT23#

H2

GEVENT5#

J1

SYS_RESET#/GEVENT19#

H6

WAKE#/GEVENT8#

F3

IR_RX1/GEVENT20#

J6

THRMTRIP#/SMBALERT#/GEVENT2#

AC19

NB_PWRGD

G1

RSMRST#

AD19

CLK_REQ4#/SATA_IS0#/GPIO64

AA16

CLK_REQ3#/SATA_IS1#/GPIO63

AB21

SMARTVOLT1/SATA_IS2#/GPIO50

AC18

CLK_REQ0#/SATA_IS3#/GPIO60

AF20

SATA_IS4#/FANOUT3/GPIO55

AE19

SATA_IS5#/FANIN3/GPIO59

AF19

SPKR/GPIO66

AD22

SCL0/GPIO43

AE22

SDA0/GPIO47

F5

SCL1/GPIO227

F4

SDA1/GPIO228

AH21

CLK_REQ2#/FANIN4/GPIO62

AB18

CLK_REQ1#/FANOUT4/GPIO61

E1

IR_LED#/LLB#/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN#/GPIO51

H4

DDR3_RST#/GEVENT7#

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9#

G5

GBE_LED2/GEVENT10#

K3

GBE_STAT0/GEVENT11#

AA20

CLK_REQG#/GPIO65/OSCIN/IDLEEXT#

H3

BLINK/USB_OC7#/GEVENT18#

D1

USB_OC6#/IR_TX1/GEVENT6#

E4

USB_OC5#/IR_TX0/GEVENT17#

D4

USB_OC4#/IR_RX0/GEVENT16#

E8

USB_OC3#/AC_PRES/TDO/GEVENT15#

F7

USB_OC2#/TCK/GEVENT14#

E7

USB_OC1#/TDI/GEVENT13#

F8

USB_OC0#/TRST#/GEVENT12#

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST#

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST#

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2#/GBE_STAT2/GPIO166

G29

FC_RST#/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

SB820M-1-GP

Part 4 of 5

HD AUDIO

GBE LAN

http://hobi-elektronika.net

3

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

GPIO

USB OC

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB_HSD13P USB_HSD13N

USB 1.1USB MISCEMBEDDED CTRL

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9N

USB_HSD8N

USB_HSD7N

USB 2.0

USB_HSD6N

USB_HSD5N

USB_HSD4N

USB_HSD3N

USB_HSD2N

USB_HSD1N

USB_HSD0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217

KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

USB_FSD1N

USB_FSD0N

USB_HSD9P

USB_HSD8P

USB_HSD7P

USB_HSD6P

USB_HSD5P

USB_HSD4P

USB_HSD3P

USB_HSD2P

USB_HSD1P

USB_HSD0P

A10 G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

USB_48M_CLK USB_RCOMP

TP_USB_PP8 TP_USB_PN8

TP_USB_PP5 TP_USB_PN5

USB_PP3 USB_PN3

SCL2 SDA2

TP2145TP2145

1

1 2

R2102

R2102 11K8R2F-GP

11K8R2F-GP

USB_PP11 54 USB_PN11 54

USB_PP10 32 USB_PN10 32

TP2140TP2140

1

TP2141TP2141

1

TP2142TP2142

1

TP2143TP2143

1

TP2114TP2114

1

TP2115TP2115

1

USB_PP2 76 USB_PN2 76

USB_PP1 63 USB_PN1 63

USB_PP0 63 USB_PN0 63

USB_PP9 73 USB_PN9 73

USB_PP4 76 USB_PN4 76

Not use

CPU_SIC 10 CPU_SID 10

SB_GPO199 24 SB_GPO200 24

Strap Pin / define to use LPC or SPI ROM

EC Not Implemented

Title

SB820M_USB&GPIO_(2/5)

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

Ansenal DJ1 AMD UMA

Device

USB1 USB3

USB2 (I/O Board)

RESERVED

WLAN

RESERVED

BLUETOOTH

CARD READER

CAMERA

RESERVED

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

21 90Thursday, May 27, 2010

1

A00

SSID = S.B

XTAL 1'nd 82.30020.851

C2209

1 2

SC12P50V2JN-3GP

C2210

1 2

SC12P50V2JN-3GP

2'nd 82.30020.791

XTAL-25MHZ-102-GP

DY

XTAL-25MHZ-102-GP

12

DY

X2201

10MR2J-L-GP

12

R2204

DY

SATA HDD

SATA ODD

SATA_X1

SATA_X2

SATA_TXP059 SATA_TXN059

SATA_RXN059 SATA_RXP059

SATA_TXP159 SATA_TXN159

SATA_RXN159 SATA_RXP159

C2201 SCD01U16V2KX-3GPC2201 SCD01U16V2KX-3GP

1 2

C2202 SCD01U16V2KX-3GPC2202 SCD01U16V2KX-3GP

1 2

C2203 SCD01U16V2KX-3GPC2203 SCD01U16V2KX-3GP

1 2

C2204 SCD01U16V2KX-3GPC2204 SCD01U16V2KX-3GP

1 2

C2205 SCD01U16V2KX-3GPC2205 SCD01U16V2KX-3GP

1 2

C2206 SCD01U16V2KX-3GPC2206 SCD01U16V2KX-3GP

1 2

C2208 SCD01U16V2KX-3GPC2208 SCD01U16V2KX-3GP

1 2

C2207 SCD01U16V2KX-3GPC2207 SCD01U16V2KX-3GP

1 2

PLACE SATA AC DECOUPLING CAPS CLOSE TO SB820M

+1.1V_RUN_AVDD_SATA

SPI ROM in KBC side

Very Close to SB820

1KR2F-3-GP

R2201

1 2 1 2

R2202 931R2F-1-GPR2202 931R2F-1-GP

SATA_ACT#66

SATA_X1

SATA_X2

SATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C

SATA_TXP1_C SATA_TXN1_C

SATA_RXN1_C SATA_RXP1_C

SATA_CALP SATA_CALN

U2B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

AH10

SATA_TX1P

AJ10

SATA_TX1N

AG10

SATA_RX1N

AF10

SATA_RX1P

AG12

SATA_TX2P

AF12

SATA_TX2N

AJ12

SATA_RX2N

AH12

SATA_RX2P

AH14

SATA_TX3P

AJ14

SATA_TX3N

AG14

SATA_RX3N

AF14

SATA_RX3P

AG17

SATA_TX4P

AF17

SATA_TX4N

AJ17

SATA_RX4N

AH17

SATA_RX4P

AJ18

SATA_TX5P

AH18

SATA_TX5N

AH19

SATA_RX5N

AJ19

SATA_RX5P

AB14

SATA_CALRP

AA14

SATA_CALRN

AD11

SATA_ACT#/GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1#/GPIO165

G2

ROM_RST#/GPIO161

SB820M-1-GP

Part 2 of 5

SERIAL ATA

HW MONITOR

SPI ROM

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE#/GPIOD145

FC_AVD#/GPIOD146

FC_WE#/GPIOD148 FC_CE1#/GPIOD149 FC_CE2#/GPIOD150

FC_INT1/GPIOD144

FC_INT2/GPIOD147

FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136

FC_ADQ9/GPIOD137 FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

FLASH

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

TEMP_COMM VIN0/GPIO175

VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

NC#G27

NC2#Y2

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

W5 W6 Y9

W7 V9 W8

B6 A6 A5 B5 C7

A3 B4 A4 C5 A7 B7 B8 A8

G27 Y2

GPIOD[150:128] are open drain GPIO pins where as GPO160 is an open drain GPO pi n. These pins are not programmed to GPIO mode by default.

If use as GPIO, need to pull up to 1.8V_RUN

TEMPIN0 TEMPIN1 TEMPIN2 TEMPIN3

VIN0 VIN1 VIN2 VIN3 MEM_1V5 VIN5 VIN6 VIN7

suggest not use HW monitor

MEM_1V5 51

VIN3 VIN2 VIN1 VIN0

TEMPIN3 TEMPIN2 TEMPIN1 TEMPIN0

VIN5 VIN6 VIN7

1 2 3 4 5

RN2201

8 7 6

SRN10KJ-6-GP

RN2202

8 7 6

SRN10KJ-6-GP

SRN10KJ-6-GP RN2203

RN2203

8 7 6

SRN10KJ-6-GP

+3.3V_ALW

http://hobi-elektronika.net

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

SB820M_SATA-IDE_(3/5)

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

22 90Thursday, May 27, 2010

of

A00

5

4

3

2

1

SSID = S.B

+3.3V_RUN

0R0603-PAD-1-GP

D D

+1.8V_RUN

0R0603-PAD-1-GP

+3.3V_RUN

C C

+1.1V_RUN +1.1V_RUN_PCIE_VDDR

PBY160808T-330Y-N-GP

+3.3V_RUN

BLM15AG221SS1D-GP

220 ohm 300mA

+1.1V_RUN +1.1V_RUN_AVDD_SATA

1 2

PBY160808T-330Y-N-GP

B B

A A

PBY160808T-330Y-N-GP

+3.3V_ALW

+1.1V_ALW +1.1V_AVDD_USB

1 2

BLM15AG221SS1D-GP

220 ohm 300mA

WOL supported: Tied +3.3V_ALW not supported: Tied +3.3V_RUN

TBDmA

SCD1U10V2KX-4GP

DY

R2301

1 2

R2302

1 2

-A00

R2306

1 2

0R0402-PAD

L2303

1 2

33R 3A

L2304

1 2

L2305

33R 3A

L2309

SCD1U10V2KX-5GP

C2341

12

+3.3V_SB_VDDIO

+1.8V_SB_VDDIO_FC

+3.3V_VDDPL_PCIE

+3.3V_VDDPL_SATA

R2307

1 2

0R0402-PAD

C2342

12

5

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

TC2301

12

DY

SCD1U10V2KX-5GP

12

DY

SCD1U10V2KX-5GP

C2313

SC1U10V3KX-3GP

C2313

SC1U10V3KX-3GP

SC10U6D3V5KX-1GP

SC2D2U6D3V3KX-GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC2D2U6D3V3KX-GP

DY

12

DY

SC1U6D3V2KX-GP

TC2303

12

SCD1U10V2KX-5GP

C2325

12

DY

SC1U6D3V2KX-GP

TC2304

12

SC1U6D3V2KX-GP

C2337

12

SCD1U10V2KX-5GP

C2343

12

C2301

12

C2307

C2314

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

C2320

C2319

12

DY

C2326

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

C2330

C2331

12

DY

SC10U6D3V5KX-1GP

C2339

C2338

12

C2344

WOL supported: Tied +1.1V_ALW not supported: Tied +1.1V_RUN

62mA 47mA

1.1V_ALW_VDDPL 3.3V_RUN_VDDPL3.3V_ALW_VDDXL

C2303

C2302

12

DY

U2C

AH1

VDDIO_33_PCIGP

V6

VDDIO_33_PCIGP

Y19

71mA

43mA

600mA

SCD1U10V2KX-5GP

C2321

C2322

12

DY

93mA

567mA

SCD1U10V2KX-5GP

C2332

C2333

12

658mA

SC10U6D3V5KX-1GP

C2340

12

DY

AE5

AC21

AA2 AB4

AC8

AA7 AA9 AF7

AA19

AF22 AE25 AF24 AC22

AE28

U26 V22 V26 V27 V28

V29 W22 W26

AD14 AJ20

AF18 AH20

AG19

AE18 AD18 AE16

A18

A19

A20

B18

B19

B20

C18

C20

D18

D19

D20

E19

C11

D11

SB820M-1-GP

VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP VDDIO_33_PCIGP

VDDIO_18_FC VDDIO_18_FC VDDIO_18_FC VDDIO_18_FC

POWER

VDDPL_33_PCIE

VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE VDDAN_11_PCIE

VDDPL_33_SATA VDDAN_11_SATA

VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA VDDAN_11_SATA

VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S VDDAN_33_USB_S

VDDAN_11_USB_S VDDAN_11_USB_S

TBDmA

R2305

1 2

0R0402-PAD

+1.1V_ALW +3.3V_RUN+3.3V_ALW

4

-A00 -A00

C2349

SC1U10V3KX-3GP

C2349

SC1U10V3KX-3GP

12

131mA

SCD1U10V2KX-5GP

C2301

Part 3 of 5

PCI/GPIO I/O

FLASH I/O

GBE LAN

PCI EXPRESSSERIAL ATA

USB I/O

PLL CLKGEN I/O

SC1U10V3KX-3GP

N13

VDDCR_11

R15

VDDCR_11

N17

VDDCR_11

U13

VDDCR_11

U17

VDDCR_11

V12

VDDCR_11

V18

VDDCR_11 VDDCR_11 VDDCR_11

W12 W18

K28 K29 J28 K26 J21 J20 K21 J22

V1 M10

CORE S03.3V_S5 I/O

VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK VDDAN_11_CLK

VDDRF_GBE_S

VDDIO_33_GBE_S

GBE PHY not used

R2308

1 2

0R0402-PAD

L7 L9

M6 P8

A21 D21 B21 K10 L10 J9 T6 T8

F26 G26

+3.3VALW_VDDIO_AZ

M8 A11

B11

3.3V_RUN_VDDPL

M21

1.1V_ALW_VDDPL

L22 F19 D6

3.3V_ALW_VDDXL

L20

VDDCR_11_GBE_S VDDCR_11_GBE_S

VDDIO_GBE_S VDDIO_GBE_S

VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S VDDIO_33_S

VDDCR_11_S VDDCR_11_S

VDDIO_AZ_S

CORE S5

VDDCR_11_USB_S VDDCR_11_USB_S

VDDPL_33_SYS

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDAN_33_HWM_S

VDDXL_33_S

C2350

12

220 ohm 300mA

http://hobi-elektronika.net

3

510mA

SC1U6D3V2KX-GP

400 mA

SCD1U10V2KX-5GP

32mA

113mA

TBDmA

197mA

C2304

12

C2315

12

R2303

1 2

0R0402-PAD

SCD1U10V2KX-5GP

C2309

12

SCD1U10V2KX-5GP

C2317

12

DY

-A00

17mA

5mA

SC1U6D3V2KX-GP

C2308

12

SC1U6D3V2KX-GP

C2316

12

+3.3V_ALW

C2329

SC2D2U6D3V3KX-GP

C2329

SC2D2U6D3V3KX-GP

12

SCD1U10V2KX-5GP

C2334

12

DY

+1.1V_RUN

SC10U6D3V5KX-1GP

C2310

12

DY

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

C2318

12

DY

+3.3V_ALW

SC2D2U6D3V3KX-GP

C2323

12

+1.1V_ALW

SCD1U10V2KX-5GP

C2327

SC1U6D3V2KX-GP

12

SC10U6D3V5KX-1GP

SCD1U10V2KX-5GP

C2335

12

SCD1U10V2KX-5GP

C2347

12

DY

C2311

12

R2304

1 2

TC2302

12

0R0603-PAD-1-GP

DY

C2324

12

DY

C2328

12

DY

L2306

1 2

BLM15AG221SS1D-GP

C2336

220 ohm 300mA

12

DY

+3.3V_ALW

SC2D2U6D3V3KX-GP

C2348

12

+3.3V_ALW

SCD1U10V2KX-5GP

C2345

12

DY

2

+1.1V_RUN+1.1V_RUN_SB_CLKGEN

-A00

+1.1V_ALW+1.1V_ALW_VDDR_USB

U2E

Part 5 of 5

Y14

VSSIO_SATA

Y16

VSSIO_SATA

AB16

VSSIO_SATA

AC14

VSSIO_SATA

AE12

VSSIO_SATA

AE14

VSSIO_SATA

AF9

VSSIO_SATA

AF11

VSSIO_SATA

AF13

VSSIO_SATA

AF16

VSSIO_SATA

AG8

VSSIO_SATA

AH7

VSSIO_SATA

AH11

VSSIO_SATA

AH13

VSSIO_SATA

AH16

VSSIO_SATA

AJ7

VSSIO_SATA

AJ11

VSSIO_SATA

AJ13

VSSIO_SATA

AJ16

VSSIO_SATA

A9

VSSIO_USB

B10

VSSIO_USB

K11

VSSIO_USB

B9

VSSIO_USB

D10

VSSIO_USB

D12

VSSIO_USB

D14

VSSIO_USB

D17

VSSIO_USB

E9

VSSIO_USB

F9

VSSIO_USB

F12

VSSIO_USB

F14

VSSIO_USB

F16

VSSIO_USB

C9

VSSIO_USB

G11

VSSIO_USB

F18

VSSIO_USB

D9

VSSIO_USB

H12

VSSIO_USB

H14

VSSIO_USB

H16

VSSIO_USB

H18

VSSIO_USB

J11

VSSIO_USB

J19

VSSIO_USB

K12

VSSIO_USB

K14

VSSIO_USB

K16

VSSIO_USB

K18

VSSIO_USB

H19

VSSIO_USB

Y4

EFUSE

D8

VSSAN_HWM

M19

VSSXL

P21

VSSIO_PCIECLK

P20

VSSIO_PCIECLK

M22

VSSIO_PCIECLK

M24

VSSIO_PCIECLK

M26

VSSIO_PCIECLK

P22

VSSIO_PCIECLK

P24

VSSIO_PCIECLK

P26

VSSIO_PCIECLK

T20

VSSIO_PCIECLK

T22

VSSIO_PCIECLK

T24

VSSIO_PCIECLK

V20

VSSIO_PCIECLK

J23

VSSIO_PCIECLK

SB820M-1-GP

Title

SB820M_POWER&GND_(4/5)

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Part 5 of 5

GROUND

VSSPL_SYS

VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK VSSIO_PCIECLK

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

1

AJ2

VSS

A28

VSS

A2

VSS

E5

VSS

D23

VSS

E25

VSS

E6

VSS

F24

VSS

N15

VSS

R13

VSS

R17

VSS

T10

VSS

P10

VSS

V11

VSS

U15

VSS

M18

VSS

V19

VSS

M11

VSS

L12

VSS

L18

VSS

J7

VSS

P3

VSS

V4

VSS

AD6

VSS

AD4

VSS

AB7

VSS

AC9

VSS

V8

VSS

W9

VSS

W10

VSS

AJ28

VSS

B29

VSS

U4

VSS

Y18

VSS

Y10

VSS

Y12

VSS

Y11

VSS

AA11

VSS

AA12

VSS

G4

VSS

J4

VSS

G8

VSS

G9

VSS

M12

VSS

AF25

VSS

H7

VSS

AH29

VSS

V10

VSS

P6

VSS

N4

VSS

L4

VSS

L8

VSS

M20

H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20

of

23 90Thursday, May 20, 2010

A00

5

SSID = S.B

4

3

2

1

REQUIRED STRAPS

D D

PCI_CLK120 PCI_CLK220 PCI_CLK320,70

PCLK_FWH20

C C

PCLK_KBC20,37 LPCCLK120

SB_GPO20021 SB_GPO19921

ACZ_SDATAOUT_R21

+3.3V_RUN +3.3V_ALW

R240210KR2J-3-GP

R240310KR2J-3-GP

12

DY

R241710KR2J-3-GP R241710KR2J-3-GP

12

R240410KR2J-3-GP R240410KR2J-3-GP

12

R241810KR2J-3-GP R241810KR2J-3-GP

R241910KR2J-3-GP

12

DY

R240110KR2J-3-GP

12

DY

R241610KR2J-3-GP

12

DY

R240510KR2J-3-GP

12

DY

R242010KR2J-3-GP R242010KR2J-3-GP

12

R240610KR2J-3-GP R240610KR2J-3-GP

12

R242110KR2J-3-GP

12

DY

R24072K2R2F-GP

12

DY

R24222K2R2F-GP R24222K2R2F-GP

12

R24082K2R2F-GP R24082K2R2F-GP

12

DY

R24232K2R2F-GP

12

DY

R240910KR2J-3-GP

12

R242410KR2J-3-GP R242410KR2J-3-GP

12

DEBUG STRAPS

PCI_AD23 20 VDDR_SEL 20,51 PCI_AD25 20 PCI_AD26 20 PCI_AD27 20

R24142K2R2J-2-GP

R24122K2R2J-2-GP

R24112K2R2J-2-GP

12

DY

R24132K2R2J-2-GP

12

DY

12

DY

R24152K2R2J-2-GP

12

B B

REQUIRED SYSTEM STRAPS

PULL HIGH

PULL LOW

AZ_SDOUT#

LOW POWER MODE

PERFORMANCE MODE

DEFAULT

PCI_CLK1

Allow PCIE GEN2

DEFAULT

Force PCIE GEN1

PCI_CLK2

WatchDOG (NB_PWRGD) ENABLED

WatchDog (NB_PWRGD) DISABLED

DEFAULT

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

(PCI_CLK4)

non_Fusion CLOCK mode

DEFAULT

Fusion CLOCK mode

USE this pin to determine INT/EXT CLK

PCLK_KBCPCLK_FWH

(LPCCLK0)

ENABLE EC

DISABLE EC

DEFAULT

LPCCLK1

DEFAULT

CLKGEN ENABLED

(Use Internal)

CLKGEN DISABLED

(Use External)

SB_GPO200 , SB_GPO199

ROM TYPE:

H, H = Reserved

H, L = SPI ROM

L, H = LPC ROM

L, L = FWH ROM

DEFAULT

PULL HIGH

PULL LOW

USE PCI PLL

BYPASS PCI PLL

PCI_AD26PCI_AD27

Disable ILA AUTORUN

Enable ILA AUTORUN

PCI_AD25 PCI_AD23

USE FC PLL

BYPASS FC PLL

PCI_AD24

USE DEFAULT PCIE STRAPS

USE EEPROM PCIE STRAPS

Disable PCI MEM BOOT

(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)

Enable PCI MEM BOOT

Note: SB820 has 15K internal P U FOR P CI _AD[27:23]

Not Applicable to SB820M but provision for pull-down is required.

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

SB820M_STRAPPING_(5/5)

A3

Taipei Hsien 221, Taiwan, R.O.C.

Ansenal DJ1 AMD UMA

24 90Thursday, May 27, 2010

1

of

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)

Size Document Number Rev

Date: Sheet

CPU (VCC_CORE)

Ansenal DJ1 AMD UMA

Taipei Hsien 221, Taiwan, R.O.C.

of

25 90Thursday, May 13, 2010

of

25 90Thursday, May 13, 2010

of

25 90Thursday, May 13, 2010

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

Size Document Number Rev

Date: Sheet

CPU (VCC_GFXCORE)

Ansenal DJ1 AMD UMA

Taipei Hsien 221, Taiwan, R.O.C.

of

26 90Thursday, May 13, 2010

of

26 90Thursday, May 13, 2010

of

26 90Thursday, May 13, 2010

1

A00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

http://hobi-elektronika.net

5

4

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

Ansenal DJ1 AMD UMA

Taipei Hsien 221, Taiwan, R.O.C.

CPU (VSS)

1

of

27 90Thursday, May 13, 2010

of

27 90Thursday, May 13, 2010

of

27 90Thursday, May 13, 2010

A00