DELL ls4764p Schematics

A
ZZZ4
ZZZ4
LS-4764P
PCB
1 1
PCB
DA80000CG00
DA80000CG00
B
C
D
E
Compal Confidential
2 2
KIU10 LS-4764P Schematics Document
Menlow-Silverthorne with Poulsbo
3 3
REV:1.0 2008/12/02
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/07/15 2011/07/15
2008/07/15 2011/07/15
2008/07/15 2011/07/15
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
KIU10 LS-4764P
KIU10 LS-4764P
KIU10 LS-4764P
E
1 20
1 20
1 20
1.0
1.0
1.0
A
B
C
D
E
Compal Confidential
Model Name : KIU10 File Name : LS-4764P
1 1
CPU-Silverthrone
1.33G/1.6G
H_A#(3..35)
H_D#(0..63)
FSB
533MHz
CPU Regulator
Clock Gen.
9UMS9610
+1.8V
+1.05VS
DDR2 64MX16X8pcsDDR2-533
K4T1G164QD
SCH- Poulsbo
SingleChannel
+0.9VS
+1.5VS
LVDS I/F1 SDIO I/F
2 2
PCIESDVO I/F PCIE
LPC BUS
AZALIA ATA100 USB2.0
200Pin Golden-Finger
LVDS I/F
SDVO I/F
PCIE
PCIE
ATA100
USB2.0
AZALIA
Audio Codec
ALC 269
Audio JackLPC BUS
Mono-Speaker
LVDS Connector
3 3
SDVO to HDMI Sil1392
LAN RTL8102EL
WLAN/WiMAX Camera
BIOS
EC
ENE KB926
page33
SPI
HDMI Connector
TP
PS/2
Port 5
Port 0,1,3
Port 6
USB Conn X 3
USB Card Reader RTS5158
DCIN/CHARGER
BATT Conn/OTP
SD/MMC/MS
+3VALW
Int.KBD
LS-4764P Main-Board
4 4
SATA HDD
Port 4
Port 2
Port 7
3G-Module
BlueTooth
TV Turner
GL831
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2008/07/15 2011/07/15
2008/07/15 2011/07/15
2008/07/15 2011/07/15
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
SIM Connector
+5VALW
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
KIU10 LS-4764P
KIU10 LS-4764P
KIU10 LS-4764P
E
2 20Tuesday, December 02, 2008
2 20Tuesday, December 02, 2008
2 20Tuesday, December 02, 2008
1.0
1.0
1.0
Voltage Rails
power plane
State
O MEANS ON X MEANS OFF
+VBAT
+5VALW
+3VALW
+1.8V
+0.9V
+5VS
+3VS
+1.8VS
+1.5VS
+CPU_CORE
+VCCP
CLOCK
A
SKU ID Table
Vcc 3.3V +/- 5%
Board ID
0
*
1 2 3 4 5 6 7 NC
100K +/- 5%Ra
Rb V min
0
8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%
AD_BID
0 V
V typ
AD_BID
0 V 0 V
V
AD_BID
max
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
S0
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
O
O
O
O
X
O
O
O
X
O
X X
X
X X X
OO
X
O
X
X
X
X
X
SKU ID
*
0 1 2 3 4 5 6 7
MB ID(H)
MB ID(L)
IEL10 IDL11 IDL01 HDL10
HDL00 HDL20 HDL30IDL12
TBD
MB ID
O MEANS ON
X MEANS OFF
H L
S3 : STR S4 : STD
15" 14"
S5 : SOFT OFF
1 1
BOM Structure USB PORT LIST
MARK FUNCTION
NC FOR ALL@
PORT DEVICE
0
2A POWER USB USB (right)
1
BT
2
USB(lEFT)3
4
3G, GPS
5
Camera
6
Card reader
7
TV Turner
EC SM Bus1 address
Device
EEPROM(24C16/02)
Address
1010 000X b
EC SM Bus2 address
Device
ADM1032
Address
1001 100X b
Address
Poulsbo SM Bus address
Device
Clock Generator ( ICS954226)
Address
1101 001Xb
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2008/07/15 2011/07/15
2008/07/15 2011/07/15
2008/07/15 2011/07/15
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
KIU10 LS-4764P
KIU10 LS-4764P
KIU10 LS-4764P
3 20Tuesday, December 02, 2008
3 20Tuesday, December 02, 2008
3 20Tuesday, December 02, 2008
1.0
1.0
1.0
5
4
3
2
1
Silverthrone Host Data Interface Silverthrone Host Data Interface
U2
H_D#[0..15]6
D D
H_DSTBN#06 H_DSTBP#06
H_DINV#06
H_D#[16..31]6
H_DSTBN#16 H_DSTBP#16
C C
H_DINV#16
CPU_BSEL26,14
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
+CPU_GTLREF
CPU_BSEL2
U2B
U2B
Y27
D[0]#
AH27
D[1]#
Y31
D[2]#
AC30
D[3]#
AE30
D[4]#
AF29
D[5]#
AA26
D[6]#
AB31
D[7]#
W30
D[8]#
AC28
D[9]#
AD31
D[10]#
AF27
D[11]#
AD27
D[12]#
AG28
D[13]#
AB25
D[14]#
AC26
D[15]#
AA28
DSTBN[0]#
AA30
DSTBP[0]#
AE28
DINV[0]#
AE24
D[16]#
AC24
D[17]#
AJ20
D[18]#
AE20
D[19]#
AJ22
D[20]#
AF25
D[21]#
AH25
D[22]#
AH23
D[23]#
AH19
D[24]#
AF23
D[25]#
AE18
D[26]#
AH17
D[27]#
AD19
D[28]#
AJ24
D[29]#
AJ18
D[30]#
AF19
D[31]#
AF21
DSTBN[1]#
AH21
DSTBP[1]#
AE22
DINV[1]#
AJ26
GTLREF
MISC
MISC
P31
TEST1
T31
TEST2
R30
BSEL[0]
M31
BSEL[1]
U28
BSEL[2]
SILVERTHORNE_FCBGA8-441
SILVERTHORNE_FCBGA8-441
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]#
DATA GRP 2
DATA GRP 2
D[44]# D[45]# D[46]#
D[47]# DSTBN[2]# DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
DATA GRP 3
DATA GRP 3
D[61]#
D[62]#
D[63]# DSTBN[3]# DSTBP[3]#
DINV[3]#
COMP[0] COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
RSVD12
AE8 AD7 AH15 AF9 AH9 AE10 AJ16 AF13 AF7 AF15 AH13 AJ14 AJ12 AH7 AJ8 AJ10 AH11 AF11 AE12
AH5 AB5 AJ6 Y1 AF5 AG4 AF3 AC6 AE6 AE4 W4 AC2 AE2 AD1 AA2 AC4 AB1 AA4 Y5
AE14 AD13 E16 F15
G2 G6 V31 G4 J2 K27
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP0
R11 27.4_0402_1% R11 27.4_0402_1%
COMP1
R15 54.9_0402_1% R15 54.9_0402_1%
COMP2
R13 27.4_0402_1% R13 27.4_0402_1%
COMP3
R14 54.9_0402_1% R14 54.9_0402_1%
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP#
1 2 1 2 1 2 1 2
H_D#[32..47] 6
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[48..63] 6
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6
H_DPRSTP# 6,18
H_DPSLP# 6 H_DPWR# 6 H_PWRGOOD 6
H_CPUSLP# 6
H_ADSTB#06
H_A#[17..31]6
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL CPU_BSEL2 CPU_BSEL1
100
133
B B
Close to CPU pin AD26 within 500mils.
+CPU_GTLREF
1
C4
C4
0.1U_0402_25V4K
0.1U_0402_25V4K
2
XDP Reserve
XDP_TDI
XDP_TMS
A A
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK
1 0
0
+1.05VS_C6
12
R20
R20 1K_0402_1%
1K_0402_1%
12
R27
R27 2K_0402_1%
2K_0402_1%
R19 56_0402_5%R19 56_0402_5%
1 2
R21 56_0402_5%R21 56_0402_5%
1 2
R23 56_0402_5%@R23 56_0402_5%@
1 2
R25 56_0402_5%@R25 56_0402_5%@
1 2
R28 56_0402_5%R28 56_0402_5%
1 2
R29 56_0402_5%R29 56_0402_5%
1 2
5
0
+1.05VS
CPU_BSEL0
1
1
Resistor placed within
0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal. COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils.
R96 1K_0402_5%
SLPIOVR#8,15
R96 1K_0402_5%
R122 1K_0402_1%R122 1K_0402_1%
1 2
+1.05VS
1 2
4
XDP_BPM#5 XDP_BPM#4
XDP_BPM#3 XDP_BPM#2
XDP_BPM#1 XDP_BPM#0
H_PWRGOOD
T4TPC24 T4TPC24
T10TPC24 T10TPC24
T11TPC24 T11TPC24
XDP_TDO XDP_TRST# XDP_TDI XDP_TMS
XDP_TCK
JP13
@JP13
@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
G1
26
G2
ACES_87151-24051-S
ACES_87151-24051-S
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
U2
1.6G@
1.6G@ SA00002M42L
SA00002M42L
H_A#[3..16]6
H_REQ#06 H_REQ#16 H_REQ#26 H_REQ#36 H_REQ#46
H_ADSTB#16
H_A20M#13
H_PBE#6
H_STPCLK#6 H_INTR6
H_NMI6 H_SMI#6
+1.05VS_C6
2008/07/15 2011/07/15
2008/07/15 2011/07/15
2008/07/15 2011/07/15
+1.05VS_C6
H_INIT#
C26 H25 G24
B27 W28 D29
C28
H1 F31
D25
M5 D27 E28 E26 F25
E30 F29
F1 E2 F5 D3 E4 F7 L2 N2 M1 P1 J4 G26
H5 T5 U4
T1
P29 R28
K31
A26 E6
G28 U30
V27 AE26
.
.
SMCLK
SMDATA
ALERT#
GND
Intel CRB1_5
1 2
R3
R3
H_ADS# H_BNR# H_BPRI#
H_DEFER# H_DRDY# H_DBSY#
H_BR0#
H_IERR# H_INIT#
H_LOCK#
H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY#
H_HIT# H_HITM#
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#
T1 TPC12T1 TPC12
H_THERMDA H_THERMDC
+CMREF
8
7
6
5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R1
R1
120_0402_5%
120_0402_5%
R2
R2
R4
R4
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
H_ADSTB#0
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1
H_A20M# H_PBE# H_IGNNE#
H_STPCLK# H_INTR H_NMI H_SMI#
R16
R16
1 2
10K_0402_5%
10K_0402_5%
AE16 AF17 AD15 AD17
Thermal Sensor
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2200P_0402_50V7K
2200P_0402_50V7K
1 2
C3
C3
1 2
+3VS +3VS
R26 10K_0402_5%R26 10K_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
H_PBE#
1 2
H_A20M#
1 2
1K_0402_1%
1K_0402_1%
H_IGNNE#
1 2
1K_0402_5%
1K_0402_5%
U2A
U2A
E22
A[3]#
A22 D21 E24 B17 A18 B23
A16
E18 D15 B19 A20 D17 B15 D19
B25 D23 E20 A24 B21
B5
A12
D5
E12
B9
A6 B13 E14 A10
B7 D13
A8
C4 A14 B11 D11
G30
J28
H27
K1 H31
L28 J26
D9
D7
E8 E10
L30 J30
K29
1 2
H_THERMDC
0
0
A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
A[17]# A[18]#
ADDR GROUP 1
ADDR GROUP 1
A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]#
A20M# FERR# IGNNE#
STPCLK# LINT0 LINT1 SMI#
RSVD7 RSVD8 RSVD9 RSVD10 RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5
RSVD13
SILVERTHORNE_FCBGA8-441
SILVERTHORNE_FCBGA8-441
+3VS
C2
C2
1
2
3
THERM#
4
2
ADS#
ADDR GROUP
ADDR GROUP
BNR#
BPRI#
DEFER#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]# RS[1]# RS[2]#
TRDY#
HIT#
HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]#
PRDY# PREQ#
TCK
TDI TDO TMS
TRST#
RSVD14
XDP/ITP SIGNALSH CLK
XDP/ITP SIGNALSH CLK
PROCHOT#
THRMDA THRMDC
THERM
THERM
THERMTRIP#
BCLK[0] BCLK[1]
VSS0
RSVD11
RSVD6
NC
NC
RSVD15
TEST4
TEST3
CMREF[1]
U3
U3
VDD
DP
DN
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
1K_0402_1%
1K_0402_1%
H_THERMTRIP#
EC_SMB_CK2H_RESET#
EC_SMB_DA2H_THERMDA
THERM_SCI#
KIU10 LS-4764P
KIU10 LS-4764P
KIU10 LS-4764P
+1.05VS_C6
H_ADS# 6 H_BNR# 6
H_BPRI# 6
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6
H_BR0# 6
H_INIT# 6,13
H_LOCK# 6
H_RESET# 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6
H_HIT# 6 H_HITM# 6
R12
R12
56_0402_5%
56_0402_5%
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
CLK_CPU_BCLK 14 CLK_CPU_BCLK# 14
+1.05VS_C6
1
C1
2
12
R24 0_0402_5%@R24 0_0402_5%@
1 2
R2210K_0402_5% R2210K_0402_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Silverthorne(1/2)-AGTL+/XDP
Silverthorne(1/2)-AGTL+/XDP
Silverthorne(1/2)-AGTL+/XDP
R5
R5
12
56_0402_5%
56_0402_5%
12
+1.05VS
PROCHOT# 8,18
H_THERMTRIP# 6
12
R17
R17 1K_0402_1%
1K_0402_1%
12
R18
R18
1K_0402_1%
1K_0402_1%
0.1U_0402_25V4KC10.1U_0402_25V4K
Check : to sb
1
+1.05VS
EC_SMB_CK2 13
EC_SMB_DA2 13
EC_THERM# 7,8,13
4 20Tuesday, December 02, 2008
4 20Tuesday, December 02, 2008
4 20Tuesday, December 02, 2008
1.0
1.0
1.0
5
4
3
2
1
+1.05VS
12
C60.1U_0402_16V7K C60.1U_0402_16V7K
12
C70.1U_0402_16V7K C70.1U_0402_16V7K
+1.05VS_C6
12
C160.1U_0402_16V7K C160.1U_0402_16V7K
12
C181U_0402_6.3V6K C181U_0402_6.3V6K
12
C201U_0402_6.3V6K C201U_0402_6.3V6K
12
C221U_0402_6.3V6K C221U_0402_6.3V6K
12
C241U_0402_6.3V6K C241U_0402_6.3V6K
+1.05VS_C6
U2C
U2C
AA14
VCCP35
J16
VCCP36
M27
VCCP0
H7
VCCPC61
H9
VCCPC62
J8
VCCPC63
AA8
VCCP1
AA10
VCCP2
AA12
VCCP3
AA16
VCCP4
AA18
VCCP5
AA20
VCCP6
AA22
VCCP7
AB7
VCCP8
AB9
VCCP9
AB11
VCCP10
AB13
VCCP11
AB15
VCCP12
AB17
VCCP13
AB19
VCCP14
AB21
VCCP15
AB23
VCCP16
H11
VCCP17
H13
VCCP18
H15
VCCP19
H17
VCCP20
H19
VCCP21
H21
VCCP22
H23
VCCP23
J10
VCCP24
J12
VCCP25
J14
VCCP26
J18
VCCP27
J20
VCCP28
J22
VCCP29
L26
VCCP30
N26
VCCP31
R26
VCCP32
U26
VCCP33
W26
VCCP34
SILVERTHORNE_FCBGA8-441
SILVERTHORNE_FCBGA8-441
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8
VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
D D
U2D
U2D
A4
VSS1
A28
VSS2
AA6
VSS4
AA24
VSS5
AB3
VSS6
AB27
VSS7
AB29
VSS8
AC8
VSS9
AC10
VSS10
AC12
VSS11
AC14
VSS12
AC16
VSS13
AC18
VSS14
AC20
VSS15
AC22
VSS16
AD3
VSS17
AD5
VSS18
AD9
VSS19
AD11
VSS20
AD21
VSS21
AD23
VSS22
AD25
VSS23
AD29
VSS24
AF1
VSS25
AF31
VSS26
AG2
VSS27
AG6
VSS28
AG8
VSS29
AG10
C C
B B
AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG30
AH3
AH29
AJ28
C10 C12 C14 C16 C18 C20 C22 C24 C30
D31
G10 G12 G14 G16 G18 G20 G22
H29
VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS41 VSS42
AJ4
VSS45 VSS46
B3
VSS48
B29
VSS49
C2
VSS51
C6
VSS52
C8
VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62
D1
VSS63 VSS64
F3
VSS65
F9
VSS66
F11
VSS67
F13
VSS68
F17
VSS69
F19
VSS70
F21
VSS71
F23
VSS72
F27
VSS73
G8
VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81
H3
VSS82 VSS83
J6
VSS84
VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100
VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85
Y29 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y11 Y9 Y7 Y3 W6 V29 V25 V23 V21 V19 V17 V15 V13 V11 V9 V7 V5 V3 T29 T27 T25 T23 T21 T19 T17 T15 T13 T11 T9 T7 T3 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P3 N28 M29 M25 M23 M21 M19 M17 M15 M13 M11 M9 M7 M3 L6 K25 K23 K21 K19 K17 K15 K13 K11 K9 K7 K3 J24
+CPU_CORE
L8 L10 L12 L14 L16 L18 L20 L22 L24 N6 N8 N10 N12 N14 N16 N18 N20 N22 N24 R6 R8 R10 R12 R14 R16 R18 R20 R22 R24 U6 U8 U10 U12 U14 U16 U18 U20 U22 U24 W8 W10 W12 W14 W16 W18 W20 W22 W24
N30
P5 R4 N4 K5 L4 R2 U2
W2
V1
<NO_STUFF>
<NO_STUFF>
1 2
C5 330U_D2_2V_Y
C5 330U_D2_2V_Y
1 2
C136 10U_0603_6.3V6MC136 10U_0603_6.3V6M
<BOM Structure>
<BOM Structure>
1 2
C9 10U_0603_6.3V6MC9 10U_0603_6.3V6M
1 2
C10 10U_0603_6.3V6MC10 10U_0603_6.3V6M
1 2
C14 1U_0402_6.3V6KC14 1U_0402_6.3V6K
1 2
C15 1U_0402_6.3V6KC15 1U_0402_6.3V6K
1 2
C17 1U_0402_6.3V6KC17 1U_0402_6.3V6K
1 2
C19 1U_0402_6.3V6KC19 1U_0402_6.3V6K
1 2
C21 1U_0402_6.3V6KC21 1U_0402_6.3V6K
1 2
C23 1U_0402_6.3V6KC23 1U_0402_6.3V6K
1 2
C25 1U_0402_6.3V6KC25 1U_0402_6.3V6K
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE
VSSSENSE
+CPU_CORE
+
+
+
12
C8220U_B2_2.5VM+C8220U_B2_2.5VM
12
C12310U_0603_6.3V6M C12310U_0603_6.3V6M
12
C12110U_0603_6.3V6M C12110U_0603_6.3V6M
12
C12210U_0603_6.3V6M C12210U_0603_6.3V6M
12
C111U_0402_6.3V6K C111U_0402_6.3V6K
12
C121U_0402_6.3V6K C121U_0402_6.3V6K
12
C131U_0402_6.3V6K C131U_0402_6.3V6K
12
C1401U_0402_6.3V6K C1401U_0402_6.3V6K
12
C1391U_0402_6.3V6K C1391U_0402_6.3V6K
12
C1381U_0402_6.3V6K C1381U_0402_6.3V6K
12
C1371U_0402_6.3V6K C1371U_0402_6.3V6K
+1.5VS
Length match within 25 mils. The trace width/space/other is 20/7/25.
1
C26
C26
0.1U_0402_16V7K
0.1U_0402_16V7K
CPU_VID[0..6] 18
2
Near pin N30
+CPU_CORE
R30
R30 100_0402_1%
100_0402_1%
1 2
R31
R31 100_0402_1%
100_0402_1%
1 2
VCCSENSE
VSSSENSE
VCCSENSE 18
VSSSENSE 18
Close to CPU pin within 500mils.
SILVERTHORNE_FCBGA8-441
SILVERTHORNE_FCBGA8-441
SA00002M42L
SA00002M42L
A A
5
<NO_STUFF>
<NO_STUFF>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/07/15 2011/07/15
2008/07/15 2011/07/15
2008/07/15 2011/07/15
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Silverthorne(2/2)-PWR/GND
Silverthorne(2/2)-PWR/GND
Silverthorne(2/2)-PWR/GND
KIU10 LS-4764P
KIU10 LS-4764P
KIU10 LS-4764P
1
1.0
1.0
5 20Tuesday, December 02, 2008
5 20Tuesday, December 02, 2008
5 20Tuesday, December 02, 2008
1.0
5
H_D#[0..63]4 H_A#[3..31] 4
D D
C C
H_NMI4 H_SMI#4
H_PBE#4
H_STPCLK#4
B B
H_INIT#4,13 H_INTR4
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
R33 24_0402_5%
R33 24_0402_5%
1 2
+H_SWNG
+H_RCOMP
H_THERMTRIP_R#
U4A
U4A
V8
H_D0#
AF4
H_D1#
V2
H_D2#
AA1
H_D3#
AC1
H_D4#
AD2
H_D5#
V4
H_D6#
Y2
H_D7#
U1
H_D8#
Y8
H_D9#
AB2
H_D10#
AF2
H_D11#
AB4
H_D12#
AF8
H_D13#
AE1
H_D14#
AB8
H_D15#
AJ1
H_D16#
AH2
H_D17#
AM8
H_D18#
AN1
H_D19#
AK4
H_D20#
AG1
H_D21#
AH8
H_D22#
AK8
H_D23#
AP8
H_D24#
AK2
H_D25#
AR1
H_D26#
AT8
H_D27#
AT2
H_D28#
AH4
H_D29#
AP4
H_D30#
AP2
H_D31#
AV4
H_D32#
BB6
H_D33#
AV6
H_D34#
AY8
H_D35#
BA1
H_D36#
AU1
H_D37#
AT6
H_D38#
AV8
H_D39#
BB4
H_D40#
AT4
H_D41#
AY6
H_D42#
AV10
H_D43#
AV2
H_D44#
BC1
H_D45#
BB2
H_D46#
AY2
H_D47#
BD2
H_D48#
BH4
H_D49#
BD10
H_D50#
BK10
H_D51#
BD6
H_D52#
BD4
H_D53#
BF2
H_D54#
BE1
H_D55#
BD8
H_D56#
BF4
H_D57#
BH10
H_D58#
BK6
H_D59#
BB8
H_D60#
BF6
H_D61#
BF10
H_D62#
BH6
H_D63#
AB10
H_NMI
AB6
H_SMI#
AH6
H_PBE#
V6
H_SWING
AD10
H_STPCLK#
AK6
H_TESTIN#
T10
H_RCOMPO
AT10
RESERVED5
AP10
RESERVED4
AM6
H_THRMTRIP#
AF10
H_INIT#
AF6
H_INTR
POULSBO_FCBGA1249
POULSBO_FCBGA1249
HOST
HOST
layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note: H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+1.05VS
12
R41
R41 1K_0402_1%
1K_0402_1%
0.1U_0402_16V4Z
R45
R45
12
2K_0402_1%
2K_0402_1%
0.1U_0402_16V4Z
1
C29
C29
2
+H_RCOMP
12
R46
R46
24.9_0402_1%
24.9_0402_1%
A A
+1.05VS
12
R42
R42
<BOM Structure>
<BOM Structure>
221_0603_1%
221_0603_1%
12
R47
R47
100_0402_1%
100_0402_1%
+H_SWNG+H_VREF
1
C30
C30
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near B3 pinwithin 100 mils from NB
5
4
H_A#3
M2
H_A3# H_A4# H_A5# H_A6# H_A7# H_A8#
H_A9# H_A10# H_A11# H_A12# H_A13# H_A14# H_A15# H_A16# H_A17# H_A18# H_A19# H_A20# H_A21# H_A22# H_A23# H_A24# H_A25# H_A26# H_A27# H_A28# H_A29# H_A30# H_A31#
H_ADS# H_ADSTB0# H_ADSTB1#
H_GVREF
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_CGVREF
H_CLKINN H_CLKINP
H_DBSY#
H_DEFER#
H_DINV0# H_DINV1# H_DINV2# H_DINV3#
H_DPWR#
H_DRDY# H_DSTBN0# H_DSTBN1# H_DSTBN2# H_DSTBN3# H_DSTBP0# H_DSTBP1# H_DSTBP2# H_DSTBP3#
H_HIT# H_HITM# H_LOCK# H_REQ0# H_REQ1# H_REQ2# H_REQ3# H_REQ4#
H_RS0# H_RS1# H_RS2#
H_CPUSLP#
H_TRDY#
H_CPUPWRGD
H_DPSLP#
H_DPRSTP#
CFG0 CFG1
BSEL2
FSB BSEL2
100
13310
CFG1 10K pull-down is required.
H_THERMTRIP_R#
4
M8 K4 P2 F4 G1 M4 F6 H6 D2 H2 J1 F2 D4 D12 H12 G11 A7 A9 A11 B6 H8 F10 B10 D6 D10 B12 B4 D8
K6 H4 B8 Y10 R1 P10 L1 M6 AD4
K10 M10 H10 AD6 AD8 AM2 AY10 BK8 P6 J9 Y4 AL1 AW1 BH8 W1 AM4 AY4 BF8
V10 T6 Y6 P4 N1 K8 P8 K2 T4 T2 T8 AH10 F12
AP6 F8 AK10
J27 B34 F28
R48
R48
1 2
24_0402_5%
24_0402_5%
<BOM Structure>
<BOM Structure>
H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_ADS# H_ADSTB#0 H_ADSTB#1 +H_VREF H_BNR# H_BPRI# H_BR0# H_RESET# +H_CGVREF
CLK_MCH_BCLK# CLK_MCH_BCLK H_DBSY# H_DEFER# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DPWR# H_DRDY# H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_HIT# H_HITM# H_LOCK# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP# H_TRDY#
CFG0
100
133
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4
H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_RESET# 4
CLK_MCH_BCLK# 14 CLK_MCH_BCLK 14
H_DBSY# 4 H_DEFER# 4 H_DINV#0 4 H_DINV#1 4 H_DINV#2 4 H_DINV#3 4 H_DPWR# 4 H_DRDY# 4 H_DSTBN#0 4 H_DSTBN#1 4 H_DSTBN#2 4 H_DSTBN#3 4 H_DSTBP#0 4 H_DSTBP#1 4 H_DSTBP#2 4 H_DSTBP#3 4
H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_REQ#0 4 H_REQ#1 4 H_REQ#2 4 H_REQ#3 4 H_REQ#4 4 H_RS#0 4 H_RS#1 4 H_RS#2 4 H_CPUSLP# 4 H_TRDY# 4
H_PWRGOOD 4 H_DPSLP# 4 H_DPRSTP# 4,18
R35 10K_0402_5% R35 10K_0402_5%
1 2
R36 10K_0402_5%@R36 10K_0402_5%@
1 2
R37 10K_0402_5%R37 10K_0402_5%
1 2
CPU_BSEL2 4,14
CFG0DDRFSB
DDRFSBFSB
100
13310 100
+1.05VS_C6
12
133
within 2" from R48
R44
R44 120_0402_5%
120_0402_5%
Security Classification
Security Classification
Security Classification
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05VS
H_THERMTRIP# 4
Issued Date
Issued Date
Issued Date
3
DDR_A_D[0..63]11,12
+H_CGVREF
In pre-ES R571=2k H_CGVREF=2/3VCCP In ES R571 choose 1k
2008/07/15 2011/07/15
2008/07/15 2011/07/15
2008/07/15 2011/07/15
3
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8
DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
+1.05VS
12
R38
R38
1K_0402_1%
1K_0402_1%
12
1
R40
R40
C27
C27
2
1K_0402_1%
1K_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
U4D
U4D
BG49
SM_DQ0
BG47
SM_DQ1
BE45
SM_DQ2
BC43
SM_DQ3
BE47
SM_DQ4
BC47
SM_DQ5
BC45
SM_DQ6
BK44
SM_DQ7
BK42
SM_DQ8
BG41
SM_DQ9
BK40
SM_DQ10
BC41
SM_DQ11
BG43
SM_DQ12
BJ43
SM_DQ13
BJ39
SM_DQ14
BG39
SM_DQ15
BC39
SM_DQ16
BK38
SM_DQ17
BG37
SM_DQ18
BK36
SM_DQ19
BJ37
SM_DQ20
BG35
SM_DQ21
BJ35
SM_DQ22
BC35
SM_DQ23
BK34
SM_DQ24
BG31
SM_DQ25
BG33
SM_DQ26
BK30
SM_DQ27
BC33
SM_DQ28
BJ33
SM_DQ29
BJ31
SM_DQ30
BC31
SM_DQ31
BJ29
SM_DQ32
BG29
SM_DQ33
BK28
SM_DQ34
BC29
SM_DQ35
BE27
SM_DQ36
BK26
SM_DQ37
BG25
SM_DQ38
BJ25
SM_DQ39
BC25
SM_DQ40
BG23
SM_DQ41
BK22
SM_DQ42
BJ21
SM_DQ43
BK24
SM_DQ44
BJ23
SM_DQ45
BG21
SM_DQ46
BC21
SM_DQ47
BK20
SM_DQ48
BJ19
SM_DQ49
BG17
SM_DQ50
BJ17
SM_DQ51
BG19
SM_DQ52
BC19
SM_DQ53
BC17
SM_DQ54
BK16
SM_DQ55
BG15
SM_DQ56
BC15
SM_DQ57
BJ13
SM_DQ58
BK12
SM_DQ59
BK14
SM_DQ60
BJ15
SM_DQ61
BC13
SM_DQ62
BC11
SM_DQ63
POULSBO_FCBGA1249
POULSBO_FCBGA1249
2
DDR_A_BS#0
BC27
DDR SYSTEM MEMORY
DDR SYSTEM MEMORY
SM_RCVENOUT
SM_BS0 SM_BS1 SM_BS2
SM_CK0 SM_CK1
SM_CK0# SM_CK1#
SM_CKE0 SM_CKE1
SM_DQS0 SM_DQS1 SM_DQS2 SM_DQS3 SM_DQS4 SM_DQS5 SM_DQS6 SM_DQS7
SM_MA0 SM_MA1 SM_MA2 SM_MA3 SM_MA4 SM_MA5 SM_MA6 SM_MA7 SM_MA8
SM_MA9 SM_MA10 SM_MA11 SM_MA12 SM_MA13 SM_MA14
SM_VREF
SM_RAS# SM_CAS#
SM_WE#
SM_CS0# SM_CS1#
SM_RCOMPO
SM_RCVENIN
BE25 BA35
BG45 BE11
BJ45 BG11
BE39 BE37
BJ47 BJ41 BC37 BK32 BG27 BE23 BK18 BG13
BJ27 BA19 BA27 BA25 BE29 BC23 BE31 BA31 BA33 BA29 BE17 BE35 BE33 BE19 BA37
BE43
BE21 BA13
BA17
BA23 BA15
BE13
BA39 BE41
DDR_A_BS#1 DDR_A_BS#2
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
+SM_VREF
DDR_A_RAS# DDR_A_CAS#
DDR_A_WE#
1 2
R32 30.1_0402_1%R32 30.1_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C173
C173
1
DDR_A_BS#0 11,12 DDR_A_BS#1 11,12 DDR_A_BS#2 11,12
M_CLK_DDR0 11,12 M_CLK_DDR1 11,12
M_CLK_DDR#0 11,12 M_CLK_DDR#1 11,12
M_CKE0 11 M_CKE1 12
DDR_A_DQS[0..7] 11,12
DDR_A_MA[0..13] 11,12
DDR_A_RAS# 11,12 DDR_A_CAS# 11,12
DDR_A_WE# 11,12
M_CS#0 11
M_CS#1 12
1
2
+0.9VS
1
C172
C172 10U_0603_6.3V6M
10U_0603_6.3V6M
2
C172,C173 close SM_RCOMPO pin
+SM_VREF
1
2
+1.8V
R39
R39 10K_0402_1%
10K_0402_1%
1 2
R43
R43 10K_0402_1%
10K_0402_1%
<BOM Structure>
<BOM Structure>
1 2
1
1.0
1.0
6 20Saturday, December 06, 2008
6 20Saturday, December 06, 2008
6 20Saturday, December 06, 2008
1.0
Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20.
C28
C28
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Poulsbo(1/5)-HOST/DDR
Poulsbo(1/5)-HOST/DDR
Poulsbo(1/5)-HOST/DDR
KIU10 LS-4764P
KIU10 LS-4764P
KIU10 LS-4764P
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