Dell lnspiron 15 5552 boardview

1 1

Compal Confidential

2 2

Schematic Document

Intel Braswell M UMA

2015-6-09 Rev: 1.0

3 3

ZZZ

PCB@

PCB 1EE LA-C571P REV1 M/B 2

DA6001DX010

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P01-Cover Page

Size Document Number Rev

Custom

LA-C571P

Date: Sheet of

1 44Tuesday, June 16, 2015

1.0

port 0port 1

P.19

Memory BUS

204pin DDR3L-SO-DIMM X1

XDP-60Pin

D D

eDP Conn.

HDMI Conn.

P.21P.20

PCIE x1

DDI x2

port 1

NGFF WLAN/BT4.0

P.28

C C

eMMC

THGBMBG8D4KBAIR

port 1

P.22

port 1

SATA ODD Conn.

B B

P.27

SATA HDD Conn.

SDMMC

SATA III x2

port 0

SM BUS

P.27

Debug Conn.

P.16

SOC

Intel Braswell-M

Quad Core (4C/4T)

TDP: 6W

FCBGA 1170-Pin

14nm

0.593mm Ball Pitch

LPC BUS

EC ENE KB9022

P.32

Single Channel

1.35V DDR3L 1066/1333/1600

USB2.0 x5

USB3.0

HD Audio

page 08~16

SPI

SPI ROM

1.8V (8MB)

P.11

port 0

USB 3.0 Conn

USB 2.0

P.25 P.25

Conn

Debug Port

Card Reader

RTS5170

Port4

HDA Codec

ALC3234

Speaker

P.23

Int. MIC

HD Camera Conn.

P.24

P.23

port 3port 2port 1

USB HUB

P.20

FE1.1s(STT)

P.26

Touch BT 4.0

Port4

P.28P.20Port1 Port2

USB2.0 Conn.

P.25

Combo Jack

P.25

P.29

Int.KBDTouch Pad

P.29

RTC CKT.

A A

DC/DC Interface CKT.

P.12

Security Classification

LED/Power On/Off

P.29P.30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

P02-Block diagram

LA-C571P

1.0

2 44Tuesday, June 16, 2015

RT8171BGQW

VGG_PWRGD

(PU600)

VR12_1_VR_ON

RT8171BGQW (PU800)

SYX196DQNC

SPOK

(PU500) (PJP500)

1 1

ADAPTER

CHARGER

1500mA

B+_3/5V

B+

SYSON

SUSP#

(FX2)

+INV_PWR_SRC

TPS51225CRUKR (PU100)

RT8207PGQW (PU200)

BATTERY

EC_ON

2 2

EC_ON

3 3

4 4

TPS51225CRUKR (PU100)

6400mA

11000mA

12mA

1000mA

4500mA

6620mA

6560 mA

+VCC_CORE

+VGG_CORE

+1.05VALWP

+0.675VSP

+1.35VP

+5VALWP

+3VALWP

+3VLP

5700mA5700mA

8uA

(JP12)

12mA

1000mA

(PJP202)

4500mA

(PJP201)

6620mA

(PJP100)

6560 mA

(PJP101)

+1.05VALW

+CHTRTC

UE1

+0.675VS

+5VALW

+3VALW

3500mA

(JPC4)

+1.35V

USB_EN#

SUSP# 5VS_EN

(RE2 0603 Short Pad)

+1.8VALW_PW RGD 3V_SOC_EN

VR12.1_VR_ON

+1.24VALW_PW RGD

(PJP400)

+1.15VALW_PW RGD

SUSP# 3VS_EN

2500mA

(JPC3)

2000mA

(PJP302)

+1.05V_VNN

+1.35V_DDR_VDDQ

(JPC6)

JDIMM1

SY6288D20AAC (UI5)

SY6288D20AAC (UI4)

EM5209VF (U38)

1500mA

4315mA

20 mA

(RE6)

+5V_USB_PWR1

+5V_USB_PWR2

(JP37)

+3VALW_EC

+3VS_TPIN

UC23 USB SW

FSUSB42MUX

EM5209VF

U37

SY8032ABC (PU300) (PJP301)

SY8032ABC (PU400) (PJP401)

SY8032ABC (PU301) (PJP303)

EM5209VF (U38)

200mA

(JP39)

800mA

5364mA

(JP36)

+3V_SOC

+1.15VALWP

+1.8VALWP

+1.24VALWP

+3VS

MODEL NAME: PCB NAME: REVISION: DATE:

+5VS

700mA

700mA1680mA

+1.15VALW

+1.8VALW

700mA700mA

ENVDD_R

(RX27 0603 Short PAD)

(RM7 1206)

+1.24VALW

SY6288C20AAC (UX4)

150mA

+3VS_WLAN_NGFF

(RR9 , 0603 Short Pad)

thermal sensor

1500mA

+5V_3V_HDD

@(JP14)

200mA

+5VS_TOUCH

@(RX29)

(RX28 , 0603 ,Short Pad)

(FX1 , 1206)

(RV54 0805 Short Pad )

(RV59 0603 Short Pad)

+3VS_CAM

+3VS_CARD

(U2407)

Power Rail Block Diagram

LA-C571PR02 2015/03/27

0.2

2015/04/13

200mA

1000mA

1500mA

(JP7)

1500mA

(JP13)

EN_DFAN1

20 mA

CAPS_LED

(RE60)

550mA

(RC190)

500mA

(RC191)

35mA

(RC87)

SUSP#

1.8VS_ON

SUSP#

(PJP404)

(JPC5)

1500mA

+VDISPLAY_VCC

+5VS_ODD_R1

+5V_3V_HDD

NCT3942S

(UE3)

KB_CAPS_PWR

1000mA

+5V_PVDD

1000mA

+5V_AUDIO

+3V_+1.8V_SDIO

+1.8V_XDP_AB

+1.8V_SPI

EM5209VF (U37)

G971ADJF11U (PU402)

+1.24V_USB_VDDQ

+LCDVDD

+5VS_TOUCH

(RS12 , Short Pad)

1000 mA

+5VS_ODD

+FAN_POWER

550mA

(JP38)

750mA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(RC192)

+1.8VS

750mA

+1.5VSP

(PJP405)

2014/11/10 2015/11/25

+1.8VS_XDP_CD

+1.5VS

Compal Secret Data

Deciphered Date

UA1 , Audio

Compal Electronics, Inc.

Title

P03-DB block diagram

Size Document Numb er Rev

LA-C571P

Date: Sheet of

3 44Tuesday, June 1 6, 2015

1.0

Voltage Rails

S0 S3 S4/S5Power Plane Description

VIN

BATT+ 12V Battery power supply

B+

1 1

+RTCVCC RTC Battery Power

+1.05VALW

+1.24VALW +1.24v Always power rail

+1.8VALW

+3VALW +3.3v Always power rail

+5VALW

+VCC_CORE Core voltage for SOC

+VGG_CORE GFX voltage for SOC

+0.675VS +0.675V power rail for DDR3L Terminator

+1.15VALW

2 2

+1.35VS ON

+1.5VS

+1.8VS

+3VS

+5VS

19V Adapter power supply

AC or battery power rail for power circuit. (19V/12V)

+1.05v Always power rail

+1.8v Always power rail

+5.0v Always power rail

+1.35V power rail for DDR3L+1.35V

+1.35v system power rail

+1.5v system power rail

+1.8v system power rail

+3.3v system power rail

+5.0v system power rail

ON ON

ON ONON

ON ON ON

ON ONON

ON ON ON

ONONON

ONON ON

ONONON+3V_SOC +3V_SOC Always power rail

ON ONON

ON ON

ON OFF OFF

ON OFF OFF+1.15VALW system power rail

ON OFFOFF

ON OFF OFF

ON OFFOFF

OFF

OFF OFF

OFFON OFF

Board ID / SKU ID Table for AD channel

BOARD ID Table

Board ID

0 1 2 3

PCB Revision

0.1

0.2

0.3

1.0

BOM Option Table

Item BOM Structure

Unpop @

CONN@Connector

XDP (Debug Port)

XDP@ EMI@EMC requirement NEMI@EMC requirement unpop LPC18@LPC18 LPC33@LPC33 RF@Rvs. RF requirement ESD@ESD requirement

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

ESD requirement unpop NESD@

NXDP@XDP (Debug Port) unpop

For JUMP JP@

3 3

For PCB For CPU SATA re-Driver

PCB@ SOC@ 601@

SOC1@

Test Point TP@ SATA re-Driver unpop N601@

43 level BOM table

4319Y031L01 MB AC571 AAL14 BSW U PEN HDMI 4319Y031L02

4 4

MB AC571 AAL14 BSW U CEL HDMI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

2014/02/26 2015/02/25

Compal Secret Data

EMI@/ESD@/XDP@/LPC33@/PCB@/ODD@/SOC@/601@/N601@/PARADE@

EMI@/ESD@/XDP@/LPC33@/PCB@/ODD@/SOC1@/601@/N601@/PARADE@

Deciphered Date

BOM Structure43 Level Description

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Date: Sheet of

Compal Electronics, Inc.

P04-Notes List

LA-C571P

1.0

4 44Tuesday, June 16, 2015

MODEL NAME:

SOC_SMB_CLK

HW3 follow Intel SCL

D D

0p92 P.43 use 1k Ohm

RP68

2.2K

RP68

SOC_SMB_CLK

SOC_SMB_DATA

SOC

+1.8VALW

AM6

AM7

BSW

RC174

1K,@

RC175

RC158

0 ohm

RC159

1K,@

I2C_5_SDA_R

C C

B B

A A

KBC KB9022QD

+1.8VALW

AB2

I2C_5_SCL

I2C_5_SDA

AC3

EC_SMB_CK2_EC

EC_SMB_DA2_EC

EC_SMB_CK1

EC_SMB_DA1

TP_CLK

TP_DATA

RC209

RC208

SOC_SMB_DATA

+1.8VALW

I2C_5_SCL_R

RP36

RE10

RE9

0 , XDP@

Q2516

Dual N-MOS

DMN63D8

+1.8VALW

Q2514

Dual

N-MOS

2.2K

4.7K

SMB_XDP_SCL

SMB_XDP_SDA

R1184

R1183

SOC_SMB_CLK_L

SOC_SMB_DATA_L

R1181

R1182

I2C_5_SDA_R_L

+3VALW_EC

+3VS_TP

10K

I2C_5_SCL_R_L

+3VALW

+3VS

Q2517

Dual

N-MOS

DMN63D8

+3VALW

+3VS

Q2515

N-MOS

JXDP1 CONN@

Dual

RE15@

Reserve

RE16@

PR717

PR719

PR8

PR9

RP36

10K

RE22

0 ohm

RE23

0 ohm

100 ohm

2.2K

EC_SMB_CK2

EC_SMB_DA2

RE17

RE19

I2C5_SCL_TP_R

I2C5_SDA_TP_R

CLK_SMB

DAT_SMB

+3VS

+3VS_TP

R2451

PBATT1

JTP

2.2K

R2449

0 ,@

RE32

POWERPU700 Charger

BATT CONN

PCB NAME: REVISION: DATE:

EC_SMB_CK2

EC_SMB_DA2

0 ,@

RE33

I2C5_SCL_TP_R

I2C5_SDA_TP_R

+3VS

THERMAL_SMB_CK2

THERMAL_SMB_DA2

SMBUS Address [?]

2015/04/13

202

DIMMA

200

U2407

SMbus Block Diagram

LA-C571 PR02 2015/03/27

0.2

SMBUS Address [?]

I2C Address [?]

Thermal

SMBUS Address [?]

Sensor

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

P05-SMBus block diagram

Size Document Number Rev

LA-C571P

Date: Sheet of

5 44Tuesday, June 16, 2015

1.0

D D

S5->S0 S0->S3 S3->S0

ACIN

2.785ms

+3VLP

EC_ON

+3VALW

+5VALW

SPOK

+1.24VALW

+1.8VALW

+3V_SOC

C C

VNN

2.948ms

455.9us

499.1us

4.732ms

229.8us

3.259ms

4.368ms

8.809ms

S0->S5

ACIN

+3VLP

EC_ON

+3VALW

+5VALW

SPOK

VNN

+1.24VALW

+1.8VALW

+3V_SOC

ON/OFF

EC_RSMRST#

PBTN_OUT#

EC_SLP_S4#

EC_SLP_S3#

SYSON

+1.35V

DDR_PWROK

VR_ON

+1.15VALW

B B

+VCC_CORE

+VGG_CORE

VGATE

SUSP#

+1.5VS

+1.8VS

+3VS

+5VS

+0.675VS

SOC_VCCA_PWROK

PMC_PLTRST#

A A

98ms

80.81ms

102.5ms

60ms

140ms

140.5ms

146.2ms

280.8ms

282.2ms

716.6us

2.917ms

1.388ms

3.12ms

1.702ms

2.509ms

3.715ms

3.94ms

7.981ms

120.9ms

135.1ms

24.9ms

1.574ms

14.2ms

1.97us

30.85ms

43.7ms

37.52ms

198.5us

194.1us

5.737us

19.34ms

19.94ms

28.1ms

211.8ms

134.4ms

3.119ms

717us

155.5ms

2.933ms

1.403ms

1.699ms

2.553ms

3.718ms

3.966ms

7.966ms

121ms

135.8ms

48.71ms

28.6ms

197.8us

198.9us

4.839us

31.38ms

1.615ms

14.14ms

18.96ms

19.58ms

27.9ms

2.939us

23.68ms

ON/OFF

EC_RSMRST#

PBTN_OUT#

EC_SLP_S4#

EC_SLP_S3#

211ms

SYSON

212.1ms

+1.35V

206.8ms

DDR_PWROK

VR_ON

+1.15VALW

+SOC_VCC

+SOC_VGG

VGATE

SUSP#

+1.5VS

+1.8VS

+3VS

+5VS

+0.675VS

SOC_VCCA_PWROK

PMC_PLTRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

P06-Power Sequence

LA-C571P

6 44Tuesday, June 16, 2015

1.0

MODEL NAME: PCB NAME: REVISION: DATE:

D D

C C

B B

2015/04/13

Power Sequence Block Diagram

LA-C571PR02 2015/03/27

0.2

AC MODE

DC MODE

VIN

BATT+

PU700 ISL88731 CHRTZ-T

PQ706 PMOS

V0.2 Modify

1.05VALW_PWRGD

15c

(VR12.1_VR_ON)

SYX198DQNC (PU500) +1.05VALW (+1.05V_VNN)

PR500

B7A6

SPOK

PU100

B+

TPS51225 CRUKR

VCOUT0_PH

A11

ON/OFFBTN#

PLT_RST#

1.05VALW_PWRGD

SPOK

+3VALW +5VALW

+3VLP,VLBATT+

EC_ON

PR300

104

112

114

15c

+1.15VALWP_ON

121

RE64

V0.2 Modify

RE63

UE1 EC9022QD

116

1.15VALWP_EC

V0.3 Modify

SY8032ABC (PU300) +1.15VALW

100

PBTN_OUT# PMU_RSTBTN#

122

SIO_SLP_S3#

SIO_SLP_S4#

123

SYSON

SUSP#

VGATE

VR_ON_EC

EM5209VF

SUSP#

(U38) +5VS, +3VS

EM5209VF (U37) +1.8VS

15g

RE62

+1.15VALW_PWRGD

Level UC7

PCH_PWROK

15b

V0.2 Modify

PR308

DDR_PWROK SOC_DRAM_PWROK

17a

SOC_VCCA_PWROK

EC_RSMRST#

R27

R35, @

Level QC7

R34

EC_KBRST#

RT8207PGQW (PU200)

15a

DDR_PWROK SOC_DRAM_PWROK

+1.24VALWP_ON

PMU_SLP_S3#

PMU_SLP_S4#

15a

SY8032ABC (PU301)

+1.24VALW

AV28

AV26

G16

F18

M16

B14

C12

V40

AD42

AD41

AD40

15d

SOC USOC1

SVID Bus

F14

UC5

+1.24VALW_PWRGD

PMU_PLTRST#

PLT_RST#

SY8032ABC (PU400) +1.8VALW

+1.8VALW_PG

3V_SOC_EN

A10

EM5209VF (U37) +3V_SOC

G971ADJF11U

SUSP#

(PU402) +1.5VS

RE12

VR_ON

A A

R464

15c

(VR12.1_VR_ON)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

13,14,15

SVID Bus

VGG_PWRGD

+VGG_CORE

RT8171BGQW

(PU800)

15e

2014/11/10 2015/11/25

15d

SVID Bus

13,14,15

RT8171BGQW (PU600)

15g

VGATE

Compal Secret Data

Deciphered Date

+VCC_CORE

15f

Compal El ectronics, Inc.

Title

P07-Power Sequence Block Diagram

Size Document Num ber Rev

Custom

LA-C571P

Date: Sheet of

7 44Tuesday, June 16, 2015

1.0

Main Func = CPU

D D

UC1

SOC@

S IC A31 FH80665017 15906 QJ4S C0 1.6G

Part Number = SA00008U 62L

C C

UC1

SOC1@

S IC A31 FH80665017 15914 QJ4V C0 1.6G

Part Number = SA00008U 52L

1 2

DDR_M0_MA[0..15 ]<19>

DDR_M0_BS2<19> DDR_M0_BS1<19> DDR_M0_BS0<19>

DDR_M0_CAS#<19> DDR_M0_RAS#<19> DDR_M0_W E#< 19> DDR_M0_CS #1< 19> DDR_M0_CS #0< 19>

DDR_M0_CL K1< 19> DDR_M0_CL K#1<19> DDR_M0_CK E1<19>

DDR_M0_CL K0<19> DDR_M0_CL K#0<19> DDR_M0_CK E0<19>

DDR_M0_ODT 0<19> DDR_M0_ODT 1<19>

+0.675V_M0_VREFC A +0.675V_M0_VREFD Q

DDR_M0_DR AMRST#<19>

DDR_M0_DM [4..7]<19>

DDR_M0_DM [0..3]<19>

DDR_M0_DQS [0..7]<19> DDR_M0_DQS #[0..7]<19>

DDR_M0_RC OMP

RC1182_0402_ 1%

DDR_M0_MA15 DDR_M0_MA14 DDR_M0_MA13 DDR_M0_MA12 DDR_M0_MA11 DDR_M0_MA10 DDR_M0_MA9 DDR_M0_MA8 DDR_M0_MA7 DDR_M0_MA6 DDR_M0_MA5 DDR_M0_MA4 DDR_M0_MA3 DDR_M0_MA2 DDR_M0_MA1 DDR_M0_MA0

DDR_M0_BS2 DDR_M0_BS1 DDR_M0_BS0

DDR_M0_CAS# DDR_M0_RAS# DDR_M0_W E# DDR_M0_CS #1 DDR_M0_CS #0

DDR_M0_CL K1 DDR_M0_CL K#1 DDR_M0_CK E1

DDR_M0_CL K0 DDR_M0_CL K#0 DDR_M0_CK E0

DDR_M0_ODT 0 DDR_M0_ODT 1

DDR_M0_DR AMRST# SOC_DRAM_PW ROK

DDR_M0_RC OMP

DDR_M0_DM 7 DDR_M0_DM 6 DDR_M0_DM 5 DDR_M0_DM 4 DDR_M0_DM 3 DDR_M0_DM 2 DDR_M0_DM 1 DDR_M0_DM 0

DDR_M0_DQS 7 DDR_M0_DQS #7 DDR_M0_DQS 6 DDR_M0_DQS #6 DDR_M0_DQS 5 DDR_M0_DQS #5 DDR_M0_DQS 4 DDR_M0_DQS #4 DDR_M0_DQS 3 DDR_M0_DQS #3 DDR_M0_DQS 2 DDR_M0_DQS #2 DDR_M0_DQS 1 DDR_M0_DQS #1 DDR_M0_DQS 0 DDR_M0_DQS #0

UC1A

BD49

DDR3_M0_MA_15

BD47

DDR3_M0_MA_14

BF44

DDR3_M0_MA_13

BF48

DDR3_M0_MA_12

BB49

DDR3_M0_MA_11

BJ45

DDR3_M0_MA_10

BE52

DDR3_M0_MA_9

BD44

DDR3_M0_MA_8

BE46

DDR3_M0_MA_7

BB46

DDR3_M0_MA_6

BH48

DDR3_M0_MA_5

BD42

DDR3_M0_MA_4

BH47

DDR3_M0_MA_3

BJ48

DDR3_M0_MA_2

BC42

DDR3_M0_MA_1

BB47

DDR3_M0_MA_0

BF52

DDR3_M0_BS_2

AY40

DDR3_M0_BS_1

BH46

DDR3_M0_BS_0

BG45

DDR3_M0_CASB

BA40

DDR3_M0_RASB

BH44

DDR3_M0_WEB

AU38

DDR3_M0_CSB_1

AY38

DDR3_M0_CSB_0

BD38

DDR3_M0_CK_1

BF38

DDR3_M0_CKB_1

AY42

DDR3_M0_CKE_1

BD40

DDR3_M0_CK_0

BF40

DDR3_M0_CKB_0

BB44

DDR3_M0_CKE_0

AT30

RSVD1

AU30

RSVD2

AV36

DDR3_M0_ODT_0

BA38

DDR3_M0_ODT_1

AT28

DDR3_M0_OCAVREF

AU28

DDR3_M0_ODQVREF

BA42

DDR3_M0_DRAMRSTB

AV28

DDR3_DRAM_PWROK

BA28

DDR3_M0_RCOMPPD

BH30

DDR3_M0_DM_7

BD32

DDR3_M0_DM_6

AY36

DDR3_M0_DM_5

BG41

DDR3_M0_DM_4

BA53

DDR3_M0_DM_3

AP44

DDR3_M0_DM_2

AT48

DDR3_M0_DM_1

AP52

DDR3_M0_DM_0

BH32

DDR3_M0_DQS_7

BG31

DDR3_M0_DQSB_7

BC30

DDR3_M0_DQS_6

BC32

DDR3_M0_DQSB_6

AT32

DDR3_M0_DQS_5

AT34

DDR3_M0_DQSB_5

BH40

DDR3_M0_DQS_4

BG39

DDR3_M0_DQSB_4

AY52

DDR3_M0_DQS_3

BA51

DDR3_M0_DQSB_3

AT42

DDR3_M0_DQS_2

AT41

DDR3_M0_DQSB_2

AV47

DDR3_M0_DQS_1

AV48

DDR3_M0_DQSB_1

AM52

DDR3_M0_DQS_0

AM51

DDR3_M0_DQSB_0

BSW-MCP-ED S_FCBGA1170

CHV_MCP_EDS

DDR0

1 OF 13

DDR3_M0_DQ_63 DDR3_M0_DQ_62 DDR3_M0_DQ_61 DDR3_M0_DQ_60 DDR3_M0_DQ_59 DDR3_M0_DQ_58 DDR3_M0_DQ_57 DDR3_M0_DQ_56

DDR3_M0_DQ_55 DDR3_M0_DQ_54 DDR3_M0_DQ_53 DDR3_M0_DQ_52 DDR3_M0_DQ_51 DDR3_M0_DQ_50 DDR3_M0_DQ_49 DDR3_M0_DQ_48

DDR3_M0_DQ_47 DDR3_M0_DQ_46 DDR3_M0_DQ_45 DDR3_M0_DQ_44 DDR3_M0_DQ_43 DDR3_M0_DQ_42 DDR3_M0_DQ_41 DDR3_M0_DQ_40

DDR3_M0_DQ_39 DDR3_M0_DQ_38 DDR3_M0_DQ_37 DDR3_M0_DQ_36 DDR3_M0_DQ_35 DDR3_M0_DQ_34 DDR3_M0_DQ_33 DDR3_M0_DQ_32

DDR3_M0_DQ_31 DDR3_M0_DQ_30 DDR3_M0_DQ_29 DDR3_M0_DQ_28 DDR3_M0_DQ_27 DDR3_M0_DQ_26 DDR3_M0_DQ_25 DDR3_M0_DQ_24

DDR3_M0_DQ_23 DDR3_M0_DQ_22 DDR3_M0_DQ_21 DDR3_M0_DQ_20 DDR3_M0_DQ_19 DDR3_M0_DQ_18 DDR3_M0_DQ_17 DDR3_M0_DQ_16

DDR3_M0_DQ_15 DDR3_M0_DQ_14 DDR3_M0_DQ_13 DDR3_M0_DQ_12 DDR3_M0_DQ_11 DDR3_M0_DQ_10

DDR3_M0_DQ_9 DDR3_M0_DQ_8

DDR3_M0_DQ_7 DDR3_M0_DQ_6 DDR3_M0_DQ_5 DDR3_M0_DQ_4 DDR3_M0_DQ_3 DDR3_M0_DQ_2 DDR3_M0_DQ_1 DDR3_M0_DQ_0

BG33 BH28 BJ29 BG28 BG32 BH34 BG29 BJ33

BD28 BF30 BA34 BD34 BD30 BA32 BC34 BF34

AV32 AV34 BD36 BF36 AU32 AU34 BA36 BC36

BH38 BH36 BJ41 BH42 BJ37 BG37 BG43 BG42

BB51 AW53 BC52 AW51 AV51 BC53 AV52 BD52

AV42 AP41 AV41 AT44 AP40 AT38 AP42 AT40

AV45 AY50 AT50 AP47 AV50 AY48 AT47 AP48

AP51 AR53 AK52 AL53 AR51 AT52 AL51 AK51

DDR_M0_D6 0 DDR_M0_D5 8 DDR_M0_D6 2 DDR_M0_D5 9 DDR_M0_D5 7 DDR_M0_D6 1 DDR_M0_D6 3 DDR_M0_D5 6

DDR_M0_D5 5 DDR_M0_D5 4 DDR_M0_D5 3 DDR_M0_D5 2 DDR_M0_D5 1 DDR_M0_D5 0 DDR_M0_D4 9 DDR_M0_D4 8

DDR_M0_D4 7 DDR_M0_D4 6 DDR_M0_D4 5 DDR_M0_D4 4 DDR_M0_D4 3 DDR_M0_D4 2 DDR_M0_D4 1 DDR_M0_D4 0

DDR_M0_D3 9 DDR_M0_D3 8 DDR_M0_D3 7 DDR_M0_D3 6 DDR_M0_D3 5 DDR_M0_D3 4 DDR_M0_D3 3 DDR_M0_D3 2

DDR_M0_D3 1 DDR_M0_D2 5 DDR_M0_D3 0 DDR_M0_D2 4 DDR_M0_D2 8 DDR_M0_D2 6 DDR_M0_D2 9 DDR_M0_D2 7

DDR_M0_D1 8 DDR_M0_D1 6 DDR_M0_D2 3 DDR_M0_D2 2 DDR_M0_D2 1 DDR_M0_D1 9 DDR_M0_D1 7 DDR_M0_D2 0

DDR_M0_D1 5 DDR_M0_D1 4 DDR_M0_D1 3 DDR_M0_D1 2 DDR_M0_D1 1 DDR_M0_D1 0 DDR_M0_D9 DDR_M0_D8

DDR_M0_D7 DDR_M0_D6 DDR_M0_D5 DDR_M0_D4 DDR_M0_D3 DDR_M0_D2 DDR_M0_D1 DDR_M0_D0

DDR_M0_D[3 2..63] <19>

DDR_M0_D[0 ..31] <19>

B B

Place close to SOC pins

+1.35V

RC5 10K_0402_1 %

Pull high 10K on page 36

1 2

SOC_DRAM_PW ROK

1 2

RC180 0 _0402_5%

SHORT@

Power Name and Connection Check OK

DDR_PWR OK

DDR_PWROK(BTM) From Power controller

DDR_PWR OK <36>

+1.35V_DDR_VDD Q + 0.675V_M0_VREFCA

RC2 4.7K_ 0402_1%

RC6 4.7K_ 0402_1%

RC8 4.7K_ 0402_1%

RC10 4.7K_0402_1 %

8 mils minimum for maximum of 300 mils in breakout area

+0.675V_M0_VREFC A_R

1 2

SD0344701 80

+0.675V_M0_VREFD Q_R

1 2

SHORT@

RC3 0 _0402_5%

1 2

SHORT@

RC9 0 _0402_5%

CC1 .1U_0402_1 6V7K

+0.675V_M0_VREFD Q+1.35V_DDR_VDD Q

CC3 .1U_0402_1 6V7K

Place close to SOC pins Place close to SOC pins

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

P08-BSW(1/8) DDR3L-CH0

LA-C571P

8 44Tuesday, June 16, 2015

1.0

Main Func = CPU

D D

C C

B B

1 2

RC11182_0402_ 1% @

Place close to SOC pins

SOC_VCCA_PWR OK<12>

1 2

C1159 22P_0402_5 0V8J

SOC_VCCA_PWR OK

ESD@

SOC_VCCA_PWR OK

DDR_M1_RC OMP

BD5 BD7

BF10

BF6 BB5 BJ9 BE2

BD10

BE8 BB8 BH6

BD12

BH7 BJ6

BC12

BB7

BF2

AY14

BH8

BG9 BA14 BH10 AU16 AY16

BD16

BF16

AY12

BD14

BF14

BB10

AT24

AU24

AV18 BA16

AT26

AU26

BA12 AV26

BA26

BH24 BD22 AY18 BG13

BA1 AP10

AT6

AP2

BH22 BG23 BC24 BC22

AT22

AT20 BH14 BG15

AY2

BA3 AT12 AT13

AV7

AV6

AM2 AM3

UC1B

DDR3_M1_MA_15 DDR3_M1_MA_14 DDR3_M1_MA_13 DDR3_M1_MA_12 DDR3_M1_MA_11 DDR3_M1_MA_10 DDR3_M1_MA_9 DDR3_M1_MA_8 DDR3_M1_MA_7 DDR3_M1_MA_6 DDR3_M1_MA_5 DDR3_M1_MA_4 DDR3_M1_MA_3 DDR3_M1_MA_2 DDR3_M1_MA_1 DDR3_M1_MA_0

DDR3_M1_BS_2 DDR3_M1_BS_1 DDR3_M1_BS_0

DDR3_M1_CASB DDR3_M1_RASB DDR3_M1_WEB DDR3_M1_CSB_1 DDR3_M1_CSB_0

DDR3_M1_CK_1 DDR3_M1_CKB_1 DDR3_M1_CKE_1

DDR3_M1_CK_0 DDR3_M1_CKB_0 DDR3_M1_CKE_0

RSVD1 RSVD2

DDR3_M1_ODT_0 DDR3_M1_ODT_1

DDR3_M1_OCAVREF DDR3_M1_ODQVREF

DDR3_M1_DRAMRSTB DDR3_VCCA_PWROK

DDR3_M1_RCOMPPD

DDR3_M1_DM_7 DDR3_M1_DM_6 DDR3_M1_DM_5 DDR3_M1_DM_4 DDR3_M1_DM_3 DDR3_M1_DM_2 DDR3_M1_DM_1 DDR3_M1_DM_0

DDR3_M1_DQS_7 DDR3_M1_DQSB_7 DDR3_M1_DQS_6 DDR3_M1_DQSB_6 DDR3_M1_DQS_5 DDR3_M1_DQSB_5 DDR3_M1_DQS_4 DDR3_M1_DQSB_4 DDR3_M1_DQS_3 DDR3_M1_DQSB_3 DDR3_M1_DQS_2 DDR3_M1_DQSB_2 DDR3_M1_DQS_1 DDR3_M1_DQSB_1 DDR3_M1_DQS_0 DDR3_M1_DQSB_0

BSW-MCP-ED S_FCBGA1170

CHV_MCP_EDS

DDR1

2 OF 13

DDR3_M1_DQ_63 DDR3_M1_DQ_62 DDR3_M1_DQ_61 DDR3_M1_DQ_60 DDR3_M1_DQ_59 DDR3_M1_DQ_58 DDR3_M1_DQ_57 DDR3_M1_DQ_56

DDR3_M1_DQ_55 DDR3_M1_DQ_54 DDR3_M1_DQ_53 DDR3_M1_DQ_52 DDR3_M1_DQ_51 DDR3_M1_DQ_50 DDR3_M1_DQ_49 DDR3_M1_DQ_48

DDR3_M1_DQ_47 DDR3_M1_DQ_46 DDR3_M1_DQ_45 DDR3_M1_DQ_44 DDR3_M1_DQ_43 DDR3_M1_DQ_42 DDR3_M1_DQ_41 DDR3_M1_DQ_40

DDR3_M1_DQ_39 DDR3_M1_DQ_38 DDR3_M1_DQ_37 DDR3_M1_DQ_36 DDR3_M1_DQ_35 DDR3_M1_DQ_34 DDR3_M1_DQ_33 DDR3_M1_DQ_32

DDR3_M1_DQ_31 DDR3_M1_DQ_30 DDR3_M1_DQ_29 DDR3_M1_DQ_28 DDR3_M1_DQ_27 DDR3_M1_DQ_26 DDR3_M1_DQ_25 DDR3_M1_DQ_24

DDR3_M1_DQ_23 DDR3_M1_DQ_22 DDR3_M1_DQ_21 DDR3_M1_DQ_20 DDR3_M1_DQ_19 DDR3_M1_DQ_18 DDR3_M1_DQ_17 DDR3_M1_DQ_16

DDR3_M1_DQ_15 DDR3_M1_DQ_14 DDR3_M1_DQ_13 DDR3_M1_DQ_12 DDR3_M1_DQ_11 DDR3_M1_DQ_10

DDR3_M1_DQ_9 DDR3_M1_DQ_8

DDR3_M1_DQ_7 DDR3_M1_DQ_6 DDR3_M1_DQ_5 DDR3_M1_DQ_4 DDR3_M1_DQ_3 DDR3_M1_DQ_2 DDR3_M1_DQ_1 DDR3_M1_DQ_0

BG21 BH26 BJ25 BG26 BG22 BH20 BG25 BJ21

BD26 BF24 BA20 BD20 BD24 BA22 BC20 BF20

AV22 AV20 BD18 BF18 AU22 AU20 BA18 BC18

BH16 BH18 BJ13 BH12 BJ17 BG17 BG11 BG12

BB3 AW1 BC2 AW3 AV3 BC1 AV2 BD2

AV12 AP13 AV13 AT10 AP14 AT16 AP12 AT14

AV9 AY4 AT4 AP7 AV4 AY6 AT7 AP6

AP3 AR1 AK2 AL1 AR3 AT2 AL3 AK3

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

P09-BSW(2/8) DDR3L-CH1

LA-C571P

9 44Tuesday, June 16, 2015

1.0

Main Func = CPU

UC1C

HDMI_TX2+<21>

SOC_DP0_HPD #<21>

SOC_DP0_CT RL_CLK<21> SOC_DP0_CT RL_DATA<21>

EDP_CPU_LANE _P0<20 > EDP_CPU_LANE _N0<20>

EDP_CPU_LANE _P1<20 > EDP_CPU_LANE _N1<20>

EDP_CPU_AUX<20> EDP_CPU_AUX#<20>

EDP_CPU_HP D<20>

SOC_DDI1_ENBKL<18> SOC_DDI1_PW M<18> SOC_DDI1_ENVDD<18 >

1 2

SHORT@

1 2

SHORT@

HDMI_TX2-<21>

HDMI_TX1+<21> HDMI_TX1-<21>

HDMI_TX0+<21> HDMI_TX0-<21>

HDMI_CLK+<21> HDMI_CLK-<21>

T78 @TP T79 @TP

T65 @TP T66 @TP T67 @TP

1 2

RC20 402_0402_ 1%

T68 @TP T69 @TP

T70 @TP T71 @TP

1 2

RC22 402_0402_ 1%

D D

<HDMI>

<eDP>

C C

B B

UART_0_CT XD_DRXD_OP<25> UART_0_CRXD_ DTXD_OP<25>

UART_0_CT XD_DRXD_OP UART_0_CRXD_ DTXD_OP

RC391 0_0402_5% RC392 0_0402_5%

HDMI_TX2+ HDMI_TX2-

HDMI_TX1+ HDMI_TX1-

HDMI_TX0+ HDMI_TX0-

HDMI_CLK+ HDMI_CLK-

SOC_DP0_AUXP SOC_DP0_AUXN

SOC_DP0_HPD #

SOC_DP0_CT RL_CLK SOC_DP0_CT RL_DATA

SOC_DDI0_ENBKL SOC_DDI0_PW M SOC_DDI0_ENVDD DDI0_PLLOBS_P DDI0_PLLOBS_N

EDP_CPU_LANE _P0 EDP_CPU_LANE _N0

EDP_CPU_LANE _P1 EDP_CPU_LANE _N1

EDP_TXP2 EDP_TXN2

EDP_TXP3 EDP_TXN3

EDP_CPU_AUX EDP_CPU_AUX#

EDP_CPU_HP D

SOC_DDI1_ENBKL SOC_DDI1_PW M SOC_DDI1_ENVDD DDI1_PLLOBS_P DDI1_PLLOBS_N

SOC_DP2_CT RL_CLK SOC_DP2_CT RL_DATA

D50

DDI0_TXP_0

C51

DDI0_TXN_0

H49

DDI0_TXP_1

H50

DDI0_TXN_1

F53

DDI0_TXP_2

F52

DDI0_TXN_2

G53

DDI0_TXP_3

G52

DDI0_TXN_3

H47

DDI0_AUXP

H46

DDI0_AUXN

W51

HV_DDI0_HPD

Y51

HV_DDI0_DDC_SCL

Y52

HV_DDI0_DDC_SDA

V52

PANEL0_BKLTEN

V51

PANEL0_BKLTCTL

W53

PANEL0_VDDEN

F38

DDI0_PLLOBS_P

G38

DDI0_PLLOBS_N

J51

DDI1_TXP_0

H51

DDI1_TXN_0

K51

DDI1_TXP_1

K52

DDI1_TXN_1

L53

DDI1_TXP_2

L51

DDI1_TXN_2

M52

DDI1_TXP_3

M51

DDI1_TXN_3

M42

DDI1_AUXP

K42

DDI1_AUXN

R51

HV_DDI1_HPD

P51

PANEL1_BKLTEN

P52

PANEL1_BKLTCTL

R53

PANEL1_VDDEN

F47

DDI1_PLLOBS_P

F49

DDI1_PLLOBS_N

F40

DDI2_TXP_0

G40

DDI2_TXN_0

J40

DDI2_TXP_1

K40

DDI2_TXN_1

F42

DDI2_TXP_2

G42

DDI2_TXN_2

D44

DDI2_TXP_3

F44

DDI2_TXN_3

D48

DDI2_AUXP

C49

DDI2_AUXN

U51

HV_DDI2_HPD

T51

HV_DDI2_DDC_SCL

T52

HV_DDI2_DDC_SDA

B53

RSVD6

A52

RSVD3

E52

RSVD9

D52

RSVD8

B50

RSVD5

B49

RSVD4

E53

RSVD10

C53

RSVD7

A51

RSVD2

A49

RSVD1

G44

RSVD11

BSW-MCP-ED S_FCBGA1170

CHV_MCP_EDS

M44

RSVD15

K44

RSVD12

K48

RSVD14

K47

RSVD13

RSVD17 RSVD16

MCSI_COMP

SDMMC1_D0 SDMMC1_D1 SDMMC1_D2

MMC1_D5 MMC1_D6 MMC1_D7

MMC1_RCLK

SDMMC2_D0 SDMMC2_D1 SDMMC2_D2

SDMMC3_D0 SDMMC3_D1 SDMMC3_D2 SDMMC3_D3

T44 T45

Y47 Y48 V45 V47 V50 V48 T41 T42

P50 P48

P47 P45 M48 M47

T50 T48

P44

MCSI_COMP

AB41

GP_CAMSB00

AB45

GP_CAMSB01

AB44

GP_CAMSB02

AC53

GP_CAMSB03

AB51

GP_CAMSB04

AB52

GP_CAMSB05

AA51

GP_CAMSB06

AB40

GP_CAMSB07

Y44

GP_CAMSB08

Y42 Y41 V40

GP_CAMSB11

EMMC_1_CLK

EMMC_1_CMD

EMMC_1_D0

EMMC_1_D1

EMMC_1_D2

EMMC_1_D3

EMMC_1_D4

EMMC_1_D5

T10

EMMC_1_D6

T12

EMMC_1_D7

T13

EMMC_1_RCL K

P13

EMMC_1_RCO MP

K10 K9

M12 M10 K7 K6

SOC_LID_OUT#

F2 D2 K3

J1 J3 H3 G2

K2 L3 P12

SDIO_3_RCOMP

1 2

RC21 15 0_0402_1%

GP_CAMSB00 <16> GP_CAMSB01 <16> GP_CAMSB02 <16> GP_CAMSB03 <16> GP_CAMSB04 <16> GP_CAMSB05 <16> GP_CAMSB06 <16> GP_CAMSB07 <16>

GP_CAMSB08 <11,16>

GP_CAMSB11 <11>

EMMC_1_CLK <22> EMMC_1_CMD <22>

EMMC_1_D0 <22> EMMC_1_D1 <22> EMMC_1_D2 <22> EMMC_1_D3 <22> EMMC_1_D4 <22> EMMC_1_D5 <22> EMMC_1_D6 <22> EMMC_1_D7 <22> EMMC_1_RCL K <22>

1 2

RC23 10 0_0402_1%

SOC_LID_OUT# <18>

RC33

80.6_0402_1 %

Should be 80_0402_1%

<eMMC>

MCSI_1_CLKP MCSI_1_CLKN

DDI0

DDI1

SDMMC1

DDI2

SDMMC2

NC's

SDMMC3

3 OF 13

MCSI_1_DP_0 MCSI_1_DN_0 MCSI_1_DP_1 MCSI_1_DN_1 MCSI_1_DP_2 MCSI_1_DN_2

MCSI and Camera interface

MCSI_1_DP_3 MCSI_1_DN_3

MCSI_2_CLKP MCSI_2_CLKN

MCSI_2_DP_0 MCSI_2_DN_0 MCSI_2_DP_1 MCSI_2_DN_1

GP_CAMERASB00 GP_CAMERASB01 GP_CAMERASB02 GP_CAMERASB03 GP_CAMERASB04 GP_CAMERASB05 GP_CAMERASB06 GP_CAMERASB07 GP_CAMERASB08

GP_CAMERASB09 GP_CAMERASB10 GP_CAMERASB11

SDMMC1_CLK

SDMMC1_CMD

SDMMC1_D3_CD_B

MMC1_D4_SD_WE

SDMMC1_RCOMP

SDMMC2_CLK

SDMMC2_CMD

SDMMC2_D3_CD_B

SDMMC3_CLK

SDMMC3_CMD

SDMMC3_CD_B

SDMMC3_1P8_EN

SDMMC3_PWR_EN_B

SDMMC3_RCOMP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

P10-BSW(3/8) DDI,MCSI,SDMMC

LA-C571P

10 44Tu esday, June 16, 2015

1.0

Main Func = CPU

D D

<WLAN>

+1.8VALW

RC231 10K_0402_5 %

RC383 10K_0402_5 %

RC242 10K_0402_5 %

RC189 10K_0402_5 %@ RC326 10K_0402_5 %@ RC174 1K_0402_5%@ RC175 1K_0402_5%@

RC104 1K_0402_5%@

C C

Pull High 10k at LED Page

SOC_SATALED#<28,32>

+1.8VALW

B B

WL_OFF#<28,32> SOC_TP_INT#<29>

BT_ON#<28>

SOC_SCI#<17> SOC_SMI#<17>

A A

PCIE_PTX_C_DRX_P2<28> PCIE_PTX_C_DRX_N 2<28> PCIE_CRX_DTX_P2<28> PCIE_CRX_DTX_N2<28>

1 2

1 2 1 2 1 2 1 2

1 2

SOC_XTAL19_IN SOC_XTAL19_OUT

CC7 12P_0402_50V8J

Change P/N to SJ10000N700

19.2MHz_12pF

1 2

RC56 4.7K_0402_5 %

1 2

RC58 4.7K_0402_5 %

GPIO_SUS6 H +1.8VALW Page 11 SOC_SCI# PH +1.8VS Page 17 for 9022 EC_SCI# PH +3.3VS Page 32 for 9012

GPIO_SUS7 H +1.8VALW Page 11 SOC_SMI# PH +1.8VALW Page 17 EC_SMI# PH +3VALW_EC Page 32

WLAN_CLKR EQ#

SOC_TS_EN

SATA_DEVSLP

SATA_LED# EMMC_1_RST # I2C_5_SCL_R I2C_5_SDA_R

SOC_SMB_ALERT #

Need to confirm leakage

+1.8VS

123

1 2

RC37 200K_0402_1%

YC1

GND

SJ10000N70 0

19.2MHZ_12PF_ 7V19200001

WL_OFF# SOC_TP_INT# SEC_GPIO_SUS10 BT_ON# SEC_GPIO_SUS9

SOC_SCI# SOC_SMI#

GP_CAMSB08<10 ,16>

GP_CAMSB11<10>

PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N 2

RC26 10K_0402_5 %

1 2

SATA_LED#

QC3 MESS138W -G_SOT323-3

DDI0_ENABLE DDI1_ENABLE

1 2 1 2 1 2

1 2 1 2

CC8 12P_0402_50V8J

SHORT@ SHORT@ SHORT@

SHORT@ SHORT@

GP_CAMSB08

GP_CAMSB11

GND

RC380 0_0402_5% RC334 0_0402_5% RC338 0_0402_5%

RC227 0_0402_5% RC228 0_0402_5%

不不不不不不不不不不不不

不不不不不不不不不不不不不不不不不不不不不不不不

1 2

C1 .1U_0402_1 6V7K

1 2

C2 .1U_0402_1 6V7K

WLAN_CLKR EQ#<28>

CLK_PCIE_WL AN< 28> CLK_PCIE_WL AN#<28>

GPIO_SUS3

GPIO_SUS6 GPIO_SUS7

不不不不不不不不

+1.8VALW

Place close to SOC pins

1 2

RC35 0_0402_5%

1 2

RC36 402_0402_1%

T120@TP T142@TP T122@TP T123@TP T124@TP

1 2

RC60 10K_0402_5 %

1 2

RC62 10K_0402_5 %@

1 2

RC64 100K_0402_ 5%

1 2

RC66 10K_0402_5 %

1 2

RC68 10K_0402_5 %@

1 2

RC80 10K_0402_5 %@

1 2

RC118 10K_0402_5 %@

1 2

RC74 10K_0402_5 %@

1 2

RC76 10K_0402_5 %@

1 2

RC386 4.7K_0402_5 %

LPC33@

1 2

RC78 10K_0402_5 %@

1 2

RC82 10K_0402_5 %@

PCIE_CTX_DRX_P2 PCIE_CTX_DRX_N2 PCIE_CRX_DTX_P2 PCIE_CRX_DTX_N2

WLAN_CLKR EQ#

CLK_PCIE_WL AN CLK_PCIE_WL AN#

CLK_PCIE_P4 CLK_PCIE_N4

PCIE_OBS_P PCIE_OBS_N

SOC_SPI_CLK SOC_SPI_CS#0 SOC_SPI_CS#1 SOC_SPI_SI SOC_SPI_SO

SOC_XTAL19_IN SOC_XTAL19_OUT

BIOS/EFI Top Swap

UC1D

C24

PCIE_TXP0

B24

PCIE_TXN0

G20

PCIE_RXP0

J20

PCIE_RXN0

A25

PCIE_TXP1

C25

PCIE_TXN1

D20

PCIE_RXP1

F20

PCIE_RXN1

B26

PCIE_TXP2

C26

PCIE_TXN2

D22

PCIE_RXP2

F22

PCIE_RXN2

A27

PCIE_TXP3

C27

PCIE_TXN3

G24

PCIE_RXP3

J24

PCIE_RXN3

AM10

PCIE_CLKREQ0B

AM12

PCIE_CLKREQ1B

AK14

PCIE_CLKREQ2B

AM14

PCIE_CLKREQ3B

A21

CLK_DIFF_P_0

C21

CLK_DIFF_N_0

C19

CLK_DIFF_P_1

B20

CLK_DIFF_N_1

C18

CLK_DIFF_P_2

B18

CLK_DIFF_N_2

C17

CLK_DIFF_P_3

A17

CLK_DIFF_N_3

C16

RSVD20

B16

RSVD19

D26

PCIE_OBSP

F26

PCIE_OBSN

V14

SPI1_CLK

Y13

SPI1_CS0_B

Y12

SPI1_CS1_B

V13

SPI1_MISO

V12

SPI1_MOSI

BSW-MCP-ED S_FCBGA1170

1 2

RC382 0_0402_5%

SHORT@

1 2

RC38 0_0402_5%

SHORT@

1 2

RC39 0_0402_5%

SHORT@

1 2

RC40 2.49K_0402_ 1%

1 2

RC41 49.9_0402_1 %

Place close to SOC pins

XDP_GPIO_DFX0<16> XDP_GPIO_DFX1<16> XDP_GPIO_DFX2<16> XDP_GPIO_DFX3<16> XDP_GPIO_DFX4<16> XDP_GPIO_DFX5<16> XDP_GPIO_DFX6<16> XDP_GPIO_DFX7<16> XDP_GPIO_DFX8<16>

GPIO_SUS5<12> GPIO_SUS6<16>

1 2

RC42 100_0402_ 1%

GPIO_SUS2 GPIO_SUS3 GPIO_SUS4 GPIO_SUS5 GPIO_SUS6 GPIO_SUS7 SEC_GPIO_SUS8 SEC_GPIO_SUS9 SEC_GPIO_SUS10 SEC_GPIO_SUS11

GP_CAMSB08 GP_CAMSB11

T133@TP

CHV_MCP_EDS

PCIe

SPI

4 OF 13

SOC_KBRST#GP_CAMSB11

SOC_XTAL19_IN_R SOC_XTAL19_OUT _R

ICLKICOMP ICLKRCOMP

XDP_GPIO_DFX0 XDP_GPIO_DFX1 XDP_GPIO_DFX2 XDP_GPIO_DFX3 XDP_GPIO_DFX4 XDP_GPIO_DFX5 XDP_GPIO_DFX6 XDP_GPIO_DFX7 XDP_GPIO_DFX8

DDI0_ENABLE

DDI1_ENABLE GPIO_SUS2 GPIO_SUS3 GPIO_SUS4 GPIO_SUS5 GPIO_SUS6 GPIO_SUS7 SEC_GPIO_SUS9 SEC_GPIO_SUS8 SEC_GPIO_SUS10 SEC_GPIO_SUS11

SOC_COLD_RE SET#

1 2

RC61 10K_0402_5 %@

1 2

RC63 10K_0402_5 %@

1 2

RC65 10K_0402_5 %@

1 2

RC67 4.7K_0402_5 %@

1 2

RC105 4.7K_0402_5 %

1 2

RC75 10K_0402_5 %@

1 2

RC77 10K_0402_5 %@

1 2

RC395 10K_0402_5 %

LPC18@

1 2

RC79 100K_0402_ 5%

1 2

RC83 100K_0402_ 5%@

SATA_TXP0 SATA_TXN0 SATA_RXP0 SATA_RXN0 SATA_TXP1 SATA_TXN1 SATA_RXP1 SATA_RXN1

SATA_LEDN

SATA_GP0

SATA

SATA_GP1 SATA_GP2 SATA_GP3

SATA_OBSP SATA_OBSN

FST_SPI_CLK

FST_SPI_CS0_B FST_SPI_CS1_B FST_SPI_CS2_B

FST_SPI_D0

FAST SPI

FST_SPI_D1 FST_SPI_D2 FST_SPI_D3

MF_HDA_RSTB

MF_HDA_SDI1

MF_HDA_CLK

MF_HDA_SDI0

MF_HDA_SYNC

MF_HDA_SDO

MF_HDA_DOCKENB

MF_HDA_DOCKRSTB

AUDIO

GP_SSP_2_CLK

GP_SSP_2_FS GP_SSP_2_TXD GP_SSP_2_RXD

HDA_BIT_CLK_C HDA_SYNC_C HDA_SDOUT_C HDA_RST#_C

SOC_KBRST# <32>

P24 M22

J26 N26 P20 N20 P26 K26 M26

AH45

A9 C9 B8 B7 B5 B4

AM40 AM41 AM44 AM45 AM47

AK48

AM48

AK41 AK42

AD51 AD52 AH50 AH48 AH51 AH52 AG51 AG53 AF52 AF51 AE51 AC51 AH40

C31

SATA_PTX_DRX_P0_C

B30

SATA_PTX_DRX_N0_ C

N28

SATA_PRX_DTX_P0_C

M28

SATA_PRX_DTX_N0_ C

C29

SATA_PTX_DRX_P1_C

A29

SATA_PTX_DRX_N1_ C

J28

SATA_PRX_DTX_P1_C

K28

SATA_PRX_DTX_N1_ C

AH3

SATA_LED#

AH2 AG3

SOC_TS_INT#

AG1

SATA_DEVSLP

AF3

EMMC_1_RST #

N30

SATA_OBS_P

M30

SATA_OBS_N

SOC_FST_SPI_CLK

SOC_FST_SPI_CS# 0

SOC_TS_EN

SOC_FST_SPI_CS# 2

SOC_FST_SPI_D0

SOC_FST_SPI_D1

SOC_FST_SPI_D2

SOC_FST_SPI_D3

AF13

HDA_RST#_C

AD6

HDA_SDIN1

AD9

HDA_BIT_CLK_C

AD7

HDA_SDIN0

AF12

HDA_SYNC_C

AF14

HDA_SDOUT_C

AB9

HDA_DOCKEN#

AB7

HDA_DOCKRST #

SOC_SPKR

SPKR

AK9 AK10 AK12 AK13

1 2

RA6 75_0402_5 %EMI@

1 2

RA5 75_0402_5 %EMI@

1 2

RA7 75_0402_5 %EMI@

1 2

RA10 75_0402 _5%EMI@

UC1E

OSCIN OSCOUT

RSVD13 RSVD17 ICLKICOMP ICLKRCOMP RSVD18 RSVD14 RSVD16 RSVD1

MF_PLT_CLK0 MF_PLT_CLK1 MF_PLT_CLK2 MF_PLT_CLK3 MF_PLT_CLK4 MF_PLT_CLK5

GPIO_DFX0 GPIO_DFX1 GPIO_DFX2 GPIO_DFX3 GPIO_DFX4 GPIO_DFX5 GPIO_DFX6 GPIO_DFX7 GPIO_DFX8

GPIO_SUS0 GPIO_SUS1 GPIO_SUS2 GPIO_SUS3 GPIO_SUS4 GPIO_SUS5 GPIO_SUS6 GPIO_SUS7 SEC_GPIO_SUS9 SEC_GPIO_SUS8 SEC_GPIO_SUS10 SEC_GPIO_SUS11 GPIO0_RCOMP GPIO_ALERT

BSW-MCP-ED S_FCBGA1170

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

iCLK

PLTFM CLK's

GPIO_DFX

GPIO_SUS

Issued Date

CHV_MCP_EDS

1 2

RC34 402_0402_ 1% RC93 10_0402_5 %EMI@

RC89 33_0402_5 %EMI@

RC97 33_0402_5 %@

RC94 10_0402_5 %EMI@ RC90 10_0402_5 %EMI@ RC91 10_0402_5 %EMI@ RC92 10_0402_5 %EMI@

HDA_BITCLK_AUDIO

RESERVED

SMBUS

5 OF 13

SATA_PTX_DRX_P0_C <27> SATA_PTX_DRX_N0_ C <27> SATA_PRX_DTX_P0_C <27> SATA_PRX_DTX_N0_ C <27> SATA_PTX_DRX_P1_C <27> SATA_PTX_DRX_N1_ C <27> SATA_PRX_DTX_P1_C <27> SATA_PRX_DTX_N1_ C <27>

SOC_TS_INT# <20> SATA_DEVSLP < 27> EMMC_1_RST # <22>

1 2

1 2 1 2 1 2 1 2

T102@TP

HDA_SDIN0 <23>

T132@TP T121@TP

SOC_SPKR <23>

For EMI

CC74 22P_0402_5 0V8J

HDA_BITCLK_AUDIO <23>

HDA_SYNC_AUDIO < 23>

HDA_SDOUT_AUD IO <23>

HDA_RST_AUDIO# <23>

RSVD3 RSVD2 RSVD9 RSVD8

RSVD5 RSVD7 RSVD4 RSVD6

RSVD11 RSVD10 RSVD12 RSVD15

I2C0_SCL I2C0_SDA

I2C1_SCL I2C1_SDA

I2C2_SCL

I2C

I2C2_SDA

I2C3_SCL I2C3_SDA

I2C4_SCL I2C4_SDA

I2C5_SCL I2C5_SDA

I2C6_SCL I2C6_SDA

RSVD21 RSVD22

MF_SMB_CLK

MF_SMB_DATA

MF_SMB_ALERTB

2014/11/10 2015/11/25

SPI_CLK

SPI_CS#0

T104@TP

SPI_CS#2

SPI_MOSI SPI_MISO SPI_WP# SPI_HOLD#

1 2

EMI@

C11 B10 F12 F10

D12 E8 C7 D6

J12 F7 J14 L13

AK6 AH7

AF6 AH6

AF9 AF7

AE4 AD2

AC1 AD3

AB2

I2C_5_SCL

AC3

I2C_5_SDA

AA1 AB3

AA3

I2C_NFC_SCL

I2C_NFC_SDA

AM6

SOC_SMB_CLK

AM7

SOC_SMB_DATA

AM9

SOC_SMB_ALERT #GPIO0_RCOMP

Compal Secret Data

<HDD>

<ODD>

RC158 0_0402_5% RC159 0_0402_5%

Deciphered Date

1 2 1 2

BIOS ROM

+1.8V_SPI

SHORT@ SHORT@

T143@TP T144@TP

SOC_SMB_CLK <16,17> SOC_SMB_DATA <16,17>

+1.8VALW +1.8V_SPI

1 2

RC86 3.3K_0402_5 %

1 2

RC88 3.3K_0402_5 %@

1 2

RC98 20K_0402_5 %@

1 2

RC99 20K_0402_5 %@

1 2

RC100 20K_0402_5 %

1 2

RC101 20K_0402_5 %

SPI_CS#0 SPI_CS#2

SPI_MOSI SPI_MISO SPI_WP# SPI_HOLD#

SPI ROM ( 8MByte/1.8V/Quad-IO )

UC2

SPI_CS#0 SPI_MISO SPI_WP#

I2C_5_SCL_R I2C_5_SDA_R

CS# DO(IO1) WP#(IO2) GND

HOLD#(IO3)

DI(IO0)

VCC

CLK

2 3 4

W25Q64D WSSIG_SO8

SA00006ZV00

Modification @ 2014/07/21

Reserve for EMI(Near SPI ROM)

1 2

SPI_CLK

I2C_5_SCL_R <29> I2C_5_SDA_R <29>

Title

P11-BSW(4/8) PCIE,SATA,I2C,CLK

Size Docu ment Number Rev

Date: Sheet of

R1002

NEMI@

33_0402_5 %

Compal Electronics, Inc.

LA-C571P

1 2

SHORT@

RC87 0_0402_5%

+1.8V_SPI

8 7

SPI_HOLD#

SPI_CLK

SPI_MOSI

C1014

NEMI@

10P_0402_5 0V8J

11 44Tu esday, June 16, 2015

CC76 .1U_0402_1 6V7K

1.0

Main Func = CPU

D D

+1.8VALW

+1.8V_XDP_AB

XDP_H_TCK

C C

B B

XDP_H_TRST #

+1.8VALW

1 2

RC147 2 0K_0402_5%

Pin Name

GPIO_SUS0

GPIO_SUS1

GPIO_SUS2

GPIO_SUS3

GPIO_SUS4

GPIO_SUS5

GPIO_SUS6

GPIO_SUS7

A A

SEC_GPIO_SUS8

SEC_GPIO_SUS9

SEC_GPIO_SUS10

GP_CAMERASB08

GP_CAMERASB09

GP_CAMERASB11

1 2

RC24 10 K_0402_5%

1 2

RC25 10 K_0402_5%

1 2

RC107 5 1_0402_5%XDP@

1 2

RC109 5 1_0402_5%XDP@

1 2

RC110 5 1_0402_5%XDP@

1 2

RC111 5 1_0402_5%XDP@

1 2

RC112 5 1_0402_5%XDP@

1 2

RC108 5 1_0402_5%XDP@

Place close to SOC pins

H_PROCHOT# _R

Purpose

DDI0 Detect

DDI1 Detect

A16 swap overdrive

DSI Display Detect

Boot BIOS Strap BBS

Flash Descriptor Security Override

DFX Boot Halt Strap, VISA Early POSM Debug Enable

DFX Sus Debug Strap

ICLK, USB2, DDI SFR Supply Select

ICLK, USB2, DDI SFR Bypass

POSM Select

ICLK Xtal OSC Bypass

CCU SUS RO Bypass

RTC OSC Bypass

USB_OC0# USB_OC1#

XDP_H_TDI XDP_H_TDO XDP_H_TMS XDP_H_PREQ_BU F#

LPC_CLK_EC<32>

1 2

CC95 .1U _0402_16V7K

ESD@

H_PROCHOT#<32,34> FAN_ALERT#<3 1>

Hardware Strap

PU/PD

XDP_H_TCK

XDP_H_TDO

XDP_H_TRST #

XDP_H_TDI

XDP_H_TMS

LPC_CLK_EC

H_PROCHOT# FAN_ALERT#

Description Default State

1: DDI0 detected 0: DDI0 not detected

1: DDI1 detected 0: DDI1 not detected

1: Normal operation 0: Change Boot Loader address

1: DSI detected 0: DSI not detected

1: Boot from SPI 0: Boot from LPC

1: Security enabled 0: Security disabled

1: Normal operation 0: Halt boot enable

1: Normal operation 0: Sus Debug enabled

1: 1.35V supply 0: 1.25V supply

1: Bypass with 1.05V 0: No bypass

1: PMC 0: Fuse controller

1: Bypass 0: No bypass

PCH_USB3_T X0_P<25> PCH_USB3_T X0_N<25> PCH_USB3_R X0_P<25> PCH_USB3_R X0_N<25>

1 2

RC43 402_0402_ 1%

1 2

CC102 .1U_0402_1 6V7KN ESD@

1 2

C1162 2 2P_0402_50V8JNESD@

1 2

C1163 2 2P_0402_50V8JNESD@

1 2

C1164 2 2P_0402_50V8JNESD@

1 2

C1165 2 2P_0402_50V8JNESD@

XDP_H_TCK<16> XDP_H_TDI<16> XDP_H_TDO<16> XDP_H_TMS<16> XDP_H_TRST #<16>

XDP_H_PRDY#<16> XDP_H_PREQ_BU F#<16>

1 2

RC47 10K_0402_5%@

1 2

RC239 0_0402_5%

1 2

RC240 0_0402_5%@

LPC_CLKRU N#<32 > LPC_FRAME#<32 >

LPC_AD0<32> LPC_AD1<32> LPC_AD2<32> LPC_AD3<32>

1 2

RC48 100_0402_ 1%

LPC_SOC_SER IRQ<17>

1 2

RC236 0_0402_5%

SHORT@

1 2

RC237 0_0402_5%

Don't care, if GPIO_SUS6 is pulled hgh

XDP_H_TCK XDP_H_TDI XDP_H_TDO XDP_H_TMS XDP_H_TRST #

XDP_H_PRDY# XDP_H_PREQ_BU F# EDM_SOC

LPC_CLKOUT 0 LPC_CLKOUT 1 LPC_CLKRU N# LPC_FRAME#

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_HVT_RC OMP LPC_SOC_SER IRQ

H_PROCHOT# _R

High

Low

High

Low

PCH_USB3_T X0_P PCH_USB3_T X0_N PCH_USB3_R X0_P PCH_USB3_R X0_N

USB3_OBS_P USB3_OBS_N

UC1F

B32

USB3_TXP0

C32

USB3_TXN0

F28

USB3_RXP0

D28

USB3_RXN0

A33

USB3_TXP1

C33

USB3_TXN1

F30

USB3_RXP1

D30

USB3_RXN1

C34

USB3_TXP2

B34

USB3_TXN2

G32

USB3_RXP2

J32

USB3_RXN2

C35

USB3_TXP3

A35

USB3_TXN3

G34

USB3_RXP3

J34

USB3_RXN3

D34

USB3_OBSP

F34

USB3_OBSN

C37

RSVD4

A37

RSVD1

F36

RSVD7

D36

RSVD6

M34

RSVD11

M32

RSVD10

C38

RSVD5

B38

RSVD2

G36

RSVD8

J36

RSVD9

N34

RSVD12

P34

RSVD13

BSW-MCP-ED S_FCBGA1170

UC1G

AF42

TCK

AD47

TDI

AF40

TDO

AD48

TMS

AB48

TRST_B

AD45

CX_PRDY_B

AF41

CX_PREQ_B

M13

RSVD5

MF_LPC_CLKOUT0

MF_LPC_CLKOUT1

LPC_CLKRUNB

LPC_FRAMEB

MF_LPC_AD0

MF_LPC_AD1

MF_LPC_AD2

MF_LPC_AD3

LPC_HVT_RCOMP

ILB_SERIRQ

RSVD23

RSVD24

P28

RSVD6

P30

RSVD7

AF50

RSVD4

AF48

RSVD3

AF44

RSVD1

AF45

RSVD2

AD50

PROCHOT_B

BSW-MCP-ED S_FCBGA1170

CHV_MCP_EDS

USB3.0

USB_HSIC_0_STROBE

USB_HSIC_1_STROBE

RESERVED

6 OF 13

CHV_MCP_EDS

PMU_RESETBUTTON_B

LPC JTAG/ITP

PWM

Reserved

7 OF 13

USB_OTG_ID

USB_DP0 USB_DN0

USB_DP1 USB_DN1

USB_DP2 USB_DN2

USB_DP3 USB_DN3

USB_DP4 USB_DN4

USB2.0

USB_OC1_B USB_OC0_B

RSVD3

USB_VBUSSNS

USB_RCOMP

USB_HSIC_0_DATA

HSICUART

USB_HSIC_1_DATA USB_HSIC_RCOMP

UART1_TXD

UART1_RXD UART1_CTS_B UART1_RTS_B

UART2_TXD

UART2_RXD UART2_CTS_B UART2_RTS_B

BRTCX1_PAD BRTCX2_PAD

BVCCRTC_EXTPAD

SRTCRST_B

RTC

COREPWROK

RSMRST_B

RTEST_B

RSVD_VSS

SUSPWRDNACK

SUS_STAT_B

PMU_SUSCLK PMU_SLP_S4_B PMU_SLP_S3_B

PMU_PLTRST_B

PMU

PMU_BATLOW_B

PMU_AC_PRESENT

PMU_SLP_S0IX_B

PMU_SLP_LAN_B

PMU_WAKE_B

PMU_PWRBTN_B

PMU_WAKE_LAN_B

SVID0_CLK

SVID0_DATA

SVID

SVID0_ALERT_B

CORE_VCC0_SENSE CORE_VSS0_SENSE CORE_VCC1_SENSE CORE_VSS1_SENSE

Voltage sense

DDI_VGG_SENSE UNCORE_VSS_SENSE2 UNCORE_VSS_SENSE1

PCH_PWR OK

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B48

USB_OTG_ID

C42

USB20_P0

B42

USB20_N0

C43

USB20_P1

B44

USB20_N1

C41

USB20_P2

A41

USB20_N2

C45

USB20_CPU_ P3

A45

USB20_CPU_ N3

B40

USB20_SOC_P 3

C40

USB20_SOC_N 3

P16

USB_OC1#

P14

USB_OC0#

B46 B47

USB_VBUSSNS

A48

USB20_RCOMP

M36 N36

K38 M38 N38

HSIC_RCOMP

AD10

UART_1_CT XD_DRXD

AD12

UART_1_CRXD_ DTXD

AD13 AD14

Y6 Y7 V9 V10

M18

BRTCX1

K18

BRTCX2

F16

BVCCRTC_EXTPAD

D18

SRTCRST#

G16

PCH_PWR OK

F18

SOC_RSMRST #

J16

RTEST#

G18

RC393 10K_0402_5%

AE3

PMU_SUSPW RDNACK

D14

PMU_SUS_ST AT#

C15

PMU_SUSCLK0

C12

PMU_SLP_S4#

B14

PMU_SLP_S3#

AF2

PMU_RSTBT N#

F14

PMU_PLTRST #

C14

PMU_BATLOW #

C13

PMU_AC_PRESEN T

A13

PMU_SLP_S0IX#

B12 N16

PMU_WAKE#

M16

PMU_PWR BTN#

P18

PMU_WAKE_L AN#

AD42

VR_SVID_CLK

AD41

SVID_DATA

AD40

VR_SVID_ALRT#

AG32

VCC_SENSEP_R

AJ32

VCC_SENSEN_R

AD29

VCC1_SENSEP

AF27

VCC1_SENSEN

AD24 AD22 AC27

UC7

NL17SZ07DFT 2G_SC70-5

SA00004BV00

Issued Date

1 2

RC362 0_0402_5%@

USB20_P0 <2 5> USB20_N0 <25>

USB20_P1 <2 5> USB20_N1 <25>

USB20_P2 <2 0> USB20_N2 <20>

USB20_CPU_ P3 <26> USB20_CPU_ N3 < 26>

USB20_SOC_P 3 <25> USB20_SOC_N 3 <25>

USB_OC1# <25> USB_OC0# <25>

1 2

RC381 49.9_0402_1 %@

1 2

RC378 0_0402_5%@

1 2

RC44 113_0402_ 1%

1 2

RC45 45.3_0402_1 %

T106@TP T105@TP

1 2

CC9 .1U_0402_16V7K

1 2

RC234 0 _0402_5%

1 2

VGG_SENSEP VGG_SENSEN VNN_SENSEP

+1.35V+3VALW

RC30 10K_0402_5 %

SHORT@

PMU_SUSPW RDNACK

T107@TP

PMU_SUSCLK0 <18> PMU_SLP_S4# <17> PMU_SLP_S3# <17> PMU_RSTBT N# <16> PMU_PLTRST # <16,17,22> PMU_BATLOW # <17> PMU_AC_PRESEN T <17 > PMU_SLP_S0IX# < 17>

PMU_PWR BTN# <16,18>

T108@TP

1 2

RC49 2.2 +-1% 0402

1 2

RC50 2.2 +-1% 0402

1 2

RC51 2.2 +-1% 0402

1 2

RC52 2.2 +-1% 0402

1.35V3.3V

SOC_VCCA_PWR OK

2014/11/10 2015/11/25

<USB3.0>

<USB2.0 / IO>

To USB Conn

V0.2 change

2014/10/30 : Intel suggest reserve RC381,RC378

Should be 112.5_0402_1%

EC_RSMRST#

VCCSENSE VSSSENSE

SOC_VCCA_PWR OK <9>

Compal Secret Data

Deciphered Date

RTC CKT

+RTCVCC

+RTCBATT

JRTC

CONN@

LOTES_AAA-BAT-054-K01

SP07000H70 0

+CHGRTC

W=20mils

+RTCVCC

0718: change to the other part to SC600001Q00

PCH_PWR OK <16,32 > EC_RSMRST# <16,32>

Route as Differential Lines

VCCSENSE <41> VSSSENSE <4 1>

VGG_SENSEP <42> VGG_SENSEN <42> VNN_SENSEP <39>

Security Flash Descriptor

GPIO_SUS5 0: Override 1: Normal Operation (internal PU)

SVID

+1.05VALW

Follow PWR Net Name --> Change to VR_SVID_CLK

Note: VR_SVID_CLK Rs & Rpu @ power side

VR_SVID_CLK

Note: SVID_ALERT# Rs @ power side

1 2

RC366 200_0402_ 1%

VR_SVID_ALRT#

Route SVID_ALERT# between SVID_CLK & SVID_DATA

Note: SVID_DATA Rpu & Rss @ power side

SVID_DATA VCC_SVID_DAT

BRTCX1

BRTCX2

ESR < 50K Ohm

1 2

RC144 20K_0402_5 %

1 2

RC145 20K_0402_5 %

CLRP1

Clear CMOS RTC Well Reset

JP12

JUMP_43X39

+CHGRTC

CC75 .1U_0402_1 6V7K

+1.8VALW

SOC_RSMRST # PCH_PWR OK

GPIO_SUS5

1 2

RC364 0_0402_5%

1 2

RC365 0_0402_5%

Size Docu ment Number Rev

Date: Sheet of

20mil

+RTCVCC

RC274 10K_0402_5% RC113 1K_0402_5% RC114 1K_0402_5%@ RC241 10K_0402_5% RC275 2.2K_0402_5% RC276 10K_0402_5%@ RC277 10K_0402_5% RC229 10K_0402_5%

CC98 .1U_0402_16V7K

RC115 100K_0402_5 % RC95 100K_0402_5 % CC96 .1U_0402_16V7K

GPIO_SUS5 <11>

TXE_DBG<32>

Note: EC programing TXE_DBG "H" for Flash BIOS

SHORT@ SHORT@

Title

P12-BSW(5/8) USB,UART,RTC,PWM

LA-C571P

RC46 10M_0402_5%

1 2

YC2

1 2

32.768KHZ_12 .5PF_9H03200042

CC10 18P_0402_5 0V8J

SRTCRST# RTEST#

JP@

112

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

ESD@

1 2 1 2

1 2

ESD@

PMU_PLTRST #

PMU_RSTBT N#

TXE_DBG

VGG_SVID_DAT

Compal Electronics, Inc.

1 2

CC83 1U _0402_6.3V6K

1 2

CC84 1U _0402_6.3V6K

SRTCRST#RTEST#

CLRP2

+3VLP

RC84 1K_0402_5%

1 2

+RTCBATT_ R

20mil

P12P2

LBAV70WT1G_ SC70-3

DC3

1 2

CC97 .1U_0402_1 6V7KE SD@

1 2

C1161 2 2P_0402_50V8JESD@

0_0402_5%

1 2

RC394

PMU_SUSPW RDNACK PMU_RSTBT N# PMU_PLTRST # PMU_BATLOW # PMU_AC_PRESEN T PMU_SLP_S0IX# PMU_PWR BTN# PMU_WAKE#

VR_SVID_CLK <41,42 >

VR_SVID_ALRT# <41,42 >

VCC_SVID_DAT <41 > VGG_SVID_DAT <42>

TXC SJ10000LV00

CC11 15P_0402_5 0V8J

V0.2 change

<USB3.0_1>

+RTCBATT

GPIO_SUS5

QC30 MESS138W -G_SOT323-3

12 44Tu esday, June 16, 2015

1.0

Main Func = CPU

+VCC_CORE

+VGG_CORE

+1.15VALW

6400mA

11A

700mA

D D

1 2

C C

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Edge

CC21 1U_0402_6.3V6K

1 2

CC23 1U_0402_6.3V6K

1 2

CC24 1U_0402_6.3V6K

1 2

CC26 1U_0402_6.3V6K

1 2

CC28 1U_0402_6.3V6K

1 2

CC29 1U_0402_6.3V6K

1 2

CC32 1U_0402_6.3V6K

1 2

CC34 1U_0402_6.3V6K

1 2

CC35 1U_0402_6.3V6K

UC1H

AF36

CORE_VCC1_S0IX3

AG33

CORE_VCC1_S0IX7

AG35

CORE_VCC1_S0IX8

AG36

CORE_VCC1_S0IX9

AG38

CORE_VCC1_S0IX10

AJ33

CORE_VCC1_S0IX14

AJ36

CORE_VCC1_S0IX15

AJ38

CORE_VCC1_S0IX16

AF30

CORE_VCC1_S0IX2

AG27

CORE_VCC1_S0IX4

AG29

CORE_VCC1_S0IX5

AG30

CORE_VCC1_S0IX6

AJ27

CORE_VCC1_S0IX11

AJ29

CORE_VCC1_S0IX12

AJ30

CORE_VCC1_S0IX13

AF29

CORE_VCC1_S0IX1

AD16

DDI_VGG_S0IX1

AD18

DDI_VGG_S0IX2

AD19

DDI_VGG_S0IX3

AF16

DDI_VGG_S0IX4

AF18

DDI_VGG_S0IX5

AF19

DDI_VGG_S0IX6

AF21

DDI_VGG_S0IX7

AF22

DDI_VGG_S0IX8

AJ19

DDI_VGG_S0IX15

AG16

DDI_VGG_S0IX9

AG18

DDI_VGG_S0IX10

AG19

DDI_VGG_S0IX11

AG21

DDI_VGG_S0IX12

AG22

DDI_VGG_S0IX13

AG24

DDI_VGG_S0IX14

AJ21

DDI_VGG_S0IX16

AJ22

DDI_VGG_S0IX17

AJ24

DDI_VGG_S0IX18

AK24

DDI_VGG_S0IX19

AK30

CORE_V1P15_S0IX1

AK35

CORE_V1P15_S0IX2

AK36

CORE_V1P15_S0IX3

AM29

CORE_V1P15_S0IX4

AK33

FUSE_V1P15_S0IX2

AJ35

FUSE_V1P15_S0IX1

AM19

DDI_V1P15_S0IX2

AK21

DDI_V1P15_S0IX1

BSW-MCP-ED S_FCBGA1170

CHV_MCP_EDS

UNCORE_V1P15_S0IX6 UNCORE_V1P15_S0IX1 UNCORE_V1P15_S0IX2 UNCORE_V1P15_S0IX3 UNCORE_V1P15_S0IX4 UNCORE_V1P15_S0IX5 UNCORE_V1P15_S0IX7 UNCORE_V1P15_S0IX8 UNCORE_V1P15_S0IX9

UNCORE_V1P15_S0IX10

8 OF 13

UNCORE_VNN_S41 UNCORE_VNN_S42 UNCORE_VNN_S43 UNCORE_VNN_S44 UNCORE_VNN_S45 UNCORE_VNN_S46 UNCORE_VNN_S47 UNCORE_VNN_S48

UNCORE_VNN_S49 UNCORE_VNN_S410 UNCORE_VNN_S411 UNCORE_VNN_S412 UNCORE_VNN_S413 UNCORE_VNN_S414

RSVD1

ICLK_GND_OFF2

iCLKDDRPCIeSATAUSB

ICLK_GND_OFF1

DDR_V1P05A_G31 DDR_V1P05A_G34 DDR_V1P05A_G32 DDR_V1P05A_G35 DDR_V1P05A_G36 DDR_V1P05A_G33

PCIE_V1P05A_G31 PCIE_V1P05A_G32

SATA_V1P05A_G32

SATA_V1P05A_G31

USB3_V1P05A_G32

USB3_V1P05A_G31

USBSSIC_V1P05A_G3

FUSE3_V1P05A_G5

FUSE_V1P05A_G3

FUSE

AA18 AA19 AA21 AA22 AA24 AA25 AC18 AC19 AC21 AC22 AC24 AC25 AD25 AD27

AA30 V33 AA32 AA33 AA35 AA36 AC32 Y30 Y32 Y33 Y35

V19 V18

AM21 AM33 AM22 AN22 AN32 AM32

V22 V24

U24 U22

V27 U27 V29

N18 U19

3500mA

4000mA

+1.05V_VNN

+1.05VALW

1 2

CC12 1U_0402_6.3V6K

1 2

CC13 1U_0402_6.3V6K

1 2

CC14 1U_0402_6.3V6K

1 2

CC15 1U_0402_6.3V6K

1 2

CC16 1U_0402_6.3V6K

1 2

CC17 1U_0402_6.3V6K

1 2

CC18 1U_0402_6.3V6K

1 2

CC19 22U_0603_6.3V6M

1 2

CC20 22U_0603_6.3V6M

1 2

CC22 1U_0402_6.3V6K

1 2

CC25 1U_0402_6.3V6K

1 2

CC27 1U_0402_6.3V6K

1 2

CC30 1U_0402_6.3V6K

1 2

CC31 1U_0402_6.3V6K

1 2

CC33 1U_0402_6.3V6K

1 2

CC36 1U_0402_6.3V6K

1 2

CC37 1U_0402_6.3V6K

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Edge

Place @ Back Side

JPC4

1 2

JUMP_43X79

B B

+1.05V_VNN+1.05VALW

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

P13-BSW(6/8) PWR1

LA-C571P

1.0

13 44Tu esday, June 16, 2015

1.0

Main Func = CPU

Place @ Back Side

Place @ Edge

D D

+1.35V_DDR_VDD Q+1.35V

JPC6

112

JUMP_43X118

JPC3

112

JUMP_43X118

C C

1 2

+1.8VALW

+3VALW

+1.8VS

+1.5VS

Need to change to 0603 package 11/16

B B

RC265, RC268, RC270, RC255

SHORT@

RC190 0_0603_ 5%

1 2

RC265 0 _0402_1%

LPC18@

1 2

RC268 0 _0402_5%

LPC33@

SHORT@

1 2

RC270 0 _0402_1%

1 2

RC255 0 _0402_1%@

+3V_+1.8V_SDIO

+3V_+1.8V_LPC

+1.8V_AUDIO

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Edge

AH4,AF4:Audio IO Supply (1.8V or 1.5V)

CC61 1U_0402_6.3V6K

CC64 1U_0402_6.3V6K

CC65 1U_0402_6.3V6K CC66 1U_0402_6.3V6K

1 2

CC38 1U_0402_6.3V6K

1 2

CC39 22U_0603_6.3V6M

1 2

CC40 1U_0402_6.3V6K

1 2

CC41 22U_0603_6.3V6M

1 2

CC47 22U_0603_6.3V6M

1 2

CC49 22U_0603_6.3V6M

1 2

CC50 22U_0603_6.3V6M

1 2

CC51 22U_0603_6.3V6M

E1,E2:SDIO Supply (1.8V or 3.3V)

1 2

CC54 1U_0402_6.3V6K

1 2

CC55 1U_0402_6.3V6K

G1:LPC IO Supply (1.8V or 3.3V)

1 2

CC58 1U_0402_6.3V6K

+1.8V_AUDIO

1 2

1 2 1 2

1 2

CC68 1U_0402_6.3V6K

1 2

CC69 1U_0402_6.3V6K

+1.35V_DDR_VDD Q

+3V_+1.8V_SDIO

+3V_+1.8V_LPC

+1.8VALW

+1.35V_DDR_VDD Q

UC1I

AN27

DDRSFR_VDDQ_G_S4

AM25

DDR_VDDQ_G_S42

BE1

DDR_VDDQ_G_S416

BE53

DDR_VDDQ_G_S419

BJ2

DDR_VDDQ_G_S426

BJ3

DDR_VDDQ_G_S427

BJ49

DDR_VDDQ_G_S428

BJ5

DDR_VDDQ_G_S429

BH50

DDR_VDDQ_G_S425

BH5

DDR_VDDQ_G_S424

BH49

DDR_VDDQ_G_S423

BH4

DDR_VDDQ_G_S422

BE3

DDR_VDDQ_G_S417

BG51

DDR_VDDQ_G_S421

BG3

DDR_VDDQ_G_S420

BJ51

DDR_VDDQ_G_S430

BJ52

DDR_VDDQ_G_S431

AY10

DDR_VDDQ_G_S414

AY44

DDR_VDDQ_G_S415

AV44

DDR_VDDQ_G_S413

AV10

DDR_VDDQ_G_S410

BE51

DDR_VDDQ_G_S418

AV38

DDR_VDDQ_G_S412

AV16

DDR_VDDQ_G_S411

AU36

DDR_VDDQ_G_S49

AU18

DDR_VDDQ_G_S48

AN36

DDR_VDDQ_G_S47

AN35

DDR_VDDQ_G_S46

AN19

DDR_VDDQ_G_S45

AN18

DDR_VDDQ_G_S44

AM36

DDR_VDDQ_G_S43

AM18

DDR_VDDQ_G_S41

SDIO_V3P3A_V1P8A_G31

SDIO_V3P3A_V1P8A_G32

SDIO_V3P3A_V1P8A_G33

AH4

UNCORE_V1P8A_G32

AF4

UNCORE_V1P8A_G31

Y18

GPIO_V1P8A_G35

AD33

GPIO_V1P8A_G31

AK18

GPIO_V1P8A_G33

AF33

GPIO_V1P8A_G32

AK19

GPIO_V1P8A_G34

BSW-MCP-ED S_FCBGA1170

+1.24VALW

CHV_MCP_EDS

DDI_VDDQ_G31 DDI_VDDQ_G32

MIPI_V1P2A_G32 MIPI_V1P2A_G31

ICLK_VSFR_G32 ICLK_VSFR_G31

CORE_VSFR_G35

9 OF 13

CORE_VSFR_G36

PCIE_V1P05A_G31

CORE_VSFR_G34 CORE_VSFR_G32 CORE_VSFR_G33 CORE_VSFR_G31

USBHSIC_V1P2A_G3

USB_VDDQ_G32 USB_VDDQ_G33

USBRTCFUSE

USB_VDDQ_G31

USBSSIC_V1P2A_G3

USB_V1P8A_G3

USB_V3P3A_G32 USB_V3P3A_G31

RTC_V3P3RTC_G52 RTC_V3P3RTC_G51

RTC_V3P3A_G51 RTC_V3P3A_G52

FUSE_V1P8A_G3

FUSE1_V1P05A_G4 FUSE0_V1P05A_G3

DDR

SHORT@

1 2

RC258 0 _0805_5%

SHORT@

1 2

RC269 0_ 0805_5%

+1.24VALW

V36 Y36

T40 P40

Y27 Y25

P38 V30 AC30

AF35 AD35 AD38 AC36

+1.24V_SOC

M41 U35 V35 H44 P41

AA29

C23 B22

C5 B6 D4 E3

U16

H10 G10 A3

RSVD_VSS

K20

RSVD1

M20

RSVD2

+1.24V_ICLK_VSFR

+1.24V_USB_VDDQ_2

1 2

CC42 1U_0402_6.3V6K

+1.24V_SOC

+1.24V_ICLK_VSFR

+1.24VALW

1 2

CC43 1U_0402_6.3V6K

1 2

CC44 1U_0402_6.3V6K

1 2

CC45 1U_0402_6.3V6K

1 2

CC46 1U_0402_6.3V6K

1 2

CC48 1U_0402_6.3V6K

1 2

CC52 1U_0402_6.3V6K

+1.24V_USB_VDDQ_2

+3V_SOC

+RTCVCC

+1.8VALW

+1.05VALW

+1.24VALW

+1.24V_USB_VDDQ _2

+RTCVCC

1 2

CC59 1U_0402_6.3V6K

+3V_SOC

1 2

CC62 1U_0402_6.3V6K

1 2

CC63 1U_0402_6.3V6K

1 2

CC67 1U_0402_6.3V6K

1 2

CC70 1U_0402_6.3V6K

1 2

CC71 1U_0402_6.3V6K

1 2

CC72 1U_0402_6.3V6K

1 2

CC73 1U_0402_6.3V6K

+1.24V_SOC

1 2

CC60 1U_0402_6.3V6K

+1.8VALW

CC53 1U_0402_6.3V6K

CC56 1U_0402_6.3V6K

CC57 1U_0402_6.3V6K

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Back SidePlace @ Edge

1 2

Place @ Edge

Place @ Back Side

Place @ Edge

Place @ Back Side

Place @ Edge

V0.2 change

+1.24V_SOC

Place @ Back Side

+1.24VALW

+1.24V_SOC

SHORT@

Place @ Edge

1 2

RC397 0_0603_5%

RC398 0_0603_5%

NOTE: +1.24V_MIPI, +1.24V_USBHSIC, +1.24V_USBSSIC are +1.24V Only. [PDG Rev0p92 P.55] When SSIC, HSIC & CSI interface is not used, the following pins can be connected to ground: CSI (T40, P40), USB HSIC (M41), USB SSIC (P41).

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2014/11/10 2015/11/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Date: Sheet of

Compal Electronics, Inc.

P14-BSW(7/8) PWR2

LA-C571P

1.0

14 44Tu esday, June 16, 2015

1.0

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Dell lnspiron 15 5552 boardview

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