Dell LATITUD E3301 Schematics

5

D D

4

3

2

1

WASP 13 CS

C C

Whiskey Lake-U

2019-01

REV : A00

B B

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

A A

DY : None Installed

T

tle

Title

Title

UMA: UMA only installed
OPS: DIS only installed

5

4

3

i

ov

ov

ov

C

C

W

W

W

C

A

A

A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

Date: Sheet

Date: Sheet

Date: Sheet

2

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

er Page

er Page

er Page

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

1 1

1 1

1 1

0

0

0

0

0

0

A

A

o

o

o

f

f

f

1

A

06

06

06

5

WWW.AliSaler.Com

4

3

2

1

WASP 13" CPU 15W + GPU 18W Block Diagram

Project code :
N5 -> 4PD0GW010001

M(GDDR5) *2

RA

V

2GB

D D

C C

DDR5

G

WWAN BD

eSIM

IO expander

IT8010FN

B B

I2C

A A

NGFF WWAN

WWAN/LTE

2nd storage

Thermal

NUVOTON
NCT7718W

KBC

MICROCHIP

EC

M

Fan Control

PWM

FAN

5

GPU

NVIDIA
N17S-G2 18W

HDMI 1.4
CONN.

13.3"
(FHD)

M.2 SSD

NGFF
WLAN

(CNVi)

2

4

65

Redriver

PI3EQX12902AZLEX

Redriver

PI3EQX12902AZLEX

PCIe x 1

PCIe x 1

SMBus

26 68

1418

Int.

26

KB

Flash ROM

26

16MB
Quad Read

TPM

NPCT750JAB

PCIE x 4

7

6-8081-82

DDI1

5

7

eDP

5

5

SATA/PCIEx4

6

3

PCIe x 1

USB2.0

6

1

CNVi

USB2.0

eSPI debug port

eSPI BUS

I2C

ouc

h PAD

T

Image sensor

SPI

25

91

4

L

ANE 5~8

LANE 10

L

ANE 10

LANE 9

PCIe x 1

PCIe x 1

6

5

nt

el CPU

I

Whiskey Lake-U

15W

WHL PCH-LP

10 USB 2.0/1.1 ports

U

SB 3.0 ports

6

igh

Definition Audio

H

3 SATA ports

PC

IE ports

6
LPC I/F

CPI

5.0

A

Channel A

Channel B

DP 1.2

USB3.1 Gen1

USB2.0

LANE 4

LPDDR3
Memory Down

SS MUX

TI
TUSB546A

I2C

TPS65982DD

1

2,13

DP1.2/USB 3.1 Gen1

7

1

USB 2.0

CC1 & CC2

CardReader

SDIO

USB2.0

I2C

Reserve path

LANE 5

I2C

SD 3.0

Realtak
RTS5100

Finger Print

e fall

re

F
Gsensor

ST
LNG2DMTR

D-MIC

3

3

92

7

0

5

5

HDA

HDA

L

L

ANE 1

ANE 6

USB2.0

USB2.0

3

CODEC

Realtek
ALC3204

USB 3.1 Gen1
Re-driver

PS8719

Camera
(HD)

5

5

2

2

7

MIC_IN/GND

HP_R/L

USB3.1 Gen1USB3.1 Gen1

<

<

<

re Design>

re Design>

re Design>

Co

Co

Co

T

le

Title

Title

it

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

Date: Sheet

V5 -> 4PD0GX010001
L -> 4PD0H6010001
PCB P/N : 18769-1
Revision: A00

USB3.1 Gen1

TypeC

Port1

7372

MicroSD Card Slot

3

3

2CH SPEAKER
(2CH 2W/4ohm)

IOBD

ni

versal Jack

U

USB3.1 Gen1
Port2

is

is

is

tron Corporation

tron Corporation

tron Corporation

W

W

W

2

2

2

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

1F

1F

1F

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

loc

loc

loc

k Diagram

k Diagram

k Diagram

B

B

B

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

AS

AS

AS

W

W

W

1

2

6Thursday, March 07, 2019

6Thursday, March 07, 2019

6Thursday, March 07, 2019

f

10

f

10

f

10

00

00

00

A

A

A

o

2

o

2

o

5

4

3

2

1

Main Func = CPU

P

E

CI_CPU24

P

OCHOT#_CPU24,44,46

R

D D

T

O

UCH_PANEL_INTR#55

T

_WAKE_KBC#24,65

P

T

UCH_PANEL_PD#55

O

H

CPUPWRGD17

_

3

D

3V_S5_PCH

T

_WAKE_KBC#

1 2

R

03 100KR2J-1-GP

3

DY

1

_VCCST_CPU

V

C C

1 2

R

08 1KR2J-1-GP

3

1

V

_VCCSTG

P

T

H

ERMTRIP#_CPU

1V_VCCSTG = 1.05V

X

P_TDO_CPU

1 2

R

3

10 51R2J-2-GP

1 2

R

17 51R2J-2-GP

3

D

X

D

P_TCLK

P

OCHOT#_CPU

R

1

_VCCSTG

V

Rb

1V_VCCSTG = 1.05V

12

R

01

3

1KR2J-1-GP

Ra

1 2

R

3

02 499R2F-2-GP

1 2

R

3

04 49D9R2F-GP

1 2

R

05 49D9R2F-GP

3

1

DY

[PECI] and [PROCHOT#]
Impedance control: 50 ohm

P

E

CI_CPU

P

OCHOT#_CPU_R

R

T

H

ERMTRIP#_CPU

B

M_N0

P

T

P

T

P

T

P

T

P

T

1

307

1

308

1

302

1

303

1

304

P

T

H

ERMTRIP#_CPU

H

CPUPWRGD

_

2

E

301

D

AZ5125-02S-R7G-GP

B

P

M_N1

B

P

M_CPU_N2

B

P

M_CPU_N3

G

P

P_E3/CPU_GP0

T

O

UCH_PANEL_INTR#

T

P

_WAKE_KBC#

T

UCH_PANEL_PD#

O

C

U_POPIRCOMP

P

P

H_POPIRCOMP

C

75.05125.07D

3

C

P

AA4

A

C

AR1

E

P

Y4

R

P

BJ1

H

T

U1

P

B

U2

P

B

U3

P

B

U4

P

B

CE9

P

G

CN3

P

G

CB34

P

G

CC35

P

G

BP27

R

P

BW25

C

P

WHISKEY-LAKE-GP

ZZ.00CPU.271

U1D

TERR#
CI
OCHOT#
RMTRIP#

M#0
M#1
M#2
M#3

P_E3/CPU_GP0
P_E7/CPU_GP1
P_B3/CPU_GP2
P_B4/CPU_GP3

OC_POPIRCOMP
H_OPIRCOMP

4

R

P

R

P

R

P

R

P

R

OC_TRST#

P

P

P
P
P

H_TRST#

C

P

C

H_JTAGX

P

R

OC_PREQ#

P

OC_PRDY#

R

P

OF 20

OC_TCK

OC_TDI
OC_TDO
OC_TMS

H_TCK

C

C

H_TDI

H_TDO

C

H_TMS

C

T6
U6
Y5
T5
AB6

W6
U5
W5
P5
Y6
P6

W2
W1

X

D

X

D

P_PREQ#
P_PRDY#

X

P_TCLK

D

X

D

P_TDI

X

P_TDO_CPU

D

X

D

P_TMS

X

D

P_TRST#

P

C

H_TCK

1

T

309

P

1

T

310

P

1

T

P

313

1

T

314

P

1

T

P

1

1

T

305

P

1

T

P

306

316

T

P

317

B B

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

P

P

P

U (THML/JTAG)

U (THML/JTAG)

U (THML/JTAG)

C

C

C

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

o

o

o

f

f

3 1

3 1

3 1

f

1

A

A

A

0

0

0

0

0

0

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

5

WWW.AliSaler.Com

Main Func = CPU

DP to HDMI1.4

H

I_DDI_TX_N057

DM

H

I_DDI_TX_P057

DM

H

I_DDI_TX_N157

DM

H

I_DDI_TX_P157

D D

DM

H

M

I_DDI_TX_N257

D

H

DM

I_DDI_TX_P257

H

M

I_DDI_TX_N357

D

H

I_DDI_TX_P357

DM

H

I_HPD_CPU57

DM

C

PU

_DP1_CTRL_CLK57

C

_DP1_CTRL_DATA57

PU

DP for Type-C Mux

D

_DDI_TX_N071

P2

D

P2

_DDI_TX_P071

D

P2

_DDI_TX_N171

D

_DDI_TX_P171

P2

D

_DDI_TX_N271

C C

P2

D

P2

_DDI_TX_P271

D

P2

_DDI_TX_N371

D

P2

_DDI_TX_P371

D

P2

_AUX_CPU_P71

D

P2

_AUX_CPU_N71

3

V_S0

D3

2

0180904 Stuff

R
10KR2J-L-GP

R
100KR2J-1-GP

4

1 2

40

2

R

01

N4

1
2 3

SRN2K2J-1-GP

R

N4

03

1
2 3

SRN2K2J-1-GP

1 2

40

3

4

4

S

IO

_EXT_SMI#

C

PU

_DP1_CTRL_DATA

C

_DP1_CTRL_CLK

PU

C

PU

_DP2_CTRL_DATA

C

PU

_DP2_CTRL_CLK

D

_HPD_CPU_R

P1

3

DP to HDMI

H
H
H
H
H
H
H
H

D
D
D
D
D
D
D
D

DM

I_DDI_TX_N0
I_DDI_TX_P0

DM
DM

I_DDI_TX_N1

DM

I_DDI_TX_P1

DM

I_DDI_TX_N2
I_DDI_TX_P2

DM
DM

I_DDI_TX_N3

DM

I_DDI_TX_P3

P2

_DDI_TX_N0
_DDI_TX_P0

P2
P2

_DDI_TX_N1

P2

_DDI_TX_P1
_DDI_TX_N2

P2
P2

_DDI_TX_P2

P2

_DDI_TX_N3

P2

_DDI_TX_P3

AL5
AL6
AJ5
AJ6

AF6
AF5
AE5
AE6

AC4
AC3
AC1
AC2

AE4
AE3
AE1
AE2

DP for Type-C Mux

1

VCCIO

V_

2

E
E

D

D

D

D

D

D

D

DP

E

E
DP

E

1

O

DP

_TXN0

E

DP

_TXP0

E

_TXN1

DP

E

_TXP1

DP

E

_TXN2

DP

E

DP

_TXP2

E

_TXN3

DP

E

_TXP3

DP

E

_AUX_N

DP

_AUX_P

DP

P_UTILS

IS

DI

1_AUX_N
1_AUX_P

DI

2_AUX_N

DI

2_AUX_P

DI

DI

3_AUX_N

DI

3_AUX_P

_BKLTEN

_VDDEN

DP

_BKLTCTL

F 20

C

1A

PU

DI

1_TXN0

D

DI

1_TXP0

D

1_TXN1

DI

D

1_TXP1

DI

D

1_TXN2

DI

D

DI

1_TXP2

D

1_TXN3

DI

D

1_TXP3

DI

D

DI

2_TXN0

D

2_TXP0

DI

D

2_TXN1

DI

D

DI

2_TXP1

D

2_TXN2

DI

D

2_TXP2

DI

D

DI

2_TXN3

D

2_TXP3

DI

D

PP

_E13/DDPB_HPD0/DISP_MISC0

G

PP

_E14/DDPC_HPD1/DISP_MISC1

G

_E15/DPPD_HPD2/DISP_MISC2

PP

G

PP

_E16/DPPE_HPD3/DISP_MISC3

G

PP

_E17/EDP_HPD/DISP_MISC4

G

AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1

AH4
AH3

AM7

AC7
AC6
AD4
AD3
AG7
AG6

CN6
CM6
CP7
CP6
CM7

CK11
CG11
CH11

1

e

DP

_TX_CPU_N0

e

_TX_CPU_P0

DP

e

DP

_TX_CPU_N1

e

DP

_TX_CPU_P1

e

_AUX_CPU_N

DP

e

DP

_AUX_CPU_P

D

_AUX_CPU_N

P2

D

P2

_AUX_CPU_P

H

DM

I_HPD_CPU

D

_HPD_CPU_R

P1

S

_EXT_SMI#

IO

e

_HPD_CPU

DP

L

KLT_EN

_B

E

_VDD_EN

DP

L

_B

KLT_CTRL

eDP

e

_TX_CPU_N055

DP

e

_TX_CPU_P055

DP

e

_TX_CPU_N155

DP

e

_TX_CPU_P155

DP

e

_AUX_CPU_N55

DP

e

DP

_AUX_CPU_P55

e

DP

B B

_HPD_CPU55

D

P1

_HPD_CPU71,72

L

KLT_EN24

_B

L

KLT_CTRL55

_B

E

DP

_VDD_EN55

G

PP

_H17_STRAP15

G

_THM_DIS#24

C6

3

D3

V_S5_PCH

R

05

N4

1
2 3

SRN10KJ-5-GP

S

A 0816

4

C
PU

_DP_HPD_P

Q

40

1

N

ote:ZZ.27002.F7C01

1

2

3 4

2N7002KDW-1-G P

6

5

D

D

75.27002.F7C

R

40

1

24D9R2F-L-GP

_HPD_CPU_R

P1

_HPD_CPU

P1

1 2

e

DP

_RCOMP_CPU

C

PU

_DP1_CTRL_CLK

C

_DP1_CTRL_DATA

PU

C

PU

_DP2_CTRL_CLK

C

PU

_DP2_CTRL_DATA

G

C6

_THM_DIS#

G

_H17_STRAP

PP

AM6

IS

D

CC8

PP

G

CC9

PP

G

CH4

PP

G

CH3

PP

G

CP4

PP

G

CN4

PP

G

CR26

PP

G

CP26

PP

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

P_RCOMP

_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
_E19/DPPB_CTRLDATA

_E20/DPPC_CTRLCLK
_E21/DPPC_CTRLDATA

_E22/DPPD_CTRLCLK
_E23/DPPD_CTRLDATA

_H16/DDPF_CTRLCLK
_H17/DDPF_CTRLDATA

(#543016) eDP_RCOMP Guideline

Signal Trace

Width

eDP_RCOMP 20 mils 25 mils 24.9 �[

(#543016) DDI Disabling and Termination Guidelines

A A

Port Strap Enable Port Disable Port

Port 1

Port 2

DDPB_CTRLDATA

DDPC_CTRLDATA

5

Isolation
Spacing

Resistor
Value

��1%

PU to 3.3 V with 2.2-k
��5% resistor

PU to 3.3 V with 2.2-k
��5% resistor

Length

<Core Design>

<Core Design>

Max = 100 mils

NC

NC

4

3

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

PU

PU

PU

(DDI/EDP)

(DDI/EDP)

(DDI/EDP)

C

C

C

AS

AS

AS

W

W

W

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

4 1

4 1

4 1

1

o

o

o

f

f

f

A

A

A

00

00

00

0

0

0

6Thursday, March 07, 2019

6Thursday, March 07, 2019

6Thursday, March 07, 2019

_

A_DQS_DN0

M

_

A_DQS_DN1

M

_

A_DQS_DN2

M

A_DQS_DN3

_

M

_

A_DQS_DN4

M

_

A_DQS_DN5

M

A_DQS_DN6

_

M

_

A_DQS_DN7

M

_

A_DQS_DP0

M

_

A_DQS_DP1

M

_

A_DQS_DP2

M

_

A_DQS_DP3

M

A_DQS_DP4

_

M

A_DQS_DP5

_

M

_

A_DQS_DP6

M

_

A_DQS_DP7

M

5

_

B_DQS_DN[7:0]13

M

B_DQS_DP[7:0]13

_

M

_

B_DQ013

M

_

B_DQ113

M

_B_DQ213

M

_

B_DQ313

M

B_DQ413

_

M

_

B_DQ513

M

B_DQ613

_

M

B_DQ713

_

M

_

B_DQ813

M

B_DQ913

_

M

_

B_DQ1013

M

B_DQ1113

_

M

_

B_DQ1213

M

_

B_DQ1313

M

_

B_DQ1413

M

_

B_DQ1513

M

B_DQS_DN0

_

M

_

B_DQS_DN1

M

_

B_DQS_DN2

M

_

B_DQS_DN3

M

B_DQS_DN4

_

M

_

B_DQS_DN5

M

_

B_DQS_DN6

M

B_DQS_DN7

_

M

_

B_DQS_DP0

M

_

B_DQS_DP1

M

_

B_DQS_DP2

M

_

B_DQS_DP3

M

B_DQS_DP4

_

M

B_DQS_DP5

_

M

_

B_DQS_DP6

M

_

B_DQS_DP7

M

M_A_DQ[0:7]

M_A_DQ[8:15]

M_A_DQ[32:39]

Main Func = CPU

A_DQS_DN[7:0]12

_

M

A_DQS_DP[7:0]12

_

M

D D

_

A_DQ012

M

_

A_DQ112

M

_A_DQ212

M

_

A_DQ312

M

A_DQ412

DQ[0:7]

DQ[8:15]

_

M

_

A_DQ512

M

A_DQ612

_

M

A_DQ712

_

M

_

A_DQ812

M

A_DQ912

_

M

_

A_DQ1012

M

A_DQ1112

_

M

_

A_DQ1212

M

_

A_DQ1312

M

_

A_DQ1412

M

_

A_DQ1512

M

M_A_DQ[40:47]

_

A_DQ1612

M

A_DQ1712

_

M

_

A_DQ1812

M

_A_DQ1912

_

A_CLK#0 12

M

A_CLK0 12

_

M

A_CLK#1 12

_

M

_

A_CLK1 12

M

_

A_CKE0 12

M

_

A_CS#0 12

M

A_ODT0 12

_

M

_

M

_

M

_

M

_

M

_A_A4 12

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

A_A0 12
A_A1 12
A_A2 12
A_A3 12

A_A5 12
A_A6 12
A_A7 12
A_A8 12
A_A9 12

A_B0 12
A_B1 12
A_B2 12
A_B3 12
A_B4 12
A_B5 12
A_B6 12
A_B7 12
A_B8 12
A_B9 12

A_CKE1 12
A_CS#1 12

M

_

A_DQ2012

M

_

A_DQ2112

M

A_DQ2212

_

M

A_DQ2312

_

M

A_DQ2412

_

M

_

A_DQ2512

M

A_DQ2612

_

M

_

A_DQ2712

M

A_DQ2812

_

M

A_DQ2912

_

M

_

A_DQ3012

M

_

A_DQ3112

M

A_DQ3212

_

M

A_DQ3312

_

M

_

A_DQ3412

M

A_DQ3512

_

M

_

A_DQ3612

M

A_DQ3712

_

M

_

A_DQ3812

M

A_DQ3912

_

M

A_DQ4012

_

M

_A_DQ4112

M

A_DQ4212

_

M

A_DQ4312

_

M

A_DQ4412

_

M

_

A_DQ4512

M

_

A_DQ4612

M

_

A_DQ4712

M

A_DQ4812

_

M

A_DQ4912

_

M

A_DQ5012

_

M

_

A_DQ5112

M

A_DQ5212

_

M

A_DQ5312

_

M

_

A_DQ5412

M

A_DQ5512

_

M

_

A_DQ5612

M

A_DQ5712

_

M

_

A_DQ5812

M

_

A_DQ5912

M

A_DQ6012

_

M

_

A_DQ6112

M

_

A_DQ6212

M

A_DQ6312

_

M

_

SM_VREF_CNTA 1 2

V

_

SM_VREF_CNTB 1 3

V

R_CA_VREF 12

D

D

A_CKE2 12

A_CKE3 12

T

T_CNTL 51

V

5

M_A_DQ[16:23]

C C

M_A_DQ[24:31]

M_A_DQ[32:39]

M_A_DQ[40:47]

M_A_DQ[48:55]

M_A_DQ[56:63]

B B

A A

_

B_DQ1613

M

B_DQ1713

_

M

_

B_DQ1813

M

_B_DQ1913

M

_

B_DQ2013

M

_

B_DQ2113

M

B_DQ2213

_

M

B_DQ2313

_

M

B_DQ2413

_

M

_

B_DQ2513

M

B_DQ2613

_

M

_

B_DQ2713

M

B_DQ2813

_

M

B_DQ2913

_

M

_

B_DQ3013

M

_

B_DQ3113

M

B_DQ3213

_

M

B_DQ3313

_

M

_

B_DQ3413

M

B_DQ3513

_

M

_

B_DQ3613

M

B_DQ3713

_

M

_

B_DQ3813

M

B_DQ3913

_

M

B_DQ4013

_

M

_B_DQ4113

M

B_DQ4213

_

M

B_DQ4313

_

M

B_DQ4413

_

M

_

B_DQ4513

M

_

B_DQ4613

M

_

B_DQ4713

M

B_DQ4813

_

M

B_DQ4913

_

M

B_DQ5013

_

M

_

B_DQ5113

M

B_DQ5213

_

M

B_DQ5313

_

M

_

B_DQ5413

M

B_DQ5513

_

M

_

B_DQ5613

M

B_DQ5713

_

M

_

B_DQ5813

M

_

B_DQ5913

M

B_DQ6013

_

M

_

B_DQ6113

M

_

B_DQ6213

M

B_DQ6313

_

M

_

B_CLK#0 13

M

_

B_CLK0 13

M

B_CLK#1 13

_

M

B_CLK1 13

_

M

_B_CKE0 13

M

B_CS#0 13

_

M

B_ODT0 13

_

M

B_A0 13

_

M

B_A1 13

_

M

B_A2 13

_

M

_

B_A3 13

M

_B_A4 13

M

_

B_A5 13

M

_

B_A6 13

M

B_A7 13

_

M

_

B_A8 13

M

B_A9 13

_

M

_

B_B0 13

M

_

B_B1 13

M

_

B_B2 13

M

_

B_B3 13

M

B_B4 13

_

M

B_B5 13

_

M

_

B_B6 13

M

B_B7 13

_

M

_

B_B8 13

M

B_B9 13

_

M

B_CKE1 13

_

M

_

B_CS#1 13

M

_

B_CKE2 13

M

B_CKE3 13

_

M

M_B_DQ[0:7]

M_B_DQ[8:15]

M_B_DQ[32:39]

M_B_DQ[40:47]

4

3

DDR4 ball type: Non-Interleaved Type

P

A_DQ0
A_DQ1
A_DQ2
A_DQ3
A_DQ4
A_DQ5
A_DQ6
A_DQ7
A_DQ8
A_DQ9
A_DQ10
A_DQ11
A_DQ12
A_DQ13
A_DQ14
A_DQ15
A_DQ32
A_DQ33
A_DQ34
A_DQ35
A_DQ36
A_DQ37
A_DQ38
A_DQ39
A_DQ40
A_DQ41
A_DQ42
A_DQ43
A_DQ44
A_DQ45
A_DQ46
A_DQ47

B_DQ32
B_DQ33
B_DQ34
B_DQ35
B_DQ36
B_DQ37
B_DQ38
B_DQ39
B_DQ40
B_DQ41
B_DQ42
B_DQ43
B_DQ44
B_DQ45

B_DQ47

AW35
AW34

AW36
AW37

A26
D26
D28
C28
B26
C26
B28
A28
B30
D30
B33
D32
A30
C30
B32
C32
H37
H34
K34
K35
H36
H35
K36
K37
N36
N34
R37
R34
N37
N35
R36

R35
AN35
AN34
AR35
AR34
AN37
AN36
AR36
AR37
AU35
AU34

AU37
AU36

BA35
BA34
BC35
BC34
BA37
BA36
BC36
BC37
BE35
BE34
BG35
BG34
BE37
BE36
BG36
BG37

WHISKEY-LAKE-GP

C

D

R0_DQ0/DDR0_DQ0

D

R0_DQ1/DDR0_DQ1

D

D

DR0_DQ2/DDR0_DQ2

D

D

R0_DQ3/DDR0_DQ3

D

R0_DQ4/DDR0_DQ4

D

D

DR0_DQ5/DDR0_DQ5

D

D

R0_DQ6/DDR0_DQ6

D

R0_DQ7/DDR0_DQ7

D

D

D

R0_DQ8/DDR0_DQ8

D

D

R0_DQ9/DDR0_DQ9

D

D

R0_DQ10/DDR0_DQ10

D

D

R0_DQ11/DDR0_DQ11

D

R0_DQ12/DDR0_DQ12

D

D

D

R0_DQ13/DDR0_DQ13

D

R0_DQ14/DDR0_DQ14

D

D

D

R0_DQ15/DDR0_DQ15

D

R0_DQ16/DDR0_DQ32

D

D

R0_DQ17/DDR0_DQ33

D

D

R0_DQ18/DDR0_DQ34

D

D

R0_DQ19/DDR0_DQ35

D

D

D

R0_DQ20/DDR0_DQ36

D

R0_DQ21/DDR0_DQ37

D

D

D

R0_DQ22/DDR0_DQ38

D

R0_DQ23/DDR0_DQ39

D

D

R0_DQ24/DDR0_DQ40

D

D

D

R0_DQ25/DDR0_DQ41

D

D

R0_DQ26/DDR0_DQ42

D

R0_DQ27/DDR0_DQ43

D

D

D

R0_DQ28/DDR0_DQ44

D

D

R0_DQ29/DDR0_DQ45

D

R0_DQ30/DDR0_DQ46

D

D

D

R0_DQ31/DDR0_DQ47

D

R0_DQ32/DDR1_DQ0

D

D

D

R0_DQ33/DDR1_DQ1

D

D

R0_DQ34/DDR1_DQ2

D

R0_DQ35/DDR1_DQ3

D

D

D

R0_DQ36/DDR1_DQ4

D

D

R0_DQ37/DDR1_DQ5

D

R0_DQ38/DDR1_DQ6

D

D

R0_DQ39/DDR1_DQ7

D

D

D

R0_DQ40/DDR1_DQ8

D

R0_DQ41/DDR1_DQ9

D

D

D

R0_DQ42/DDR1_DQ10

D

R0_DQ43/DDR1_DQ11

D

D

R0_DQ44/DDR1_DQ12

D

D

R0_DQ45/DDR1_DQ13

D

D

D

R0_DQ46/DDR1_DQ14

D

R0_DQ47/DDR1_DQ15

D

D

D

R0_DQ48/DDR1_DQ32

D

D

R0_DQ49/DDR1_DQ33

D

R0_DQ50/DDR1_DQ34

D

D

D

R0_DQ51/DDR1_DQ35

D

R0_DQ52/DDR1_DQ36

D

D

D

R0_DQ53/DDR1_DQ37

D

DR0_DQ54/DDR1_DQ38

D

D

R0_DQ55/DDR1_DQ39

D

D

R0_DQ56/DDR1_DQ40

D

D

R0_DQ57/DDR1_DQ41

D

R0_DQ58/DDR1_DQ42

D

D

D

R0_DQ59/DDR1_DQ43

D

D

R0_DQ60/DDR1_DQ44

D

R0_DQ61/DDR1_DQ45

D

D

D

R0_DQ62/DDR1_DQ46

D

R0_DQ63/DDR1_DQ47

D

D

ZZ.00CPU.271

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

B_DQ0

M

B_DQ1

_

M

B_DQ2

_

M

_

B_DQ3

M

B_DQ4

_

M

_B_DQ5

M

B_DQ6

_

M

B_DQ7

_

M

_

B_DQ8

M

_

B_DQ9

M

B_DQ10

_

M

_

B_DQ11

M

_B_DQ12

M

B_DQ13

_

M

_

B_DQ14

M

B_DQ15

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_B_DQ46

M

_

M

DQ Bit Swapping is allowed within the same byte, a nd Byte Swapping is allowed within the same channel.
Clock (CLK and CLK#) and Strobe ( DQS and DQS#) dif ferential signal swapping within a pair is not allow ed. Also differen tial
clock pair to c lock pair swapping within a channel is not allowed.

4

U1B

2 OF 20

D

R0_CKN0/DDR0_CKN0

D

R0_CKP0/DDR0_CKP0

D

D

DR0_CKN1/DDR0_CKN1

D

D

R0_CKP1/DDR0_CKP1

D

DR0_CKE0/DDR0_CKE0

D

D

R0_CKE1/DDR0_CKE1

D

R0_CKE2/NC

D

D

D

R0_CKE3/NC

D

D

R0_CS#0/DDR0_CS#0

D

D

R0_CS#1/DDR0_CS#1

D

R0_ODT0/DDR0_ODT0

D

D

C

/DDR0_ODT1

N

D

R0_CAB9/DDR0_MA0

D

R0_CAB8/DDR0_MA1

D

D

R0_CAB5/DDR0_MA2

D

D

/DDR0_MA3

C

N

/DDR0_MA4

C

N

D

R0_CAA0/DDR0_MA5

D

R0_CAA2/DDR0_MA6

D

D

D

R0_CAA4/DDR0_MA7

D

R0_CAA3/DDR0_MA8

D

D

R0_CAA1/DDR0_MA9

D

D
D

R0_CAB7/DDR0_MA10

D

D

R0_CAA7/DDR0_MA11

D

R0_CAA6/DDR0_MA12

D

D

D

R0_CAB0/DDR0_MA13

D

R0_CAB2/DDR0_MA14

D

D

D

R0_CAB1/DDR0_MA15

D

R0_CAB3/DDR0_MA16

D

D

D

R0_CAB4/DDR0_BA0

D

R0_CAB6/DDR0_BA1

D

D

D

R0_CAA5/DDR0_BG0

D

R0_CAA8/DDR0_ACT#

D

D

R0_CAA9/DDR0_BG1

D

D

R0_DQSN0/DDR0_DQSN0

D

D

D

R0_DQSP0/DDR0_DQSP0

D

R0_DQSN1/DDR0_DQSN1

D

D

R0_DQSP1/DDR0_DQSP1

D

D

R0_DQSN2/DDR0_DQSN4

D

D

D

R0_DQSP2/DDR0_DQSP4

D

R0_DQSN3/DDR0_DQSN5

D

D

D

R0_DQSP3/DDR0_DQSP5

D

D

R0_DQSN4/DDR1_DQSN0

D

R0_DQSP4/DDR1_DQSP0

D

D

D

R0_DQSN5/DDR1_DQSN1

D

R0_DQSP5/DDR1_DQSP1

D

D

D

R0_DQSN6/DDR1_DQSN4

D

DR0_DQSP6/DDR1_DQSP4

D

D

R0_DQSN7/DDR1_DQSN5

D

D

R0_DQSP7/DDR1_DQSP5

D

/DDR0_ALERT#

C

N

C

/DDR0_PAR
N
D

R_VREF_CA

D

R0_VREF_DQ0

D

D

D

R0_VREF_DQ1

D

R1_VREF_DQ

D

D

R_VTT_CTL

D

D

_

A_CLK#0

V32

M

A_CLK0

_

V31

M

A_CLK#1

_

T32

M

_

A_CLK1

T31

M

A_CKE0

_

U36

M

_

A_CKE1

U37

M

A_CKE2

_

U34

M

_

A_CKE3

U35

M

_

A_CS#0

AE32

M

A_CS#1

_

AF32

M

A_ODT0

_

AE31

M

AF31

_

A_B9

AC37

M

A_B8

_

AC36

M

_

A_B5

AC34

M

AC35
AA35

_

A_A0

AB35

M

_

A_A2

AA37

M

A_A4

_

AA36

M

_

A_A3

AB34

M

_

A_A1

W36

M

A_B7

_

Y31

M

_

A_A7

W34

M

A_A6

_

AA34

M

_

A_B0

AC32

M

A_B2

_

AC31

M

_

A_B1

AB32

M

_

A_B3

Y32

M

A_B4

_

W32

M

_

A_B6

AB31

M

A_A5

_

V34

M

A_A8

_

V35

M

A_A9

_

W35

M

_

A_DQS_DN0

C27

M

A_DQS_DP0

_

D27

M

_

A_DQS_DN1

D31

M

_A_DQS_DP1

C31

M

A_DQS_DN4

_

J35

M

_

A_DQS_DP4

J34

M

A_DQS_DN5

_

P34

M

_

A_DQS_DP5

P35

M

_

B_DQS_DN0

AP35

M

_

B_DQS_DP0

AP34

M

_

B_DQS_DN1

AV34

M

_

B_DQS_DP1

AV35

M

B_DQS_DN4

_

BB35

M

B_DQS_DP4

_

BB34

M

_

B_DQS_DN5

BF34

M

B_DQS_DP5

_

BF35

M

W37
W31

R_CA_VREF

D

F36

D

_

SM_VREF_CNTA

D35

V

D37

_

SM_VREF_CNTB

E36

V

M

_PGCNTL

C35

S

3

M_A_DQS0

M_A_DQS1

M_A_DQS4

M_A_DQS5

M_B_DQS0

M_B_DQS1

M_B_DQS4

M_B_DQS5

M

S

_PGCNTL

M_A_DQ[16:23]

M_A_DQ[24:31]

M_A_DQ[48:55]

M_A_DQ[56:63]

M_B_DQ[16:23]

M_B_DQ[24:31]

M_B_DQ[48:55]

M_B_DQ[56:63]

5

01

G

Q

S

PJA138KA-GP

084.00138.0A31

_

A_DQ16

M

_

A_DQ17

M

A_DQ18

_

M

A_DQ19

_

M

_

A_DQ20

M

_

A_DQ21

M

A_DQ22

_

M

_

A_DQ23

M

A_DQ24

_

M

_

A_DQ25

M

A_DQ26

_

M

_

A_DQ27

M

A_DQ28

_

M

A_DQ29

_

M

A_DQ30

_

M

A_DQ31

_

M

_

A_DQ48

M

A_DQ49

_

M

_

A_DQ50

M

_

A_DQ51

M

A_DQ52

_

M

_

A_DQ53

M

_

A_DQ54

M

A_DQ55

_

M

_

A_DQ56

M

_

A_DQ57

M

A_DQ58

_

M

_

A_DQ59

M

A_DQ60

_

M

_

A_DQ61

M

A_DQ62

_

M

A_DQ63

_

M

_

B_DQ16

M

_

B_DQ17

M

B_DQ18

_

M

B_DQ19

_

M

_

B_DQ20

M

B_DQ21

_

M

_B_DQ22

M

B_DQ23

_

M

B_DQ24

_

M

_

B_DQ25

M

_

B_DQ26

M

B_DQ27

_

M

_

B_DQ28

M

_B_DQ29

M

B_DQ30

_

M

_

B_DQ31

M

B_DQ48

_

M

_

B_DQ49

M

_

B_DQ50

M

_

B_DQ51

M

_

B_DQ52

M

_

B_DQ53

M

B_DQ54

_

M

B_DQ55

_

M

_

B_DQ56

M

B_DQ57

_

M

_

B_DQ58

M

B_DQ59

_

M

B_DQ60

_

M

B_DQ61

_

M

_

B_DQ62

M

_B_DQ63

M

J22
H25
G22
H22
F25

J25
G25
F22
D22
C22
C24
D24
A22
B22
A24
B24
G31
G32
H29
H28
G28
G29
H31
H32

L31

L32
N29
N28

L28

L29
N31
N32

AJ29

AJ30
AM32
AM31
AM30
AM29

AJ31

AJ32
AR31
AR32
AV30
AV29
AR30
AR29
AV32
AV31
BA32
BA31
BD31
BD32
BA30
BA29
BD29
BD30
BG31
BG32
BK32
BK31
BG29
BG30
BK30
BK29

C

WHISKEY-LAKE-GP

ZZ.00CPU.271

2

P

U1C

R1_DQ0/DDR0_DQ16

D
D

D

R1_DQ1/DDR0_DQ17

D

R1_DQ2/DDR0_DQ18

D
D

DR1_DQ3/DDR0_DQ19
D

D

R1_DQ4/DDR0_DQ20

D

R1_DQ5/DDR0_DQ21

D
D

DR1_DQ6/DDR0_DQ22
D

D

R1_DQ7/DDR0_DQ23

D

R1_DQ8/DDR0_DQ24

D
D

D

R1_DQ9/DDR0_DQ25

D
D

R1_DQ10/DDR0_DQ26

D
D

R1_DQ11/DDR0_DQ27

D
D

R1_DQ12/DDR0_DQ28

D

R1_DQ13/DDR0_DQ29

D
D

D

R1_DQ14/DDR0_DQ30

D

R1_DQ15/DDR0_DQ31

D
D

D

R1_DQ16/DDR0_DQ48

D

R1_DQ17/DDR0_DQ49

D
D

R1_DQ18/DDR0_DQ50

D
D

R1_DQ19/DDR0_DQ51

D
D

R1_DQ20/DDR0_DQ52

D
D

D

R1_DQ21/DDR0_DQ53

D

R1_DQ22/DDR0_DQ54

D
D

D

R1_DQ23/DDR0_DQ55

D

R1_DQ24/DDR0_DQ56

D
D

R1_DQ25/DDR0_DQ57

D
D

D

R1_DQ26/DDR0_DQ58

D
D

R1_DQ27/DDR0_DQ59

D

R1_DQ28/DDR0_DQ60

D
D

D

R1_DQ29/DDR0_DQ61
D
D

R1_DQ30/DDR0_DQ62
D

R1_DQ31/DDR0_DQ63

D
D
D

R1_DQ32/DDR1_DQ16
D

R1_DQ33/DDR1_DQ17

D
D
D

R1_DQ34/DDR1_DQ18
D
D

R1_DQ35/DDR1_DQ19
D

R1_DQ36/DDR1_DQ20

D
D
D

R1_DQ37/DDR1_DQ21
D
D

R1_DQ38/DDR1_DQ22
D

R1_DQ39/DDR1_DQ23

D
D

R1_DQ40/DDR1_DQ24

D
D
D

R1_DQ41/DDR1_DQ25
D

R1_DQ42/DDR1_DQ26

D
D
D

R1_DQ43/DDR1_DQ27
D

R1_DQ44/DDR1_DQ28

D
D

R1_DQ45/DDR1_DQ29

D
D

R1_DQ46/DDR1_DQ30

D
D
D

R1_DQ47/DDR1_DQ31
D

R1_DQ48/DDR1_DQ48

D
D
D

R1_DQ49/DDR1_DQ49
D
D

R1_DQ50/DDR1_DQ50
D

R1_DQ51/DDR1_DQ51

D
D
D

R1_DQ52/DDR1_DQ52
D

R1_DQ53/DDR1_DQ53

D
D
D

R1_DQ54/DDR1_DQ54
D
DR1_DQ55/DDR1_DQ55
D
D

R1_DQ56/DDR1_DQ56
D
D

R1_DQ57/DDR1_DQ57
D
D

R1_DQ58/DDR1_DQ58
D

R1_DQ59/DDR1_DQ59

D
D
D

R1_DQ60/DDR1_DQ60
D
D

R1_DQ61/DDR1_DQ61
D

R1_DQ62/DDR1_DQ62

D
D
D

R1_DQ63/DDR1_DQ63
D

3 OF 20

R1_CKN0/DDR1_CKN0

D
D

D

R1_CKP0/DDR1_CKP0

D

R1_CKN1/DDR1_CKN1

D
D

DR1_CKP1/DDR1_CKP1
D

R1_CKE0/DDR1_CKE0

D
D

DR1_CKE1/DDR1_CKE1
D

D

R1_CKE2/NC

D

R1_CKE3/NC

D
D

D

R1_CS#0/DDR1_CS#0

D
D

R1_CS#1/DDR1_CS#1

D
D

R1_ODT0/DDR1_ODT0

D

/DDR1_ODT1

C
N

D

R1_CAB9/DDR1_MA0

D

R1_CAB8/DDR1_MA1

D
D

D

R1_CAB5/DDR1_MA2

D

/DDR1_MA3

C
N

/DDR1_MA4

C
N

R1_CAA0/DDR1_MA5

D
D

R1_CAA2/DDR1_MA6

D
D

D

R1_CAA4/DDR1_MA7

D

R1_CAA3/DDR1_MA8

D
D

D

R1_CAA1/DDR1_MA9

D

R1_CAB7/DDR1_MA10

D
D

R1_CAA7/DDR1_MA11

D
D

D

R1_CAA6/DDR1_MA12

D
D

R1_CAB0/DDR1_MA13

D

D

R1_CAB2/DDR1_MA14
D
D

R1_CAB1/DDR1_MA15
D

R1_CAB3/DDR1_MA16

D
D

R1_CAB4/DDR1_BA0

D

D

D

R1_CAB6/DDR1_BA1

D

D

R1_CAA5/DDR1_BG0

D

D

R1_CAA9/DDR1_BG1

D

D

R1_CAA8/DDR1_ACT#
D

R1_DQSN0/DDR0_DQSN2

D
D
D

R1_DQSP0/DDR0_DQSP2

D

R1_DQSN1/DDR0_DQSN3

D
D
D

R1_DQSP1/DDR0_DQSP3

D

R1_DQSN2/DDR0_DQSN6

D
D

R1_DQSP2/DDR0_DQSP6

D
D

R1_DQSN3/DDR0_DQSN7

D
D
D

R1_DQSP3/DDR0_DQSP7

D

R1_DQSN4/DDR1_DQSN2

D
D
D

R1_DQSP4/DDR1_DQSP2
D
D

R1_DQSN5/DDR1_DQSN3
D

R1_DQSP5/DDR1_DQSP3

D
D
D

R1_DQSN6/DDR1_DQSN6
D

R1_DQSP6/DDR1_DQSP6

D
D
D

R1_DQSN7/DDR1_DQSN7
D
DR1_DQSP7/DDR1_DQSP7
D

C

/DDR1_ALERT#

N

C

/DDR1_PAR

N

AM_RESET#

R
D

D

R_RCOMP0

D

R_RCOMP1

D
D
D

R_RCOMP2

D

_

B_CLK#0

AF28

M

_

B_CLK0

AF29

M

B_CLK#1

_

AE28

M

B_CLK1

_

AE29

M

_

B_CKE0

T28

M

B_CKE1

_

T29

M

_

B_CKE2

V28

M

B_CKE3

_

V29

M

B_CS#0

_

AL37

M

_

B_CS#1

AL35

M

B_ODT0

_

AL36

M

AL34

B_B9

_

AG36

M

B_B8

_

AG35

M

_

B_B5

AF34

M

AG37
AE35

_

B_A0

AF35

M

B_A2

_

AE37

M

_

B_A4

AC29

M

_

B_A3

AE36

M

B_A1

_

AB29

M

_

B_B7

AG34

M

_

B_A7

AC28

M

B_A6

_

AB28

M

_

B_B0

AK35

M

_

B_B2

AJ35

M

B_B1

_

AK34

M

B_B3

_

AJ34

M

_

B_B4

AJ37

M

B_B6

_

AJ36

M

B_A5

_

W29

M

B_A9

_

Y28

M

_B_A8

W28

M

A_DQS_DN2

_

H24

M

_

A_DQS_DP2

G24

M

_

A_DQS_DN3

C23

M

A_DQS_DP3

_

D23

M

_

A_DQS_DN6

G30

M

_A_DQS_DP6

H30

M

A_DQS_DN7

_

L30

M

_

A_DQS_DP7

N30

M

B_DQS_DN2

_

AL31

M

_

B_DQS_DP2

AL30

M

_

B_DQS_DN3

AU31

M

_

B_DQS_DP3

AU30

M

_

B_DQS_DN6

BC31

M

_

B_DQS_DP6

BC30

M

B_DQS_DN7

_

BH31

M

B_DQS_DP7

_

BH30

M

Y29
AE34
BU31

_RCOMP_0

M

BN28

S
M

_RCOMP_1

BN27

S

M_RCOMP_2

BN29

S

Layout Note:

M_A_DQS2

M_A_DQS3

M_A_DQS6

M_A_DQS7

M_B_DQS2

M_B_DQS3

M_B_DQS6

M_B_DQS7

01 200R2F-L-GP

5
R

1 2

5

02 80D6R2F-L-GP

1 2

R
5

03 162R2F-GP

1 2

R

1

#543016

Design Guidelin e:
SM_RCOMP keep r outing length less than 500 mils.

D

3V_S5

3

12

06

5

R

10KR2J-L-GP

5

02_G

Q

D

G

S

2N7002K-2-GP

02

5

Q

Notice:ZZ.2N702 .J3101

84.2N702.J31

3V_S0

D
3

12

5

07

R

10KR2J-L-GP

T_CNTL

T
V

D

<Core Design>

<Core Design>

<Core Design>

W

W

W

stron Corporation

stron Corporation

stron Corporation

i

i

i

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

1

1

2

2

2

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

i

tle

Title

Title

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

2

2

2

A

A

A

Date: Sheet

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

C

C

C

P

P

P

U_(DDR)

U_(DDR)

U_(DDR)

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

A

A

A

W

W

W

1

5 1

5 1

5 1

f

f

f

o

o

o

0

0

0

0

0

0

A

A

A

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

5

WWW.AliSaler.Com

Main Func = CPU

C

FG

C

315

FG

C

415

D D

C C

B B

FG

1 2

R

60

1 49D9R2F-GP

T

P6

3

C

4

FG

C

FG

I

TP

1

18

_RCOMP

_PMODE

4

M4

M3

AB5

W4

CG2
CG1

BV24
BV25

BK36
BK35

W3

AM4

AM3

3

SV

R

SV

R

D_TP#CN36

SV

R

SV

R

SV

R

SV

R

SV

R

SV

R

SV

R

SV

R

SV

R

D_TP#CR35

SV

R

1

OF 20

7

D_TP#F37
D_TP#F34

_TRIG

ST

I

D_TP#BJ36
D_TP#BJ34

BK34

P#

T

BR18

P#

T

D_TP#BT9
D_TP#BT8

D_TP#BP8
D_TP#BP9

SV

D#CR4

R

SV

D#CP3

R

SV

D#CR3

R

D_TP#AT3

D_TP#AU3

D#AN1

SV

R

SV

D#AN2

R

D#AN4

SV

R

SV

D#AN3

R

ST

_TP0

I

ST

_TP1

I

_TRIG0

ST

I

ST

_TRIG1

I

P#

BP34

T

SS

V

P#

BP35

T

F37
F34
CP36
CN36

BJ36
BJ34

BK34
BR18

BT9
BT8

BP8
BP9

CR4

CP3
CR3

AT3
AU3

AN1
AN2

AN4
AN3

AL2
AL1

AL4
AL3

BP34

P36

B
BP35

CR35

I

ST

_TRIG

1

T

P6

20

TPAD14-OP-GP

C

1Q

PU

T4

R4
T3
R3

J4

J3

R2
N2
R1
N1

J2
L2
J1
L1

L3

N3

L4

N4

H4
H3

WHL QS/CFL/WHL_ES1_CNL U

FG

0

C

1

FG

C

2

FG

C

FG

3

C

4

FG

C

5

FG

C

FG

6

C

FG

7

C

8

FG

C

9

FG

C

FG

10

C

11

FG

C

12

FG

C

FG

13

C

14

FG

C

15

FG

C

FG

16

C

FG

18

C

FG

17

C

19

FG

C

_RCOMP

FG

C

TP

_PMODE

I

SV

D#CG2

R

D#CG1

SV

R

D#H4

SV

R

SV

D#H3

R

SV

D#BV24

R

D#BV25

SV

R

SV

D#BK36

R

D#BK35

SV

R

SV

D#W3

R

D#AM4

SV

R

D_TP#AM3

SV

R

2

1

<Core Design>

<Core Design>

E1

KT

OCC#

S

A A

WHISKEY-LAKE-GP

S

KT

OCC#

1

T

P6

19

ZZ.00CPU.271

5

4

3

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

PU

PU

PU

(CFG/IST)

(CFG/IST)

(CFG/IST)

C

C

C

AS

AS

AS

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

W

W

W

o

o

o

f

f

6 1

6 1

6 1

f

1

A

A

A

00

00

00

0

0

0

6Thursday, March 07, 2019

6Thursday, March 07, 2019

6Thursday, March 07, 2019

5

4

3

2

1

Main Func = CPU

V

C

CCORE_SENSE46

V

SCORE_SENSE46

S

S

ID_DATA_CPU46

V

D D

S

V

ID_CLK_CPU46

S

ID_ALERT#_CPU46

V

1

_VCCST_CPU

V

#

544669

CLOSE TO CPU

12

R

26

7

SVID DATA

C C

S

ID_DATA_CPU_R

V

SVID CLOCK

S

V

ID_CLK_CPU_R

B B

SVID ALERT

S

ID_ALERT#_CPU_R

V

100R2F-L1-GP-U

1 2

R

09 0R0402-PAD

7

1 2

R

32 0R0402-PAD

7

1 2

R

7

28 220R2J-L2-GP

1

V

_VCCST_CPU

DY

1

V

_VCCST_CPU

12

S

ID_DATA_CPU

V

#544669
CLOSE TO VR

12

R

7

23

54D9R2F-L1-GP

S

V

ID_CLK_CPU

#

544669

CLOSE TO CPU

R

7

27

56R2J-4-GP

S

ID_ALERT#_CPU

V

1

_CPU_CORE

V

C

P

AN9

V

AN10

V

AN24

V

AN26

V

AN27

V

AP2

V

AP9

V

AP24

V

AP26

V

AR5

V

AR6

V

AR7

V

AR8

V

AR10

V

AR25

V

AR27

V

AT9

V

AT24

V

AT26

V

AU5

V

AU6

V

AU7

V

AU8

V

AU9

V

AU24

V

AU25

V

AU26

V

AU27

V

AV2

V

AV5

V

AV7

V

AV10

V

AV27

V

AW5

V

AW6

V

AW7

V

AW8

V

AW9

V

AW10

V

BB9

R

BC24

R

AY9

R

BB24

R

WHISKEY-LAKE-GP

ZZ.00CPU.271

U1L

CCORE

C

CCORE

C

CCORE

C
C

CCORE
CCORE

C

CCORE

C
C

CCORE

C

CCORE
CCORE

C

CCORE

C
C

CCORE
CCORE

C

CCORE

C
C

CCORE
CCORE

C

CCORE

C

CCORE

C
C

CCORE

C

CCORE

C

CCORE
CCORE

C
C

CCORE

C

CCORE
CCORE

C
C

CCORE

C

CCORE

C

CCORE

C

CCORE
CCORE

C
C

CCORE

C

CCORE
CCORE

C
C

CCORE
CCORE

C
C

CCORE
CCORE

C
C

CCORE
CCORE

C

CCORE

C

VD#BB9

S
S

VD#BC24

S

VD#AY9
VD#BB24

S

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

C

C_SENSE

V

S_SENSE

S

V

I

DALERT#

V

V

R

1

2

OF 20

CCORE

C

CCORE

C

CCORE

C
C

CCORE
CCORE

C

CCORE

C
C

CCORE

C

CCORE
CCORE

C

CCORE

C
C

CCORE
CCORE

C

CCORE

C
C

CCORE
CCORE

C

CCORE

C

CCORE

C
C

CCORE

C

CCORE

C

CCORE
CCORE

C
C

CCORE

C

CCORE
CCORE

C
C

CCORE

C

CCORE

C

CCORE

C

CCORE
CCORE

C
C

CCORE

C

CCORE
CCORE

C
C

CCORE
CCORE

C
C

CCORE

I

DSCK

V

DSOUT

I

VD#Y3

S

CSTG

C

V

AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27

AN6
AN5

AA3

AA1

AA2

Y3

BG3

1

_CPU_CORE

V

V

C

CCORE_SENSE

V

SCORE_SENSE

S

S

V

ID_ALERT#_CPU_R

S

V

ID_CLK_CPU_R

S

V

ID_DATA_CPU_R

1

V

_VCCSTG

1

_CPU_CORE

V

12

R

7

100R2F-L1-GP-U

12

R

7

100R2F-L1-GP-U

19

V

CCORE_SENSE

C

V

S

SCORE_SENSE

20

Layout Note:

1

. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm

3. Length match<25mil

SVID_543016:

L

ayout Note:
The total Length of Data and Clock (from CPU to each
inch).
Route the Alert signal between the Clock and the Data signals.

A A

5

VR) must be equal (��0.1

4

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

U (VCORE/VID)

U (VCORE/VID)

U (VCORE/VID)

P

P

P

C

C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

Date: Sheet

Date: Sheet

3

Date: Sheet

2

C

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

o

o

o

f

f

7 1

7 1

7 1

f

1

A

A

A

0

0

0

0

0

0

06

06

06

5

WWW.AliSaler.Com

Main Func = CPU

1

VCCGT

V_

V

GT_SENSE46

SS

V

GT_SENSE46

CC

V

SA_SENSE46

D D

C C

B B

A A

SS

V

C

C

1

V_

1

V_

SA_SENSE46

VCCGT

12

R

80

100R2F-L1-GP-U

12

R

80

100R2F-L1-GP-U

VCCSA

12

R

81

100R2F-L1-GP-U

12

R

80

100R2F-L1-GP-U

7

V

GT_SENSE

CC

V

GT_SENSE

SS

8

0

V

SA_SENSE

CC

V

SA_SENSE

SS

9

5

C

A5
A6

A8
A11
A12
A14
A15
A17
A18
A20

B3

B4

B6

B8
B11
B14
B17
B20

C2

C3

C6

C7

C8

C11
C12
C14
C15
C17
C18
C20

D4

D7

D11
D12
D14
D15
D17
D18
D20

E4

F5

F6

F7

F8
F11
F14
F17
F20

G11
G12
G14
G15
G17
G18
G20

H5

H6

H7

H8

H11

WHISKEY-LAKE-GP

ZZ.00CPU.271

4

1M

PU

WHL QS/CFL/WHL_ES1_CNL U

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

GT

CC

V

CC

GT

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT_SENSE

V

SS

GT_SENSE

V

4

3

1

V_S3

D2

1

VCCGT

H12
H14
H15
H17
H18
H20
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N10
P2
P8
R9
T8
T9
T10
U8
U10
V9
W8
W9
AA9
AB2
AB8
AB9
AB10
AC8
AD9
AE8
AE9
AE10
AF2
AF8
AF10
AG8
AG9
AH9
AJ8
AJ10
AK2
AK9
AL8
AL9
AL10
AM8
V2
Y8
Y10
E3
D2

V_

V

CC

V

SS

1

V_

CPU_CORE

GT_SENSE
GT_SENSE

12

C

4

80

DY

SC1U10V2KX-1DLGP

1

V_

VCCST_CPU

1 2

C

1 SC1U10V2KX-1DLGP

80

1

V_

1 2

C

2 SC1U10V2KX-1DLGP

80

1

D2

V_VCCSFR_OC

1 2

C

80

3 SC1U10V2KX-1DLGP

1

V_

VCCST_CPU

C

12

80
7

3

0.12 A

SC22U6D3V3MX-1-DL-GP

SC1U10V2KX-1DLGP

C

12

80
6

1

OF 20

3

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

CC

GT

V

GT

CC

V

GT

CC

V

GT

CC

V

CC

GT

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

GT

V

GT

CC

V

CC

CORE

V

CORE

CC

V

CORE

CC

V

CC

CORE

V

CORE

CC

V

CC

CORE

V

CC

CORE

V

CORE

CC

V

CORE

CC

V

CORE

CC

V

CC

CORE

V

CORE

CC

V

CC

CORE

V

CORE

CC

V

CC

CORE

V

CC

CORE

V

CORE

CC

V

CC

CORE

V

CORE

CC

V

CORE

CC

V

CC

CORE

V

CORE

CC

V

CORE

CC

V

CORE

CC

V

CC

CORE

V

CC

CORE

V

CORE

CC

V

0.04 A

VCCSTG

12

2

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

CC

V

SS

V

SS

V

CC

V

1

OF 20

4

CC

IO_OUT
IO_OUT

CC

IO_OUT

CC

IO_OUT

CC
CC

IO_OUT
IO_OUT

CC

IO_OUT

CC
CC

IO_OUT

CC

IO_OUT
IO_OUT

CC

IO_OUT

CC
CC

IO_OUT
IO_OUT

CC

IO_OUT

CC
CC

IO_OUT
IO_OUT

CC

SA

CC

V

CC

SA

V

CC

SA

V

CC

SA

V

SA

CC

V

CC

SA

V

CC

SA

V

SA

CC

V

CC

SA

V

CC

SA

V

CC

SA

V

CC

SA

V

SA

CC

V

CC

SA

V

CC

SA

V

SA

CC

V

IO_SENSE
IO_SENSE

SA_SENSE
SA_SENSE

C

1N

PU

AD36
AH32
AH36

AM36

AN32

AW32

AY36
BE32
BH36

R32

Y36

BC28

BP11

BP2

BG1
BG2

BL27

BM26

BR11

BT11

SCD1U16V2KX-3DLGP

C

80
5

Q

DD

V

Q

DD

V

Q

DD

V

DD

Q

V

Q

DD

V

Q

DD

V

DD

Q

V

DD

Q

V

Q

DD

V

Q

DD

V

DD

Q

V

D#BC28

SV

R

ST

CC

V

CC

ST

V

STG

CC

V

CC

STG

V

PLL_OC

CC

V

CC

PLL_OC

V

CC

PLL

V

CC

PLL

V

WHISKEY-LAKE-GP

AK24
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18

BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25

BP28
BP29

BE7
BG7

1

1

V_

VCCIO

+

VCCIO(ICCMAX.=2.73A

1

V_

V

SS

SA_SENSE

V

SA_SENSE

CC

ZZ.00CPU.271

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

(VCCGT/VCCIO/VDDQ/VCCSA)

(VCCGT/VCCIO/VDDQ/VCCSA)

(VCCGT/VCCIO/VDDQ/VCCSA)

PU

PU

PU

C

C

C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

AS

AS

AS

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

W

W

W

o

o

o

f

f

8 1

8 1

8 1

f

1

VCCSA

A

A

A

00

00

00

0

0

0

6Thursday, March 07, 2019

6Thursday, March 07, 2019

6Thursday, March 07, 2019

5

D D

C C

4

3

2

1

(Blanking)

B B

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

A A

T

tle

Title

Title

i

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

R

R

R

eserved)

eserved)

eserved)

(

(

(

2

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

o

o

o

f

f

9 1

9 1

9 1

f

1

A

A

A

0

0

0

0

0

0

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

5

WWW.AliSaler.Com

Main Func = CPU

1

CPU_CORE

V_

4

1V_CPU_CORE

3

22U 0603 x 39 (7DY)

2

1

P

P

P

C1

002

VCCGT

12

U42

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

022

C1

12

DY

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

D D

C C

1

V_

P

C1

C1

003

023

12

U42

P

12

004

U42

024

C1

U42

12

P

C1

12

P

C1

C1

005

12

P

C1

12

006

12

U42

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

026

025

C1

12

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

VCCGT

P

P

037

C1

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

B B

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

038

C1

12

039

C1

12

P

P

C1

12

041

040

C1

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

P

12

P

12

C1

C1

C1

007

027

12

P

12

U42

008

028

C1

DY

22U 0603 x 35 (9 DY)

P

P

C1

12

042

043

C1

12

P

P

C1

009

12

P

029

C1

12

P

044

C1

12

P

C1

C1

010

030

045

011

12

P

031

C1

12

P

046

C1

12

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

C1

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

C1

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

P

C1

012

12

U42

P

032

C1

12

DY

P

047

C1

12

P

C1

C1

013

12

12

P

P

034

C1

12

P

12

C1

12

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

048

C1

C1

12

014

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

036

DY

049

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

P

12

P

12

P

12

C1

C1

C1

C1

015

079

050

DY

016

12

U42

P

080

C1

12

P

051

C1

12

P

P

12

P

12

P

12

C1

C1

017

12

U42

P

081

C1

C1

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

052

C1

C1

12

P

P

018

12

U42

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

082

12

U42

P

053

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

C1

C1

C1

C1

019

083

054

12

U42

P

12

P

12

020

084

C1

055

C1

P

C1

021

12

P

056

C1

12

P

P

057

C1

12

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

C1

065

12

A A

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

5

P

058

066

059

C1

12

P

C1

067

12

DY

C1

12

P

C1

12

P

P

060

C1

C1

12

12

P

P

C1

C1

068

12

12

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

061

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

069

DY

P

062

070

DY

DY

063

C1

12

P

C1

001

12

4

C1

12

P

C1

12

DY

P

064

C1

12

1

V_

VCCSA

VCCSA

P

P

C1

071

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

P

C1

072

12

12

22U 0603 x 8 (3DY)

P

P

C1

C1

073

DY

074

12

3

P

C1

C1

075

12

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

076

12

DY

P

P

12

C1

C1

077

DY

078

12

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

T

le

Title

Title

it

PU

PU

PU

_(Power CAP1)

_(Power CAP1)

_(Power CAP1)

C

C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

C

AS

AS

AS

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

W

W

W

o

o

o

f

0 1

f

0 1

f

0 1

1

1

1

1

A

A

A

00

00

00

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

5

4

3

2

1

Main Func = CPU

UNSLICED GT

1

V

_VCCGT

PCH DERIVED RAILS

D D

1

D

0V_S5

12

C

1

102

DY

12

12

C

1

112

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

12

C

C

1

1

128

129

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

1U 0402 x 6

12

C

1

103

DY

DY

12

C

1

104

12

12

C

C

1

1

105

106

DY

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

12

C

1

107

+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)

1

V

_VCCIO

12

C

1

133

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

VCCIO

+VCCIO(ICCMAX.=2.73A)

12

12

C

C

1

1

134

135

DY

DY

12

C

12

C

1

1

109

108

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

12

12

C

C

1

1

110

111

1

0V_S5

130

4

D

SC22U6D3V3MX-1-DL-GP

C
1
115

DY

12

12

12

12

C

C

136

1

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

SC1U10V2KX-1DLGP

C
1
114

12

C

137

1

138

1

C C

3

D

3V_S5_PCH

R

1

103

1 2

0R0603-PAD

1

D

8V_S5

R

1

104

1 2

B B

A A

0R0603-PAD

3

D

3

D

1

D

3V_VCCPRIM

SC10U6D3V3MX-DL-GP

C
1
123

12

DY

5

3V_VCCPRIM

12

C

113

1

DY

SC22U6D3V3MX-1-DL-GP

8V_VCCPRIM

12

C

1

122

DY

SC22U6D3V3MX-1-DL-GP

1

2V_S3

D

12

12

C

C

132

DY

131

1

1

DY

SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP

12

C

1

1

0V_S5

D

139

3

12

C

116

1

1

12

C

140

1

12

C

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

12

C

1

SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP

117

12

12

C

C

141

1

1

0V_S5

D

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<Core Design>

<Core Design>

<Core Design>

T

tle

Title

Title

i

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

1

0V_S5

D

SC10U6D3V3MX-DL-GP

C
1
120

12

DY

P

P

P

U_(Power CAP2)

U_(Power CAP2)

U_(Power CAP2)

C

C

C

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

C
1
121

12

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SC1U10V2KX-1DLGP

A

A

A

0

0

0

0

0

o

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f

f

f

1 106Thursday, March 07, 2019

1 106Thursday, March 07, 2019

1 106Thursday, March 07, 2019

1

1

1

1

0

Main Func = MEMORY

WWW.AliSaler.Com

5

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B11

M

8

_DQ52

_A

B10

M

9

_A

_DQ55

B9

M

0

_DQ50

_A

B8

M

1

_DQS_DP7

_A

L10

M

_A_DQS_DN7

L11

M

_A

_DQS_DP4

G10

M

_DQS_DN4

_A

G11

M

_DQS_DP5

_A

P10

M

_A

_DQS_DN5

P11

M

_A

_DQS_DP6

D10

M

_DQS_DN6

_A

D11

M

AM

3

B

R

Q0

AM

B

4

R

Q1

_A

_ODT0

8

J

M

DT

12

R

240R2F-1-GP

12
01

_DQ58

_A

M

_A

_DQ60

M

_DQ62

_A

M

_A

_DQ59

M

_DQ57

_A

M

_DQ61

_A

M

_DQ56

_A

M

_A

_DQ63

M

_A

_DQ47

M

_A

_DQ46

M

_A

_DQ41

M

_DQ44

_A

M

_DQ42

_A

M

_A

_DQ43

M

_DQ40

_A

M

_A

_DQ45

M

2_ZQ0
2_ZQ1

12

R

240R2F-1-GP

12
04

D6

V_VREF_S0

0

1

12

22

12

R

8K2R2F-1-GP

24

12

_S

_V

REF_CA_DIMMA

M

12

12

R

8K2R2F-1-GP

D2

V_S3

1

12

12

R

8K2R2F-1-GP

12

12

R

8K2R2F-1-GP

12

R

12

R

12

68
C

12

DY

D6
0

240R2F-1-GP

12
02

240R2F-1-GP

12
03

VTT 1uF(0402) x4 VTT 10uF(0603)x2

12

12

69

70

C

C

12

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

3

23

27

A_

VREF

C

26

V_VREF_S0

12

46 38D3R2F-GP

1 2

R

14 38D3R2F-GP

12

1 2

R

15 38D3R2F-GP

12

1 2

R

12

16 38D3R2F-GP

1 2

R

12

17 80D6R2F-L-GP

1 2

R

12

18 80D6R2F-L-GP

1 2

R

19 80D6R2F-L-GP

12

1 2

R

12

20 80D6R2F-L-GP

1 2

R

21 80D6R2F-L-GP

12

1 2

R

12

49 80D6R2F-L-GP

1 2

R

52 80D6R2F-L-GP

12

1 2

R

R

1
2
3
4 5

SRN68J-3-GP

R

1
2 3

SRN68J-5-GP

12

05 68R2-GP

1 2

R

06 68R2-GP

12

1 2

R

R

1
2 3

SRN68J-5-GP

R

1
2 3

SRN68J-5-GP

12

07 68R2-GP

1 2

R

08 68R2-GP

12

1 2

R

R

1
2 3

SRN68J-5-GP

R

1
2
3
4 5

SRN68J-3-GP

12

71

C

12

DY

1 2

10R2F-L1-GP

1 2

5D1R2F-GP

N1

201

N1

202

206

N1

N1

207

203

N1

205

N1

D6

V_VREF_S0

0

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

R

12

28

R

12

65

C

12

8
7
6

4

4

4

4

8
7
6

12

C

12

M_VREF_CNTA

V

12

50

C

SCD022U16V2KX-3DLGP

2 1

V_

VREF_PATH1

+

12

12

25

R

24D9R2F-L-GP

DR

_CA_VREF

D

51

12

C

SCD022U16V2KX-3DLGP

2 1

V_

VREF_PATH3

+

12

29

12

R

24D9R2F-L-GP

20180912 For layout

20180912 For layout

66

_A

M

_A

M

_A

M

_A

M

_A_CS#0

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A_B4

M

_A

M

_A

M

_A

M

_A

M

_A

M

_A

M

_CLK0
_CLK#0
_CLK1
_CLK#1

_CS#1
_ODT0

_CKE0
_CKE1
_CKE2
_CKE3

_A2
_A3
_A1
_A0

_A7
_A6

_A5
_A4

_A9
_A8

_B1
_B0

_B5

_B2
_B3

_B9
_B8
_B6
_B7

V_S3

D2
1

12

56

C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

V_S3

D2
1

1245

C

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

D2

V_S3

1

31

12
C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

D2V_S3
1

VDDCA 10uF(0603) x1

12

11

12

C

SC10U6D3V3MX-DL-GP

D2

V_S3

1

12

18
C

12

DY

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

V_S3

D2
1

09

12
C

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

V_S3

D8
1

12

76

C

12

V_S3

D8
1

01

12
C

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

2

VDDQ 1uF(0402) x8

12

12

12

12

57

58

C

12

VDDQ 10uF(0603) x3

C

12

59

C

C

C

12

12

12

1249

1248

C

12

VDDCA 1uF(0402) x4

42

44

75

12

12

12

C

C

C

12

12

12

VDD2 1uF(0402) x6

12

12

12

20

C

12

47

12
C

12

12

78

C

12

53

12
C

12

12

21

C

C

12

12

DY

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

12

79

C

12

2

19

C

12

VDD2 10uF(0603) x3

10

12

C

12

VDD1 1uF(0402) x4

12

77

C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

VDD1 10uF(0603) x3

52

12

C

12

12

60

61

C

12

DY

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

12

26

27

C

12

DY

1

12

12

63

62

C

C

12

12

DY

DY

<Core Design>

<Core Design>

<Core Design>

W

W

W

tron Corporation

tron Corporation

tron Corporation

is

is

is

88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

88, Sec.1, Hsin Tai Wu Rd ., Hsichih,

1F,

1F,

1F,

2

2

2

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PD

PD

PD

DR3-CHA

DR3-CHA

DR3-CHA

Taipei Hsien 221, Taiwan, R.O.C.

W

W

W

AS

P 13" WHL-U

AS

P 13" WHL-U

AS

P 13" WHL-U

1

12 1

12 1

12 1

f

f

f

o

o

o

00

00

00

A

A

A

06

06

06

it

le

Title

Title

T

L

L

L

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

2

2

2

A

A

A

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019
Date: Sheet

Date: Sheet

Date: Sheet

Main Func = MEMORY

5

B_DQS_DN[7:0]5

_

M

B_DQS_DP[7:0]5

_

M

D D

_

M

_

M

_B_DQ25

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_B_DQ215

M

_

M

_

M

_

M

_

M

_

M

_

M

_B_DQ285

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

C C

B B

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

M
M
M
M
M
M
M
M
M
M

M
M
M
M
M
M
M
M
M
M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_B_CS#15

M

_

SM_VREF_CNTB5

V

_

M

A

C

_

B_DQS_DN0

M

_

B_DQS_DN1

M

_

B_DQS_DN2

M

B_DQS_DN3

_

M

_

B_DQS_DN4

M

_

B_DQS_DN5

M

B_DQS_DN6

_

M

_

B_DQS_DN7

M

_

B_DQS_DP0

M

_

B_DQS_DP1

M

_

B_DQS_DP2

M

_

B_DQS_DP3

M

B_DQS_DP4

_

M

B_DQS_DP5

_

M

_

B_DQS_DP6

M

_

B_DQS_DP7

M

B_DQ05
B_DQ15

B_DQ35
B_DQ45
B_DQ55
B_DQ65
B_DQ75
B_DQ85
B_DQ95
B_DQ105
B_DQ115
B_DQ125
B_DQ135
B_DQ145
B_DQ155
B_DQ165
B_DQ175
B_DQ185
B_DQ195
B_DQ205

B_DQ225
B_DQ235
B_DQ245
B_DQ255
B_DQ265
B_DQ275

B_DQ295
B_DQ305
B_DQ315
B_DQ325
B_DQ335
B_DQ345
B_DQ355
B_DQ365
B_DQ375
B_DQ385
B_DQ395
B_DQ405
B_DQ415
B_DQ425
B_DQ435
B_DQ445
B_DQ455
B_DQ465
B_DQ475
B_DQ485
B_DQ495
B_DQ505
B_DQ515
B_DQ525
B_DQ535
B_DQ545
B_DQ555
B_DQ565
B_DQ575
B_DQ585
B_DQ595
B_DQ605
B_DQ615
B_DQ625
B_DQ635

_

B_A05
B_A15

_

B_A25

_
_

B_A35
B_A45

_
_B_A55
_

B_A65
B_A75

_
_B_A85
_

B_A95

_

B_B05

_

B_B15

_

B_B25

_

B_B35
B_B45

_
_

B_B55
B_B65

_
_

B_B75
B_B85

_

B_B95

_

B_CLK05
B_CLK#05

B_CLK15
B_CLK#15

B_CKE05
B_CKE15
B_CKE25
B_CKE35

B_CS#05

B_ODT05

_VREF12

8V_S3

D

1

A3
U3
A4
U4
A5
U5
A6
U6

A10

D

2V_S3

U10

1

D4
P4
D5
G5
H5
J5
K5
L5
P5
D6
H6
J6
K6
P6
A8
U8
A9

U9
H12
K12

F2

G2

L2

M2

H3

E8

H8

K8

N8

H9

J9

J10
A11
H11
K11
U11
C12
E12
G12
L12
N12
R12

8V_S3

D

1

A3
U3
A4
U4
A5
U5
A6
U6

A10

D

2V_S3

U10

1

D4
P4
D5
G5
H5
J5
K5
L5
P5
D6
H6
J6
K6
P6
A8
U8
A9

U9
H12
K12

F2

G2

L2

M2

H3

E8

H8

K8

N8

H9

J9

J10
A11
H11
K11
U11
C12
E12
G12
L12
N12
R12

OF 2

AM3A

1

R

D

D1

V

D1

D

V

D1

D

V

D

D1

V

D

D1

V

D

D1

V

D

D1

V

D1

D

V

D

D1

V

D1

D

V

D2

D

V

D2

D

V

D2

D

V

D2

D

V

D

D2

V

D2

D

V

DD2

V

D

D2

V

D2

D

V

DD2

V

D

D2

V

D2

D

V

D

D2

V

D

D2

V

D

D2

V

D

D2

V

D2

D

V

D

D2

V

D2

D

V

D

D2

V

DCA

D

V

DCA

D

V

DCA

D

V

D

DCA

V

DCA

D

V

DQ

D

V

DQ

D

V

D

DQ

V

D

DQ

V

DQ

D

V

D

DQ

V

D

DQ

V

DQ

D

V

D

DQ

V

DQ

D

V

D

DQ

V

D

DQ

V

DQ

D

V

D

DQ

V

D

DQ

V

DQ

D

V

DQ

D

V

K4E6E304EE-EGCF-GP-COLAY-U1

ZZ.00PAD.JX1

A

M4A

R

D

D1

V

D1

D

V

D

D1

V

D1

D

V

D

D1

V

DD1

V

D

D1

V

D

D1

V

D

D1

V

D1

D

V

D

D2

V

D2

D

V

D

D2

V

D2

D

V

D2

D

V

D2

D

V

D

D2

V

D

D2

V

D2

D

V

D

D2

V

D2

D

V

D

D2

V

D2

D

V

DD2

V

D

D2

V

D2

D

V

D2

D

V

D

D2

V

D

D2

V

D2

D

V

DCA

D

V

D

DCA

V

DCA

D

V

D

DCA

V

D

DCA

V

D

DQ

V

D

DQ

V

D

DQ

V

DQ

D

V

D

DQ

V

DQ

D

V

D

DQ

V

D

DQ

V

DQ

D

V

DQ

D

V

D

DQ

V

DDQ

V

DQ

D

V

D

DQ

V

DQ

D

V

D

DQ

V

DQ

D

V

K4E6E304EE-EGCF-GP-COLAY-U1

ZZ.00PAD.JX1

B2

S

S

H2

V

S

S

K2

V

S

S

T2

V

S

S

T3

V

S

S

E4

V

S

S

N4

V

S

S

R4

V

S

S

T4

V

S

S

B5

V

S

S

C5

V

S

S

E5

V

S

S

F5

V

S

S

M5

V

S

S

N5

V

S

S

R5

V

S

S

T5

V

S

S

L6

V

SS

J12

V

S

S

V

C3

S

SCA

D3

V

SCA

S

G3

V

S

SCA

P3

V

S

SCA

F4

V

S

SCA

G4

V

S

SCA

J4

V

SCA

S

M4

V

S

SCA

V

B6

SQ

S

C6

V

SQ

S

E6

V

SQ

S

F6

V

SQ

S

G6

V

S

SQ

M6

V

SQ

S

N6

V

S

SQ

R6

V

SQ

S

T6

V

SQ

S

G9

V

S

SQ

L9

V

S

SQ

H10

V

SQ

S

K10

V

S

SQ

B12

V

S

SQ

D12

V

SQ

S

F12

V

S

SQ

M12

V

SQ

S

P12

V

S

SQ

T12

V

S

SQ

V

OF 2

1

B2

S

S

H2

V

S

S

K2

V

S

S

T2

V

S

S

T3

V

S

S

E4

V

SS

N4

V

S

S

R4

V

S

S

T4

V

S

S

B5

V

S

S

C5

V

S

S

E5

V

S

S

F5

V

S

S

M5

V

S

S

N5

V

S

S

R5

V

S

S

T5

V

S

S

L6

V

S

S

J12

V

S

S

V

C3

SCA

S

D3

V

S

SCA

G3

V

SCA

S

P3

V

SSCA

F4

V

S

SCA

G4

V

SCA

S

J4

V

SCA

S

M4

V

S

SCA

V

B6

S

SQ

C6

V

SQ

S

E6

V

S

SQ

F6

V

SQ

S

G6

V

S

SQ

M6

V

S

SQ

N6

V

S

SQ

R6

V

S

SQ

T6

V

S

SQ

V

G9

S

SQ

L9

V

SQ

S

H10

V

S

SQ

K10

V

SQ

S

B12

V

S

SQ

V

D12

S

SQ

F12

V

SQ

S

M12

V

SQ

S

V

P12

S

SQ

V

T12

SSQ

V

A

_VREF

C

VREF_CA_DIMMB

_

M

C

1

12

314

A

_VREF

C

_

VREF_CA_DIMMB

M

C

1

12

329

4

OF 2

A

M3B

2

R

_

B_CLK0

J3

K

_

B_CLK#0

_

B_CKE0

_

B_CKE1

_

B_CS#0
B_CS#1

_

_

B_A0

_

B_A1

_

B_A2
B_A3

_

B_A4

_
_

B_A5

_

B_A6
B_A7

_
_

B_A8
B_A9

_

C

1
315

_

B_CLK1
B_CLK#1

_

B_CKE2

_

B_CKE3

_

_

B_CS#0

_B_CS#1

_

B_B0
B_B1

_
_

B_B2
B_B3

_
_

B_B4
_B_B5
_

B_B6
_

B_B7
_

B_B8

B_B9

_

C

1
330

SCD047U25V2KX-4-GP

SCD047U25V2KX-4-GP

_T

J2

C

K

_C

C

K3

E0

K

K4

C

K

E1

C

L3

S

0#

L4

C

1#

S

C

R2

0

A

P2

C

1

A

N2

C

A

2

N3

C

3

A

M3

C

A4

F3

C

A

5

E3

C

6

A

E2

C

A7

D2

C

A

8

C2

C

9

A

C

L8

M

0

G8

D

M

1

P8

D

M

2

D8

D

3

M

D

H4

R

EF_CA

J11

V

EF_DQ

R

V

A1

U#A1

N

A2

D

N

U#A2

A12

D

U#A12

N

A13

D

N

U#A13

B1

D

D

U#B1

N

B13

D

D

U#B13

N

T1

D

D

N

U#T1

T13

D

D

N

U#T13

U1

D

D

U#U1

N

U2
U12
U13

C4

K9

R3

J3
J2

K3

K4

L3
L4

R2

P2

N2

N3

M3

F3
E3
E2
D2
C2

L8
G8
P8
D8

H4

J11

A1
A2

A12
A13

B1

B13

T1

T13

U1
U2

U12
U13

C4
K9
R3

D

D

N

U#U2

D

D

N

U#U12

D

D

U#U13

N

D

#C4

C

N

C

#K9

N

C

#R3

N

K4E6E304EE-EGCF-GP-COLAY-U1

ZZ.00PAD.JX1

M4B

A

R

K

_T

C

K

_C

C

E0

K

C

K

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C

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S

C

S

1#

C

0

A

C

1

A

C

A

2

C

A

3

C

4

A

C

A

5

C

6

A

C

A

7

C

8

A

C

A9

C

0

M

D

1

M

D

M

2

D

M

3

D

EF_CA

R

V

R

EF_DQ

V

N

U#A1

D

N

U#A2

D

N

U#A12

D

N

U#A13

D

D

N

U#B1

D

D

U#B13

N

D

D

N

U#T1

D

D

U#T13

N

D

D

N

U#U1

D

D

N

U#U2

D

D

U#U12

N

D

D

U#U13

N

D

C#C4

N

#K9

C

N

C

#R3

N

K4E6E304EE-EGCF-GP-COLAY-U1

ZZ.00PAD.JX1

Q
Q
Q
Q
Q
Q
Q
Q

Q
Q
Q
Q
Q
Q
Q
Q

M
M

M
M

M
M

M
M
M
M
M
M
M
M
M
M

SCD047U25V2KX-4-GP

12

M
M

M
M

M
M

M
M
M
M
M
M
M
M
M
M

SCD047U25V2KX-4-GP

12

S0_T
S0_C
S1_T
S1_C
S2_T
S2_C
S3_T
S3_C

OF 2
2

S0_T
S0_C
S1_T
S1_C
S2_T
S2_C
S3_T
S3_C

_

B_DQ27

P9

Q

0

M

_

B_DQ26

N9

D

Q

1

M

B_DQ24

_

N10

D

Q

2

M

_

B_DQ30

N11

D

3

Q

M

_

B_DQ29

M8

D

Q

4

M

B_DQ28

_

M9

D

5

Q

M

_

B_DQ25

M10

D

M

Q

6

B_DQ31

_

M11

D

M

7

Q

_

B_DQ7

F11

D

M

8

Q

_

B_DQ6

F10

D

M

9

Q

_

B_DQ3

F9

D

M

10

Q

_

B_DQ5

F8

D

M

Q

11

B_DQ2

_

E11

D

M

12

Q

B_DQ1

_

E10

D

M

Q13

_

B_DQ4

E9

D

M

Q

14

_

B_DQ0

D9

D

M

15

Q

B_DQ15

_

T8

D

M

Q16

_

B_DQ13

T9

D

M

Q

17

B_DQ14

_

T10

D

M

18

Q

_

B_DQ9

T11

D

M

Q

19

B_DQ10

_

R8

D

M

Q

20

_

B_DQ12

R9

D

M

Q

21

B_DQ11

_

R10

D

M

Q

22

B_DQ8

_

R11

D

M

23

Q

B_DQ18

_

C11

D

M

Q

24

B_DQ19

_

C10

D

M

25

Q

_

B_DQ21

C9

D

M

Q

26

B_DQ16

_

C8

D

M

27

Q

_

B_DQ20

B11

D

M

28

Q

_

B_DQ22

B10

D

M

29

Q

B_DQ23

_

B9

D

M

30

Q

_

B_DQ17

B8

D

M

Q

31

D

B_DQS_DP3

_

L10

M

_

B_DQS_DN3

L11

M

_

B_DQS_DP0

G10

M

B_DQS_DN0

_

G11

M

_

B_DQS_DP1

P10

M

B_DQS_DN1

_

P11

M

_

B_DQS_DP2

D10

M

B_DQS_DN2

_

D11

M

A

M3_ZQ0

B3

R

Q

0

A

M3_ZQ1

B4

Z

R

1

Q

Z

B_ODT0

_

J8

M

D

T

O

_

B_DQ63

P9

M

Q

0

B_DQ61

_

N9

D

M

Q

1

_

B_DQ62

N10

D

M

Q

2

B_DQ58

_

N11

D

M

3

Q

B_DQ60

_

M8

D

M

Q

4

B_DQ57

_

M9

D

M

Q

5

_

B_DQ56

M10

D

M

6

Q

_B_DQ59

M11

D

M

Q

7

F11

D

8

Q

F10

D

9

Q

F9

D

10

Q

F8

D

Q

11

E11

D

Q

12

E10

D

13

Q

E9

D

Q

14

D9

D

15

Q

_

B_DQ44

T8

D

M

Q

16

_

B_DQ41

T9

D

M

17

Q

B_DQ46

_

T10

D

M

Q18

B_DQ42

_

T11

D

M

Q

19

_

B_DQ40

R8

D

M

20

Q

B_DQ45

_

R9

D

M

21

Q

_

B_DQ43

R10

D

M

Q

22

B_DQ47

_

R11

D

M

Q

23

C11

D

24

Q

C10

D

Q

25

C9

D

26

Q

C8

D

Q

27

B11

D

28

Q

B10

D

Q

29

B9

D

Q

30

B8

D

Q

31

D

_B_DQS_DP7

L10

M

_

B_DQS_DN7

L11

M

B_DQS_DP4

_

G10

M

B_DQS_DN4

_

G11

M

_

B_DQS_DP5

P10

M

_

B_DQS_DN5

P11

M

B_DQS_DP6

_

D10

M

_

B_DQS_DN6

D11

M

A

M4_ZQ0

B3

R

Q

0

M4_ZQ1

A

Z

B4

R

Q1

Z

_

B_ODT0

J8

M

D

T

O

_

M

_

M

_

M

_

M

_

M

_

M

_B_DQ32

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

_

M

B_DQ39
B_DQ38
B_DQ34
B_DQ37
B_DQ35
B_DQ36

B_DQ33

B_DQ49
B_DQ52
B_DQ51
B_DQ55
B_DQ48
B_DQ53
B_DQ54
B_DQ50

12

R

240R2F-1-GP
1
301

12

R

240R2F-1-GP
1
303

3

D

2V_S3

1

12

320

1

R

8K2R2F-1-GP

323

1

_

_

VREF_CA_DIMMB

M

12

1

321

R

8K2R2F-1-GP

6V_VREF_S0

D

0

341 38D3R2F-GP

1

1 2

R

1

310 38D3R2F-GP

1 2

R

311 38D3R2F-GP

1

1 2

R

1

312 38D3R2F-GP

1 2

R

1

313 80D6R2F-L-GP

1 2

R

314 80D6R2F-L-GP

1

1 2

R

315 80D6R2F-L-GP

1

1 2

R

1

316 80D6R2F-L-GP

1 2

R

1

317 80D6R2F-L-GP

1 2

R

318 80D6R2F-L-GP

1

1 2

R

1

319 80D6R2F-L-GP

1 2

R

N1301

R

12

R

240R2F-1-GP
1
302

12

R

240R2F-1-GP
1
304

1
2
3
4 5

SRN68J-3-GP

1302

N

R

1
2 3

SRN68J-5-GP

1

305 68R2-GP

1 2

R

306 68R2-GP

1

1 2

R

N

1306

R

1
2 3

SRN68J-5-GP

N

1307

R

1
2 3

SRN68J-5-GP

N

1303

R

1
2 3

SRN68J-5-GP

308 68R2-GP

1

1 2

R

1

307 68R2-GP

1 2

R

1304

N

R

1
2 3

SRN68J-5-GP

N

1308

R

1
2 3

SRN68J-5-GP

R

1 2

10R2F-L1-GP

8
7
6

4

4

4

4

4

4

SM_VREF_CNTB

V

1

339

C

SCD022U16V2KX-3DLGP

2 1

V

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+

12

1

322

R

24D9R2F-L-GP

_

B_CLK0

M

B_CLK#0

_

M

_

B_CLK1

M

_

B_CLK#1

M

_

B_CS#0

M

B_CS#1

_

M

_

B_ODT0

M

_

B_CKE0

M

B_CKE1

_

M

_

B_CKE2

M

B_CKE3

_

M

B_A2

_

M

B_A3

_

M

_

B_A1

M

B_A0

_

M

_

B_A6

M

B_A7

_

M

B_A5

_

M

_

B_A4

M

20180912 For layout

B_A9

_

M

B_A8

_

M

B_B1

_

M

B_B0

_

M

B_B4

_

M

_

B_B3

M

_

B_B2

M

_

B_B5

M

20180912 For
layout

B_B9

_

M

_

B_B8

M

_

B_B6

M

B_B7

_

M

D

2V_S3

1

341

1

C

12

DY

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

2V_S3

D
1

VDDQ 10uF(0603) x2

1

350

C

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

D2V_S3
1

VDD2 1uF(0402) x6

323

1

C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

D

2V_S3

1

VDD2 10uF(0603) x2

333

1

C

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

D

2V_S3

1

VDDCA 1uF(0402) x4

1

310

C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

D

8V_S3

1

VDD1 1uF(0402) x4 VDD1 10uF(0603) x2

304

1

C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
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6V_VREF_S0

D
0

VTT 1uF(0402) x4 VTT 10uF(0603)x2

367

1
C

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

2

VDDQ 1uF(0402) x8

342

344

343

1
C

12

325

1
C

12

1

312

C

12

348

1
C

12

369

1
C

12

DY

352

1

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C

12

12

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SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

331

326

1

1

C

C

12

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

1

313

C

12

349

1

C

12

370

1

C

12

DY

1
C

12

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1

351

C

12

324

1
C

12

334

1
C

12

1

311

C

12

317

1
C

12

368

1

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12

355

353

354

1

1

1

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C

C

12

12

12

DY

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332

1
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12

322

1

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SC10U6D3V3MX-DL-GP

D

8V_S3

1

356

338

1

1

C

C

12

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

6V_VREF_S0

D
0

372

371

1

1

C

C

12

12

SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP

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A A

<Core Design>

<Core Design>

<Core Design>

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F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

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Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

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Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019
Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

0

0

0

5

WWW.AliSaler.Com

D D

C C

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(Blanking)

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<Core Design>

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Title

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4

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Date: Sheet

Date: Sheet

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Date: Sheet

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W

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, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

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06Thursday, March 07, 2019

Main Func = PCH

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KR19,27

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U_SMB_ALERT#_P018

P

S

I_SI_CPU18,25,91

P

S

P

I_WP_CPU18,25

S

P

I_HOLD_CPU18,25

H

D

A_SDOUT_CPU19

C

V_RGI_DT20,61

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C

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D D

U_SMB_ALERT#18

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P_B22_GSPI1_MOSI20

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C

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I
N

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P

P_H2321

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R

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T

G

P_H17_STRAP4

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5

3

3

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DY

12

12

DY

12

R

DY

20KR2J-L2-GP

12

R

1

4K7R2J-L-GP

12

R

1

20KR2J-L2-GP

R

1

508

100KR2F-L3-GP

S

R

509

1

4K7R2J-L-GP

S

KR

P

1

501

504

C

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U_SMB_ALERT#_P0

505

P

I_WP_CPU

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GPP_C5

SPI0_IO2

4

GPP_B18

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3

3

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3V_S5_PCH

3

D

3V_S5_PCH

DY

12

12

DY

D

3V_S5_PCH

12

R

DY

1KR2J-1-GP

12

R

DY

1KR2J-1-GP

12

R

1

20KR2J-L2-GP

12

R

519

1

10KR2J-L-GP

R

1

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100KR2F-L3-GP

S

R

511

1

4K7R2J-L-GP

502

1

503

1

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R

T

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12

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G

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P_B22_GSPI1_MOSI

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1553

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P_H17_STRAP

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527

1

1KR2J-1-GP

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100KR2F-L3-GP

S

R

507

1

1KR2J-1-GP

P

I_SI_CPU

GPP_B23

GPP_H21

GPP_F2 /
CNV_RGI_DT / UART0_TXD

1

D

8V_S5

12

DY

3

D

DY

R

20KR2J-L2-GP

C

12

R

3V_S5_PCH

12

R

12

R

515

1

C

U_SMB_ALERT#_P1

P

555

1

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1

522

4K7R2J-L-GP

523

1

20KR2J-L2-GP

V_RGI_DT

N

2

3

D

3V_S5_PCH

12

R

3

3

3V_VCCDSW

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12

DY

12

12

DY

D

3V_S5_PCH

12

DY

12

DY

R

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4K7R2J-L-GP

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20KR2J-L2-GP

R

4K7R2J-L-GP

R

4K7R2J-L-GP

1

520

4K7R2J-L-GP

1

521

4K7R2J-L-GP

GPP_C2

G

P

P_H21

551

1

C

552

1

1

513

514

1

I

U_SMB_ALERT#

P

G

P

N

PUT3VSEL

1

P_H23

(#543016)

DISPLAY PORT PRESENCE STRAP

0 : ENABLED

CFG[4]

3

D

3V_VCCDSW

12

R

524

12

DY

1

100KR2F-L3-GP

R

1

525

20KR2J-L2-GP

G

P

D_7

1

8V_VCCPRIM

D

12

GPP_R2 / HDA_SDO /

B B

I2S0_TXD / HDACPU_SDO

DY

R

1

512

4K7R2J-L-GP

H

D

A_SDOUT_CPU

An external Display Port device is connected to the Embedded Display Port.

1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.

C

G4

F

12

R

1

518

1KR2J-1-GP

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

0 : ENABLED

CFG[3]

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

1 : DISABLED

PCH strap pin:

C

F

G3

12

R

1

517

1KR2J-1-GP

DY

A A

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

u

u

u

stom

stom

stom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

C

C

C

1

W

W

W

stron Corporation

stron Corporation

stron Corporation

i

i

i

2

2

2

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

U (Strap pins)

U (Strap pins)

U (Strap pins)

P

P

P

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

A

A

A

0

0

0

0

0

0

o

o

o

15 106Thursday, March 07, 2019

15 106Thursday, March 07, 2019

15 106Thursday, March 07, 2019

f

f

f

5

WWW.AliSaler.Com

Main Func = PCH

PCIE

W

LA

N_PCIE_RX_N61

W

LA

N_PCIE_RX_P61

W

LAN_PCIE_TX_N61

W

LA

N_PCIE_TX_P61

W

N_PCIE_RX_N1166

WA

W

WA
W
W

W
W
W
W

S

SD

S

SD

S

SD_SATA_TX_N63

S

SD

S

SD

S

SD

S

SD

S

SD

S

SD

S

SD_PCIE_RX_P263

S

SD

S

SD

S

SD

S

SD

S

SD

S

SD

G
G
G
G

G
G
G
G

G
G
G
G

G
G
G
G

WA

W

A

WA

WA

WA

WA

_SATA_RX_N63
_SATA_RX_P63

_SATA_TX_P63

_PCIE_RX_N163
_PCIE_RX_P163
_PCIE_TX_N163
_PCIE_TX_P163

_PCIE_RX_N263

_PCIE_TX_N263
_PCIE_TX_P263

_PCIE_RX_N363
_PCIE_RX_P363
_PCIE_TX_N363
_PCIE_TX_P363

_PCIE_RX_N076

FX
FX

_PCIE_RX_P076
_PCIE_TX_N076

FX

_PCIE_TX_P076

FX

_PCIE_RX_N176

FX

_PCIE_RX_P176

FX

_PCIE_TX_N176

FX
FX

_PCIE_TX_P176

FX

_PCIE_RX_N276

FX

_PCIE_RX_P276
_PCIE_TX_N276

FX
FX

_PCIE_TX_P276

_PCIE_RX_P376

FX
FX

_PCIE_RX_N376
_PCIE_TX_N376

FX
FX_PCIE_TX_P376

U

SB1_USB30_RX_N66

U

SB

U

SB

U

SB

U

SB

U

SB

U

SB

U

SB

W
W

m

CA

S
M

P

W

N_PCIE_RX_P1166
N_PCIE_TX_N1166
N_PCIE_TX_P1166

N_PCIE_RX_N1266
N_PCIE_RX_P1266
N_PCIE_TX_N1266
N_PCIE_TX_P1266

USB3.0

1_USB30_RX_P66

1_USB30_TX_N66
1_USB30_TX_P66

4_USB30_RX_N71
4_USB30_RX_P71

4_USB30_TX_N71
4_USB30_TX_P71

USB2.0

U

4_USB20_N72

SB

U

SB

4_USB20_P72

U

SB

1_USB20_N66

U

SB

1_USB20_P66

C

CD

_USB20_N55

C

_USB20_P55

CD

B

T_USB20_N61

B

SB20_P61

T_U

F

_USB20_N92

P1

F

_USB20_P92

P1

WA

N_USB20_N66

W

N_USB20_P66

A

U

SB_OC0#66

U

SB

RD_PCIE#_SATA24

SD_DEVSLP63

2_

SSD_PEDET63

CH

_SATA_LED#64

S

D_DEVSLP66

S

_OC3#72

5

D D

C C

B B

A A

GPU

3

V_S0

D3

3

D3V_S5_PCH

2

ND_M2_SSD_PEDET#

G

FX

_PCIE_TX_N0

G

FX

_PCIE_TX_P0

G

_PCIE_TX_N1

FX

G

X

_PCIE_TX_P1

F

G

_PCIE_TX_N2

FX

G

FX

_PCIE_TX_P2

G

_PCIE_TX_N3

FX

G

_PCIE_TX_P3

FX

#543016:
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2.

(#543611)
The SATALED# signal is open-collector and
requires a weak external pull-up (8.2 k�[ to 10 k�[)
Vcc3_3.

1 2

R

16

06 10KR2J-L-GP

1 2

R

1

08 10KR2J-L-GP

6

R

601

N1

1

8

2

7

3

6

4 5

SRN10KJ-6-GP

1 2

R

01 0R2J-L-GP

16

DY

1 2

R

02 0R2J-L-GP

16

DY

1 2

R

03 113R2F-GP

16

R

16

05

1 2

0R0402-PAD

4

1 2

C

16

06 SCD22U16V2KX-DL-G P

OPS

1 2

C

6

05 SCD22U16V2KX-DL-G P

1

OPS

1 2

C

08 SCD22U16V2KX-DL-G P

16

OPS

1 2

C

16

07 SCD22U16V2KX-DL-G P

OPS

1 2

C

16

10 SCD22U16V2KX-DL-G P

OPS

1 2

C

09 SCD22U16V2KX-DL-G P

16

OPS

1 2

C

16

12 SCD22U16V2KX-DL-G P

OPS

1 2

C

16

11 SCD22U16V2KX-DL-G P

OPS

WLAN

2ND M.2

SSD

1 2

R

16

04

100R2F-L1-GP-U

P

CH

_SATA_LED#

S

IO

_EXT_SCI#

U

_OC3#

SB

U

SB

_OC2#

U

_OC1#

SB

U

SB

_OC0#

U

SB

2_ID

U

SB

2_VBUSSENSE

U

COMP

SB

m

CARD_PCIE#_SATA

F

rom EC

4

to

G

FX

_PCIE_RX_N0

G

_PCIE_RX_P0

FX

G

FX

_PCIE_TX_C_N0

G

FX

_PCIE_TX_C_P0

G

_PCIE_RX_N1

FX

G

_PCIE_RX_P1

FX

G

_PCIE_TX_C_N1

FX

G

X

_PCIE_TX_C_P1

F

G

FX

_PCIE_RX_N2

G

_PCIE_RX_P2

FX

G

_PCIE_TX_C_N2

FX

G

FX

_PCIE_TX_C_P2

G

FX

_PCIE_RX_N3

G

FX

_PCIE_RX_P3

G

_PCIE_TX_C_N3

FX

G

_PCIE_TX_C_P3

FX

W

LA

N_PCIE_RX_N

W

LA

N_PCIE_RX_P

W

N_PCIE_TX_N

LA

W

LA

N_PCIE_TX_P

W

WA

N_PCIE_RX_N11

W

WA

N_PCIE_RX_P11

W

A

N_PCIE_TX_N11

W

W

WA

N_PCIE_TX_P11

W

N_PCIE_RX_N12

WA

W

A

N_PCIE_RX_P12

W

W

N_PCIE_TX_N12

WA

W

N_PCIE_TX_P12

WA

S

SD

_PCIE_RX_N3

S

_PCIE_RX_P3

SD

S

_PCIE_TX_N3

SD

S

SD

_PCIE_TX_P3

S

SD_PCIE_RX_N2

S

SD

_PCIE_RX_P2

S

_PCIE_TX_N2

SD

S

SD

_PCIE_TX_P2

S

SD

_PCIE_RX_N1

S

_PCIE_RX_P1

SD

S

_PCIE_TX_N1

SD

S

SD

_PCIE_TX_P1

S

SD

_SATA_RX_N

S

SD

_SATA_RX_P

S

_SATA_TX_N

SD

S

SD

_SATA_TX_P

P

CI

E_RCOMPN

P

CI

E_RCOMPP

C

PU

1H

BW9

CI

P

BW8

CI

P

BW4

CI

P

BW3

CI

P

BU6

CI

P

BU5

CI

P

BU4

CI

P

BU3

CI

P

BT7

CI

P

BT6

CI

P

BU2

CI

P

BU1

CI

P

BU9

CI

P

BU8

CI

P

BT4

CI

P

BT3

CI

P

BP5

CI

P

BP6

CI

P

BR2

CI

P

BR1

CI

P

BN6

CI

P

BN5

CI

P

BR4

CI

P

BR3

CI

P

BN10

CI

P

BN8

CIE11_RXP/SATA0_RXP

P

BN4

CI

P

BN3

CI

P

BL6

CI

P

BL5

CI

P

BN2

CI

P

BN1

CI

P

BK6

CI

P

BK5

CI

P

BM4

CI

P

BM3

CI

P

BJ6

CI

P

BJ5

CI

P

BL2

CI

P

BL1

CI

P

BG5

CIE15_RXN/SATA1B_RXN

P

BG6

CI

P

BL4

CI

P

BL3

CI

P

BE5

CI

P

BE6

CI

P

BJ4

CI

P

BJ3

CI

P

CE6

CI

P

CE5

CI

P

CR28

PP

G

CP28

PP

G

CN28

PP

G

CM28

PP

G

WHISKEY -LAKE-GP

ZZ.00CPU.271

3

E5_RXN/USB31_5_RXN
E5_RXP/USB31_5_RXP
E5_TXN/USB31_5_TXN
E5_TXP/USB31_5_TXP

E6_RXN/USB31_6_RXN
E6_RXP/USB31_6_RXP
E6_TXN/USB31_6_TXN
E6_TXP/USB31_6_TXP

E7_RXN
E7_RXP
E7_TXN
E7_TXP

E8_RXN
E8_RXP
E8_TXN
E8_TXP

E9_RXN
E9_RXP
E9_TXN
E9_TXP

E10_RXN
E10_RXP
E10_TXN
E10_TXP

E11_RXN/SATA0_RXN

E11_TXN/SATA0_TXN
E11_TXP/SATA0_TXP

E12_RXN/SATA1A_RXN
E12_RXP/SATA1A_RXP
E12_TXN/SATA1A_TXN
E12_TXP/SATA1A_TXP

E13_RXN
E13_RXP
E13_TXN
E13_TXP

E14_RXN
E14_RXP
E14_TXN
E14_TXP

E15_RXP/SATA1B_RXP
E15_TXN/SATA1B_TXN
E15_TXP/SATA1B_TXP

E16_RXN/SATA2_RXN
E16_RXP/SATA2_RXP
E16_TXN/SATA2_TXN
E16_TXP/SATA2_TXP

E_RCOMP_N
E_RCOMP_P

_H12/M2_SKT2_CFG0
_H13/M2_SKT2_CFG1
_H14/M2_SKT2_CFG2
_H15/M2_SKT2_CFG3

3

CI

E1_RXN/USB31_1_RXN

P

CI

E1_RXP/USB31_1_RXP

P

E1_TXN/USB31_1_TXN

CI

P

E1_TXP/USB31_1_TXP

CI

P

E2_RXN/USB31_2_RXN/SSIC_1_RXN

CI

P

CI

E2_RXP/USB31_2_RXP/SSIC_1_RXP

P

E2_TXN/USB31_2_TXN/SSIC_1_TXN

CI

P

E2_TXP/USB31_2_TXP/SSIC_1_TXP

CI

P

CI

E3_RXN/USB31_3_RXN

P

CI

E3_RXP/USB31_3_RXP

P

E3_TXN/USB31_3_TXN

CI

P

E3_TXP/USB31_3_TXP

CI

P

CI

E4_RXN/USB31_4_RXN

P

E4_RXP/USB31_4_RXP

CI

P

E4_TXN/USB31_4_TXN

CI

P

E4_TXP/USB31_4_TXP

CI

P

U

SB

_VBUSSENSE

PP

G

PP

G

U

_E9/USB2_OC0#/GP_BSSB_CLK

_E10/USB2_OC1#/GP_BSSB_DI

PP

_E11/USB2_OC2#

G

_E12/USB2_OC3#

PP

G

_E4/DEVSLP0

PP

G

_E5/DEVSLP1

PP

G

PP

_E6/DEVSLP2

G

PP

_E0/SATAXPCIE0/SATAGP0

G

_E1/SATAXPCIE1/SATAGP1

PP

G

PP

_E2/SATAXPCIE2/SATAGP2

G

PP

_E8/SATALED#/SPI1_CS1#

G

8

O

F 20

2N_1

SB

U

SB

2P_1

U

2N_2

SB

U

SB

2P_2

U

2N_3

SB

U

2P_3

SB

U

SB

2N_4

U

2P_4

SB

U

SB

2N_5

U

SB

2P_5

U

SB

2N_6

U

2P_6

SB

U

SB

2N_7

U

SB

2P_7

U

2N_8

SB

U

SB

2P_8

U

2N_9

SB

U

2P_9

SB

U

SB

2N_10

U

SB

2P_10

U

SB2_COMP

SB

U

SV

D#AR3

R

2

CB5

U

SB

1_USB30_RX_N

CB6

U

1_USB30_RX_P

SB

CA4

U

SB

1_USB30_TX_N

CA3

U

SB

1_USB30_TX_P

BY8
BY9
CA2

(#545659)

CA1

The xHCI controller supports USB Debug port
on all USB3.0 capable ports.

BY7
BY6
BY4
BY3

BW6

U

SB

4_USB30_RX_N

BW5

U

SB

4_USB30_RX_P

BW2

U

4_USB30_TX_N

SB

BW1

U

4_USB30_TX_P

SB

CE3

U

SB

1_USB20_N

CE4

U

1_USB20_P

SB

CE1
CE2

CG3
CG4

CD3

U

SB

4_USB20_N

CD4

U

SB

4_USB20_P

CG5

F

1

_USB20_N

P

CG6

F

P1

_USB20_P

CC1

C

_USB20_N

CD

CC2

C

D

_USB20_P

C

CG8
CG9

CB8
CB9

W

CH5

WA

N_USB20_N

W

CH6

WAN_U SB20_P

B

CC3

SB20_N

T_U

B

CC4

T_U

SB20_P

CC5

U

SB

COMP

U

CE8

2_ID

SB

_ID

U

CC6

2_VBUSSENSE

SB

U

CK6

_OC0#

SB

U

CK5

SB

_OC1#

U

CK8

SB

_OC2#

U

CK9

_OC3#

SB

S

CP8

O

_EXT_SCI#

I

W

CR8

SS

D_DEVSLP

S

CM8

SD

_DEVSLP

CN8

2

CM10

_M2_SSD_PEDET#

ND
M

CP10

SSD_PEDET

2_

P

CN7

_SATA_LED#

CH

AR3

IO board USB3.1

USB3.1 Type C

USB3.1 Type C

Fingerprint Reader

CAMERA

1

Layout Note:

1. Trace Width: 4 mils min (breakout) 12-15 mils (trace)
Note: Must maintain low DC resistance routing (<0.1 ohm).

2. Isolation Spacing: At least 12 mils to any adjacent
high speed I/O.

(#543016)
Unused SATAGP[2:0]/GPP_E[2:0] pins
must be terminated to either 3.3 V rail or GND
using 8.2 K�[ to 10 K�[ on the motherboard.
Do not use both pull-up and pull-down.
Either pull-up or pull-down is acceptable.

(

#571021_CFLU) When used as DEVSLP, no external pull-up or pull-down

termination required from SATA Host DEVSLP.

<Core Design>

<Core Design>

<Core Design>

is

is

is

tron Corporation

tron Corporation

tron Corporation

W

W

W

2

2

2

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

1F

1F

1F

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PU

PU

PU

_(PCIE/SATA/USB)

_(PCIE/SATA/USB)

_(PCIE/SATA/USB)

C

C

C

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

AS

AS

AS

W

W

W

16 1

16 1

16 1

1

00

00

00

A

A

A

o

o

o

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

f

f

f

5

D

8V_VCCPRIM

Main Func = PCH

Y

S_PWROK24

S

E

SET_OUT#24,26

R

C

CST_PWRGD24,40,46

D D

0180905

2
EMC add

C C

B B

20180918
EMC Modify

V

C

H_RSMRST#24,64

P

_5V_PWRGD25,45

V

3

_SLP_S0#40,91

M

P

M

_SLP_S3#40

P

_SLP_S4#40,51,92

M

P

O_PWRBTN#24

I

S

C

_IN#44

A

N

PUT3VSEL15

I

L

TRST#_CPU61,63,66,76,91

P

_

CPUPWRGD3

H

S
Y
S_PWROK

12

P
L
TRST#_CPU

AZ5725-01FDR7G-GP

E

12

D
1701

R
E
SET_OUT#

AZ5725-01FDR7G-GP

E

12

D
1702

DY

DY

P
M

_RSMRST#

12

V
C
CST_PWRGD_R

AZ5725-01FDR7G-GP

E

12

D
1706

DY

3
V
_5V_PWRGD

TVL5VB1-DFN1006-2L-GP

E
D
1703

TVL5VB1-DFN1006-2L-GP

E

12

D
1704

DY

C

CST_PWRGD

V

AZ5725-01FDR7G-GP

E
D
1707

#543016 Rev0.7

1. VCCST_PWRGD is only 1.0 V tolerant.

2. VCCST_PWRGD must go low during Sx pwr states,
regardless of the voltage level of VCCST

1

D

3V_VCCDSW

3

TC

_AUX_S5

R

3V_VCCPRIM

D

3

D

3V_S5

3

SACK#_R

U

S

E

SET_OUT#

R

_RSMRST#

M

P

716

1

R
100KR2F-L3-GP

1 2

1

R

1

R

1

R

1

R

1

R

1

R

4

738 10KR2J-L-GP

1 2

DY

N

1704

R

1
2 3

707 10KR2J-L-GP

1 2

#544669 (CRB): 330k.

730 330KR2J-L1-GP

1 2

731 100KR2F-L3-GP

1 2

701 10KR2J-L-GP

1 2

721 10KR2J-L-GP

1 2

717 10KR2J-L-GP

1

R

1
2 3

1

708

R
0R2J-2-GP

1 2
1 2

D3V_S0

3

12

DY

12

4

SRN10KJ-5-GP

1 2

1703

N

R

4

SRN100KJ-6-GP

1 2

DY

706 0R0402-PAD

1

R

1

704 0R0402-PAD

R

718

1

R

100KR2F-L3-GP

C

CST_PWRGD_R

V

719

1

R

47KR2F-GP

_SUS_PWR_ACK_R

E

M

12

DY

E

_SUS_PWR_ACK_R

M

C

_PRESENT

A

IE_WAKE#_CPU

C

P

N_WAKE#

A

L

M

_INTRUDER#

S

X

T_PWR_GATE#

E

D

P_DBRESET#

X

P

D11/LANPHYPC

G

Y

S_PWROK

S

_RSMRST#

M

P

M

_PCH_PWROK

P

M

_PCH_PWROK

P

H_DPWROK

C

P

711

1

C
SCD1U16V2KX-3DLGP

3

P

U1K

C

H_PLTRST#

C

P

D

P_DBRESET#

X

_RSMRST#

M

P

CPUPWRGD

_

H

CCST_PWRGD_R

V

S_PWROK

Y

S

M

_PCH_PWROK

P

H_DPWROK

C

P

_SUS_PWR_ACK_R

E

M

U

SACK#_R

S

CIE_WAKE#_CPU

P

N_WAKE#

A

L

P

D11/LANPHYPC

G

BJ35

P_B13/PLTRST#

P

G

CN10

Y

S_RESET#

S

BR36

MRST#

S

R

AR2

OCPWRGD

R

P

BJ2

C

CST_PWRGOOD

V

CR10

S_PWROK

Y

S

BP31

C

H_PWROK

P

BP30

W_PWROK

S

D

BV34

P_A13/SUSWARN#/SUSPWRDACK

P

G

BY32

P

P_A15/SUSACK#

G

BU30

A

KE#

W

BU32

D2/LAN_WAKE#

P

G

BU34

PD11/LANPHYPC

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

3V_AUX_S5

D

3

727

1

R

1 2

10KR2J-L-GP

R
1
726

V

_5V_POK#

3

100KR2J-1-GP

701

1

Q

1

S1

D1

2 5

G2

G

1

D2

S2

PJT138KA-GP

M

_RSMRST#

P

6

43

12

075.00138.0A7C

Reserve by NON DS3 function 20150413

1

702

Q

3V_AUX_S5

D

3

737

1

R

1 2

100KR2J-1-GP

M

_RSMRST#_M

P

1

2

3 4

2N7002KDW-1-GP

75.27002.F7C

713

1

TRST#_CPU

L

P

1

715

R

100KR2J-1-GP

DY

12

12

DY

R

1 2

0R0402-PAD

1

701

C
SC220P50V2KX-3DLGP

H_PLTRST#

C

P

2

1

OF 20

1

_SLP_S0#

M

BJ37

P_B12/SLP_S0#

P

G

P

D4/SLP_S3#

G

D5/SLP_S4#

P

G

P

D10/SLP_S5#

G

L

P_SUS#

S

P_LAN#

L

S

D9/SPL_WLAN#

P

G

P

D6/SLP_A#

G

P

D3/PWRBTN#

G

D1/ACPRESENT

P

G

P

D0/BATLOW#

G

TRUDER#

N

I

P

P_B11/EXT_PWR_GATE#

G

N
ote:ZZ.27002.F7C01

6

5

(PDG#543016)
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <

<Core Design>

<Core Design>

<Core Design>

P_B2/VRALERT#

P

G

702

1

R

1 2

1KR2J-1-GP

701

1

D
RB520S30-GP

83.R2003.A8M

PUT3VSEL

N

I

KA

C

H_RSMRST#

P

V

_5V_PWRGD

3

C

A

C

A

M

P

P

M

_SLP_S3#

BU36

P

_SLP_S4#

M

BU27

P

M

_SLP_S5#

BT29

P

BU29
BT31

X_EN_WOWL

U

BT30

A

M

_SLP_A#

BU37

P

I

O_PWRBTN#

BU28

S

_PRESENT

C

BU35

A

C

H_BATLOW#

BV36

P

_INTRUDER#

M

BR35

S

X

T_PWR_GATE#

CC37

E

CC36

R

ALERT#

V

BT27

N

PUT3VSEL

I

ATLOW#:

B

Pull-up required even if not implemented.

3V_VCCDSW

D

3

12

R
10KR2J-L-GP

12

R
10KR2J-L-GP

DY

_IN#

_PRESENT

_RSMRST#

1

722

1

723

1

1

1
1

1

1

C

P

100 ns.

P

1710

T

P

1715

T

1706

P

T

1714

P

T

P

1708

T

H_BATLOW#

A A

Title

Title

Title

P

P

P

U_(POWER MANAGEMENT)

U_(POWER MANAGEMENT)

U_(POWER MANAGEMENT)

C

C

C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

stom

stom

stom

u

u

u

C

C

C

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

W

W

W

stron Corporation

stron Corporation

stron Corporation

i

i

i

W

W

W

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

1

1

2

2

2
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

A

A

A

17 106Thursday, March 07, 2019

17 106Thursday, March 07, 2019

17 106Thursday, March 07, 2019

1

A

A

A

0

0

0

0

0

f

f

f

o

o

o

0

Main Func = PCH

WWW.AliSaler.Com

5

1

D8

3

3

D3

3

D3

V_S0

V_VCCPRIM

1 2

R

21 10KR2J-L-GP

18

SERIRQ PH:
PDG: 8.2k
CRB: 10k

D3

V_S0

1 2

R

20 10KR2J-L-GP

18

DY

V_S5_PCH

R

N1

807

1

8

2

7

3

6

4 5

SRN2K2J-4-GP

R

N1

811

1

4

2 3

SRN2K2J-1-GP

1 2

R

18

37 150KR2J-GP

R

W

N_CLKREQ_CPU_N

LA

W

WA

N_CLKREQ_CPU_N

S

SD

_CLKREQ_CPU_N

C

_PCIE_PEG_REQ#

LK

R

TC

_AUX_S5

1

4

18

01

G
AP

-OPEN

N1

1
2
3
4 5

SRN15J-GP

1 2

33R2F-3-GP

23

R

N1

801

SRN20KJ-1-GP

12

C

18

05

SC1U10V2KX-1DLGP

E

SP

E

SP

E

SP

E

SP

E

SP

R

813

N1

1
2
3
4 5

SRN10KJ-6-GP

12

06
18

C

SC1U10V2KX-1DLGP

I_CPU_IO0_R
I_CPU_IO2_R
I_CPU_IO1_R
I_CPU_IO3_R

I_CPU_CLK_R

8
7
6

21

G

Layout: Place at the open door ar ea.

E

SP

S

IO

C

PU

C

PU

C

PU

C

PU

C

PU

C

PU

C

PU

806

R

05

18

S

RT

R

TC

I_ALERT#

_RCIN#

_SMB_SDA
_SMB_SCL
_SMB_SDA_P0
_SMB_SCL_P0

_SMB_SCL_P1
_SMB_SDA_P1

_SMB_ALERT#_P1

8
7
6

C_RST#

_RST#

E

I_IO[3..0]24,68

SP

C

PU

_SMB_ALERT#_P115

S

D D

C C

B B

A A

PI

S

PI

S

PI

S

PI

S

PI

S

PI

S

PI

C

PU

_SMB_SCL_P124,26,79

C

PU

_SMB_SDA_P124,26,79

E

SP

E

SP

E

SP

S

US

T

PM

F

FS_

C

PU

_SMB_ALERT#_P015

C

PU

_SMB_ALERT#15

P

J

3_PCIE_WAKE#61

IO

C

IN_XTAL_LCP_R61

LK

W

N_CLK_CPU_N61

LA

W

LA

N_CLK_CPU_P61

W

N_CLKREQ_CPU_N61

LA

S

SD

_CLK_CPU_N63

S

SD

_CLK_CPU_P63

S

_CLKREQ_CPU_N63

SD

G

CLK_CPU_N76

FX_

G

FX_

CLK_CPU_P76

C

_PCIE_PEG_REQ#76

LK

W

WA

N_PCIE_CLK_N66

W

WA

N_PCIE_CLK_P66

W

WA

N_CLKREQ_CPU_N66

E

I_IO3

SP

E

I_IO1

SP

E

SP

I_IO2

E

SP

I_IO0

_SI_CPU15,25,91

_HOLD_CPU15,25
_WP_CPU15,25

_SO_CPU25,91

_CLK_CPU25,91

_CS_CPU_N025

_CS_CPU_N291

I_CS#24,68
I_RESET#24,68

I_CLK24,68

_CLK24,61

_SPI_IRQ#91

INT170

JECT_ID021

RO

5

E

I_IO0

SP

E

SP

I_IO2

E

SP

I_IO1

E

SP

I_IO3

E

I_CLK

SP

GPU

WLAN

2nd SSD

SSD

4

S
S
S
S
S
S

S

T
F

P

R

CIN#:

Frequency to Avoid: 33 MHz

S
E

For eSPI

PCH strap pin:

eSPI or LPC

SML0ALERT# /
GPP_C5

This signal has a weak internal pull-down.

G

CLK_CPU_N

FX_

G

FX_

CLK_CPU_P

C

_PCIE_PEG_REQ#

LK

W

LA

N_CLK_CPU_N

W

N_CLK_CPU_P

LA

W

LA

N_CLKREQ_CPU_N

W

WA

N_PCIE_CLK_N

W

WA

N_PCIE_CLK_P

W

N_CLKREQ_CPU_N

WA

S

SD

_CLK_CPU_N

S

SD

_CLK_CPU_P

S

SD

_CLKREQ_CPU_N

4

Sampled at rising edge of RSMRST#

This signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.

CF32

CE32

CF30

CE31

CE30

CF31

X

K_BIASREF

CL

12

R

18

03

60D4R2F-GP

PI

_CLK_CPU

PI

_SO_CPU

PI

_SI_CPU

PI

_WP_CPU
_HOLD_CPU

PI

_CS_CPU_N0

PI

PI

_CS_CPU_N2

PM

_SPI_IRQ#

FS_

INT1

RO

JECT_ID0

IO

_RCIN#

SP

I_ALERT#

C

PU

AW2

LK

C

AY3

LK

C

PP

G

BC1

LK

C

BC2

LK

C

PP

G

BD3

LK

C

BC3

LK

C

PP

G

BH3

LK

C

BH4

LKOUT_PCIE_P3

C

PP

G

BA1

LK

C

BA2

LK

C

PP

G

BE1

LK

C

BE2

LK

C

PP

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

CH37
CF37
CF36
CF34
CG34
CG36
CG35
CH34

CF20
CG22
CF22
CG23
CH23
CG20

CH7
CH8
CH9

BV29
BV28

1J

OUT_PCIE_N0
OUT_PCIE_P0
_B5/SRCCLKR EQ0#

OUT_PCIE_N1
OUT_PCIE_P1
_B6/SRCCLKR EQ1#

OUT_PCIE_N2
OUT_PCIE_P2
_B7/SRCCLKR EQ2#

OUT_PCIE_N3

_B8/SRCCLKR EQ3#

OUT_PCIE_N4
OUT_PCIE_P4
_B9/SRCCLKR EQ4#

OUT_PCIE_N5
OUT_PCIE_P5
_B10/SRCCLK REQ5#

C

PU

1E

0_CLK

PI

S

PI

0_MISO

S

PI

0_MOSI

S

Strap

0_IO2

PI

S

PI

0_IO3

S

0_CS0#

PI

S

PI

0_CS1#

S

PI0_CS2#

S

PP

_D1/SPI1_CLK/BK1 /SBK1

G

_D2/SPI1_MISO_IO1/BK2/SBK2

PP

G

_D3/SPI1_MOSI_IO0/BK3/SBK3

PP

G

PP

_D21/SPI1_IO2

G

_D22/SPI1_IO3

PP

G

PP

_D0/SPI1_CS0#/BK 0/SBK0

G

CLK

L_

C

L_

DATA

C

RST#

L_

C

_A0/RCIN#/TIME_SYNC1

PP

G

PP

_A6/SERIRQ

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

LK

OUT_ITPXDP_N

C

OUT_ITPXDP_P

LK

C

PD

8/SUSCLK

G

X

CL

K_BIASREF

X

LK

C

RT

S

R

1

0

TA

X

L_OUT

TA

IN_XTAL

R
R

CRST#

TC

OF 20

TC
TC

RST#

3

5

O

F 20

CK14

C

PU

CH15
CJ15

CH14
CF15
CG15

CN15
CM15
CC34

CA29
BY29
BY27
BV27
CA28
CA27

BV32
BV30
BY30

R

18

40

1 2

33R2F-3-GP

R

18

39

1 2

33R2F-3-GP

_SMB_SCL

C

PU

_SMB_SDA

C

PU

_SMB_ALERT#

C

_SMB_SCL_P0

PU

C

_SMB_SDA_P0

PU

C

PU

_SMB_ALERT#_P0

C

_SMB_SCL_P1

PU

C

PU

_SMB_SDA_P1

C

PU

_SMB_ALERT#_P1

E

I_CPU_IO0_R

SP

E

SP

I_CPU_IO1_R

E

SP

I_CPU_IO2_R

E

I_CPU_IO3_R

SP

E

I_CS#

SP

E

I_RESET#

SP

E

SP

I_CPU_CLK_R

12

X

_24M_X2_R

TL

R

41

18

1MR2J-1-GP

X

_24M_X1_R

TL

_C0/SMBCLK

PP

G

PP

_C1/SMBDATA

G

PP

_C2/SMBALERT#

G

PP

_C3/SML0CLK

G

_C4/SML0DATA

PP

G

Strap

PP

_C5/SML0ALERT #

G

_C6/SML1CLK

PP

G

PP

_C7/SML1DATA

G

_B23/SML1ALERT #/PCHHOT#

PP

G

PP

_A1/LAD0/ESPI_IO0

G

_A2/LAD1/ESPI_IO1

PP

G

PP

_A3/LAD2/ESPI_IO2

G

_A4/LAD3/ESPI_IO3

PP

G

PP

_A5/LFRAME#/ESPI_CS#

G

PP_A14/SUS_STAT #/ESPI_RESET#

G

PP

_A9/CLKOUT_LP C0/ESPI_CLK

G

_A10/CLKOUT_L PC1

PP

G

PP

_A8/CLKRUN#

G

X

AU1

DP

X

AU2

DP

S

BT32

US

X

CK3

TL

L_IN

X

CK2

TL

X

CJ1

CL

C

CM3

LK

X

BN31

TL

X1

X

BN32

TL

X2

S

BR37

RT

R

BR34

TC

3

1

_CLK_CPU_N
_CLK_CPU_P

_CLK

_24M_X1_CPU
_24M_X2_CPU

K_BIASREF
IN_XTAL_LCP_R

_32K_X1_CPU
_32K_X2_CPU

C_RST#
_RST#

T

1

T

D

on't Change R1839,R1840 To Short Pad

For RF Immunity Requirement.

X

_24M_X2_CPU

TL

X

_24M_X1_CPU

TL

P1

808
807

P1

X

TL

X

TL

41

2

3

D3

DY

R

18

06

1 2

0R0402-PAD

_32K_X2_CPU

_32K_X1_CPU

12

C

C

18

08 SC15P50V2JN-DL-GP

X

18

XTAL-24MHZ-182-GP

082.30006.0531

2 3

C

18

07 SC15P50V2JN-DL-GP

2

V_VCCDSW

12

R

18

19

10KR2J-L-GP

J

IO

3_PCIE_WAKE#

R

15

18

1 2

10MR2J-L-GP

X

02

18

1 2

XTAL-32D768KHZ-98-GP

082.30003.0301

common part

18

04

SC15P50V2JN-DL-GP

1 2

01

1 2

1

12

C

18

03

SC15P50V2JN-DL-GP

<Core Design>

<Core Design>

<Core Design>

W

W

W

tron Corporation

tron Corporation

tron Corporation

is

is

is

2

2

2

88, Sec.1, Hsin Tai Wu Rd., Hsichih,

88, Sec.1, Hsin Tai Wu Rd., Hsichih,

88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F,

1F,

1F,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

T

it

le

Title

Title

C

C

C

(SPI/ESPI/SMBS/XTAL/CLK)

(SPI/ESPI/SMBS/XTAL/CLK)

(SPI/ESPI/SMBS/XTAL/CLK)

PU

PU

PU

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

us

us

us

tom

tom

tom

Date: Sheet

Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

W

W

W

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

AS

AS

AS

1

18 106Thursday, March 07, 2019

18 106Thursday, March 07, 2019

18 106Thursday, March 07, 2019

00

00

00

A

A

A

o

o

o

f

f

f

5

Main Func = PCH

H

D

A_SDIN0_CPU27

H

A_SYNC_CODEC27

D

H

A_BITCLK_CODEC27

D D

C C

D

H

D

A_SDOUT_CODEC27

D

M

IC_SCL_CPU55

D

IC_SDA_CPU55

M

B

T

_PCMFRM_RSTN61

B

_PCMOUT_CLKREQ061

T

K

B

_LED_BL_DET65

D

G

PU_PWROK24,85

S

P

KR15,27

M

_FWP_SW98

E

H

D

A_SDOUT_CPU15

S

D

_PWR_EN#33

S

_SDATA033

D

S

_SDATA133

D

S

D

_SDATA233

S

D

_SDATA333

S

_CLK33

D

S

_CMD33

D

S

_CD_N33

D

S

_WP33

D

T

1903

P

TPAD14-OP-GP

3

D

3V_S5

12

fTPM

12

TPM

1

4

H

D

A_SYNC_CPU

H

A_BITCLK_CPU

D

H

D

A_SDOUT_CPU

H

D

A_SDIN0_CPU

H

A_RST_N_CPU

D

K

B

_LED_BL_DET

G

P

P_H1_SFRM

G

P

P_H2_CLKREQ0

D

IC_SCL_CPU

M

D

M

IC_SDA_CPU

T

M_ID

P

D

G

PU_PWROK

S

P

KR

R

1

910

10KR2J-L-GP

T

P

M_ID

R

911

1

10KR2J-L-GP

C

U1G

P

BN34

D

H

BN37

D

H

BN36

D

H

BN35

D

H

BL36

D

H

BL35

D

H

CK23

P

G

BL37

2

S1_SFRM/SNDW2_CLK

I

BL34

2

S1_TXD/SNDW2_DATA

I

CJ32

P

G

CH32

P

G

CH29

P

G

CH30

P

G

CP24

P

G

CN24

P

G

CK25

P

G

CJ25

P

G

CF35

P

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

3

A_SYNC/I2S0_SFRM
A_BCLK/I2S0_SCLK
A_SDO/I2S0_TXD
A_SDI0/I2S0_RXD
A_SDI1/I2S1_RXD/SNDW1_DATA
A_RST#/I2S1_SCLK/SNDW1_CLK
P_D23/I2S_MCLK

P_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
P_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
P_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
P_H3/I2S2_RXD/CNV_BT_I2S_SDO

P_D19/DMIC_CLK0/SNDW4_CLK
P_D20/DMIC_DATA0/SNDW4_DATA

P_D17/DMIC_CLK1/SNDW3_CLK
P_D18/DMIC_DATA1/SNDW3_DATA

P_B14/SPKR

H

D

A_SYNC_CODEC

Layout Note:

H

D

A_BITCLK_CODEC

H

A_SDOUT_CODEC

D

M

E

_FWP_SW

P_A17/SD_VDD1_PWR_EN#/ISH_GP7

P

G

1 2

R

908 0R2J-L-GP

1

R

1920 & R1921 need to close for merge prepare

1 2

R

920 0R2J-L-GP

1

1 2

R

1

921 33R2F-3-GP

1 2

R

909 1KR2J-1-GP

1

G
G
G
G

P_A16/SD_1P8_SEL

P

G

7

OF 20

P

P_G0/SD_CMD

G
P

P_G1/SD_DATA0
P_G2/SD_DATA1

P

P_G3/SD_DATA2

P

P_G4/SD_DATA3

P

P

P_G5/SD_CD#

G

P_G6/SD_CLK

P

G

P_G7/SD_WP

P

G

D

_1P8_RCOMP

S

D

_3P3_RCOMP

S

H

H
H

2

CH36
CL35
CL36
CM35
CN35
CH35
CK36
CK34

BW36
BY31

CK33
CM34

D

A_SYNC_CPU

D

A_BITCLK_CPU
A_SDOUT_CPU

D

S

D

_CMD

S

_SDATA0

D

S

D

_SDATA1

S

D

_SDATA2

S

D

_SDATA3

S

_CD_N

D

S

D

_CLK

S

D

_WP

S

D

_PWR_EN#

S

D

_RCOMP

1 2

R

1

901

200R2F-L-GP

1

Strap pin:

B B

A A

Port B /
Port C Detected

DDPB_CTRLDATA

DDPC_CTRLDATA

Sampled at rising edge of PCH_PWROK

0 = Port B is not detected.
1 = Port B is detected.

*

0 = Port C is not detected.
1 = Port C is detected.

*

These two signals have weak internal pull-down.

5

B

_PCMFRM_RSTN

T

B

_PCMOUT_CLKREQ0

T

H

A_BITCLK_CODEC

D

4

3

1 2

R

913 33R2F-3-GP

1

1 2

R

1

912 33R2F-3-GP

12

E

C

1901

DY

SC10P50V2JN-4DLGP

2

0180904

EMC add

G

P_H1_SFRM

P

G

P_H2_CLKREQ0

P

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

P

P

P

U (HDA/I2S/SD/DMIC)

U (HDA/I2S/SD/DMIC)

U (HDA/I2S/SD/DMIC)

C

C

C

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

o

o

o

f

f

f

9 106Thursday, March 07, 2019

9 106Thursday, March 07, 2019

9 106Thursday, March 07, 2019

1

1

1

1

A

A

A

0

0

0

0

0

0

5

WWW.AliSaler.Com

4

3

2

1

Main Func = PCH

C

1F

EM

_CONFIG2

PU

CC27

PP

_B15/GSPI0_CS0#

G

CC32

_A7/PIRQA#/GSPI0_CS1#

PP

G

CE28

PP

_B16/GSPI0_CLK

G

CE27

_B17/GSPI0_MISO

PP

G

CE29

PP

_B18/GSPI0_MOSI

G

CA31

_B19/GSPI1_CS0#

PP

G

CA32

PP

_A11/PME#/GSPI1_CS1 #/SD_VDD2_PWR_ EN#

G

CC29

_B20/GSPI1_CLK

PP

G

CC30

PP

_B21/GSPI1_MISO

G

CA30

_B22/GSPI1_MOSI

PP

G

CK20

PP

_F5/CNV_BRI_RSP

G

CG19

_F6/CNV_RGI_DT

PP

G

CJ20

PP

_F4/CNV_BRI_DT

G

CH19

_F7/CNV_RGI_RSP

PP

G

CR12

_C20/UART2_ RXD

PP

G

CP12

PP

_C21/UART2_ TXD

G

CN12

_C22/UART2_ RTS#

PP

G

CM12

PP

_C23/UART2_ CTS#

G

CM11

_C16/I2C0_SDA

PP

G

CN11

PP

_C17/I2C0_SCL

G

CK12

PP

_C18/I2C1_SDA

G

CJ12

_C19/I2C1_SCL

PP

G

CF27

PP

_H4/I2C2_SDA

G

CF29

_H5/I2C2_SCL

PP

G

CH27

_H6/I2C3_SDA

PP

G

CH28

PP

_H7/I2C3_SCL

G

CJ30

_H8/I2C4_SDA

PP

G

CJ31

PP

_H9/I2C4_SCL

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

1

D8V_S5

12

R

29

20

10KR2J-L-GP

16GB

4GB/8GB

12

R

20

10KR2J-L-GP

M

EM

22

Strap

_CONFIG1

1

D8V_S5

12

R

10KR2J-L-GP

8GB

12

R

10KR2J-L-GP

4GB/16GB

11

10

01

00

11

10

01

00

1

0

18

20

20

17

PP

_D9/ISH_SPI_CS#/GSPI2_C S0#

G

_D10/ISH_SPI_CLK/GSP I2_CLK

PP

G
PP

_D11/ISH_SPI_MISO/GSPI2_MISO

G

PP_D12/ISH_SPI_MOSI/GSPI2_MOS I

G

_H10/I2C5_SDA/ISH_I2C2 _SDA

PP

G

PP

_H11/I2C5_SCL /ISH_I2C2_SCL

G

G
G

_D15/ISH_UART0 _RTS#/GSPI2_CS1#

PP

G
PP

_D16/ISH_UART0 _CTS#/SML0BALERT#

G

PP

_C12/UART1_ RXD/ISH_UART1_RXD

G

PP_C13/UART1 _TXD/ISH_UART1_TXD

G

_C14/UART1_ RTS#/ISH_UART1_RT S#

PP

G

PP

_C15/UART1_ CTS#/ISH_UART1_CT S#

G

_A12/ISH_GP6/BM_BUS Y#/SX_EXIT_HOLDOFF#

PP

G

MappingSetting

DIMM Design

Micron

Hynix

Samsung

N/A

16GB

8GB

4GB

SDP

DDP

1

D8V_S5

12

R

16

20

10KR2J-L-GP

DY

M

EM

_CONFIG0

12

R

20

15

10KR2J-L-GP

DY

C

_I2C_SDA_P155

PU

C

_I2C_SCL_P155

PU

C

PU

_I2C_SDA_P065,66

C

_I2C_SCL_P065,66

PU

U

T_2_CRXD_DTXD68

AR

U

T_2_CTXD_DRXD68

AR

C

PU

D D

C C

_I2C_SCL_ISH070

C

PU

_I2C_SDA_ISH070

C

_BRI_DT61

NV

C

NV

_RGI_RSP61

C

NV

_RGI_DT15,61

C

NV

_BRI_RSP61

G

SE

N2_INT1_C70

G

SE

N2_INT2_C70

F

FS_

INT270

T

AB

LE_MODE#24

G

_FB_EN79,86

C6

P

IR

QA#91

N

MODE#24

B_

B

RD_ID221

OA

N

RB

_BIT15

R

_DET#15,25

TC

K

B_

DET#65

G

PU

_EVENT#79

D

U_HOLD_RST#76

GP

D

U_PWR_EN86

GP

S

IO

_EXT_WAKE#24

G

_B22_GSPI1_MOSI15

PP

D

_PANEL_EN55

BC

W

WA

N_GPO_PEREST#66

W

WA

M_CARD_PWR_OFF#66

L

_CL_SIO#24,64,67,92

ID

CY19 Board ID Mapping table

ID

B B

Board ID[2:1]

B

OA

RD_ID2

3

D3

V_S0

R

48 51KR2J-1-GP

20

R

20

49 51KR2J-1-GP

R

20

43 10KR2J-L-GP

R

2053 10KR2J-L-GP

R

20

44 10KR2J-L-GP

R

20

45 10KR2J-L-GP

R

46 10KR2J-L-GP

20

3

D3

V_S5_PCH

R

41 10KR2J-L-GP

20

R

20

42 10KR2J-L-GP

R

02 10KR2J-L-GP

20

M

_CHA_EN

EM

Description

Board SKU ID

B

OA

R

20

08

10KR2J-L-GP

RD_ID1

12

1 2

DEBUG

1 2

DEBUG

1 2

DY

1 2

DY

1 2
1 2
1 2

1 2

1 2

R

N2

009

1
2 3

OPS

SRN10KJ-5-GP

1 2

P

ull high to enable DDR

1

V_S5

D8

12

R

20

31

10KR2J-L-GP

12

R

20

30

10KR2J-L-GP

DY

3

D3

V_S0

12

R
10KR2J-L-GP

DY

12

R
10KR2J-L-GP

G

PU

_EVENT_MCP#

P

IR

QA#

G

_FB_EN_MCP

C6

V

M_ID1

RA

N

RB

_BIT

D

_PANEL_EN

BC

G

PP

_B22_GSPI1_MOSI

C

_BRI_RSP

NV

C

NV

_RGI_DT

C

NV

_BRI_DT

C

_RGI_RSP

NV

U

AR

T_2_CRXD_DTXD

U

AR

T_2_CTXD_DRXD

S

_EXT_WAKE#

IO

K

DET#

B_

C

PU

_I2C_SDA_P0

C

TPAD

PU

C

PU

C

PU

M

EM

M

EM

M

EM

M

EM

M

EM

M

EM

_I2C_SCL_P0

_I2C_SDA_P1
_I2C_SCL_P1

_CONFIG0
_CONFIG1

_CONFIG2
_CONFIG3

_CONFIG4
_CHA_EN

CY19 MEM_CONFIG Mapping table

Description

On-board memory configuration

for chip vendor

On-board memory configuration

for total memory size per channel

U

AR

T_2_CRXD_DTXD

U

AR

T_2_CTXD_DRXD

D

BC

_PANEL_EN

P

QA#

IR

F

INT2

FS_

K

DET#

B_

I

R_

CAM_DET#

S

IO

_EXT_WAKE#

L

ID

_CL_SIO_TAB#

G

PU

G

_FB_EN

C6

1 2

R

_EVENT#

20

03 0R0402-PAD

1 2

R

20

04 0R0402-PAD

RO13_WHLU_20180205
CNV_RGI_DT
CNV_BRI_DT
PDG 0.7 P393 request series 75 ohm

Touch panel

D

4

GP

U_HOLD_RST#

D

GP

U_PWR_EN

N

MODE#

B_

1

V_S5

D8

12

R

20

33

10KR2J-L-GP

M

_CHB_EN

EM

12

R

20

32

10KR2J-L-GP

DY

ID

MEM_CONFIG[4:3]

MEM_CONFIG[2:1]

MappingSetting

11

10

01

00

10

20

20

09

KBL-U

KBL-R

N/A

SKL-U

MEM_CONFIG[0]

1

D8V_S5

12

R

20

10KR2J-L-GP

Micron

M

EM

_CONFIG4

12

R

20

10KR2J-L-GP

Samsung/Hynix

13

M

14

SDP/DDP Configuration

1

D8V_S5

12

R

11

20

10KR2J-L-GP

Hynix

EM

_CONFIG3

12

R

20

12

10KR2J-L-GP

Samsung/Micron

M

6

O

PP

_D5/ISH_I2C0_SDA

G

_D6/ISH_I2C0_SCL

PP

G

_D7/ISH_I2C1_SDA

PP

G

_D8/ISH_I2C1_SCL

PP

G

PP

_D13/ISH_UART0 _RXD

PP_D14/ISH_UART 0_TXD

PP

_A18/ISH_GP0

G

_A19/ISH_GP1

PP

G

_A20/ISH_GP2

PP

G

PP

_A21/ISH_GP3

G

_A22/ISH_GP4

PP

G

PP

_A23/ISH_GP5

G

F 20

CN22

W

M_CARD_PWR_OFF#

WA

CR22

D

U_HOLD_RST#

GP

CM22

I

R_

CAM_DET#

CP22

CK22
CH20

CH22
CJ22

CJ27
CJ29

CM24
CN23
CM23
CR24

CG12
CH12
CF12
CG14

BW35
BW34
CA37
CA36
CA35
CA34
BW37

R

TC

_DET#

C

PU

_I2C_SDA_ISH0

C

PU

_I2C_SCL_ISH0

W

WA

N_GPO_PEREST#

M

EM

_CHB_EN

D

U_PWR_EN

GP

V

M_ID2

RA

B

RD_ID1

OA

F

FS_

INT2

G

SE

N2_INT1_ISH

G

SE

N2_INT2_ISH

I

SH

_TABLE_MODE#

L

ID

_CL_SIO#

L

ID

_CL_SIO_TAB#

2

0180904 Follow CY19

KBLR:GPP_F10~F11: 1.8V only
CFLU:GPP_H10~H11: ?V

(

to the same voltage rail as the device/end point.

(PDG#543016) If the UART/GPIO functionality is also
the signals can be left as no-connect.

R

20

R

20

R

20

C

PU

_I2C_SDA_ISH0

C

_I2C_SCL_ISH0

PU

PDG#543016) Ensure that all I2C interface on-board terminations are pulled up

1 2

25 0R0402-PAD

1 2

26 0R0402-PAD

1 2

27 0R0402-PAD

G

SE

G

SE

T

AB

N2_INT1_C
N2_INT2_C
LE_MODE#

1
2 3

R

007

N2

SRN1KJ-7-GP

not used,

3

D3

V_S0

4

CY19 VRAM ID Mapping table

DescriptionID

dGPU VRAM sizeVRAM_ID[2:1]

3

V_S0

D3

12

R

10KR2J-L-GP

UMA

V

M_ID2

RA

12

R

10KR2J-L-GP

2GB VRAM/4GB VRAM

11

10

01

00

3

20

38

V

M_ID1

RA

37

20

MappingSetting

UMA Board

N/A

DIS Board with 4GB VRAM

DIS Board with 2GB VRAM

V_S0

D3

12

R

20

35

10KR2J-L-GP

4GB VRAM/UMA

12

R

34

20

10KR2J-L-GP

2GB VRAM

A A

<Core Design>

<Core Design>

<Core Design>

W

W

W

tron Corporation

tron Corporation

tron Corporation

is

is

is

2

2

2

88, Sec.1, Hsin Tai Wu Rd., Hsichih,

88, Sec.1, Hsin Tai Wu Rd., Hsichih,

88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F,

1F,

1F,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

us

us

us

tom

tom

tom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

C

C

C

PU

PU

PU

_(LPSS/ISH)

_(LPSS/ISH)

_(LPSS/ISH)

W

W

W

Taipei Hsien 221, Taiwan, R.O.C.

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

AS

AS

AS

1

00

00

00

A

A

A

o

o

o

f

f

f

20 106Thursday, March 07, 2019

20 106Thursday, March 07, 2019

20 106Thursday, March 07, 2019

5

4

3

2

1

Main Func = PCH

3

D

G

D_715

P

G

P_H2115

P

G

P_H2315

D D

G

T

C C

P

P

OJECT_ID018

R

B

ARD_ID220

O

P

PC_H18_VCCIO_LPM40

UCH_DETECT55

O

C

N

V_WR_CLK_DP21,61

C

V_WR_CLK_DN21,61

N

C

V_WR_CLK_DP21,61

N

C

N

V_WR_CLK_DN21,61

C

N

V_WR_DP061

C

V_WR_DN061

N

C

N

V_WR_DP161

C

V_WR_DN161

N

W

I

FI_RF_EN61

B

L

UETOOTH_EN61

C

N

V_WT_CLK_DP61

C

N

V_WT_CLK_DN61

C

V_WT_DP061

N

C

N

V_WT_DN061

C

V_WT_DP161

N

C

V_WT_DN161

N

W

AN_BB_RST#66

W

3V_S0

1 2

R

110 10KR2J-L-GP

2

DY

1 2

R

101 150R2F-1-GP

2

1 2

R

108 200R2F-L-GP

2

T

O

UCH_DETECT

G

P

PC_H18_BOOTMPC

1 2

R

120 75KR2J-GP

2

DY

S

P

C

E

M

1 2

R

102

2

0R0402-PAD

1 2

R

119

2

0R0402-PAD

K_ID

V_WT_RCOMP

N

MC_RCOMP

T

O

UCH_DETECT_R

G

P

PC_H18_VCCIO_LPM

W

W

AN_BB_RST#

C

N

V_WR_DN0

C

N

V_WR_DP0

C

N

V_WR_DN1

C

N

V_WR_DP1

C

N

V_WT_DN0

C

V_WT_DP0

N

C

N

V_WT_DN1

C

V_WT_DP1

N

C

N

V_WR_CLK_DN

C

N

V_WR_CLK_DP

C

N

V_WT_CLK_DN

C

N

V_WT_CLK_DP

C

N

V_WT_RCOMP

P

OJECT_ID1

R

P

OJECT_ID2

R

S

K_ID

P

B

L

UETOOTH_EN

T

UCH_DETECT_R

O

B

ARD_ID2

O

W

W

AN_BB_RST#

PROJECT_ID[3:2]PROJECT_ID[1:0]

1

D

8V_VCCPRIM

12

R

2

B B

10KR2J-L-GP

12

R

10KR2J-L-GP

DY

111

2

112

P

OJECT_ID1

R

1

D

8V_VCCPRIM

12

DY

12

R

2

113

10KR2J-L-GP

P

OJECT_ID0

R

R

2

114

10KR2J-L-GP

1

D

8V_VCCPRIM

12

R

2

117

10KR2J-L-GP

Inspiron/Vostro

P

OJECT_ID3

R

12

R

2

118

10KR2J-L-GP

Latitude

C

P

U1I

CR30

CP30

CM30
CN30

CN32
CM32

CP33

CN33

CN31

CP31

CP34

CN34

CP32

CR32

CP20
CK19

CG17

CR14

CP14
CN14
CM14

CJ17
CH17

CF17

V_WR_D0N

N

C

V_WR_D0P

N

C

V_WR_D1N

N

C

V_WR_D1P

N

C

N

V_WT_D0N

C

V_WT_D0P

N

C

N

V_WT_D1N

C

V_WT_D1P

N

C

N

V_WR_CLKN

C

V_WR_CLKP

N

C

V_WT_CLKN

N

C

N

V_WT_CLKP

C

N

V_WT_RCOMP#CP32

C

V_WT_RCOMP#CR32

N

C

P

P_F0/CNV_PA_BLANKING

G

P

P_F1

G

P_F2

P

G

P

P_C8/UART0_RXD

G

P

P_C9/UART0_TXD

G

P

P_C10/UART0_RTS#

G

P_C11/UART0_CTS#

P

G

P

P_F8/CNV_MFUART2_RXD

G

P_F9/CNV_MFUART2_TXD

P

G

P_F23/A4WP_PRESENT

P

G

WHISKEY-LAKE-GP

ZZ.00CPU.271

1

D

8V_VCCPRIM

12

R

2

115

10KR2J-L-GP

Inspiron/Latitude

P

OJECT_ID2

R

12

R

2

116

10KR2J-L-GP

Vostro

P_H18/CPU_C10_GATE#

P

G

P_H19/TIMESYNC0

P

G

P_D4/IMGCLKOUT0/BK4/SBK4

P

G

P_H20/IMGCLKOUT1

P

G

P

P_F12/EMMC_DATA0

G

P

P_F13/EMMC_DATA1

G

P_F14/EMMC_DATA2

P

G

P

P_F15/EMMC_DATA3

G

P

P_F16/EMMC_DATA4

G

P_F17/EMMC_DATA5

P

G

P

P_F18/EMMC_DATA6

G

P

P_F19/EMMC_DATA7

G

P

P_F20/EMMC_RCLK

G

P_F21/EMMC_CLK

P

G

P

P_F11/EMMC_CMD

G

P

P_F22/EMMC_RESET#

G

ID Description

PROJECT_ID[1:0]

<Core Design>

<Core Design>

<Core Design>

G
G
G

G

M

MC_RCOMP

E

Project TypePROJECT_ID[3:2]

Project Series

9

P
P
P
P

G

OF 20

P_H21
P_H22
P_H23
P_F10

P

G

P

P_F3

CN27

G

P

PC_H18_BOOTMPC

CM27

CF25

G

P_H21

P

CN26
CM26

G

P_H23

P

CK17

BV35

G

P

D7

CN20

CG25
CH25

CR20
CM20
CN19
CM19
CN18
CR18
CP18
CM18

CM16
CP16
CR16
CN16

CK15

D_7

P

R

OJECT_ID3

W

FI_RF_EN

I

G

PP_F:

VCCPGPPF = 1.8V Only

E

MC_RCOMP

M

Setting

Mapping

Inspiron

11

Vostro

10

Latitude

01

Reseved

00

N/A

11 3000 Sereis

10

5000 Sereis

01

7000 Sereis

00

N/A

istron Corporation

istron Corporation

istron Corporation

W

W

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

P

P

P

U_(POWER1)

U_(POWER1)

U_(POWER1)

C

C

C

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

A

A

A

0

0

0

0

0

0

o

o

o

f

f

f

1 106Thursday, March 07, 2019

1 106Thursday, March 07, 2019

1 106Thursday, March 07, 2019

2

2

2

1

5

WWW.AliSaler.Com

4

3

2

1

Main Func = PCH

V

CC

V

CC

V

CC

V

A_BCLK_1P05

CC

V

CC

V

CC

V

CC

A_XTAL_1P05

V

CC

V

CC

V

CC

V

CC

V

CCDPHY_1P24

V

V

CC

V

V
V
V
V
V

V

V

_B0/CORE_VID0

PP

G

PP

_B1/CORE_VID1

G

1

6

OF 20

CC

PRIM_3P3

RTC

CC

V

PRIM_1P05

CP

RTC

D

PRIM_1P05

APLL_1P05

APLL_1P05

A_SRC_1P05

DPHY_1P24
DPHY_1P24

DPHY_1P24
DPHY_1P24

CC

DSW_3P3

A_19P2_1P05

PRIM_1P8

CC

PRIM_1P8

CC
CC

PRIM_1P8

CC

PRIM_1P8
PRIM_1P8

CC

CC

PRIM_3P3

PRIM_3P3

CC

CB16

BR23

BY20
BP24

BR20

BT12

BP14

BR14

BU12

CP5

BY24
CA24

BY23
CA23
CP25

BT23

BR12

CC18
CC19
CD18
CD19
CP23

BW23

BP23

CB36
CB35

V

0.

V

0.

85A_VID0
85A_VID1

3

D3

V_VCCPRIM

3

V_VCCPRTC

D3

1

V_S5

D0

V

1

V_S5

D0

1

D0

V_S5

1

D0

V_S5

1

D0

V_S5

1

D0

V_S5

1

D0

V_VCCA_XTAL

1

D2

4V_VCCDPHY

1

2

4V_VCCDPHY_EC

D

3

D3

V_VCCDSW

1

D0

V_S5

1

V_VCCPRIM

D8

3

3

V_VCCPRIM

D

1
1

CC

RTCEXT

12

DY

T

P2

201

T

202

P2

C

01

22

SCD1U16V2KX-3DLGP

3

V_VCCPRIM

D3

C

12

W25

AJ27

AH26

02

22

C

PU

1O

K12

SV

D#K12

R

K14

D#K14

SV

R

K15

SV

D#K15

R

K17

D#K17

SV

R

K18

D#K18

SV

R

K20

D#K20

SV

R

L25

SV

D#L25

R

M24

SV

D#M24

R

M26

D#M26

SV

R

P24

D#P24

SV

R

P26

SV

D#P26

R

R24

SV

D#R24

R

R25

D#R25

SV

R

R26

D#R26

SV

R

V24

D#V24

SV

R

SV

D#W25

R

Y24

D#Y24

SV

R

Y25

SV

D#Y25

R

G2

D#G2

SV

R

G1

D#G1

SV

R

C34

SV

D#C34

R

G3

D#G3

SV

R

G4

D#G4

SV

R

A34

D#A34

SV

R

B35

SV

D#B35

R

SV

D#AJ27

R

D#AH26

SV

R

L5

SVD#L5

R

WHISKEY -LAKE-GP

ZZ.00CPU.271

C

C

03

22

22

12

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

WHL QS/CFL U/WHL ES1_CNL U22

C

04

05

22

12

SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP

1

5

OF 20

AA24

SV

D#AA24

R
R
R
R
R
R
R
R

C

22

12

SV

SV
SV
SV
SV
SV
SV

R
R
R
R

06

SV

SV
SV
SV

R

D#AA26

D#AB25
D#AC24
D#AC25
D#AC26
D#AD24
D#AD26

D#V25
D#T25
D#A35
D#D34

D#N5

SV

12

AA26
AB25
AC24
AC25
AC26
AD24
AD26
V25
T25
A35
D34
N5

C

07

22

1

V_S5

D0

C

22

12

1

D0

R

TC_AUX_S5

C

14

12

22

12

SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP

V_S5

C

22

12

1 2

0R0603-PAD

1 2

0R0603-PAD

1 2

0R0603-PAD

1 2

0R0603-PAD

15

R

22

R

22

R

22

R

22

C

22

12

1

D0

C

17

22

12

V_VCCA_XTAL

1

V_VCCPRIM_MPHY

D0

1

V_VCCAMPHYPLL

D0

3

D3V_VCCPRTC

02

03

05

04

16

C

PU

1P

1

D0

V_S5

1

D8

3

1

D0

V_S5

12

DY

1

1

V_VCCPRIM_MPHY

D0

1

D0

V_VCCAMPHYPLL

3

1

V_VCCPRIM_MPHY

D0

V_VCCPRIM

D3

V_VCCPRIM

2.57A

C

SC1U10V2KX-1DLGP
2
2
23

V_VCCDSW

D0

V_VCCPRIM

D3

12

1

V_S5

D0

1

V_S5

D0

1

D0

V_S5

1

D0

V_S5

D D

C C

3

V_VCCDSW

D3

12

C

24

22

SC1U10V2KX-1DLGP

Layout Note:

B B

C2224 close to BR24

BP20

PRIM_1P05

CC

V

BW16

CC

PRIM_1P05

V

BW18

PRIM_1P05

CC

V

BW19

CC

PRIM_1P05

V

BY16

PRIM_1P05

CC

V

CA14

PRIM_1P05

CC

V

CC15

CC

PRIM_1P8

V

CD15

CC

PRIM_1P8

V

CD16

PRIM_1P8

CC

V

CP17

PRIM_1P8

CC

V

CB22

CC

PRIM_3P3

V

CB23

PRIM_3P3

CC

V

CC22

PRIM_3P3

CC

V

CC23

PRIM_3P3

CC

V

CD22

CC

PRIM_3P3

V

CD23

PRIM_3P3

CC

V

CP29

CC

PRIM_3P3

V

BU15

PRIM_CORE

CC

V

BU22

E

SCD1U16V2KX-3DLGP

C2
201

V

BV15

V

BV16

V

BV18

V

BV19

V

BV20

V

BV22

V

BW20

V

BW22

V

CA12

V

CA16

V

CA18

V

CA19

V

CA20

V

CB12

V

CB14

V

CB15

V

BT24

V

BU14

V

BV12

V

BW12

V

BW14

V

BY12

V

BY14

V

BV2

V

BR15

V

CC12

V

BR24

V

BT20

V

BV23

V

BT18

V

BT19

V

BU18

V

BU19

V

BT22

V

BP22

V

BV14

V

WHISKEY -LAKE-GP

ZZ.00CPU.271

CC

PRIM_CORE
PRIM_CORE

CC

PRIM_CORE

CC

PRIM_CORE

CC
CC

PRIM_CORE

CC

PRIM_CORE
PRIM_CORE

CC
CCPRIM_CORE
CC

PRIM_CORE

CC

PRIM_CORE

CC

PRIM_CORE

CC

PRIM_CORE
PRIM_CORE

CC
CC

PRIM_CORE

CC

PRIM_CORE

CC

PRIM_CORE
PRIM_CORE

CC

DSW_1P05

CC

CC

APLL_1P05

PRIM_MPHY_1P05

CC
CC

PRIM_MPHY_1P05

CC

PRIM_MPHY_1P05

CC

PRIM_MPHY_1P05
PRIM_MPHY_1P05

CC

AMPHYPLL_1P05

CC

APLL_1P05

CC

DUSB_1P05

CC

DSW_3P3

CC

HDA

CC

CC

SPI

CC

PRIM_1P05
PRIM_1P05

CC
CC

PRIM_1P05

CC

PRIM_1P05

CC

PRIM_1P05

CC

PRIM_1P05

PRIM_MPHY_1P05

CC

1

V_VCCAMPHYPLL

D0

C

SC22U6D3V3MX-1-DL-GP

22

12

08

DY

A A

5

1

V_VCCPRIM

D8

C

22

12

09

C

SC1U10V2KX-1DLGP

DY

SC1U10V2KX-1DLGP

22

12

10

4

3

V_VCCPRTC

D3

C

C

SC1U10V2KX-1DLGP

22

12

12

11

C

SC1U10V2KX-1DLGP

SCD1U16V2KX-3DLGP

22

22

12

22

21

Layout Note:

0

.1uF:
C2221 near BR23
1uF:
C2222 near BR23

3

1

V_VCCDSW

D0

12

C

22

13

SC1U10V2KX-1DLGP

1

V_VCCA_XTAL

D0

12

C

22

19

SC1U10V2KX-1DLGP

1

V_VCCPRIM_MPHY

D0

12

C

22

20

SC22U6D3V3MX-1-D L-GP

2

1

4V_VCCDPHY_EC

D2

12

C

22

18

SC4D7U6D3V3KX-DLG P

<Core Design>

<Core Design>

<Core Design>

is

is

is

tron Corporation

tron Corporation

tron Corporation

W

W

W

2

2

2

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

, 88, Sec.1, H sin Tai Wu Rd., Hsichih,

1F

1F

1F

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

T

le

Title

Title

it

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

Date: Sheet

PU

PU

PU

C

C

C

_(RSVD)

_(RSVD)

_(RSVD)

AS

AS

AS

W

W

W

Taipei Hsien 221, Taiwan, R.O.C.

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

22 1

22 1

22 1

1

00

00

00

A

A

A

o

o

o

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

f

f

f

5

4

3

2

1

Main Func = PCH

2

1

C

P

CR34

V

D D

C C

B B

BT5

V

BY5

V

CP35

V

CM37

V

CK37

V

AW1

V

CM1

V

BD6

V

AY4

V

B34

V

E35

V

A4

V

AE24

V

AE26

V

AF25

V

AG24

V

AG26

V

AH24

V

AH25

V

B2

V

B36

V

C36

V

C37

V

CN1

V

CN2

V

CN37

V

CP2

V

D1

V

A32

V

F33

V

A3

V

BJ7

V

CJ36

V

A36

V

BK10

V

CJ4

V

AB27

V

BK2

V

CK1

V

AB3

V

BK28

V

AB30

V

BK3

V

CK4

V

AB33

V

BK33

V

CK7

V

AB36

V

BK4

V

CL2

V

AB4

V

BK7

V

CM13

V

AB7

V

BL25

V

CM17

V

AC10

V

BL28

V

CM21

V

AC27

V

BL29

V

CM25

V

AC30

V

BL30

V

CM29

V

BL31

V

CM31

V

AD33

V

BL32

V

CM33

V

AD35

V

WHISKEY -LAKE-GP

ZZ.00CPU.271

U1R

OF 20

8

BL7

S

S
S

S
S

S
S

S
S

S
S

S
S

S

S

S
S

S

S

S

S

S
S

S
S

S

S

S

S

S

S

S
S

S
S

S

S

S

S

S
S

S

S

S
S

S
S

S

S

S

S

S
S

S

S

S

S

S
S

S
S

S
S

S
S

S
S

S
S

S

S

S

S

S

S

S
S

S
SS

S

S
S

S
S

S
S

S
S

S
S

S
S

S
S

S
S

S
S

S

S

S

S

S

S

S
S

S
S

S
S

S

S

S
S

S

S

S

S

S
S

S

S

S

S

S
S

S
S

S

S

S
S

S

S

S

S

S
S

S

S

S
S

S

S

S

V

AE25

S

S

V

BM33

S

S

V

CM5

S

S

V

AE27

S

S

V

BM35

S

S

V

CM9

S

S

V

AE30

S

S

V

BM36

S

S

V

CN13

S

S

V

AE7

S

S

V

BM9

S

S

V

CN17

S

S

V

AF27

S

S

V

BN30

S

S

V

CN21

S

S

V

AF3

S

S

V

BN7

S

S

V

CN25

S

S

V

AF30

S

S

V

CN29

S

S

V

AF33

S

S

V

BP15

S

S

V

AF36

S

S

V

AF4

S

S

V

CN5

S

S

V

AF7

S

S

V

BP25

S

S

V

CN9

S

S

V

AG10

S

S

V

BP3

S

S

V

CP1

S

S

V

BP32

S

S

V

CP11

S

S

V

AH27

S

S

V

BP33

S

S

V

CP13

S

S

V

AH28

S

S

V

BP4

S

S

V

CP15

SS

V

AH29

S

S

V

BP7

S

S

V

CP19

S

S

V

AH30

S

S

V

CP21

S

S

V

AH31

S

S

V

BR19

S

S

V

CP27

S

S

V

AH33

S

S

V

BR25

S

S

V

AH35

S

S

V

CP37

S

S

V

AJ25

S

S

V

BT15

S

S

V

AJ28

S

S

V

BT16

S

S

V

CP9

S

S

V

AJ7

S

S

V

CR2

S

S

V

AK3

S

S

V

CR36

S

S

V

AK33

S

S

V

D21

S

S

V

AK36

S

S

V

BT25

S

S

V

D25

S

S

V

AK4

S

S

V

BT28

S

S

V

AL28

S

S

V

BT33

S

S

V

D5

S

S

V

AL29

S

S

V

BT35

V

D6

V

AL32

V

BT36

V

D8

V

AL7

V

D9

V

AM10

V

BU11

V

E23

V

AM28

V

E27

V

AM33

V

BU23

V

E29

V

AM35

V

BU24

V

E31

V

BU25

V

E33

V

AN25

V

BU7

V

E9

V

AN28

V

BV11

V

F12

V

AN29

V

F15

V

AN30

V

F18

V

AN31

V

BV3

V

F2

V

AN7

V

BV31

V

F21

V

AN8

V

BV33

V

F24

V

BV4

V

F3

V

AP3

V

BW11

V

F4

V

AP33

V

BW15

V

G21

V

AP36

V

G27

V

AP4

V

G33

V

AR28

V

G35

V

G36

V

AT33

V

BW24

V

G9

V

AT35

V

H21

V

AT36

V

BW7

V

H27

V

AT4

V

BY11

V

AU10

V

BY15

V

H9

V

AU28

V

BY22

V

J12

V

AU29

V

J15

V

WHISKEY -LAKE-GP

ZZ.00CPU.271

U1S

BY25

S

S
S

S

S

S
S

S

S

S
S

S

S

S

S

S
S

S

S

S

S

S
S

S

S

S
S

S
S

S
S

S
S

S
SS
S

S
S

S
S

S
S

S

S

S

S

S
SS
S

S

S

S

S

S

S

S
S

S
S

S

S

S
SS
S

S
S

S

S

S
S

S

S

S
S

S
S

S
S

S

S

S

S

S
S

S
S

S
S

S

S

S
S

S
S

S
S

S

S

S
S

S

S

S
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CD12

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CD25

T7

BC8

CE33

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BD28
CE35

U7
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V26

BD35

CE7

V27
BD36
CF11

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BE10
CF14

V30
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CF19

V33
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WHISKEY -LAKE-GP

ZZ.00CPU.271

OF 20

U1T

0

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A A

5

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3

2

<Core Design>

<Core Design>

<Core Design>

i

i

i

stron Corporation

stron Corporation

stron Corporation

W

W

W

2

2

2

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

1

1

1

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

T

tle

Title

Title

i

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

P

P

P

U_(VSS)

U_(VSS)

U_(VSS)

C

C

C

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

A

A

A

W

W

W

o

o

o

3 106Thursday, March 07, 2019

3 106Thursday, March 07, 2019

3 106Thursday, March 07, 2019

2

2

2

f

f

1

f

0

0

0

0

0

0

A

A

A

Main Func = KBC

WWW.AliSaler.Com

K

[0..16]65

SO

K

0

SO

K

1

SO

K

2

SO

K

SO

3

K

SO

4

K

SO

5

K

SO

6

K

SO

7

K

SO

8

K

SO

9

K

SO

10

K

SO

11

K

12

SO

K

13

SO

K

14

SO

K

15

SO

K

16

D D

C C

B B

SO

P

EC

I_CPU3

P

RO

CHOT#_CPU3,44,46

T

P_

WAKE_KBC#3,65

L

_B

KLT_EN4

G

C6

_THM_DIS#4

m

CA

RD_PCIE#_SATA16

S

_PWRBTN#17

IO

S

_PWROK17

YS

R

ET_OUT#17,26

ES

V

CC

ST_PWRGD17,40,46

P

_RSMRST#17,64

CH

C

_SMB_SCL_P118,26,79

PU

C

_SMB_SDA_P118,26,79

PU

S

US

_CLK18,61

E

SP

I_CS#18,68

E

SP

I_RESET#18,68

E

SP

I_CLK18,68

D

GP

U_PWROK19,85

S

IO

_EXT_WAKE#20

T

AB

LE_MODE#20

N

MODE#20

B_

L

ID

_CL_SIO#20,64,67,92

V

CC

DSW_EN25

R

RST_ON25

TC

F

AN

_TACH126

F

1_PWM26

AN

N

B_

MUTE#27

B

EE

P27

A

LW

ON40

P

ID43

S_

P

BA

T_PRES#43,44

H

W_

ACAVIN_NB43,44

A

DIS43,44

C_

P

BA

T_CHG_SMBDAT43,44

P

BA

T_CHG_SMBCLK43,44

A

D_

IA44

H

ACAV_IN44,64

W_

D

GP

UHOT#44,79

P

M_PWRGD53

RI

L

_TST55

CD

P

AN

EL_BKEN55

L

_VCC_TEST_EN55

CD

P

EL_MONITOR55

AN

T

OU

CH_REPORT_SW55

S

SD

_SCP#63,66

E

C_

D_INHIB64

S

YS

_LED_MASK#_R64

M

K_SATA_LED#64

AS

C

HG

_AMBER_LED#64

B

AT

T_WHITE_LED#64

K

_PWRBTN#64,92

BC

P

_DIS#65

TP

C

AP

_LED#_R65

K

LED_PWM65

B_

C

_TP_SIO_I2C_DAT65

LK

D

AT

_TP_SIO_I2C_CLK65

U

SB

_EN#66

U

3_

PD#_EC66

T

YP

EC_SMBDA72

T

YP

EC_SMBCLK72

G

PU

_THM_SMBDAT66

G

PU

_THM_SMBCLK66

L

ID

_POWER_ON#_R67

H

T_DEBUG_TX68

OS

U

1_SMBINT#72

PD

T

EC_DCIN1_EN#74

YP

F

_SCAN#92

PR

M

E_

FWP98

5

1

R

V_S5

D8

E

SP

I_IO[3..0]18,68

E

I_IO0

SP

E

SP

I_IO1

E

I_IO2

SP

E

SP

K

I_IO3

SI

[0..7]65

K

SI

0

K

SI

1

K

SI

2

K

SI

3

K

SI

4

K

SI

5

K

6

SI

K

7

SI

R

3

D3

V_ECVBAT

R

3

V_S5_KBC

D3

R

24

R

24

R

24

R

24

3

D3

V_S5

R

24

R

24

3

D3

V_S0

R

24

R

24

C

24

D

UHOT#

GP

V

ST_PWRGD

CC

L

ID

_POWER_ON#_R

G

C6

_THM_DIS#_EC

G

PU

_THM_SMBDAT

G

_THM_SMBCLK

PU

T

OU

CH_REPORT_SW

eDP backlight
Control from EC

L

R

KLT_EN

_B

0R2J-L-GP

eDP backlight
Control from PCH

I

P_CLK

CS

I

CS

P_DAT

H

OST_DEBUG_TX

I

CS

P_CLR

O13_20171101

GPIO002:open drain

1 2

DY

24

56 100KR2J-1-GP

1 2

24

97 100KR2J-1-GP

R

413

N2

1

4

2 3

SRN2K2J-1-GP

R

N2

402

1

4

2 3

SRN4K7J-8-GP

1 2

60 10KR2J-L-GP

1 2

15 100KR2J-1-GP

1 2

DY

03 100KR2J-1-GP

1 2

DY

04 100KR2J-1-GP

1 2

DY

08 10KR2J-L-GP

1 2

34 100KR2J-1-GP

R

405

N2

1

8

2

7

3

6

4 5

SRN100KJ-5-GP

1 2

49 10KR2F-2-GP

1 2

35 100KR2J-1-GP

1 2

18 SC1U10V2KX-1DLGP

1 2

R

24

77 0R0402-PAD

1 2

R

24

82 0R0402-PAD

1 2

R

95 0R0402-PAD

24

1 2

R

47 0R0402-PAD

24

1 2

R

05 0R0402-PAD

24

1 2

R

24

06 0R0402-PAD

D

24

02

A K

RB751VM-40TE-17-GP

83.R2004.J8F

P

EL_BKEN_EC

AN

L

1 2

KLT_EN_L

_B

DY

24

27

3

3

D3

D3

V_S5_KBC

12

12

R

24

14

10KR2J-L-GP

DEBUG

For USB TypeC

T
T

P
P

G

P

I

I

V_S5_KBC

R

24

100KR2J-1-GP

S

YS

L

ID

YP

EC_SMBCLK
EC_SMBDA

YP

BA

T_CHG_SMBDAT

BA

T_CHG_SMBCLK

_PWR_LEVEL

PU

T_PRES#

BA

CS

P_CLK

P_DAT

CS

C

LK

_TP_SIO

U

SB

_EN#

m

RD_PCIE#_SATA

CA

L

ID

_CL_SIO#

B

1_LED#

AT

B

2_LED#

AT

S

SD

_SCP#

U

SB

_PWR_SHR_EN_L#

V

R_

CAP

C

C

L

80

_LED_MASK#_R

_POWER_ON#

G

_PWR_LEVEL

PU

R

UN

PWROK

L

ID

_POWER_ON#

G

C6

_THM_DIS#

PU

_SMB_SDA_P1

_SMB_SCL_P1

PU

ID

_CL_SIO#

D

24

01

1

2

BAT54C-12-GP

75.00054.A7D

3

D3

V_S5_KBC

3

P

EL_BKEN

AN

D

B3

7
1

2
3
4

DEBUG

5
6
8

A

CES-CON6-58-GP

20.K0691.006

For eSPI

3

D3

4

V_S5_KBC

R

N2

1
2
3
4 5

SRN100KJ-5-GP

R

N2

1
2
3
4 5

SRN100KJ-5-GP

R

N2

1
2
3
4 5

SRN100KJ-5-GP

R

N2

1
2
3
4 5

SRN100KJ-5-GP

B

AT

3

D3

C

C

_LED#_R

AP

P

RO

3

D3

1

D8

412

409

410

411

2_LED#

V_S5

_AMBER_LED#

HG

CHOT

V_S5

12

S
S

V_S5

R

1 2

24

24

C

C

0R0603-PAD

21

16

12

1U16V2KX-3DLGP

CD

1U16V2KX-3DLGP

CD

1

D8

R

24

01

1 2

0R0402-PAD

8

K

SO

8

7

K

3

SO

6

K

SO

1

K

2

SO

8

K

5

SO

7

K

SO

4

6

K

SO

7

K

6

SO

8

K

SO

13

7

K

SO

14

6

K

SO

10

K

SO

11

8

K

SO

0

7

K

SO

12

6

K

15

SO

K

SO

16

PH 3D3V_S5 in RN2405

Q

24

1

2

3 4

2N7002KDW-1-GP

75.27002.F7C

common part

Q

24

14

D

Notice:ZZ.2N702.J3101

2N7002K-2-GP

84.2N702.J31

Q

08

24

G

S

Notice:ZZ.2N702.J3101

2N7002K-2-GP

84.2N702.J31

24

V_S5_KBC

3

16

3

RTC GEN 9 reset circuit

I
f don't need RTC alarm wake up,

can change to 3D3V_AUX_S5

3

V_RTC

D3

12

R

24

73

3

D3

46

24

C

23

12

D3

V_S5_KBC

N

6

ote:ZZ.27002.F7C01

5

SCD1U16V2KX-3DLGP

G

S

D

24

C

10

12

S

1U16V2KX-3DLGP

CD

S

1U16V2KX-3DLGP

CD

S

CD

1U16V2KX-3DLGP

3

D3

R

1
2
3
4 5

SRN10KJ-6-GP

R

1
2
3
4 5

SRN10KJ-6-GP

B

AT

3

D3

B

AT

3

P

RO

24

C

11

12

V_S5_KBC

N2

403

404

N2

T_WHITE_LED#

V_S5

1_LED#

D3

V_S0

12

CHOT#_CPU

12

8
7
6

8
7
6

R

24

89

100KR2J-1-GP

C

24
12

12

AP

V_S5_KBC

24

24

24

C

24

C

29

K

SI

K

SI

K

SI

K

SI

K

SI

K

SI

K

SI

K

SI

_LED#

12

S
S
S

SCD1U16V2KX-3DLGP

2
1
3
0

7
6
4
5

C

13

12

1U16V2KX-3DLGP

CD

1U16V2KX-3DLGP

CD
CD

1U16V2KX-3DLGP

C

14

V

1
3

R

P
S
E
L
T
P

A
P
L
H

K
K
K
K
K
K
K
K

K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
C

A

F
T
B

E
E
E
E

E
S
E
E

B
B

12

CAP

R_

VREF_CPU

V_
D3

V_ECVBAT

PWROK

UN

EL_MONITOR

AN

_SCP#

SD

D_INHIB

C_
CD

_TST

AB

LE_MODE#

RO

CHOT

LW

ON

OW

ER_SW_IN#

ID

_POWER_ON#

ACAV_IN

W_

0

SI

1

SI

2

SI

3

SI

4

SI

5

SI
SI

6

SI

7

SO0
SO

1

SO

2

SO

3

SO

4

SO

5

SO

6

SO

7

SO

8
9

SO

10

SO

11

SO
SO

12

SO

13
14

SO
SO

15
16

SO
AP

_LED#

DIS

C_

PR

_SCAN#

P_

WAKE_KBC#

KL

T_IN_EC

SP

I_IO0
I_IO1

SP

I_IO2

SP

I_IO3

SP

SP

I_RESET#
_LED_MASK#

YS

I_CLK

SP
SP

I_CS#

AT

2_LED#

AT

1_LED#

C

15

5

1

9
3

4
6

5
2

8

1

03

54

18
22
95

122

48

20
21
25
26
85
83

121
127
126
128

98
99

6

7
104
105
107
108

2

14
15
16
37
38
39
50
46
68
72
74
75
76
77
86
92
93

3

69
71
42
33
67

59
60
61
62

53
55
57
58

1
106

70

Power Switch Logic(PSL)

K

BC

_PWRBTN#

0R0402-PAD

3

12

C

24

28

SCD1U16V2KX-3DLGP

U

01

24

TR

V

TR

V

TR

V

TR

V

TR

V

TR

V

TR

_33_18

V

R_

CAP

V

AC

_VREF

D

RE

F_CPU

V

T

BA

V

O057/VCC_PWR GD

PI

G

PI

O020/CMP_VIN0

G

O021/CMP_VIN1

PI

G

PI

O165/CMP_VREF0

G

PI

O166/CMP_VREF1/ UART_CLK

G

PI

O124/CMP_VOUT0

G

O120/CMP_VOUT1

PI

G

CI

_OUT/GPIO036

V

_IN0#/GPIO163

CI

V

CI

_IN1#/GPIO162

V

_OVRD_IN/GPIO164

CI

V

PI

O143/KSI0/DTR#

G

O144/KSI1/DCD #

PI

G

PI

O005/SMB00_D ATA/SMB00_DATA18/KSI2

G

O006/SMB00_C LK/SMB00_CLK 18/KSI3

PI

G

PI

O147/KSI4/DSR #

G

O150/KSI5/RI#

PI

G

PI

O151/KSI6/RTS#

G

O152/KSI7/CTS#

PI

G

O027/KSO00/P VT_IO1

PI

G

PI

O015/KSO01/P VT_CS#

G

O016/KSO02/P VT_SCLK

PI

G

PI

O017/KSO03/P VT_IO0

G

O045/BCM_INT1#/KS O04

PI

G

PIO046/BCM_DAT1/K SO05

G

PI

O047/BCM_CLK1 /KSO06

G

PI

O025/KSO07/P VT_IO2

G

O055/PWM2/ KSO08/PVT_IO3

PI

G

PI

O102/KSO09/C R_STRAP

G

O106/KSO10

PI

G

O110/KSO11

PI

G

O111/KSO12

PI

G

PI

O112/PS2_CL K1A/KSO13

G

O113/PS2_DAT1A/KSO1 4

PI

G

PI

O125/KSO15

G

PI

O132/KSO16

G

PI

O140/KSO17

G

O001/SPI_CS# /32KHZ_OUT

PI

G

O103/SPI_IO0

PI

G

O105/SPI_IO1

PI

G

PI

O052/SPI_IO2

G

O062/SPI_IO3

PI

G

PI

O101/SPI_CLK

G

PI

O040/LAD0/ESPI _IO0

G

O041/LAD1/ESPI _IO1

PI

G

PI

O042/LAD2/ESPI _IO2

G

O043/LAD3/ESPI _IO3

PI

G

PI

O061/LPCPD#/ ESPI_RESET#

G

PI

O063/SER_IRQ/ ESPI_ALERT#

G

O034/PCI_CLK /ESPI_CLK

PI

G

PI

O044/LFRAME#/ES PI_CS#

G

O157/LED0/TST_CL K_OUT

PI

G

PI

O156/LED1

G

O104/LED2

PI

G

MEC1418-NU-D0-GP

071.01418.000K

3

V_ECVBAT

D3

12

R

24

51

100KR2J-1-GP

R

24

32

P

1 2

1KR2J-1-GP

12

C

24

27

SC2D2U10V3KX-1DLGP-U

D3

V_ECVBAT

PI

O007/SMB01_D ATA/SMB01_DATA18

G

PI

O010/SMB01_C LK/SMB01_CLK 18

G

O012/SMB02_D ATA/SMB02_DATA18

PI

G

PI

O013/SMB02_C LK/SMB02_CLK 18

G

O130/SMB03_D ATA/SMB03_DATA18

PI

G

PI

O131/SMB03_C LK/SMB03_CLK 18

G

O141/SMB04_D ATA/SMB04_DATA18

PI

G

PI

O142/SMB04_C LK/SMB04_CLK 18

G

PI

O123/SHD_CS#/BS S_STRAP

G

PI

G

PI

G

PI

G

PI

G

PI

O126/SHD_SCLK

G

G
G
G

PI

O030/BCM_INT0#/PW M4

G

O031/BCM_DAT0/PW M5

PI

G

PI

O032/BCM_CLK0 /PWM6

G

G

G
G

G
G

G
G
G
G
G
G

PI

O023/ADC6/A20M

G

G

PI

O114/PS2_CL K0

G

O115/PS2_DAT0

PI

G

PI

O026/PS2_CL K1B

G

PI

O127/PS2_DAT1B

G

PI

O035/SB-TSI_CL K

G

O033/PECI_DAT/SB_ TSI_DAT

PI

G

O116/TFDP_DATA/UART_RX

PI

G

PI

O117/TFDP_CLK/ UART_TX

G

PI

O145(ICSP_CL OCK)

G

PI

O146(ICSP_DATA)

G

O011/SMI#/EMI_ INT#

PI

G

ES

ET_IN#/GPIO014

R

G

PI

G

PI

G

PI

G

O107/RESET_OUT#

PI

G

B

PWR_PRES/GP IO003

YS

S

OW

ER_SW_IN#

O133/SHD_IO0
O134/SHD_IO1
O135/SHD_IO2
O136/SHD_IO3

O053/PWM0

PI
PI

O054/PWM1

PI

O056/PWM3

O002/PWM7

PI

PI

O160/DAC_0
O161/DAC_1

PI

PI

O050/TACH0

PI

O051/TACH1

PI

O121/ADC0
O122/ADC1

PI
PI

O155/ADC2
O154/ADC3

PI
PI

O153/ADC4
O022/ADC5

PI

O024/ADC7

PI

A

O060/KBRST

PI
O064/LRESET#

O067/CLKRUN#

O100/EC_SCI#

CS

I
GP

V

DC

_VREF

X
X

P_MCLR

O/GPIO004

A

SS

_VBAT

For eSPI

3

D3

TA
TA

V
V
V
V
V

DY

L1
L2

S

VS

SS
SS
SS
SS
SS

V_S5_KBC

12

R

12

R

100KR2J-1-GP

100KR2J-1-GP

1

D0

V_S5

8
9
11
12
89
91
96
97

27
28
29
30
31
32

44
45
47
34
35
36
4

23
24

40
41

114
113
111
110
109
116
117
118
115

78
79

52
88

90
94

80
81

101
102

123
125

10
13
49
56
63
66
73
87
119
120

112

17
5

1
4

6
8

4
00

1

124

0R resistor or connect directly.

52

24

K

SO

24

53

Layout Note:

Need very close to EC

1

1 2

R

V_

VREF_CPU

24

02

0R0402-PAD

12

C

24

06

SCD1U16V2KX-3DLGP

P

BA

T_CHG_SMBDAT

P

BA

G

PU

G

PU

T

YP

T

YP

C

LK

D

AT

P

CH

S

YS

P

BA

P

RI

R

TC

U

PD

K

B_

B

EE

F

AN

N

B_

P

S_

G
C6_DIS

G

C6

H

W_

F

AN

m

CA

I

ATT

_B

L

CD

B

OA

I

_A

DP

M

OD

S

IO

P

AN

U

SB

C

LK

D

AT

S

IO

V

CC

P

TP

H

_P

M

E_

H

OS

I

CS

I

CS

M

EC

M

EC

G

PU

U

SB

M

AS

T

YP

L

ID

_CL_SIO#

R

ES

I

CS

N

B_

S

YS

E

C_

R

1 2

0R0402-PAD

Layout Note:

C
onnect GND and AGND planes via either

T_CHG_SMBCLK
_THM_SMBDAT
_THM_SMBCLK
EC_SMBDA
EC_SMBCLK

_TP_SIO_I2C_DAT

_TP_SIO_I2C_CLK

_RSMRST#
_PWROK
T_PRES#

M_PWRGD

RST_ON
1_SMBINT#

LED_PWM

P
1_PWM
MODE#

ID

_THM_DIS#_EC

ACAVIN_NB

1_TACH

RD_PCIE#_SATA

_VCC_TEST_EN

RD_ID

EL_ID

_EXT_WAKE#

EL_BKEN_EC

_PWR_SHR_EN_L#

_TP_SIO

_TP_SIO

_PWRBTN#

DSW_EN

_DIS#
ECI

FWP

T_DEBUG_TX

P_CLK
P_DAT

_XTAL1_R

_XTAL2

_PWR_LEVEL

_EN#

K_SATA_LED#

EC_DCIN1_EN#

ET_OUT#
P_CLR
MUTE#

PWR_PRES

AGND

24

45

E

C_

BATTER /CHARGER
CPU/ Thermal/TYPEC

3

12

R

24

07 0R2J-L-GP

1

A

FT

P2402

Layout Note:

R

37 43R2J-GP

24

12

C

DY

24

SC100P50V2JN-3DLGP

N
eed very close to EC, PDG: <0.5 inches.

R

24

61 0R2J-L-GP

3

D3

V_AUX_S5

12

R

24

DY

1KR2J-1-GP

12

R

24

100KR2J-1-GP

AGND

D3

1 2

1 2

1 2

GPIO123 (BSS_STRAP)GPIO102 (CR_STRAP)

Already pull low
on CPU side

T

402

P2

9

TPAD14-OP-GP

CR_STRAP BSS_STRAP

X0

0

1

1 Use 3.3V Shared SPI

V_S0

R

DY

05

63

54

10KR2J-L-GP

DY

1

2

DIS : 64.64925.6DL

24

30

D

24

03

F

A K

AN

_TACH1

L1SS355T1G-GP

83.00355.G1F

U

3_

PD#_EC

M

EC1416��s pin 118 (GPIO024).
This pin is a strap option pin.
It should be pulled up to enable Comparator 0 function for
thermal shutdown function.

P

EC

I_CPU

S

US

_CLK

A

R

IA

D_

R

24

Need very close to EC

1 2

DY

23 330R2J-3-GP

24

1 2

40 0R0402-PAD

Layout Note:

B

T_IN_EC

KL

P

_RSMRST#

CH

Source

Use 3.3V Private SPI

Use eSPI Flash Channel

B

OA

RD_ID

24
08

12

E

AGND

C_

U
MA : 64.27025.6DL

M

EL_ID

OD

24
07

12

E

C_

AGND

12

C

DY

24

41

SC2200P50V2KX-2DLGP

E

C_

AGND

12

R

55

24

100KR2J-1-GP

SCD1U16V2KX-3DLGP

C

SCD1U16V2KX-3DLGP

C

L

3

12

PCB_REV

12

E

3

12

MODEL_ID

12

E

I

_B

KLT_EN

_B

V_S5_KBC

D3

R

37K4R2F-1-GP

R

100KR2F-L3-GP

AGND

C_

D3

V_S5

R

27KR2F-L-GP

R

100KR2F-L3-GP

C_

AGND

3

D3

12

E

ATT

C_

24

43

24

44

24

42

41

24

V_S5_KBC

C

24

22

SCD1U16V2KX-3DLGP

AGND

I

E

S

DY

BOARD_ID

VERSION A/D

Waps_X00

Waps_X01

Waps_X02

Waps_A00

Waps_X03

Waps_X04

Waps_X05

Waps_A01

Waps_A02

Waps_A03

MODEL_ID_DET

(GPIO153)

TBD

TBD

Waps 13" UMA

TBD

TBD

Waps 13" DIS

TBD

TBD

TBD

TBD

1 2

DP

_A

12

C

24

35

SC2200P50V2KX-2DLGP

AGND

C_

_LED_MASK#

YS

12

C

24

36

SC2200P50V2KX-2DLGP

D

U_PWROK

GP

R

330R2J-3-GP

R

PULL-LOW

RESISTOR

RESISTOR

100.0K

10.0K

100.0K

17.8K

100.0K

27.0K

37.4K

100.0K

100.0K

49.9K

100.0K

64.9K

100.0K

82.5K

107K

100.0K

154K

100.0K

200K

PULL-LOW

RESISTOR

RESISTOR

100.0K

10.0K

100.0K

17.8K

100.0K

27.0K

100.0K

37.4K

100.0K

49.9K

100.0K

64.9K

100.0K

82.5K

100.0K

107K 1.594V

100.0K

154K

100.0K

200K

M

EC

_XTAL1_R

12

M
icrochip: Use CL=9p Xtal�AC = 10p

RUNPWROK assert,
delay 10ms; PCH_PWROK assert.

21

24

1 2

24

71 0R2J-L-GP

???

X

1 2

XTAL-32D768KHZ-98-GP

082.30003.0301

C

24

25

SC18P50V2JN-1DLGP

A

D_

150KR2F-L-GP

P

R2

12

455

DY

1 2

12

115KR2F-GP

R

24
57

DY

DY

12

DY

24

IA

R

0R2J-L-GP

R

01

24

DY

24

10KR2J-L-GP

EC

_XTAL2

12

10

S

G

26

VOLTAGEPUL L-HIGH

3.0V

2.801V

2.598V

2.402V

2.201V

2.001V

1.808V

1.594V100.0K

1.299V

1.100V

VOLTAGEPUL L-HIGH

3.0V

2.801V

2.598V

2.402V

2.201V

2.001V

1.808V

1.299V

1.100V

M

C

24

24

SC18P50V2JN-1DLGP

_LED_MASK#_R

YS

_THM_DIS#_EC

C6

1

A A

<Core Design>

<Core Design>

<Core Design>

T

it

le

Title

Title

K

K

K

BC

BC

BC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

us

us

us

tom

tom

tom

W

W

W

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

W

W

W

is

is

is

2

2

2

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Nuvoton MEC1416

Nuvoton MEC1416

Nuvoton MEC1416

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

AS

AS

AS

1

tron Corporation

tron Corporation

tron Corporation

o

o

o

24 106

24 106

24 106

f

f

f

A

A

A

00

00

00

5

Main Func = SPI Flash

S

P

I_WP_CPU15,18

S

P

I_HOLD_CPU15,18

S

PI_CS_CPU_N018

S

I_CLK_CPU18,91

P

S

I_SI_CPU15,18,91

P

S

P

D D

I_SO_CPU18,91

S

PI_CS_CPU_N0

S

P

I_SO_CPU

S

P

I_WP_CPU

1 2

R

2

506 33R2F-3-GP

1 2

R

2

507 33R2F-3-GP

3

3V_S5_PCH

D

12

R

2

519

4K7R2J-L-GP

4

S

P

I_SO_ROM

S

P

I_WP_ROM

3

D3V_S5_PCH

12

C

501

2

DY

SC10U6D3V3MX-DL- GP

1
2
3
4

W25Q128J VSIQ-GP

B

I

OS1

S

#

C

O

O

/IO1

D
W
G

LD#/RESET#/IO3

H

#/IO2

P

D

N

072.25128.0B51

12

C

SCD1U16V2KX-3DLGP

D

3

S

P

I_CLK_CPU

12

E

502

2

3

3V_S5_PCH

D

8

C

C

V

7

S

P

I_HOLD_ROM

6

S

P

K

L

C

/IO0

I

I_CLK_ROM

5

S

I_SI_ROM

P

R

2

503 15R2F-2-GP

R

2

508 33R2F-3-GP

R

2

509 33R2F-3-GP

DY

1 2
1 2
1 2

2501

C

SC10P50V2JN-4DLG P

2

0180904

EMC add

S

P

I_HOLD_CPU

S

P

I_CLK_CPU

S

I_SI_CPU

P

2

1

Main Func = RTC

C C

B B

A A

R

TC

RST_ON24

V

CDSW_ EN24

C

3

_5V_PWRG D17,45

V

3

_5V_DSW_ OK52,53

V

R

TC_DET#15,20

5

+

R

TC_VCC

12

R

504

2

10MR2J-L-GP

3

4

ETY-CON2-22-G P-U

3

3V_AUX_S5

D

12

R
0R0402-PAD

3

D

3V_RTC_SYS

RTC

R

TC

1

1

2

20.F1841.002

Delivery Voltage 3.19V

505

2

Q

505

2

G

S

Notice:ZZ.2N702.J3101

2N7002K-2-GP

84.2N702.J31

R

TC_VCC_C

D

2

501

1

2

BAT54C-12-GP

75.00054.A7D

D

+

TC_VCC

R

12

R

1KR2J-1-GP

3

3V_RTC

D

3

12

C

SCD1U16V2KX-3DLGP

R

_DET#

TC

1

A

FT

P2508

2

510

1

A

FT

P2507

4

3

3V_RTC

D

DS

Q

507

2

PJA3415-GP

G

084.03415.0031

503

2

R

567

2

R

1 2

TC

R

516

2

1 2

0R0603-PAD

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

3

3

3

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

Date: Sheet

Date: Sheet

Date: Sheet

V

C

CDSW_ EN

3

3V_S5

D

12

R

2

520

100KR2J-1-GP

12

C

525

2

DY

SC1U10V2KX-1DLGP

R

TC

RST_ON

1MR2J-1-GP

12

R

2518

3

D

3V_S5

12

R

514

D

2

3

V

_5V_PWRG D

3

503

1

2

BAT54A-11-GP

75.BAT54.07D

3

3V_S5

D

2

10KR2J-L-GP

3

V

3

_5V_DSW_ OK

U

2

502

4

N

O

E

5

G

N

O

I

SY6288C20AAC-GP

074.06288.007B

2

C

N

U

100KR2J-1-GP

3

D

3V_VCCDSW

3

#

2

D

1

T

R

_AUX_S5

TC

G

_3P3_EN_G

C

2517

SCD022U16V2KX-3DLG P

2 1

3

D

3V_S5_PCH

l

l

l

ash/RTC

ash/RTC

ash/RTC

F

F

F

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

A

A

A

W

W

W

12

R

511

2

4K7R2J-L-GP

R

TC

_3P3_EN_D

D

Q

2

510

2N7002K-2-GP

84.2N702.J31

e:ZZ.2N702.J3101

otic
N

S

i

i

i

stron Corporation

stron Corporation

stron Corporation

W

W

W

2

2

2

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

1

1

1

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

5 106

5 106

5 106

2

2

2

1

0

0

0

0

0

0

A

A

A

o

o

o

f

f

f

5

WWW.AliSaler.Com

4

3

2

1

Main Func = Thermal Sensor

C

PU

_SMB_SCL_P118,24,79

C

_SMB_SDA_P118,24,79

PU

P

E_HW_SHUTDOW N#40

D D

C C

UR

F

N

1_PWM24

A

F

N

_TACH124

A

R

ES

ET_OUT#17,24

P

RST#_CPU17,61,63,66,76,91

LT

Q

03

26

C

LMBT3904LT1G-GP

B

84.T3904.H11

E

2

.System Sensor, Put on palm rest

DY

N

12

N

7718_DXP

CT

SC470P50V2KX-3DLGP

C
26

06

CT

7718_DXN

3

D3

V_S0

DY

SC10U6D3V3MX-DL-GP

C
26

12

01

12

SCD1U16V2KX-3DLGP

C

26

12

02

SC2200P50V2KX-2DLGP

C
26

07

Layout Note:

C2607 close THM2601

Layout Note:

Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

T

_C
RIT#

12

R

26

0R0402-PAD

T

3

D3

V_S0

R

3

D3

V_S5

R

U

26

01

1

DD

V

2

+

D

3

-

D

4

RIT#

_C

T

NCT7718W-GP

74.07718.0B9

01

R

ET_OUT#

ES

HE

RM_SYS_SHDN#

1 2

03 7K5R2F-1-GP

26

1 2

04 7K5R2F-1-GP

26

8

CL

S

7

DA

S

6

A

RT#

LE

RT#

A

ND

G

G

S

LE

5

Q

02

26

Notice:ZZ.2N702.J3101

2N7002K-2-GP

84.2N702.J31

A

RT#

LE

3

D3

V_S0

T

_C

RIT#

1

23

R

602

DY

12

C

PU

_SMB_SCL_THM

C

_SMB_SDA_THM

PU

SCD1U16V2KX-3DLGP

C
26

12

08

DY

N2

SRN2K2J-1-GP

4

SCD1U16V2KX-3DLGP

C
26

09

Q

1

2

3 4

2N7002KDW-1-G P

3

V_S0

D3

26

01

N

ote:ZZ.27002.F7C01

6

5

C

_SMB_SDA_P1

PU

75.27002.F7C

C

_SMB_SCL_P1

PU

P

E_HW_SHUTDOW N#

UR

D

12

C

26

10

DY

SCD1U16V2KX-3DLGP

PWM FAN1

S

B B

5

V_

S0

R

26

12

1 2

0R0603-PAD

F

AN

_TACH1

F

1_PWM

AN

5

V_

A A

FAN_VCC

Layout Note:

SC4D7U6D3V3KX-DLGP

C
26

12

04

1

A

1
1

FT

A

FT

A

FT

5

12

P2601
P2602
P2603

SCD1U16V2KX-3DLGP

C
26

05

ignal Routing Guideline:

Trace width = 15mil

5

FAN_VCC

V_

E
C2

602

20180904
EMC add

1

4

F

AN

F

AN

E
C2

12

601

DY

S

C1

0P50V2JN-4DLGP

S

0P50V2JN-4DLGP

C1

A

FT

P2604

_TACH1
1_PWM

12

DY

F

1

AN

1

2
3
4

ACES-CON4-29-GP

5

6

20.F1639.004

KBC T8

3

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

HE

HE

HE

RMAL NCT7718W/Fan

RMAL NCT7718W/Fan

RMAL NCT7718W/Fan

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

Date: Sheet

2

AS

AS

AS

P 13" WHL-U

P 13" WHL-U

W

W

W

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

P 13" WHL-U

o

o

o

f

6 1

f

6 1

f

6 1

2

2

2

1

00

00

00

A

A

A

06

06

06

5

4

3

2

1

Main Func = Audio

H

D

A_SDIN0_CPU19

H

D

A_SDOUT_CODEC19

H

DA_SYNC_CODEC19

H

A_BITCLK_CODEC19

D

D D

C C

A

U

D_SPK_R+29

A

D_SPK_R-29

U

A

U

D_SPK_L+29

A

U

D_SPK_L-29

D

M

IC_SCL_CODEC55

D

MIC_SDA_CODEC55

P

_SLP_S3#17,40

M

A

D_SENSE29,66

U

N

_MUTE#24

B

S

PKR15,19

B

E

EP24

A

U

D_RING29,6 6

A

D_SLEEVE29,66

U

L

NE1_L29

I

L

I

NE1_R29

L

NE1_VREFO29

I

M

C2_VREFO_R29

I

A

U

D_HP1_JACK_L29,66

A

UD_HP1_JACK_R29,66

moat

1

D

+

5

8V_S0

V_PVDD

Analog
Digital

1 2

R

719

2

0R0402-PAD

>2A

5

V

_S0

1 2

R

2

701

0R0805-PAD

1 2

R

707

2

0R0805-PAD

1

8V_S0

D

R

2

709

1 2

0R0402-PAD

1

.8V power rail should be supplied by
linear regulator, not awitching
regulator.if switch regulator is
unavilable, please make sure that switch
frequency operates at out-band(over 20KHz)

12

C

710

2

SC10U6D3V3MX-DL- GP

A

D_AGND

U

12

+

5

V_PVDD

1

8V_CPVDD

D

A

A

C

C

SCD1U16V2KX-3DLGP

SC10U6D3V3MX-DL-GP

2

2

12

714

713

C

C

SCD1U16V2KX-3DLGP

SC10U6D3V3MX-DL-GP

2

2

12

12

718

717

U

D_AGND

U

D_AGND

Layout Note:

C

711

2

SC10U6D3V3MX-DL- GP

S

peaker trace
width >40mil @
2W4ohm speaker
power

DVDD must >= DVDD_IO

3

3V_S0

D

B B

S

KR

P

B

E

EP

A A

1 2

R

715 0R0603-PAD

2

R

2

1 2

0R0402-PAD

R

2

1 2

0R0402-PAD

O

pen drain output.
pull up to DVDD or
max. 5V

3

D

3V_RTC

3

D

3V_S0

H

DA_SDIN0_CPU

H

D

A_BITCLK_CODEC

741

734

+

V_1D8V_DVDD

3

C

C

SC2D2U10V3KX-1DLGP-U

SCD1U16V2KX-3DLGP
2
740

2

12

741

D

703

2

1

2

BAT54C-12-GP

75.00054.A7D

A

U

3

V

3

D

V

H

DA_CODEC_SDIN0

H

D

A_BITCLK_CODEC_R

12

H

D

A_SPKR_R

K

B

C_BEEP_R

For RTC Gen9 reset circuit change power rail.
20170921

1 2

R

708 0R0402-PAD

2

1 2

R

716 100KR2J-1-GP

2

DY

1 2

R

2

724 22R2J-L1-GP

1 2

R

2

723 22R2J-L1-GP

5

D_PC_BEEP_C

12

R

1KR2J-1-GP
2
735

D3_STB

SS

C

735

2

SCD1U16V2KX-3DLGP

1 2

C

SC100P50V2JN-3DLGP

2739

12

DY

A

U

D_PC_BEEP

4

Audio Codec Chip ALC3204

A

D_HP1_JACK_L

U

A

D_HP1_JACK_R

U

C

C

2

2

708

709

12

SC2D2U10V3KX-1DLGP-U

C

B
P

30

29

P
B

VDD

C

P
C

IO0/DMIC-DATA12

DD

P

V
D

G

1

2

IC_SDA_CODEC
M

D

12

SC2D2U10V3KX-1DLGP-U

C
P

C

VEE
B
N

28

27

26

25

N
B

VEE

C

P

-OUT-L

-OUT-R

C

P

P

H

H

ALC3204

Q

FN40 (5X5)

071.03204.0003

IO1/DMIC-CLK

ATA-OUT

O3-CAP

T-CLK

P

D

I

D

G

S

B

3

IC_SCL_CODEC
M

D

L

4

5

6

A_BITCLK_CODEC_R

A_SDOUT_CODEC

O3_CAP

D

D

D

L

H

H

12

A

U

D_AGND

A

D_AGND

U

I

NE1_VREFO

24

7

A_CODEC_SDIN0
D

H

C

2

722

SC10U6D3V3MX-DL- GP

E

C

E

C

E

C

E

C

E

C

R

2

R

2

R

2

1 2

N

A

U

D_SENSE

B

_MUTE#

L

O2_CAP

D

+

V_1D8V_AVDD

3

A

U

D_SPK_L+

A

D_SPK_L-

U

A

U

D_SPK_R-

A

U

D_SPK_R+

P

D

B_R

+

V_1D8V_DVDD

3

12

R

1 2

200KR2F-L-GP

1

8V_CPVDD

D

C

SC2D2U10V3KX-1DLGP-U

2

12

12

705

U

701

2

31

V

A

32

D

L

33

V

A

34

V

P

35

P

S

36

P

S

37

P

S

38

P

S

39

V

P

40

DB

P

41

N

G

ALC3204-CG-GP- U

+

V_1D8V_DVDD

3

C

SC10U6D3V3MX-DL-GP

2

12

720

place close to pin1

20180911

717

R

712

2

1 2

0R0402-PAD

+

V_1D8V_DVDD

3

12

Vendor stuff

P

D

R

2

710

100KR2J-1-GP

A

U

D_HPJD_N

R

2

100KR2J-1-GP

2

711

C

2
704

SS2

O2-CAP

DD2

DD1

K-L+

K-L-

K-R-

K-R+

DD2

D

12

B_R

3

SCD1U16V2KX-3DLGP

C

SCD1U16V2KX-3DLGP
2
721

A

D_AGND

U

12

C

2

702

SC2D2U10V3KX-1DLGP -U

12

L

D
O1_CAP

O1-CAP
D
L

V

A

A

I

NE1-L

L

I

NE1-R

L

33STB

D

V

I

C2-CAP

M

EEV/MIC2-R

L

S

I

NG2/MIC2-L

R

/LINE1-JD_JD1

BEEP

C

P

_DET
C
D

+

V_1D8V_DVDD

3

12

2
702

DD1

V

SS1

C

2
723

2

EMC modify

R

100KR2J-1-GP

A

U

20

19

18

17

16

15

14

13

12

11

SC4D7U6D3V3KX-DLGP

0180904

A

M

L

U

I

C2_VREFO_R

D_VREF

23

22

21

EF
R

V

C2-VREFO

I
M

NE1-VREFO-L

I

L

P

H

ATA-IN

DD-IO

NC

V

D

Y

S

D

S

8

9

10

A_SYNC_CODEC

SS

D

V

H

D

moat

1 2

2701 SC1KP50V2KX-1DLGP

1 2

2702 SC1KP50V2KX-1DLGP

1 2

2703 SC1KP50V2KX-1DLGP

1 2

2704 SC1KP50V2KX-1DLGP

1 2

2705 SC1KP50V2KX-1DLGP

1 2

704 0R0603-PAD

1 2

705 0R0603-PAD

1 2

706 0R0603-PAD

Layout Note:

Tied at point only under
Codec or near the Codec

C

SC2D2U10V3KX-1DLGP-U

2

12

703

D_AGND

+

5

V_AVDD

L

NE1_L

I

L

NE1_R

I

V

D3_STB

3

M

I

C_CAP

A

UD_SLEEVE

A

D_RING

U

A

U

D_HPJD_N

A

D_PC_BEEP

U

place close to pin8

2

+

V_AVDD

5

A

U

D_AGND

1 2

C

715 SC10U6D3V3MX-D L-GP

2

R

C

SC10U6D3V3MX-DL-GP

2707

12

12

2

703 0R0603-PAD

C
2

706

Analog
Digital

moat

1 2

SCD1U16V2KX-3DLGP

Layout Note:

P

lace close to Pin 20

A

U

A

U

moat

D_AGND

D_AGND

5

_S0

V

Azalia I/F EMI

D

H

H

D

D

A_BITCLK_CODEC

A_SDOUT_CODEC

E

E

C

12

2709

DY

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

Date: Sheet

SC22P50V2JN-9-GP

SC22P50V2JN-9-GP

C

12

2710

DY

u

u

u

dio Codec ALC3204

dio Codec ALC3204

dio Codec ALC3204

A

A

A

A

SP 13" WHL-U

A

SP 13" WHL-U

A

SP 13" WHL-U

W

W

W

D

M

M

IC_SDA_CODEC

IC_SCL_CODEC

E

E

SC22P50V2JN-9-GP

SC33P50V2JN-3DLGP

C

DY

12

C

12

2711

2706

DY

20180911
Vendor add

i

i

i

stron Corporation

stron Corporation

stron Corporation

W

W

W

2

2

2

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

F, 88, Sec.1, H sin Tai Wu Rd., Hsic hih,

1

1

1

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

7 106Thursday, March 07, 2019

7 106Thursday, March 07, 2019

7 106Thursday, March 07, 2019

2

2

2

1

0

0

0

0

0

0

A

A

A

o

o

o

f

f

f

5

WWW.AliSaler.Com

D D

C C

4

3

2

1

(Blanking)

B B

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

A A

T

le

Title

Title

it

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

W

W

W

AS

AS

AS

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Re

Re

Re

served)

served)

served)

(

(

(

P 13" WHL-U

P 13" WHL-U

P 13" WHL-U

o

o

o

f

8 1

f

8 1

f

8 1

2

2

2

1

A

A

A

00

00

00

06Thursday, March 07, 2019

06Thursday, March 07, 2019

06Thursday, March 07, 2019

5

Main Func = Audio

4

3

2

1

Speaker

Layout Note:

S

K1

Speaker trace width >40mil @ 2W4ohm speaker power

A

D_SPK_R+

U

A

U

D D

A

D_SPK_R+27

U

A

U

D_SPK_R-27

A

U

D_SPK_L-27

A

D_SPK_L+27

U

D_SPK_R-

A

D_SPK_L+

U

A

U

D_SPK_L-

CONN Pin

Pin1

1 2

E

2901 0R3J-0-U-GP

R

1 2

E

R

2902 0R3J-0-U-GP

1 2

E

2903 0R3J-0-U-GP

R

1 2

E

2904 0R3J-0-U-GP

R

Net name

SPK_L+

E

E

C

C

2901

2902

12

12

12

Pin2 SPK_L-

Pin3

Pin4

C C

L

NE1_VREFO

L

I

NE1_VREFO27

M

I

C2_VREFO_R27

A

D_HP1_JACK_L27,66

U

A

U

D_HP1_JACK_R27,66

L

NE1_L27

I

L

NE1_R27

I

A

D_SLEEVE27,66

U

A

D_RING27,66

U

A

U

B B

D_SENSE27,66

I

M

C2_VREFO_R

I

A

D_RING

U

A

D_HP1_JACK_L

U

L

NE1_L

I

A

D_HP1_JACK_R

U

L

I

NE1_R

A

U

D_SLEEVE

SPK_R+

SPK_R-

20180911
Vendor modify

1 2

C

2

907 SC10U6D3V3MX-DL-GP

1 2

C

2

908 SC10U6D3V3MX-DL-GP

S

1KP50V2KX-1DLGP

C

S

C

1KP50V2KX-1DLGP

S

1KP50V2KX-1DLGP

C

S

1KP50V2KX-1DLGP

C

3

1

L

L

I

I

NE1_VREFO_L

NE1_VREFO_R

1

23

R

SRN4K7J-8-GP

4

2

N

2902

A

D_SPK_R+_C

U

A

U

D_SPK_R-_C

A

D_SPK_L+_C

U

A

U

D_SPK_L-_C

E

E

C

C

2903

2904

12

D

2

901

BAW56-9-GP-U

75.00056.07D

R

N

2901

1
2 3

SRN2K2J-1-GP

A

U

D_SPK_L-_C

A

D_SPK_L+_C

U

A

U

D_SPK_R-_C

A

U

D_SPK_R+_C

20180911
Vendor modify

4

P

1

2
3
4

ACES-CON4-29-GP

5

6

20.F1639.004

1
1
1
1

A

F

TP2901

A

F

TP2902

A

TP2903

F

A

TP2904

F

<Core Design>

<Core Design>

<Core Design>

A

U

D_SENSE

1

0 mils

A

12

C

909

2

DY

SC10U6D3V3MX-DL-GP

U

D_AGND

istron Corporation

istron Corporation

istron Corporation

W

W

A A

Title

Title

Title

Audio IO

Audio IO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

Audio IO

A

A

A

SP 13" WHL-U

SP 13" WHL-U

SP 13" WHL-U

W

W

W

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

2

W

2

2

2

1

1

1

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

o

o

o

f

f

f

9 106

9 106

9 106

2

2

2

1

0

0

0

0

0

0

A

A

A

5

WWW.AliSaler.Com

D D

C C

4

3

2

1

(Blanking)

B B

<Core Design>

<Core Design>

<Core Design>

istron Corporation

istron Corporation

istron Corporation

W

W

A A

T

le

Title

Title

it

(

(

(

Reserved)

Reserved)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A

A

A

4

4

4

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

2

Reserved)

AS

AS

AS

P 13" WHL-U

P 13" WHL-U

W

W

W

Thursday, March 07, 2019

Thursday, March 07, 2019

Thursday, March 07, 2019

P 13" WHL-U

W

2

2

2

1F

1F

1F

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

, 88, Sec.1, Hsin Tai Wu Rd., Hsichi h,

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

o

o

o

f

0 1

f

0 1

f

0 1

3

3

3

1

00

00

00

A

A

A

06

06

06