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Inspiron N411Z
Schematic
48 pgs1.09 Mb0
Schematic
5 pgs137.54 Kb0
Setup Manual
96 pgs2.46 Mb0

Dell Inspiron N411Z Schematic

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Page 1
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1
R05 DB USB3.0*2, RJ45 and Combo Jack Block Diagram
Label
D D
Label
Label
Label
PCIE
AR8152B
C C
DB_Connector 50 pin
PCIE
NEC UPD720200A
B B
PG 02
USB3.0
USB3.0
RJ45 CONN
PG 02
USB3.0 CONN
USB3.0 CONN
PG 04
PG 04PG 03
Combo Jack
PG 05
PG 2
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
5
4
3
2
Friday, June 17, 2011
PROJECT :
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
R05
R05
R05
1 5
1 5
1
1 5
Page 2
5
4
3
2
1
Close to Pin37
LAN + USB3.0 + Combo Jack CONNECTOR
51
CON1
CON1
FPC/FFC_50 P
D D
C C
B B
FPC/FFC_50 P
2/10: modify pin define, same as MB. 2/14: change QPN to DFFC50FR015. 2/14: change footprint from lap-yba-fpc-019-p03-50p-l to fh52-50s-0_5sh-50p-l-smt (follow GM7C).
51
52
52
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
*4.7uH/70 0mA_8_NC
*4.7uH/70 0mA_8_NC
L2
L2
2/15: follow SS8 ST2 schematic (use 0805).
TRANSFORMER
A A
C27 close to L8206. C28 and C29 close to Pin7 of transformer. C30 and C31 close to Pin2 of transformer.
C271U/6.3V_4 C271U/6.3V_4 C280.1U/10V_4 C280.1U/10V_4 C290.1U/10V_4 C290.1U/10V_4 C30100P/50V_4 C30100P/50V_4 C31100P/50V_4 C31100P/50V_4
AVDD_CEN
3/31 Change CON3 footprint : lap-yba-fpc-019-p03-50p-l
AGND
PCIE_CLK_REQ5#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_TXN6
PCIE_TXP6
PCIE_RXN6 PCIE_RXP6
EC_PCIE_WAKE#
+3.3V_SUS
+5V_ALW +5V_SUS
PCIE_W AKE# 3 PCIE_CLK_REQ4# 3 CLK_PCIE_USB30P 3
CLK_PCIE_USB30N 3
PCIE_RXN4 3 PCIE_RXP4 3
4/2
PT
Close to pin40
+VDDCT+1.7V_LX
12
C24
C24
0.1U/10V
0.1U/10V
MDI0-
MDI0+ MDI1+
MDI1-
EXT_MIC_L 5 JACK_SENSE 5 +5VA_R 5 HPOUT_RB 5 HPOUT_LB 5
SMIB 3 USB_SIDE_EN 4
PLTRST# 3
PCIE_TXN4 3 PCIE_TXP4 3
C25
C25 1U/6.3V
1U/6.3V
Rotate for EMI
U2
16
RX+
15
CT
14
RX-
9
TX-
10
CMT
11
TX+
NS0013B LFU2NS0013B LF
C26
C26 10U/6.3V/X5R_6
10U/6.3V/X5R_6
RD+
RD-
CT
TD+
TD-
CT
These Caps close LAN Chip VDD33 pins
Close to pin40
SJ1 SJ_060 3SJ1 SJ_060 3
2
112
C9 10UC910U
Y1
1 2
C18
C18
33P/50V/NPO_4
33P/50V/NPO_4
25MHzY125MHz
PCIE_RXN6
C1 0.1U/ 10VC1 0.1U/ 10V
PCIE_RXP6
C2 0.1U/ 10VC2 0.1U/ 10V
+3.3V_LA N+3.3V_SUS
C11
C11
C10
C10 1U
1U
10
10
LAN_XTAL2LAN_XTAL1
0.1U/ 10V
0.1U/ 10V
10
10
C19
C19 33P/50V/NPO_4
33P/50V/NPO_4
C12
C12 1000P
1000P
PCIE_TXN6 PCIE_TXP6
CLK_PCIE_LANN CLK_PCIE_LANP
TP1TP1 TP2TP2
R2
2.37K/FR22.37K/F
PCIE_RXN6 _C PCIE_RXP6_C
LAN_SMBDAT
LAN_SMBCLK PLTRST# EC_PCIE_WAKE#
PIN 28 NC for AR8152
LAN_XTAL1 LAN_XTAL2
2/14: Follow UM8C (DB1)
SWR LDO LED_LINK 1 0 Default
+3.3V_LA N
R14 *5.1K_NCR14 *5.1K_NC R13 *5.1K_NCR13 *5.1K_NC
LED_ACT
12
LED_LINK
12
Pin 38,39 internal pull up 36k ohm
R7 4.7K/J_4R7 4.7K/J_4
L1 close to U1
L1
L1
1 2
HCB1608K F-181T15_6
HCB1608K F-181T15_6
LAN_MX0-
1
LAN_MX0+
3
TXCT0
2
LAN_MX1-
6
LAN_MX1+ MDI0+
8
TXCT1
7
AVDD_CEN
R11 75/FR11 75/F
R12 75/FR12 75/F
CRB use 2KV
TXCT0_R
2/21 P/N CH2100GKI04 EOD change to CH2100GKI12
C34
C34 1000P/3KV/X7R_1 8
1000P/3KV/X7R_1 8
R8 4.7K/J_4R8 4.7K/J_4
Overclock enable disable LED_ACT 1 0 Default
LED_ACT
12
LED_LINK
12
U1
U1
29
TX_N
30
TX_P
36
RX_N
35
RX_P
32
REFCLKN
33
REFCLKP
26
SMDATA
25
SMCLK
2
PERSTn
3
WAKEn
10
RBIAS
27
TESTMODE
28
TEST_RST
8
XTLI
7
XTLO
41
GND_PAD
AR8151/A R8152
AR8151/A R8152
*6.8P/50V_4_NC
*6.8P/50V_4_NC
Atheros
Atheros
AR8151
AR8151 AR8152
AR8152
H1
1
H3
H3
1
PAD1
PAD1
1
MDI1+ MDI1-
MDI0-
C35
C35
DVDDL_REG
AVDDH_REG
AVDDL_REG
VDDCT_REG/CLKREQn
CLKREQn/LED2
C88 0.1U/ 10VC88 0.1U/ 10V C89 1U/0603 /10VC89 1U/0603 /10V
C88, C89 Close to U1,Pin4
h-c118d118nH1h-c118d118n
h-tc335bc276d118p2
h-tc335bc276d118p2
spad-pad-1np
spad-pad-1np
C32
C32
*6.8P/50V_4_NC
*6.8P/50V_4_NC
C36
C36 *6.8P/50V_4_NC
*6.8P/50V_4_NC
DVDDL
LX
VDD33
AVDDH AVDDH
AVDDL AVDDL AVDDL AVDDL
VDDCT
TRXN[3] TRXP[3] TRXN[2] TRXP[2] TRXN[1] TRXP[1] TRXN[0] TRXP[0]
LED0 LED1
H2
H2
h-tc217bc276d94p2
h-tc217bc276d94p2
1
H4
H4
h-o118x138d118x138n
h-o118x138d118x138n
1
PAD2
PAD2
spad-pad-2np
spad-pad-2np
1
For EMI
C33
C33 *6.8P/50V_4_NC
*6.8P/50V_4_NC
24 37
40 1 9
16 22
6 13 19 31 34
4 5
21 20 18 17 15 14 12 11
38 39 23
C708 Close to Pin24
+1.1V_DVDD
C7 0.1U/ 10VC7 0.1U/ 10V
+1.7V_LX
+3.3V_LA N
+2.7V_AV DD
C8 0.1U/ 10VC8 0.1U/ 10V
+1.1V_AV DD
PIN 13,19 NC for AR8152
C15 0.1U/ 10VC15 0.1U/ 10V C16 0.1U/ 10VC16 0.1U/ 10V
+VDDCT_L
1 2
R46 0_4R46 0_4
PIN 17,18,20,21 NC for AR8152
MDI1­MDI1+ MDI0­MDI0+
LED_ACT LED_LINK
PCIE_CLK_REQ5#
+VDDCT_L +VDDCT_L
+VDDCT
C17 0.1 U/ 10VC17 0.1 U/ 10V
R3 49.9/F_4R3 49.9/F_4
1 2
R4 49.9/F_4R4 49.9/F_4
1 2
R5 49.9/F_4R5 49.9/F_4
1 2
R6 49.9/F_4R6 49.9/F_4
1 2
2/8: Add screw.
2/10: change FP to rj45-c100g5-108a4-l-8p-luv.
TXCT0_R
change RJ45 CONN from DFTJ08FR197 to DFTJ08FR740 on 5/19 modify
+1.1V_DVDD +2.7V_AV DD
C3
0.1U/ 10VC30.1U/ 10V
2/14: Option for pin4/pin5
󱣋󲛥
Pin45
󴽬󳲙󴳀󰻏󶁜󴞱󳢃󳀃
󱣋󲛥
Pin45
󲯛󴽬󳲙󴳀󰻏󶁜󴞱󳢃󳀃
C17 Close to U1,Pin5
Close to LAN chip
C20
C20
C21
C21 1000P/50V_4
1000P/50V_4
0.1U/10V
0.1U/10V
R9 75/FR9 75/F
R10 75/FR10 75/F
LAN_MX1-
LAN_MX1+ LAN_MX0­LAN_MX0+
Close to Pin9
C5
0.1U/ 10VC50.1U/ 10V
+1.1V_AV DD
C13
C13
0.1U/ 10V
0.1U/ 10V
C6 1U/6.3VC61U/6.3V
C14
C14 1U/6.3V
1U/6.3V
C23
C23 1000P/50V_4
1000P/50V_4
C4 1U/6.3VC41U/6.3V
Close to Pin6
LDO Mode
SWR Mode
C22
C22
0.1U/ 10V
0.1U/ 10V
2/9: Change QPN to DFTJ08FR197.
1/31: Change QPN / FP.
CN1 C100F3-10 804-LCN1 C100F3-10 804-L
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CHSGND110CHSGND2
9
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
LAN(AR8151B/RJ45 CONN)
LAN(AR8151B/RJ45 CONN)
LAN(AR8151B/RJ45 CONN)
R05
R05
R05
2 5Friday, June 17, 2011
2 5Friday, June 17, 2011
1
2 5Friday, June 17, 2011
1A
1A
1A
Page 3
1
2
3
4
5
6
7
8
C49:CH6102K9A01->CH61002ZA36
A A
C52
C52
C53
C49
C49
10U/10V_8
10U/10V_8
+3.3V_SUS
(100mA)
C65
C65
C64
C64
C63
C63 10U/10V_8
10U/10V_8
C63:CH6102K9A01->CH61002ZA36
CLK_PCIE_USB30P2 CLK_PCIE_USB30N2
PCIE_RXP42
C83
C83 1U/10V_6
1U/10V_6
PCIE_RXN42
PLTRST#2
PCIE_WAKE#2
R18
R18
PCIE_CLK_REQ4#2
10K
10K
1 2
+3.3V_SUS
D3
B B
RB500V-40D3RB500V-40
D1:BCRB501VZ16->VCRB500VZ29
0.01U
0.01U
0.1U
0.1U 25V
25V
10V
10V
X7R
X7R
X7R
X7R
SMIB2
PCIE_RXP4 PCIE_RXN4
C72 0.1U/10VC72 0.1U/10V C73 0.1U/10VC73 0.1U/10V
PCIE_TXP42
PCIE_TXN42
PLTRST# PCIE_CLK_REQ4#
+3.3V_SUS +3.3V_SUS
Change R54,R50 to RP1 by Ryan
2/14: Add 0.01u
C67
C67
C66
C66
0.01U
0.01U
0.01U
0.01U 25V
25V
25V
25V
X7R
X7R
X7R
X7R
PCIE_RXP4_C PCIE_RXN4_C
PCIE_TXP4 PCIE_TXN4
SJ15 *SJ0402SJ15 *SJ0402
112
SJ16 *SJ0402SJ16 *SJ0402
112
1 3
RP1 10KRP1 10K
SJ17 *SJ0402SJ17 *SJ0402
112
USB_SPI_CLK USB_CS# USB_WR# USB_RD#
C68
C68
0.01U
0.01U 25V
25V X7R
X7R
2 2
2 4
2
C74:CH5104K9906->CH5102Z3919
SMIB
R47
R47 10K_4
10K_4
Y2
24MHZY224MHZ
C84
Add 10K pull down for SMIB
C C
C84 12P
12P 50V
50V
COG
COG
Please select X'tal (+/- 30ppm)
XIN
XOUT
USB3.0_CSEL
C85
C85 12P
12P 50V
50V COG
COG
C50
C50
0.01U
0.01U 25V
25V X7R
X7R
C92
C92
0.01U
0.01U 25V
25V X7R
X7R
C51
C51
0.1U
0.1U 10V
10V X7R
X7R
U4
U4
B2
PECLKP
B1
PECLKN
D2
PETXP
D1
PETXN
F2
PERXP
F1
PERXN
H2
PERSTB
K1
PEWAKEB
K2
PECREQB
J2
AUXDET
J1
PSEL
H1
SMIB
P5
PONRSTB
M2
SPISCK
N2
SPICSB
N1
SPISI
M1
SPISO
K13
GND
K14
GND
J13
GND
P4
GND
C14
GND
N14
XT1
M14
XT2
P6
CSEL
A1
GND
A2
GND
A3
GND
A4
GND
A5
GND
A7
GND
A9
GND
A11
GND
A13
GND
A14
GND
B3
GND
B4
GND
B5
GND
B7
GND
B9
GND
B11
GND
B13
GND
B14
GND
C1
GND
C2
GND
C3
GND
C10
GND
C11
GND
C53
0.1U
0.1U
0.1U
0.1U
10V
10V
10V
10V
X7R
X7R
X7R
X7R
D10
F14
F13
VDD33
C12
L10
VDD33
VDD33
VDD33G4VDD33F3VDD33L9VDD33
VDD33G3VDD33
GNDD3GNDD4GND
GNDE2GND
GND
GND
GND
GND
E1
D11
D12
D13
D14
GND
GND
C13
+1.05V_USB3.0
(700mA)
C54
C54
C55
C55
0.01U
0.01U
*0.01U_NC
*0.01U_NC
25V
25V
25V
25V
X7R
X7R
X7R
X7R
P3
L14
L13
N5
N4
VDD33
VDD33
VDD33N6VDD33
VDD33
VDD10C5VDD10C6VDD10C4VDD10C7VDD10D5VDD10C8VDD10C9VDD10D8VDD10D9VDD10E3VDD10E4VDD10
UPD720200AF1-DAP-SSA-A
UPD720200AF1-DAP-SSA-A
GNDF4GNDF6GNDF7GNDF8GNDF9GND
GND
F11
F12
GNDG1GNDG2GNDG6GNDG7GNDG8GNDG9GND
GND
E13
E14
C56
C56
0.01U
0.01U 25V
25V X7R
X7R
G11
+3.3V_SUS
L3
L3 BLM21PG600SN1D
BLM21PG600SN1D
C59
C59
C60
P13
U3TXDP2 U3TXDN2
U2DM2 U2DP2
U3RXDP2 U3RXDN2
OCI2B OCI1B
PPON2
PPON1 U3TXDP1 U3TXDN1
U2DM1
U2DP1 U3RXDP1
U3RXDN1
RREF
U2AVSS U2PVSS U3AVSS
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
GNDL4GNDL3GNDL2GNDL1GNDK4GNDK3GND
C60
C61
C61
C62
C69
C69
0.01U
0.01U X7R
X7R 25V
25V
C62
5P
5P
10U/10V_8
10U/10V_8
50V
50V 0603
0603 NPO
NPO
C94:CH6102K9A01->CH61002ZA36
L4
L4
BLM21PG600SN1D
C70
C70
0.1U
0.1U X7R
X7R 10V
10V
BLM21PG600SN1D
C71
C71 10U/10V_8
10U/10V_8
+3.3V_SUS
C43:CH6102K9A01->CH61002ZA36
0.1U
0.1U
0.01U
0.01U
10V
10V
25V
25V
X7R
X7R
X7R
X7R
2/10: add USB3.0 *2 port
B6 A6
N8 P8
B8 A8 G14
H13 H14
J14 B10 A10
N10 P10
B12
A12
P12 N12
N11 D6 P14
P11 P9 P7 P2 P1 N13 N9 N7 N3 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 L12 L11 L7 L6
USB32_P2­USB32_P2+
USB30_OC2# USB30_OC1#
USB32_P1­USB32_P1+
R20 1.6K/F_4R20 1.6K/F_4
2/14: follow SS8 (ST-2) change to +3.3_SUS.
Maximum 3A Low-Dropout Voltage Requlator EN input Bias Current 12uA
CHANGE U5 ADD C37 R15 FOR EOD 06/17
Close to chip Use 1% RES
+3.3V_SUS
+3.3V_SUS
+5V_ALW
10U/6.3V/X5R_8
10U/6.3V/X5R_8
USB3.0_TX2+ 4 USB3.0_TX2- 4
USB32_P2- 4 USB32_P2+ 4
USB3.0_RX2+ 4
USB3.0_RX2- 4
USB30_OC2# 4 USB30_OC1# 4
USB_P2_EN 4 USB_P1_EN 4
USB3.0_TX1+ 4 USB3.0_TX1- 4
USB32_P1- 4 USB32_P1+ 4
USB3.0_RX1+ 4
USB3.0_RX1- 4
C86
C86
C87
C87
0.1U/10V/X7R_4
0.1U/10V/X7R_4
R1510K R1510K
12
C37
C37
0.1U
0.1U 10v
10v X7R
X7R
U5 G966A-25ADJF11UU5 G966A-25ADJF11U
1
POK
GND
2
VEN
ADJ
3
VIN
VO
VPP4NC
9
9
C91
C91 1U/6.3V/X5R_4
1U/6.3V/X5R_4
0616 change RT9018B-18psp to G966-25ADJF1UF for EOD
USB30_OC1# USB_P1_EN
USB30_OC2# USB_P2_EN
8 7 6 5
2
1 3
RP2 10KRP2 10K
1 3
RP3 10KRP3 10K
R23
R23
R1
60.4K/F_6
60.4K/F_6
R2
R24
R24 191K/F_6
191K/F_6
+3.3V_SUS
4
2
+3.3V_SUS
4
Vout=0.8*(R1+R2/R2)
+1.05V_USB3.0
C57
C57
C58
C58
0.01U
0.01U
*0.01U_NC
*0.01U_NC
25V
25V
25V
25V
X7R
X7R
X7R
X7R
E11
E12
H11
K11
K12
L8
VDD10
VDD10H3VDD10H4VDD10L5VDD10
VDD10
VDD10
VDD10
U3AVDD33D7U2AVDD33
GNDJ3GNDJ4GNDJ6GNDJ7GNDJ8GND
H12
GND
J9
J12
J11
GNDH7GNDH8GNDH9GND
GND
GND
GND
H6
G12
G13
USB3.0_CSEL
2
SJ14
SJ14
2
SJ0402
SJ0402
1
1
D D
Change R27 to short jump
Clock select signal
USB3.0_CSEL
1
High = External 48Mhz Low = 24MHz X'tal
2
For USB3.0 512Kbit (64K Byte)
+3.3V_SUS
3
USB_CS# USB_SPI_CLK USB_WR# USB_RD#
+3.3V_SUS
R19
R19
12
R26
R26
47K
47K
R17 33R17 33
10K
10K
U3
U3
1
CE#
6
SCK
5
SI
2
SO
3
WP#
W25X40BVSNIG
W25X40BVSNIG
4
HOLD#
+3.3V_SUS
8
VDD
7
C46
C46
0.1U
0.1U
4
VSS
10V
10V X7R
X7R
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
5
6
Friday, June 17, 2011
7
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
NEC USB 3.0
NEC USB 3.0
NEC USB 3.0
R05
R05
R05
3 5
3 5
3 5
8
1A
1A
1A
Page 4
A
B
C
D
E
2/15 U6 and U7 change value for layout 2/15 swap pin4 and pin6
Change Current limite to uPI solution
+5V_SUS
4 4
USB_P1_EN3
C74 1U
C74 1U
2
10
10
+5V_SUS
C75 0.1U/16VC75 0.1U/16V
12
R34
R34 47K_4
47K_4
31
Q21
Q21 2N7002W-7-F
2N7002W-7-F
12
U7
U7 UP7534BRA8-15
UP7534BRA8-15
2
IN1 IN23OUT2
4
EN#
1
GND
OUT3 OUT1
8 7 6
5
OC#
+USB_SIDE_PW R1
(1.5A)
USB30_OC1# 3
USB_P2_EN3
Change Current limite to uPI solution
+5V_SUS
10
10
12
R35
R35 47K_4
47K_4
31
C77 0.1U/16VC77 0.1U/16V
Q24
Q24 2N7002W-7-F
2N7002W-7-F
12
C76 1U
C76 1U
+5V_SUS
2
U6
U6 UP7534BRA8-15
UP7534BRA8-15
2
IN1 IN23OUT2
4
EN#
1
GND
OUT3 OUT1
8 7 6
5
OC#
+USB_SIDE_PW R2
(1.5A)
USB30_OC2# 3
2/15: follow SS8 ST2 schematic (use 2N7002).
31
Q22
Q22
USB_SIDE_EN2
3 3
2
*2N7002W -7-F_NC
*2N7002W -7-F_NC
USB_SIDE_EN2
2
31
Q23
Q23 *2N7002W -7-F_NC
*2N7002W -7-F_NC
2/21 change P/N BCST2304Z00
Change ESD1 from Depop to Pop
ESD1
ESD1
1
1
2
2 334
TVL ST23 04 AD0
TVL ST23 04 AD0
U2P1+
6
6
5
5
U2P1-
4
2/15 swap pin4 and pin6 2/21 change P/N BCST2304Z00
Change ESD2 from Depop to Pop
ESD2
ESD2
1
1
2
2 334
TVL ST23 04 AD0
TVL ST23 04 AD0
U2P2+
6
6
5
5
U2P2-
4
+USB_SIDE_PW R1
+USB_SIDE_PW R2
2/18
Change L6 from pop to Depop
C85,C86:CH6221M9A03->CH6221M9A01
2 2
+USB_SIDE_PW R1 +USB_SIDE_PW R2
CN2
CN2
1
VBUS
2
D-
USB2.0
USB2.0
3
D+
4
GND
5
SSRX-
6
SSRX+
USB 3.0
USB 3.0
8
SSTX-
9
SSTX+
7
GND
USB3
USB3
GND GND GND GND
10 11 12 13
C78
C78 22U/6.3V_8
22U/6.3V_8
USB3.0_TX1-_D
C79
C79 22U/6.3V_8
22U/6.3V_8
C81 0.1U/10V/X7R_4C81 0.1U/10V/X7R_4 C82 0.1U/10V/X7R_4C82 0.1U/10V/X7R_4
close to conn
12
C80
C80
0.1U/10V/X7R_4
0.1U/10V/X7R_4
100 mil
U2P1­U2P1+
USB3.0_RX1-_D USB3.0_RX1+_D
USB3.0_TX1-_C USB3.0_TX1+_CUSB3.0_TX1+_D
C85,C86:CH6221M9A03->CH6221M9A01
C102
C102 22U/6.3V_8
22U/6.3V_8
3/31 Change CN2 footprint to usb-uea111sc-c54d2-7h-9p 3/31 Change CN3 footprint to usb-uea111sc-c54d2-7h-9p
USB3.0_TX2-_D
C103
C103 22U/6.3V_8
22U/6.3V_8
C101 0.1U/10V/X7R_4C101 0.1U/10V/X7R_4 C105 0.1U/10V/X7R_4C105 0.1U/10V/X7R_4
close to conn
12
C104
C104
0.1U/10V/X7R_4
0.1U/10V/X7R_4
100 mil
U2P2­U2P2+
USB3.0_RX2-_D USB3.0_RX2+_D
USB3.0_TX2-_C USB3.0_TX2+_CUSB3.0_TX2+_D
CN3
CN3
1
VBUS
2
D-
USB2.0
USB2.0
3
D+
4
GND
5
SSRX-
6
SSRX+
USB 3.0
USB 3.0
8
SSTX-
9
SSTX+
7
GND
USB3
USB3
GND GND GND GND
10 11 12 13
USB32_P1-3
USB32_P1+3
USB32_P2+3
ChangeR32,R33 from Depop to Pop
DLP11SN900HL2L
DLP11SN900HL2L
2/18
Change L7 from pop to Depop ChangeR36,R37 from Depop to pop
USB32_P2-3
L6
L6
1 2
L7
L7
1 2
DLP11SN900HL2L
DLP11SN900HL2L
U2P1­U2P1+
34
PT
U2P2­U2P2+
34
USB3.0 EMC
USB3.0_RX1-3 USB3.0_RX1+3
SJ18 *SJ0402SJ18 *SJ0402
112
SJ19 *SJ0402SJ19 *SJ0402
112
USB3.0_RX1-_D
2
USB3.0_RX1+_D
2
Change L6 from Depop to Pop
USB3.0_TX1+3 USB3.0_TX1-3
1 1
SJ20 *SJ0402SJ20 *SJ0402 SJ21 *SJ0402SJ21 *SJ0402
2
112
2
112
USB3.0_TX1+_D USB3.0_TX1-_D
PT
PT
USB3.0_TX1-_C USB3.0_TX1+_C
USB3.0_RX1-_D USB3.0_RX1+_D
Copy from R03 (QT)
U8
U8
1 2 3 4 5
IN1 IN2 GND_1 IN3 IN4
TVU1240R1A
TVU1240R1A
10
O1
9
O2
7
O3
6
O4
USB3.0_TX1-_C USB3.0_TX1+_C
USB3.0_RX1-_D USB3.0_RX1+_D
PT
USB3.0_RX2-3 USB3.0_RX2+3
Change L10 from Depop to Pop
PT
USB3.0_TX2+3 USB3.0_TX2-3
SJ22 *SJ0402SJ22 *SJ0402 SJ23 *SJ0402SJ23 *SJ0402
SJ24 *SJ0402SJ24 *SJ0402 SJ25 *SJ0402SJ25 *SJ0402
112 112
112 112
2 2
2 2
USB3.0_RX2-_D USB3.0_RX2+_D
USB3.0_TX2+_D USB3.0_TX2-_D
2/142/14
USB3.0_TX2-_C USB3.0_TX2+_C
USB3.0_RX2-_D USB3.0_RX2+_D
Copy from R03 (QT)
U10
U10
1 2 3 4 5
IN1 IN2 GND_1 IN3 IN4
TVU1240R1A
TVU1240R1A
10
O1
9
O2
7
O3
6
O4
USB3.0_TX2-_C USB3.0_TX2+_C
USB3.0_RX2-_D USB3.0_RX2+_D
PT
Change L7 from Depop to Pop
Quanta Computer Inc.
Quanta Computer Inc.
L7 swap pin
A
B
Change L11 from Depop to Pop
C
L7 swap pin
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
Friday, June 17, 2011
D
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
USB 3.0 CONN
USB 3.0 CONN
USB 3.0 CONN
R05
R05
R05
4 5
4 5
4 5
E
1A
1A
1A
Page 5
5
D D
4
3
2
1
Combo Jack default is for Apple iPhone design
2/14: Change library of schematic.
CON2
C C
CON2
AUDIO_JACK-COMBO/BLACK
AUDIO_JACK-COMBO/BLACK
7 1 2 6 3 4 5
AGND
EXT_MIC_L 2 HPOUT_LB 2 HPOUT_RB 2
+5VA_R 2 JACK_SENSE 2
B B
A A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
Friday, June 17, 2011
Date: Sheet of
5
4
3
2
Friday, June 17, 2011
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Audio Jack(COMBO)
Audio Jack(COMBO)
Audio Jack(COMBO)
R05
R05
R05
5 5
5 5
5 5
1
1A
1A
1A
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